JP2002271025A - Printed wiring board and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board which has a capacitor inside and has its connection reliability improved, and to provide a manufacturing method for the printed wiring board. SOLUTION: On a chip capacitor 20 incorporated in a core substrate 30, a relatively large via hole 52 is formed, and in an inter-layer insulating layer 60 on the core substrate 30, via holes 69 connected to the via hole 52 are arranged. Consequently, terminals 21 and 22 of the chip capacitor 20 and the via hole 52 can securely be connected. Further, the surfaces of the metallized terminals 21 and 22 are coated with conductive paste 26, so the surfaces of the terminals 21 and 22 can be flat and the connectivity with the via hole 52 can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board on which electronic components such as an IC chip are mounted, and more particularly to a printed circuit board having a built-in capacitor.

[0002]

2. Description of the Related Art At present, in a printed wiring board for a package substrate, a chip capacitor is sometimes mounted on a surface for the purpose of, for example, smoothly supplying power to an IC chip.

Since the reactance of the wiring from the chip capacitor to the IC chip depends on the frequency, a sufficient effect cannot be obtained even if the chip capacitor is surface-mounted with the increase in the driving frequency of the IC chip. For this reason, the present applicant has proposed a technique in Japanese Patent Application No. 11-248311 in which a recess is formed in a core substrate and a chip capacitor is accommodated in the recess. Japanese Patent Application Laid-Open No. 6-326472 discloses a technique for embedding a capacitor in a substrate.
JP-A-7-263519, JP-A-10-256429
JP-A-11-45555, JP-A-11-1269
No. 78 and JP-A-11-31868.

Japanese Patent Application Laid-Open No. 6-326472 discloses a technique for embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, power supply noise is reduced, and a space for mounting a chip capacitor is not required, and the size of the insulating substrate can be reduced. In addition, Japanese Patent Application Laid-Open
No. 263619 discloses a technique for embedding a capacitor in a substrate made of ceramic, alumina, or the like. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.

[0005]

However, the above-mentioned Japanese Patent Application Laid-Open No. 6-326472 and Japanese Patent Application Laid-open No.
Cannot reduce the distance between the IC chip and the capacitor too much, and could not reduce the inductance as required at present in the higher frequency range of the IC chip. In particular, in the case of a resin-made multilayer build-up wiring board, disconnection between a terminal of a chip capacitor and a via due to a difference in the coefficient of thermal expansion between a capacitor made of ceramic and a core substrate made of resin and an interlayer resin insulating layer. Peeling occurred between the capacitor and the interlayer resin insulation layer, cracks occurred in the interlayer resin insulation layer, and high reliability could not be achieved for a long period of time.

On the other hand, in the invention of Japanese Patent Application No. 11-248311, when there is a displacement in the arrangement of the capacitor, the connection between the terminal of the capacitor and the via cannot be made accurately, and the power supply from the capacitor to the IC chip is not possible. There was a fear that it would not be possible.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a battery having a built-in capacitor,
An object of the present invention is to provide a printed wiring board with improved connection reliability and a method for manufacturing the printed wiring board.

[0008]

According to the first aspect of the present invention, there is provided a printed wiring board comprising a resin insulating layer and a conductive circuit laminated on a core substrate, wherein the core substrate has a capacitor. And a plurality of relatively small upper layers connected to one lower via are formed in the interlayer resin insulating layer on the upper surface of the core substrate by forming a relatively large lower via connected to the terminal of the capacitor. A technical feature is that a via is provided, and a conductive paste is applied to the surface of the metallized electrode of the capacitor.

According to the present invention, a capacitor is built in the core substrate, a relatively large lower via connected to a terminal of the capacitor is formed on the capacitor, and one lower via is formed in the interlayer resin insulating layer on the upper surface of the core substrate. And a plurality of relatively small upper-layer vias connected to the upper layer. As a result, it is possible to connect the terminals of the capacitor and the lower vias in accordance with the displacement of the arrangement of the capacitor, and it is possible to reliably supply power from the capacitor to the IC chip.
Also, by providing a plurality of relatively small upper vias, it is possible to obtain the same effect as connecting the inductance components in parallel. Therefore, the high frequency characteristics of the power supply line and the ground line are increased, and the power supply is insufficient or the ground level is low. IC due to fluctuation of
Malfunction of the chip can be prevented. further,
Since the wiring length can be reduced, the loop inductance can be reduced.

It is desirable that the recess be filled with a resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if a stress originating from the capacitor is generated, the stress can be reduced by the filled resin. The resin also has the effect of reducing adhesion and migration between the capacitor and the core substrate.

In addition, since the conductive paste is applied to the surface of the metallized electrode of the capacitor, the surface becomes completely flat. Therefore, when an opening is formed in the resin layer by laser, the resin does not remain on the surface of the electrode, and the connection reliability between the electrode and the via by plating can be improved.

According to the second aspect, since the metal layer is provided on the conductive paste of the electrode of the capacitor, it is possible to prevent the occurrence of migration at the electrode and to further reduce the connection resistance.

According to the third aspect, the surface of the capacitor is subjected to a roughening treatment. As a result, the adhesion between the chip capacitor made of ceramic and the connection layer made of resin and the interlayer resin insulation layer is increased, and the connection layer and the interlayer resin insulation layer are peeled off at the interface even when the heat cycle test is performed. Nothing.

According to a fourth aspect of the present invention, the surface of the capacitor is subjected to a wettability improving treatment such as silane coupling or application of a resin film. Thereby, the adhesion between the ceramic chip capacitor and the connection layer and the interlayer resin insulation layer is increased, and the connection layer and the interlayer resin insulation layer do not peel at the interface even when the heat cycle test is performed. .

In the fifth and sixth aspects, a filled via having a flat surface is used as the lower layer via. This gives 1
A plurality of upper vias can be directly connected to the lower via. Therefore, the connectivity between the lower via and the upper via can be improved, and power can be reliably supplied from the capacitor to the IC chip.

According to the present invention, one capacitor is accommodated in a recess formed in the core substrate. This allows
Since the capacitor is arranged in the core substrate, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced.

According to the eighth aspect, since a large number of capacitors can be accommodated in the recess, high integration of the capacitors is possible.

In the ninth aspect, a resin is filled between the core substrate and the capacitor, and the coefficient of thermal expansion of the resin is set to be smaller than that of the core substrate, that is, close to that of a capacitor made of ceramic. For this reason, in the heat cycle test, even if internal stress is generated due to a difference in the coefficient of thermal expansion between the core substrate and the capacitor, cracks, peeling, and the like hardly occur on the core substrate, and high reliability can be achieved.

In a tenth aspect, a capacitor is provided on the surface in addition to the capacitor housed in the substrate. Since the capacitor is housed in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance is reduced, and power can be supplied instantaneously. Because a capacitor is provided, a large-capacity capacitor can be attached.
Large power can be easily supplied to the IC chip.

In the eleventh aspect, the capacitance of the capacitor on the surface is equal to or larger than the capacitance of the capacitor on the inner layer.
There is no shortage of power supply in the high frequency range, and the desired IC
The operation of the chip is ensured.

In the twelfth aspect, since the inductance of the capacitor on the surface is equal to or larger than the inductance of the capacitor in the inner layer, there is no shortage of power supply in a high frequency region, and a desired operation of the IC chip is ensured.

According to the thirteenth aspect, since a chip capacitor having an electrode formed inside the outer edge is used, a large external electrode can be obtained even when conduction is established via a via, and the allowable range of alignment is widened, so that connection failure is eliminated. .

In the fourteenth aspect, since a capacitor having electrodes formed in a matrix is used, it is easy to accommodate a large chip capacitor in the core substrate. Therefore, the capacitance can be increased, so that an electrical problem can be solved. Further, even after various thermal histories, the printed wiring board is less likely to warp.

According to a fifteenth aspect, a plurality of chip capacitors for multi-cavity may be connected to the capacitor. As a result, the capacitance can be adjusted appropriately, and I
The C chip can be operated.

According to a sixteenth aspect of the present invention, there is provided a method of manufacturing a printed wiring board, which comprises at least the following steps (a) to (e): (B) forming a resin insulating layer on the upper surface of the capacitor; (c) forming a relatively large lower via connected to a terminal of the capacitor in the resin insulating layer. (D) forming an interlayer resin insulation layer on the upper surface of the core substrate; (e) forming a plurality of relatively small upper vias connected to one lower via on the interlayer resin insulation layer. Arranging.

In the sixteenth aspect, the capacitor is built in the core substrate, and a relatively large lower via connected to the capacitor terminal is formed on the capacitor, and one lower via is provided in the interlayer resin insulating layer on the upper surface of the core substrate. And a plurality of relatively small upper-layer vias connected to the upper layer. As a result, it is possible to connect the terminals of the capacitor and the lower vias in accordance with the displacement of the arrangement of the capacitor, and it is possible to reliably supply power from the capacitor to the IC chip. Also, by providing a plurality of relatively small upper vias, it is possible to obtain the same effect as connecting the inductance components in parallel. Therefore, the high frequency characteristics of the power supply line and the ground line are increased, and the power supply is insufficient or the ground level is low. I due to fluctuation of
Malfunction of the C chip can be prevented. Furthermore, since the wiring length can be shortened, the loop inductance can be reduced.

Further, since the conductive paste is applied to the surface of the electrode of the capacitor, the surface becomes completely flat. For this reason, when an opening is formed in the resin layer with a laser,
The resin does not remain on the surface of the electrode, and the connection reliability between the electrode and the via by plating can be improved.

In the seventeenth aspect, one capacitor is accommodated in a recess formed in the core substrate. Thus, since the capacitor is arranged in the core substrate, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced.

According to the eighteenth aspect, since a large number of capacitors can be accommodated in the recess, high integration of the capacitors becomes possible.

According to a nineteenth aspect, a through hole is formed in a resin material containing a resin serving as a core material, and a resin material is attached to the resin material having the through hole to form a core substrate having a concave portion. ing. Thereby, a core substrate having a concave portion with a flat bottom can be formed.

In the twentieth and twenty-first aspects, a filled via having a flat surface is used as the lower via. This makes it possible to directly connect a plurality of upper vias to one lower via. Therefore, the connectivity between the lower via and the upper via can be improved, and power can be reliably supplied from the capacitor to the IC chip.

In the invention according to claim 22, the upper surfaces of the capacitors are made uniform by applying pressure or hitting the upper surfaces of the plurality of capacitors in the concave portion. Thereby,
When the capacitors are provided in the recesses, the heights can be made uniform even if the sizes of the plurality of capacitors vary, and the core substrate can be made smooth. Therefore, the smoothness of the core substrate is not impaired, and the upper interlayer resin insulating layer and the conductive circuit can be appropriately formed, so that the defective product occurrence rate of the printed wiring board can be reduced.

In the thermosetting resin film used in the interlayer resin insulating layer and the connection layer of the present invention, particles which are soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble particles”) are hardly soluble in an acid or an oxidizing agent. , Hardly soluble resin). In addition, the "poorly soluble" used in the present invention
The term "soluble" refers to a substance having a relatively high dissolution rate when immersed in a solution containing the same acid or oxidizing agent for the same time as "soluble" for convenience, and a substance having a relatively low dissolution rate for convenience. Called "poorly soluble".

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and an acid or an oxidizing agent. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In the present invention, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

As the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

Examples of the soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

Examples of the soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin film can be ensured, and thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed on the interlayer resin insulating layer using an acid or an oxidizing agent. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, a via opening can be formed in the interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, polyimide resin,
Examples thereof include polyphenylene resin, polyolefin resin, and fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolak type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolak type epoxy resin, alkylphenol novolak type epoxy resin, biphenol F type epoxy resin, and naphthalene type epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin film used in the present invention, the soluble particles are desirably substantially uniformly dispersed in the hardly-soluble resin. A roughened surface having unevenness with a uniform roughness can be formed, and even when a via or a through hole is formed in a resin film, the adhesion of a metal layer of a conductive circuit formed thereon can be secured. Because. Alternatively, a resin film containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby, since the portions other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin film, the amount of the soluble particles dispersed in the poorly soluble resin is desirably 3 to 40% by weight based on the resin film. If the amount of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities. If the amount exceeds 40% by weight, the soluble particles may be dissolved using an acid or an oxidizing agent. In addition, there is a case where the resin film is melted to a deep portion of the resin film and the insulation between the conductor circuits via the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.

The resin film desirably contains a curing agent and other components in addition to the soluble particles and the hardly soluble resin. As the curing agent, for example,
Imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and microcapsules of these curing agents, and organic materials such as triphenylphosphine, tetraphenylphosphonium, and tetraphenylborate. Phosphine compounds and the like can be mentioned.

The content of the curing agent is desirably 0.05 to 10% by weight based on the resin film. 0.
If the amount is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidizing agent into the resin film is increased, and the insulating property of the resin film may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

The other components include, for example, fillers such as inorganic compounds or resins which do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the printed wiring board can be improved by matching the thermal expansion coefficient, improving heat resistance and chemical resistance, and the like.

Further, the resin film may contain a solvent. As the solvent, for example, acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Ethyl acetate, butyl acetate, cellosolve acetate, and aromatic hydrocarbons such as toluene and xylene. These may be used alone or in combination of two or more.

[0052]

Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a cross section of the printed wiring board 10, and FIG. 8 shows a state where the IC chip 90 is mounted on the printed wiring board 10 shown in FIG. FIG. 9A is an enlarged view of the via 52 in FIG. 7, and FIG. 9B is a diagram illustrating a state in which a plurality of vias 69 are arranged in the via 52 in FIG. It is a schematic diagram which shows the state which looked at.

As shown in FIG. 7, the printed wiring board 10
Core substrate 30 accommodating a plurality of chip capacitors 20
And build-up wiring layers 80A and 80B. Plural chip capacitors 20 housed in core substrate 30
A relatively large via 52 is connected to the terminals 21 and 22. Also, the build-up wiring layers 80A, 80B
Is composed of interlayer resin insulation layers 60 and 160. A conductive circuit 68 and a relatively small via 69 are formed in the interlayer resin insulating layer 60, and a conductive circuit 168 and a relatively small via 169 are formed in the interlayer resin insulating layer 160. On the interlayer resin insulating layer 160, a solder resist layer 70 is provided.

As shown in FIG. 10A, the chip capacitor 20 includes a first electrode 21 and a second electrode 22, and first and second electrodes 21 and 22.
A first conductive film 24 connected to the first electrode 21 side and a second conductive film 25 connected to the second electrode 22 side. A plurality of sheets are arranged facing each other. The surfaces of the first electrode 21 and the second electrode 22 are coated with a conductive paste 26.

Here, the first electrode 21 and the second electrode 22
Consists of a metallization of Ni, Pb or Ag metal.
The conductive paste 26 is made of a paste containing metal particles such as Cu, Ni or Ag. Here, the particle size of the metal particles is desirably 0.1 to 10 μm, and most preferably 1 to 5 μm. As the conductive paste, an organic conductive paste obtained by adding a thermosetting resin such as an epoxy resin or a polyphenylene sulfide (PPS) resin to metal particles is preferable. The thickness of the conductive paste 26 is 1 to 30 μm.
m is desirable. If the thickness is less than 1 μm, unevenness on the electrode surface cannot be eliminated, while if it exceeds 30 μm, the effect is not particularly improved. Here, a thickness of 5 to 20 μm is most desirable. Note that a paste in which two or more kinds of particles having different diameters are mixed can be used, and further, a metal paste having two or more kinds of different diameters can be coated.

The electrodes 21 and 22 of the chip capacitor are made of metallized and have irregularities on the surface. Therefore, when the metal layer is used in a state where the metal layer is exposed, the resin may remain on the irregularities in the step of forming the opening 42 in the resin insulating layer 40 by laser. In this case, the first,
A connection failure between the second electrodes 21 and 22 and the via 52 occurs. In the present embodiment, the surfaces of the first and second electrodes 21 and 22 are smoothed by the conductive paste 26, and when the opening 42 covered on the electrode is formed, no resin residue remains and the via 52 Can improve the connection reliability with the electrodes 21 and 22 at the time of formation.

Further, a roughened layer 23a is provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. Therefore, the chip capacitor 20 made of ceramic, the adhesive material 34 made of resin, and the resin insulating layer 40
The adhesion between the adhesive material 34 and the resin insulating layer 40 at the interface does not occur even when the heat cycle test is performed. The roughened layer 23a can be formed by polishing the surface of the chip capacitor 20 after firing, or by performing a roughening process before firing.

As shown in FIG. 8, the via 169 of the upper build-up wiring layer 80A is provided with the pad 9 of the IC chip 90.
2, a solder bump 76U for connection to No. 2 is formed. On the other hand, the via 16 of the lower buildup wiring layer 80B
9, a solder bump 76D for connection to the pad 95 of the daughter board 94 is formed.

As the core substrate, a substrate made of resin was used. For example, a resin material used for a general printed wiring board such as a glass epoxy resin-impregnated base material and a phenol resin-impregnated base material can be used. However, a substrate made of ceramic, AIN, or the like cannot be used as the core substrate. This is because the substrate has poor external formability, and may not be able to accommodate a capacitor, and voids are generated even when filled with resin.

Further, since a plurality of chip capacitors 20 are accommodated in the concave portions 32 formed in the core substrate 30, the chip capacitors 20 can be arranged at a high density. Further, since a plurality of chip capacitors 20 are accommodated in the recess 32, the heights of the chip capacitors 20 can be made uniform. Therefore, the resin layer 4 on the chip capacitor 20
Since 0 can be made to have a uniform thickness, the via 52 can be formed appropriately. In addition, since the distance between the IC chip 90 and the chip capacitor 20 is reduced, the loop inductance can be reduced.

Further, as shown in FIG. 7 and FIG. 9A which is an enlarged view of the via 52 of FIG. 7, a plurality of vias 69 of the upper build-up wiring layer 80A are connected to one via 52. I have. As shown in FIG. 9B, the large via 52 has an inner diameter of 1
25 μm, land diameter 165 μm, small via 69
The inner diameter is 25 μm and the land diameter is 65 μm. On the other hand, the chip capacitor 20 is formed in a rectangular shape,
The first terminal 21 and the second terminal 21 are also formed in a rectangular shape having a side of 250 μm. For this reason, even if the disposition position of the chip capacitor 20 is shifted by several tens μm,
0, the first terminal 21 and the second terminal 22 can be connected to the via 52.
Power supply to the C chip 90 can be reliably performed.
Also, by providing a plurality of vias 69, an effect similar to that of connecting the inductance components in parallel can be obtained, so that the high frequency characteristics of the power supply line and the ground line are enhanced, and the IC due to insufficient power supply or fluctuations in the ground level. Malfunction of the chip can be prevented. Further, since the wiring length from the IC chip to the chip capacitor 20 can be reduced, the loop inductance can be reduced.

As shown in FIG. 7, the via 52 is formed as a filled via having a flat surface by filling with plating. This makes it possible to directly connect the plurality of vias 69 on the via 52. Therefore, the connectivity between the via 52 and the via 69 can be improved, and power can be reliably supplied from the chip capacitor 20 to the IC chip 90. In the present embodiment, the filled via is formed by plating. However, instead of this, a filled via in which a resin is filled inside and a metal film is disposed on the surface may be used as the via 52.

The coefficient of thermal expansion of the resin filler 36 and the adhesive material 34 below the chip capacitor 20 is determined by the core substrate 30.
And smaller than the resin insulation layer 40, that is, close to the chip capacitor 20 made of ceramic. For this reason, in the heat cycle test, even if internal stress is generated due to a difference in thermal expansion coefficient between the core substrate 30 and the resin insulating layer 40 and the chip capacitor 20, cracks, peeling, etc. And high reliability can be achieved.

The resin layer 3 between the chip capacitors 20
6, since the through-hole 54 is formed, the signal line does not pass through the chip capacitor 20 made of ceramic, so that reflection due to impedance discontinuity due to the high dielectric substance and propagation delay due to passage through the high dielectric substance do not occur.

Next, a method of manufacturing the printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.

(1) First, a core substrate 30 made of an insulating resin substrate is used as a starting material (see FIG. 1A). Next, on one surface of the core substrate 30, a recess 32 for disposing a capacitor is formed by counterboring or by forming a through hole in an insulating resin and pressing and bonding (see FIG. 1B). At this time, the recess 32 is formed to be wider and larger than an area where a plurality of capacitors can be arranged. Thus, a plurality of capacitors can be reliably provided on the core substrate 30.

(2) Then, an adhesive material 34 is applied to the recess 32 using a printing machine (see FIG. 1C). Alternatively, the concave portion can be coated with an adhesive material by a method such as potting, die bonding, or attaching an adhesive sheet. An adhesive material having a smaller coefficient of thermal expansion than the core substrate is used. Next, a plurality of chip capacitors 20 made of ceramic are bonded to the recesses 32 via an adhesive material 34 (see FIG. 1D). Here, by arranging the plurality of chip capacitors 20 in the recess 32 having a smooth bottom, the heights of the plurality of chip capacitors 20 are uniform. Therefore, the resin insulating layer 40 can be formed with a uniform thickness on the core substrate 30 in a step described later, and the vias 52 can be appropriately formed.

Then, the upper surfaces of the chip capacitors 20 are pressed or hit so that the upper surfaces of the plurality of chip capacitors 20 have the same height (FIG. 1 (E)).
reference). By this step, when a plurality of chip capacitors 20 are arranged in the recess 32, even if the sizes of the plurality of chip capacitors 20 vary, the heights can be completely made uniform, and the core substrate 30 Can be smoothed.

(3) Thereafter, a space between the chip capacitors 20 in the concave portions 32 is filled with a thermosetting resin, and heat-cured to form a resin layer 36 (see FIG. 2A). At this time, as the thermosetting resin, epoxy, phenol, polyimide, and triazine are preferable. Thus, the chip capacitor 20 in the recess 32 can be fixed. The resin layer 36 has a smaller coefficient of thermal expansion than the core substrate.

In addition, a resin such as a thermoplastic resin may be used. In addition, a filler may be impregnated in the resin in order to match the coefficient of thermal expansion. Examples of the filler include an inorganic filler, a ceramic filler, and a metal filler.

(4) Further, the above-mentioned epoxy resin or polyolefin resin is applied thereon by using a printing machine to form a resin insulating layer 40 (see FIG. 2B). Note that a resin film may be attached instead of applying the resin.

Other than the above, a thermosetting resin, a thermoplastic resin, a photosensitive resin, a composite of a thermosetting resin and a thermoplastic resin,
One or more resins such as a composite of a photosensitive resin and a thermoplastic resin can be used. They may have a two-layer structure.

(5) Next, the resin insulating layer 40 is irradiated with a laser.
A relatively large via opening 42 is formed (see FIG. 2).
(C)). At this time, since the surfaces of the electrodes 21 and 22 of the chip capacitor 20 are smooth due to the conductive paste 26, the resin does not remain on the electrodes. After that, desmear processing is performed. Exposure and development processing can be used instead of laser. Then, a through hole 44 for a through hole is formed in the resin layer 36 by a drill or a laser, and is cured by heating (see FIG. 2D). In some cases, a roughening treatment using an acid, an oxidizing agent, or a chemical solution, or a roughening treatment using a plasma treatment may be performed. Thereby, the adhesion of the roughened layer is ensured.

(6) Thereafter, a copper plating film 46 is formed on the surface of the resin insulating layer 40 by electroless copper plating (FIG. 3).
(A)). Ni and Cu instead of electroless plating
Sputtering with a target of Ni / Cu
A metal layer may be formed. In some cases, the electroless plating film may be formed after the formation by sputtering. At this time, the electrodes 21 and 22 of the chip capacitor 20 are
Since the resin does not remain on the surface of the electrode 21, the copper plating film 46 can be appropriately formed on the electrodes 21 and 22.

(7) Next, a photosensitive dry film is stuck on the surface of the copper plating film 46, a mask is placed thereon, and exposure and development are performed to form a plating resist 48 having a predetermined pattern. Then, the core substrate 30 is immersed in the electrolytic plating solution, a current is passed through the copper plating film 46, and the portion where the plating resist 48 is not formed is filled with the electrolytic plating 50 (FIG. 3).
(B)).

(8) Then, the plating resist 48 is added with 5%
After stripping and removing with NaOH, the copper plating film 46 under the plating resist 48 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to form a filled via structure including the copper plating film 46 and electrolytic copper plating 50. A relatively large via 52 and a through hole 54 are formed. The large via diameter is desirably in the range of 100 to 600 μm. In particular, the thickness is desirably 125 to 350 μm. In this case, it was formed at 165 μm. The through hole was formed at 250 μm. Then, an etching solution is sprayed on both surfaces of the substrate 30 by spraying to etch the surface of the via 52 and the land surface of the through hole 54, thereby forming a roughened surface 52α on the entire surface of the via 52 and the through hole 54. (See FIG. 3C).

(9) Thereafter, a resin filler 56 containing an epoxy resin as a main component is filled in the through hole 54,
Dry (see FIG. 3 (D)).

(10) A thermosetting resin film having a thickness of 50 μm is applied to both surfaces of the substrate 30 having undergone the above steps at a temperature of 50 to 50 μm.
Vacuum-compression lamination at a pressure of 5 kg / cm ² while increasing the temperature to 150 ° C. to provide an interlayer resin insulation layer 60 (FIG. 4).
(A)). The degree of vacuum during vacuum compression is 10 mmHg. As the resin film, an epoxy resin or an olefin resin can be used.

(11) Next, a relatively small via opening 61 of 65 μm is formed in the interlayer resin insulating layer 60 by a CO ₂ gas laser (see FIG. 4B). The relatively small via diameter is desirably in the range of 25 to 100 μm. Thereafter, desmear treatment is performed using oxygen plasma.

(12) Next, plasma treatment is performed using SV-4540 manufactured by Japan Vacuum Engineering Co., Ltd. to roughen the surface of the interlayer resin insulating layer 60, thereby forming a roughened surface 60α (FIG. 4 (C)). )reference). At this time, argon gas was used as the inert gas, electric power 200 W, gas pressure 0.6 Pa,
Plasma treatment is performed at a temperature of 70 ° C. for 2 minutes.
Roughening treatment may be performed with an acid or an oxidizing agent. Further, the thickness of the roughened layer is desirably 0.1 to 5 μm.

(13) Next, after replacing the argon gas inside using the same apparatus, sputtering using Ni and Cu as targets was performed at a pressure of 0.6 Pa, a temperature of 80 ° C.
The process is performed under the conditions of electric power of 200 W and time of 5 minutes, and the Ni / Cu metal layer 62 is formed on the surface of the interlayer resin insulating layer 60. At this time, the thickness of the formed Ni / Cu metal layer 62 is 0.2
μm (see FIG. 4D). A plating film such as electroless plating or a plating film may be formed on a sputter.

(14) A commercially available photosensitive dry film is adhered to both surfaces of the substrate 30 after the above treatment, a photomask film is placed thereon, and the film is exposed to light at 100 mJ / cm ^2. Develop with sodium, thickness 15
A μm plating resist 64 is provided. Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 6 having a thickness of 15 μm.
6 (see FIG. 5A). The additive in the electrolytic plating aqueous solution is Capparaside HL manufactured by Atotech Japan.

[Electroplating aqueous solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (Capparaside HL, manufactured by Atotech Japan) 19.5 ml / l [Electroplating conditions] Current density 1 A / dm ² Time 65 minutes Temperature 22 ± 2 ℃

(15) The plating resist 64 is made of 5% NaO
After removing by H, Ni / C under the plating resist
The u-metal layer 62 is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the Ni / Cu metal layer 6 is removed.
Then, a plurality of relatively small vias 69 connected to the conductor circuit 68 and the via 52, each of which is formed by the electrode 2 and the electrolytic plating film 66, are formed (see FIG. 5B). In the present embodiment, the via 52
Has a filled via structure, a plurality of vias 69 can be directly connected to the via 52.

(16) Next, the substrate is washed with water and dried, and then the surface of the conductive circuit 68 is etched by spraying an etching solution on both surfaces of the substrate by spraying.
A roughened surface 68α is formed on the entire surface of the conductive circuit 68 (FIG. 5).
(C)). As an etching solution, a mixture of 10 parts by weight of an imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride, and 78 parts by weight of ion-exchanged water is used.

(17) Next, the above (10) to (16)
Is repeated to form a further upper interlayer resin insulation layer 160 and conductive circuit 168 (including via 169).
Is formed (see FIG. 5D).

(18) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight, and a 50% epoxy group was acrylated. Oligomer for imparting properties (molecular weight 4000) 46.67
15 parts by weight of a bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) of 80% by weight dissolved in methyl ethyl ketone, imidazole hardener (trade name: 2E4MZ-CN)
1.6 parts by weight, 3 parts by weight of a polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., trade name: R604) as a photosensitive monomer,
Similarly, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name:
1.5 parts by weight of DPE6A) and 0.71 part by weight of a dispersant antifoaming agent (manufactured by San Nopco, trade name: S-65) are placed in a container, stirred and mixed to prepare a mixed composition. Of benzophenone (manufactured by Kanto Kagaku) and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to give a viscosity of 25.
A solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s at ° C is obtained. The viscosity was measured using a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm with rotor No. 4, and at 6 rpm with rotor N.
According to o.3.

(19) Next, the solder resist composition is applied to both sides of the substrate 30 to a thickness of 20 μm,
After performing a drying process under the conditions of 20 ° C. for 20 minutes and 70 ° C. for 30 minutes, a 5 mm-thick photomask on which a pattern of the solder resist opening is drawn is applied to the solder resist layer 70.
And exposed to ultraviolet light of 1000 mJ / cm ² ,
Openings 71U and 71D are formed by developing with a DMTG solution (see FIG. 6A). Further, a commercially available solder resist such as LPSR may be used.

(20) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 was formed was coated with nickel chloride (2.3 × 10 ⁻¹ mol / l) and sodium hypophosphite (2.8 × 10 ⁻¹ mol / l). 10 ^-1 mol / l) and an electroless nickel plating solution having a pH of 4.5 containing sodium citrate (1.6 × 10 ^-1 mol / l) for 20 minutes.
A nickel plating layer 72 having a thickness of 5 μm is formed on U and 71D. Further, the substrate was coated with potassium potassium cyanide (7.
6 × 10 ⁻³ mol / l), ammonium chloride (1.9 × 10 ⁻³ mol / l)
10 ^-1 mol / l), sodium citrate (1.2 × 1
0 ^-1 mol / l), sodium hypophosphite (1.7 × 1
(0 ^-1 mol / l) of the electroless plating solution at 80 ° C. for 7.5 minutes to form a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 72 (FIG. 6 ( B)
reference).

(21) Thereafter, the solder resist layer 70
The solder bumps (solder bodies) 76U and 76D are formed by printing a solder paste on the openings 71U and 71D of the solder paste and performing reflow at 200 ° C. Thereby, the printed wiring board 10 having the solder bumps 76U and 76D can be obtained (see FIG. 7).

Next, mounting of the IC chip on the printed wiring board 10 completed in the above-described steps and mounting on the daughter board will be described with reference to FIG. The IC chip 9 is placed so that the solder pads 92 of the IC chip 90 correspond to the solder bumps 76U of the completed printed wiring board 10.
The IC chip 90 is mounted by placing the “0” and performing reflow. Similarly, the printed wiring board 10 is attached to the daughter board 94 by reflowing so that the pads 95 of the daughter board 94 correspond to the solder bumps 76D of the printed wiring board 10.

Next, a printed wiring board according to a modification of the first embodiment of the present invention will be described with reference to FIG. In the first embodiment described above, only the chip capacitors 20 housed in the core substrate 30 are provided. However, in a modified example, the large-capacity chip capacitors 98 are provided on the front and back surfaces.
Has been implemented.

FIG. 10B shows a cross section of a chip capacitor 20 according to a first modification of the first embodiment. In the first embodiment, the surface of the capacitor is subjected to a roughening treatment to improve the adhesiveness with the resin. However, in the first modification, the polyimide film 23b is formed instead of this to improve the surface wettability. Has been improved. Instead of the polyimide film, the surface of the capacitor may be subjected to a silane coupling treatment.

In the first modification, the conductive paste 2
6, a composite metal film 28 composed of an electroless copper plating film 28a and an electrolytic copper plating film 28b is formed. The thickness of the composite metal film 28 is desirably 0.1 to 10 μm.
５5 μm is optimal. Instead of a composite metal film, it is also possible to form a single-layer metal film.

In the first modification, the electrode 2 of the capacitor 20
Since the metal layer 28 is provided on the conductive pastes 1 and 22, the occurrence of migration at the electrodes 21 and 22 can be prevented, and the connection resistance can be further reduced. The electrodes 21 and 22 made of metallized
Although there are irregularities on the surface, the irregularities can be completely eliminated by applying the conductive paste 26 and further providing the metal layer 28, whereby the adhesion to the via 52 can be increased and the connection resistance can be reduced.

The IC chip instantaneously consumes a large amount of power and performs complicated arithmetic processing. Here, in order to supply large power to the IC chip side, in a modified example, a chip capacitor 20 and a chip capacitor 98 for power supply are provided on the printed wiring board. The effect of the chip capacitor will be described with reference to FIG.

FIG. 12 shows the voltage supplied to the IC chip on the vertical axis and the time on the horizontal axis. Here, the two-dot chain line C
Indicates voltage fluctuation of a printed wiring board without a power supply capacitor. When the power supply capacitor is not provided, the voltage greatly decreases. A broken line A indicates a voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. Although the voltage does not drop much as compared with the two-dot chain line C, the rate-limiting power supply cannot be performed sufficiently because the loop length is long. That is, the voltage drops at the start of power supply. The two-dot chain line B indicates the voltage drop of the printed wiring board incorporating the chip capacitor described above with reference to FIG. Although the loop length has been shortened,
Since a large-capacity chip capacitor cannot be accommodated in the core substrate 30, the voltage fluctuates. here,
A solid line E indicates the voltage fluctuation of the printed wiring board of the modification in which the chip capacitor 20 in the core substrate described above with reference to FIG. 11 and the large-capacity chip capacitor 98 are mounted on the surface. Chip capacitor 2 near the IC chip
0, a large-capacity (and relatively large inductance) chip capacitor 20, and a large-capacity (and relatively large inductance) chip capacitor 98.
, Voltage fluctuations are minimized.

Next, a printed wiring board 110 according to a second embodiment of the present invention will be described with reference to FIG. In the first embodiment described above, the case where the BGA is provided has been described. The second embodiment is almost the same as the first embodiment, but is configured as a PGA system in which connection is made via conductive pins 96 as shown in FIG. Note that a conductive paste is formed on the electrode as in the first embodiment, or a conductive paste and a composite metal layer are formed as in the first modification of the first embodiment.

Next, a method of manufacturing the printed wiring board described above with reference to FIG. 20 will be described with reference to FIGS.

(1) First, through holes 33a for accommodating chip capacitors are formed in a laminated plate 30α formed by laminating four prepregs 31 impregnated with epoxy resin. On the other hand, a laminate 3 formed by laminating two prepregs 31
0β is prepared (see FIG. 13A). Here, as the prepreg 31, one containing a reinforcing material such as BT, phenol resin, or glass cloth in addition to epoxy can be used.

(2) Next, the laminated plate 30α and the laminated plate 30β
The core substrate 30 having the concave portion 33 capable of accommodating the plurality of chip capacitors 20 is formed by press-bonding and heating and curing (see FIG. 13B).

(3) Then, an adhesive material 34 is applied to the position where the capacitor is provided in the concave portion 33 by using a potting (dispenser) (see FIG. 13C). Alternatively, the concave portion can be coated with an adhesive material by a method such as printing, die bonding, or attaching an adhesive sheet. Thereafter, the plurality of chip capacitors 20 made of ceramic are accommodated in the recesses 33 via the adhesive material 34 (FIG. 13).
(D)).

(4) After that, a thermosetting resin is filled between the chip capacitors 20 in the concave portions 33, and heat-cured to form a resin layer 36 (see FIG. 14A). At this time,
As the thermosetting resin, epoxy, phenol, polyimide, and triazine are preferable. Thus, the chip capacitor 20 in the recess 33 can be fixed.

(5) Further, the above-mentioned epoxy or polyolefin resin is applied thereon using a printing machine to form a resin insulating layer 40 (FIG. 14B).
reference). Note that a resin film may be attached instead of applying the resin.

(6) Next, a relatively large via opening 42 is formed in the resin insulating layer 40 by exposure / development processing or laser (see FIG. 14C). The large via diameter is
It is desirable to be in the range of 100 to 600 μm. In particular, the thickness is desirably 125 to 350 μm. In this case, it was formed at 165 μm. Then, a through hole 44 for a through hole having a diameter of 250 μm is formed in the resin layer 36 by a drill or a laser, and is cured by heating (FIG. 14D).
reference).

(7) After applying a palladium catalyst to the substrate 30, the core substrate is immersed in an electroless plating solution.
The electroless plating film 45 is uniformly deposited (FIG. 15A)
reference). Then, the opening 4 in which the electroless plating film 45 is formed is formed.
2 is filled with a resin filler and dried. Thereby, a resin layer 47 is formed inside the opening 42.
(B)).

(8) Thereafter, a photosensitive dry film is adhered to the surface of the electroless plating film 45, a mask is placed, and exposure and development are performed to form a plating resist 48 having a predetermined pattern. Then, the core substrate 30 is added to the electrolytic plating solution.
To form a cover plating 51 made of an electroless plating film (see FIG. 15C).

(9) After the above steps, the plating resist 48
Is removed with 5% NaOH, the electroless plated film 45 under the plating resist 48 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and a relatively large via 53 and a through hole 54 having a filled via structure are formed. (Fig. 1
5 (D)). By forming the via 53 with a filled via structure, a plurality of vias 69 can be directly connected to one via 53 in a process described later.

(10) Then, the substrate 30 is washed with water and acid degreased, and then soft-etched. Then, an etching solution is sprayed on both surfaces of the substrate 30 by spraying, so that the surface of the via 53 and the land surface of the through hole 54 are The inner wall is etched to form a roughened surface 53α on the entire surface of the via 53 and the through hole 54 (see FIG. 16A). As an etching solution, an etching solution comprising 10 parts by weight of an imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride (Mec etch bond manufactured by Mec Co., Ltd.)
Use

(11) Next, bisphenol F type epoxy
Simonomer (manufactured by Yuka Shell Co., molecular weight: 310, YL9
83U) 100 parts by weight, silane coupling agent on the surface
The average coated particle size is 1.6 μm and the largest particle
Having a diameter of 15 μm or less _Two Spherical particles (Adtech
CRS 1101-CE) 170 parts by weight and
Belling agent (Perenol S4 manufactured by San Nopco) 1.5
Put the parts by weight in a container, stir and mix to
Resin filler 56 having a degree of 23 ± 1 ° C. and 45-49 Pa · s
Is prepared. In addition, as a curing agent, an imidazole curing agent
(Shikoku Chemicals, 2E4MZ-CN) 6.5 parts by weight
Was. After that, a resin filler 56 is placed in the through hole 54.
Fill and dry (see FIG. 16B).

(12) Next, 30 parts by weight of a bisphenol A type epoxy resin (epoxy equivalent 469, manufactured by Yuka Shell Epoxy Co., Ltd., Epicoat 1001), a cresol novolak type epoxy resin (epoxy equivalent 215, epicron manufactured by Dainippon Ink and Chemicals, Inc.) N-673) 40 parts by weight, triazine structure-containing phenol novolak resin (phenolic hydroxyl equivalent 120, phenolite KA-7052 manufactured by Dainippon Ink and Chemicals, Inc.) 30 parts by weight, ethyl diglycol acetate 20 parts by weight, solvent naphtha 20 parts by weight The mixture was heated and dissolved while stirring, and 15 parts by weight of a terminal epoxidized polybutadiene rubber (Denalex R-45EPT manufactured by Nagase Kasei Kogyo Co., Ltd.) and 2-phenyl-4,
5-bis (hydroxymethyl) imidazole pulverized product
5 parts by weight, 2 parts by weight of finely divided silica, and 0.5 part by weight of a silicon-based antifoaming agent are added to prepare an epoxy resin composition.
The resulting epoxy resin composition is applied on a 38 μm-thick PET film using a roll coater so that the thickness after drying becomes 50 μm, and then dried at 80 to 120 ° C. for 10 minutes to form an interlayer resin. A resin film for an insulating layer is produced.

(13) On both surfaces of the substrate, a resin film for an interlayer resin insulating layer slightly larger than the substrate 30 prepared in (12) is placed on the substrate 30, and the pressure is 4 kgf / cm ² , the temperature is 80 ° C., and the substrate is crimped. After temporarily compressing and cutting under the condition of a time of 10 seconds, the interlayer resin insulating layer 60 is formed by applying a vacuum laminator by the following method (see FIG. 16C). That is, a resin film for an interlayer resin insulating layer is formed on the substrate 30 with a degree of vacuum of 0.5 Torr.
r, pressure 4 kgf / cm ² , temperature 80 ° C, pressure bonding time 60
The main bonding is performed under the condition of seconds, and then, the thermosetting is performed at 170 ° C. for 30 minutes.

(14) Next, on the interlayer resin insulation layer 60,
Mask 57 having a through hole 57a having a thickness of 1.2 mm
Through the CO ₂ gas laser to the interlayer resin insulation layer 60,
A relatively small via opening 61 of 65 μm is formed (see FIG. 16D). A relatively small via diameter is 25
It is desirable that the thickness be in the range of 100 μm.

(15) Substrate 3 with Via Opening 61 Formed
0 is immersed in a solution containing 60 g / l of permanganic acid at 80 ° C. for 10 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer 60, thereby including the inner wall of the via opening 61. The surface of the interlayer resin insulation layer 60 is a roughened surface 60α (see FIG. 17A). Roughening treatment may be performed with an acid or an oxidizing agent. The roughened layer is
0.1-5 μm is desirable.

(16) Next, the substrate 30 after the above-described processing
Is immersed in a neutralizing solution (manufactured by Shipley) and then washed with water. Further, by applying a palladium catalyst to the surface of the substrate 30 which has been subjected to a surface roughening treatment (roughening depth: 3 μm),
A catalyst nucleus is attached to the surface of the interlayer resin insulation layer 60 and the inner wall surface of the via opening 61.

(17) Next, the substrate 30 is immersed in an electroless copper plating aqueous solution having the following composition to form an electroless copper plating film 63 having a thickness of 0.6 to 3.0 μm on the roughened surface 60α. (See FIG. 17B). [Electroless plating aqueous solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α'-bipyridyl 40 mg / l Polyethylene glycol (PEG) 0.10 g / l [Electroless plating conditions] 40 minutes at a liquid temperature of 35 ° C

(18) A commercially available photosensitive dry film is affixed to the electroless copper plating film 63, and a mask is placed thereon.
Exposure is performed at 00 mJ / cm ² , and development processing is performed using a 0.8% aqueous sodium carbonate solution to provide a plating resist 64 having a thickness of 30 μm. Next, the substrate 30 is washed with water at 50 ° C. to be degreased, washed with water at 25 ° C., further washed with sulfuric acid, and then subjected to electrolytic copper plating under the following conditions to obtain a 20 μm-thick electrolytic copper plating film. 66 (FIG. 17)
(C)). [Electroplating aqueous solution] sulfuric acid 2.24 mol / l copper sulfate 0.26 mol / l additive 19.5 ml / l (manufactured by Atotech Japan, Capparaside HL) [electroplating conditions] current density 1 A / dm ² hours 65 minutes Temperature 22 ± 2 ℃

(19) Plating resist 64 is made of 5% NaO
After stripping and removing with H, the electroless plating film 63 under the plating resist 64 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and is composed of the electroless copper plating film 63 and the electrolytic copper plating film 66. A conductor circuit 68 having a thickness of 18 μm and a relatively small via 69 are formed (see FIG. 17D). Thereafter, the same treatment as in (10) is performed, and a roughened surface 68α is formed with an etching solution containing a cupric complex and an organic acid (see FIG. 18A).

(20) Subsequently, the above (13) to (19)
By repeating this step, the upper interlayer resin insulation layer 160, the conductor circuit 168, and the via 169 are further formed (see FIG. 18B).

(21) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight was sensitized with a 50% epoxy group acrylated. Oligomer for imparting properties (molecular weight 4000) 46.67
15 parts by weight of a bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) of 80% by weight dissolved in methyl ethyl ketone, imidazole hardener (trade name: 2E4MZ-CN)
1.6 parts by weight, 4.5 parts by weight of a bifunctional acrylic monomer (trade name: R604, manufactured by Kyoei Chemical Co., Ltd.) as a photosensitive monomer, and similarly polyvalent acrylic monomer (trade name: DPE6A, manufactured by Kyoei Chemical Co., Ltd.) 5 parts by weight and 0.71 part by weight of a dispersion antifoaming agent (manufactured by San Nopco Co., Ltd., trade name: S-65) are placed in a container, and stirred and mixed to prepare a mixed composition. 2.0 parts by weight of benzophenone (manufactured by Kanto Kagaku) as a weight initiator and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to give a viscosity of 2 parts.
A solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s at 5 ° C. is obtained. The viscosity was measured by
60 rpm with a type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.)
In the case of No. 4, the rotor No. 4 was used, and in the case of 6 rpm, the rotor No. 3 was used.

(22) Next, on both sides of the multilayer wiring board,
20 μm of the solder resist composition prepared in (21)
Apply with a thickness of Then, at 70 ° C for 20 minutes at 70 ° C
After performing a drying process under the condition of for 30 minutes, a 5 mm-thick photomask on which the pattern of the opening of the solder resist is drawn is brought into close contact with the solder resist composition, and the
Exposure with ultraviolet rays of mJ / cm ² and development processing with a DMTG solution are performed to form openings 71U and 71D. Then, at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, and at 120 ° C. for 1 hour.
Heat treatment at 150 ° C. for 3 hours to cure the solder resist composition.
20 μm thick solder resist layer 7 having 71D
0 is formed (see FIG. 19A). As the solder resist composition, a commercially available solder resist composition can be used.

(23) Next, the substrate on which the solder resist layer 70 has been formed is coated with nickel chloride (2.3 × 10 ^-1 mol).
/ L), sodium hypophosphite (2.8 × 10 ^-1 mol)
/ L), sodium citrate (1.6 × 10 ^-1 mol /
2) in the electroless nickel plating solution having pH = 4.5 containing l)
By immersing for 0 minute, a nickel plating layer 72 having a thickness of 5 μm is formed in the openings 71U and 71D. Furthermore, the substrate gold potassium cyanide ^{(7.6 × 10 -3 mol / l} ), ammonium chloride ^{(1.9 × 10 -1 mol / l} ), sodium citrate (1.2 × 10 ^-1 mol / l), immersed in an electroless gold plating solution containing sodium hypophosphite (1.7 × 10 ⁻¹ mol / l) at 80 ° C. for 7.5 minutes to form a layer having a thickness of 0% on the nickel plating layer 72. A 0.03 μm gold plating layer 74 is formed (see FIG. 19B).

(24) Thereafter, tin-opening is placed in the opening 71U of the solder resist layer 70 on the surface of the substrate on which the IC chip is mounted.
Print solder paste containing lead. Further, a solder paste is printed as the conductive adhesive 97 in the opening 71D on the other surface. Next, the conductive connection pin 96 is attached to and supported by a suitable pin holding device, and the fixing portion 98 of the conductive connection pin 96 is brought into contact with the conductive adhesive 97 in the opening 71D. Then, reflow is performed to fix the conductive connection pins 96 to the conductive adhesive 97. Also, the conductive connection pins 9
As a method of attaching 6, the conductive adhesive 97 formed in a ball shape or the like is put into the opening 71D, or the conductive adhesive 97 is joined to the fixing portion 98 to attach the conductive connection pin 96. , And then reflow.

Thereafter, the opening 71 of the printed wiring board 110 is
Solder pad 9 of IC chip 90 is attached to U-side solder bump 76.
2 is mounted, and the IC chip 90 is mounted by reflowing the IC chip 90 (FIG. 2).
0).

Next, a printed wiring board according to a third embodiment of the present invention will be described with reference to FIG. The printed wiring board 210 of the third embodiment is almost the same as the above-described first embodiment. However, in the printed wiring board 210 of the third embodiment, one chip capacitor 20 is accommodated in the recess 35 formed in the core substrate 30. Since the chip capacitor 20 is arranged in the core substrate 30, the distance between the IC chip 90 and the chip capacitor 20 is shortened, and the loop inductance can be reduced. Note that a conductive paste is formed on the electrode as in the first embodiment, or a conductive paste and a composite metal layer are formed as in the first modification of the first embodiment.

Next, the configuration of a printed wiring board according to a fourth embodiment of the present invention will be described with reference to FIG. The configuration of the printed wiring board of the fourth embodiment is substantially the same as that of the above-described first embodiment. However, the core substrate 3
The chip capacitors 20 housed to 0 are different. FIG.
2 shows a plan view of the chip capacitor. FIG.
(A) shows a chip capacitor for multi-piece cutting before cutting, and a dashed line in the drawing shows a cutting line. In the printed wiring board of the first embodiment described above, the first electrode 21 and the second electrode 22 are arranged on the side edges of the chip capacitor as shown in the plan view of FIG. FIG. 22 (C)
Indicates a chip capacitor for multi-cavity cutting according to the fourth embodiment before cutting, and a dashed line in the drawing indicates a cutting line. In the printed wiring board of the fourth embodiment, FIG.
As shown in the plan view, a first electrode 21 and a second electrode 22 are provided inside the side edge of the chip capacitor. In addition,
The electrode is formed with a conductive paste as in the first embodiment, or a conductive paste and a composite metal layer as in the first modification of the first embodiment.

In the printed wiring board according to the fourth embodiment,
Since the chip capacitor 20 having the electrode formed inside the outer edge is used, a large-capacity chip capacitor can be used.

Next, a printed wiring board according to a first modification of the fourth embodiment will be described with reference to FIG.
FIG. 23 is a plan view of the chip capacitor 20 housed in the core substrate of the printed wiring board according to the first modification. In the above-described first embodiment, a plurality of small-capacity chip capacitors are housed in the core substrate. In the first modification, a large-capacity large-format chip capacitor 20 is housed in the core substrate. Here, the chip capacitor 20 is
The electrode 21, the second electrode 22, the dielectric 23, and the first electrode 2
1, a second conductive film 25 connected to the second electrode 22 side, and upper and lower surfaces of a chip capacitor not connected to the first conductive film 24 and the second conductive film 25. And a connection electrode 27. The IC chip side and the daughter board side are connected via the electrodes 27. In addition, a conductive paste, as in the first embodiment,
Alternatively, a conductive paste and a composite metal layer are formed as in the first modification of the first embodiment.

In the printed wiring board of the first modification, a large-sized chip capacitor 20 is used, so that a large-capacity chip capacitor can be used. Further, since the large chip capacitor 20 is used, the printed wiring board does not warp even if the heat cycle is repeated.

A printed wiring board according to a second modification will be described with reference to FIG. FIG. 24A shows a chip capacitor for multi-piece cutting before cutting, in which a dashed line shows a normal cutting line, and FIG. 24B shows a plan view of the chip capacitor. . As shown in FIG. 24B, in the second modification, a plurality of (three in the example in the figure) multi-chip chip capacitors are connected and used in a large format. Note that a conductive paste is formed on the electrode as in the first embodiment, or a conductive paste and a composite metal layer are formed as in the first modification of the first embodiment.

In the second modification, a large-sized chip capacitor 20 is used, so that a large-capacity chip capacitor can be used. Further, since the large chip capacitor 20 is used, the printed wiring board does not warp even if the heat cycle is repeated.

In the above-described fourth embodiment, the chip capacitor is built in the printed wiring board. However, a plate-shaped capacitor in which a conductor film is provided on a ceramic plate may be used instead of the chip capacitor. .

Here, with respect to the printed wiring board of the first embodiment, the chip capacitor 20 embedded in the core substrate is used.
And the inductance of the chip capacitor mounted on the back surface of the printed wiring board (the surface on the daughter board side) are shown below. In case of single capacitor Embedded type 137pH Backside mounted type 287pH When 8 capacitors are connected in parallel Embedded type 60pH Backside mounted type 72pH As shown above, when using a single capacitor, it is connected in parallel to increase the capacity In addition, the inductance can be reduced by incorporating a chip capacitor.

Next, the result of the reliability test will be described. Here, the rate of change of the capacitance of one chip capacitor in the printed wiring board of the first embodiment was measured. Capacitance change rate (measuring frequency 100Hz) (measuring frequency 1kHz) Steam 168 hours: 0.3% 0.4% HAST 100 hours: −0.9% −0.9% TS 1000cycles: 1.1% 1.3%

In the Steam test, steam was applied and the humidity was kept at 100%. In the HAST test, the relative humidity was 100%,
It was left at an applied voltage of 1.3 V and a temperature of 121 ° C. for 100 hours. In the TS test, 30 minutes at -125 ° C and 30 minutes at 55 ° C
The test of standing for 1000 minutes was repeated 1000 times.

In the above reliability test, it was found that a printed wiring board having a built-in chip capacitor could achieve the same reliability as the existing surface mount type capacitor. As described above, in the TS test,
Due to the difference in the coefficient of thermal expansion between the ceramic capacitor and the core substrate made of resin and the interlayer resin insulation layer, even if internal stress occurs, disconnection between the terminal of the chip capacitor and the via, insulation of the chip capacitor and the interlayer resin It was found that peeling between the layers and cracks did not occur in the interlayer resin insulating layer, and high reliability could be achieved for a long period of time.

[0137]

According to the structure of the present invention, since the via of the present invention is formed between the conductor circuit and the capacitor, the desired performance can be maintained without delaying the operation due to insufficient power supply. It did, and did not cause any problems even when subjected to reliability tests. Further, even if a via of the interlayer insulating layer is formed or a positional shift is caused by the via, an allowable range thereof is widened, so that electrical connectivity is ensured.

In addition, since the conductive paste is applied to the surface of the capacitor electrode, the surface becomes completely flat. For this reason, when an opening is formed in the resin layer with a laser,
The resin does not remain on the surface of the electrode, and the connectivity between the electrode and the via by plating can be improved.

[Brief description of the drawings]

FIG. 1 (A), (B), (C), (D), (E)
It is a manufacturing process figure of the printed wiring board concerning a 1st embodiment of the present invention.

FIGS. 2A, 2B, 2C, and 2D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 3A, 3B, 3C, and 3D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 4A, 4B, 4C, and 4D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 5A, 5B, 5C, and 5D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 6A and 6B are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a sectional view of the printed wiring board according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a state in which an IC chip is mounted on the printed wiring board according to the first embodiment of the present invention.

FIG. 9A is an enlarged view of a via 52 in FIG.
(B) is an arrow B diagram of (A).

FIG. 10A is a sectional view of a chip capacitor according to the first embodiment, and FIG. 10B is a sectional view of a chip capacitor according to a first modification of the first embodiment;

FIG. 11 is a cross-sectional view of a printed wiring board according to a modification of the first embodiment of the present invention.

FIG. 12 is a graph showing changes in power supplied to an IC chip and time.

FIGS. 13A, 13B, 13C, and 13D are manufacturing process diagrams of the printed wiring board according to the second embodiment of the present invention.

14A, 14B, 14C, and 14D are manufacturing process diagrams of a printed wiring board according to the second embodiment of the present invention.

FIGS. 15A, 15B, 15C, and 15D are manufacturing process diagrams of a printed wiring board according to the second embodiment of the present invention.

FIGS. 16A, 16B, 16C, and 16D are manufacturing process diagrams of a printed wiring board according to the second embodiment of the present invention.

FIGS. 17A, 17B, 17C, and 17D are manufacturing process diagrams of a printed wiring board according to the second embodiment of the present invention.

FIGS. 18A and 18B are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.

FIGS. 19A and 19B are manufacturing process diagrams of a printed wiring board according to the second embodiment of the present invention.

FIG. 20 is a cross-sectional view showing a state in which an IC chip is mounted on a printed wiring board according to a second embodiment of the present invention.

FIG. 21 is a sectional view showing a state in which an IC chip is mounted on a printed wiring board according to a third embodiment of the present invention.

FIGS. 22 (A), (B), (C), and (D) are plan views of a chip capacitor of a printed wiring board according to a fourth embodiment.

FIG. 23 is a plan view of a chip capacitor of a printed wiring board according to a fourth embodiment.

FIGS. 24A and 24B are plan views of a chip capacitor of a printed wiring board according to a modification of the fourth embodiment.

[Explanation of symbols]

 Reference Signs List 20 chip capacitor 21 first electrode 22 second electrode 23 dielectric 23a roughened surface 23b polyimid film 26 conductive paste 28a electroless copper plating film 28b electrolytic copper plating film 28 composite metal film 30 core substrate 32 recess 33 recess 35 recess 36 Resin layer 40 Resin insulation layer 52 Via 53 Via 60 Interlayer resin insulation layer 68 Conductor circuit 69 Via 70 Solder resist layer 71U, 71D Opening 72 Nickel plating layer 74 Gold plating layer 76 Solder bump 90 IC chip 92 Solder pad (IC chip side) ) 94 daughter board 95 solder pad (daughter board side) 96 conductive connecting pin 97 conductive adhesive 98 fixing part 160 interlayer resin insulating layer 168 conductive circuit 169 via

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 23/12 H01G 4/38 A H05K 1/18 H01L 23/12 BNF term (Reference) 5E082 AA01 CC01 DD15 EE23 5E336 AA04 AA14 BB03 BB15 BC02 BC26 CC32 CC36 CC43 CC53 CC55 EE07 EE08 EE17 GG11 GG16 5E346 AA06 AA12 AA15 AA32. GG27 GG28 HH02 HH11

Claims (22)

[Claims] 1. A printed wiring board comprising a resin insulating layer and a conductor circuit laminated on a core substrate, wherein a capacitor is built in the core substrate, and a relatively large lower via connected to a terminal of the capacitor is provided. Forming a plurality of relatively small upper vias connected to one lower via in an interlayer resin insulating layer on the upper surface of the core substrate;
A printed wiring board to which a conductive paste is applied. 2. The printed wiring board according to claim 1, wherein a metal layer is provided on the conductive paste of the electrodes of the capacitor. 3. The printed wiring board according to claim 1, wherein the surface of the capacitor is subjected to a roughening treatment. 4. The printed wiring board according to claim 1, wherein the surface of the capacitor is subjected to a surface wettability improving treatment. 5. The printed wiring board according to claim 1, wherein the lower via is a filled via having a flat surface filled with plating. 6. The printed wiring board according to claim 1, wherein the lower via is a filled via formed by filling a resin therein and forming a metal film on a surface thereof. 7. The printed wiring board according to claim 1, wherein one of the capacitors is accommodated in a recess formed in the core substrate. 8. The printed wiring board according to claim 1, wherein a plurality of the capacitors are accommodated in a recess formed in the core substrate. 9. Between the core substrate and the capacitor,
The printed wiring board according to claim 1, wherein the printed wiring board is filled with a resin having a smaller coefficient of thermal expansion than the core substrate. 10. The printed wiring board according to claim 1, wherein a capacitor is mounted on a surface of the printed wiring board. 11. The printed wiring board according to claim 10, wherein the capacitance of the chip capacitor on the surface is equal to or larger than the capacitance of the chip capacitor in the inner layer. 12. The printed wiring board according to claim 10, wherein the inductance of the chip capacitor on the front surface is equal to or greater than the inductance of the chip capacitor in the inner layer. 13. The printed wiring board according to claim 1, wherein a chip capacitor having an electrode formed inside an outer edge is used as the capacitor. 14. The printed wiring board according to claim 1, wherein a chip capacitor having electrodes formed in a matrix is used as said capacitor. 15. The printed wiring board according to claim 1, wherein a plurality of chip capacitors for multi-cavity are connected and used as the capacitor. 16. A method for manufacturing a printed wiring board, comprising at least the following steps (a) to (e): (a) A capacitor in which a conductive paste is coated on a metallized electrode on a core substrate. (B) forming a resin insulating layer on the upper surface of the capacitor; (c) forming a relatively large lower via connected to a terminal of the capacitor on the resin insulating layer; (d) Forming an interlayer resin insulation layer on the upper surface of the core substrate; and (e) arranging a plurality of relatively small upper vias connected to the one lower via in the interlayer resin insulation layer. 17. The printing method according to claim 16, further comprising, before the step (a), a step of forming a recess in the core substrate and accommodating one of the capacitors in the recess. Manufacturing method of wiring board. 18. The printing method according to claim 16, further comprising, before the step (a), a step of forming a recess in the core substrate and accommodating a plurality of the capacitors in the recess. Manufacturing method of wiring board. 19. A method of forming a core substrate having a concave portion by forming a through hole in a resin plate and pasting the resin plate to the resin plate having the through hole before the step (a). The method for manufacturing a printed wiring board according to claim 16, comprising: 20. The method for manufacturing a printed wiring board according to claim 16, wherein, when forming the lower layer via, plating is filled to form a filled via having a flat surface. 21. The printed wiring board according to claim 16, wherein when the lower via is formed, a filled via having a metal film disposed on the surface is formed after filling the inside with a resin. Manufacturing method. 22. After the step (a), a pressure is applied from above to the upper surfaces of the plurality of capacitors in the recesses,
The method for manufacturing a printed wiring board according to claim 18, further comprising a step of adjusting the height of the upper surface of the capacitor.