JPH11312868A - Multilayer wiring board with built-in element and its manufacture - Google Patents

Multilayer wiring board with built-in element and its manufacture

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Publication number
JPH11312868A
JPH11312868A JP11821498A JP11821498A JPH11312868A JP H11312868 A JPH11312868 A JP H11312868A JP 11821498 A JP11821498 A JP 11821498A JP 11821498 A JP11821498 A JP 11821498A JP H11312868 A JPH11312868 A JP H11312868A
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layers
element
wiring
resin
insulating
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JP11821498A
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JP3236818B2 (en )
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Katsura Hayashi
桂 林
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Kyocera Corp
京セラ株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a multilayer wiring board with built-in element which can be reduced in size and improved in element packaging density, and a method for manufacturing the wiring board.
SOLUTION: After forming a plurality of insulating layers 3a-3d containing an uncured thermosetting resin, on which wiring circuit layers 2 composed of via hole conductors 1 formed by filling up via holes with metal powder and/or metal foil, etc., are formed, a resin film 5 which has a glass-transition temperature higher than that the thermosetting resin contained in the insulating layers 3a-3d has and is mounted with such an electric element 8 as the tape carrier package, etc., is put between each insulating layers 3a-3d and is unified with the adjacent insulating layers. Then the laminated body is heated to the curing temperature of the thermosetting resin.
COPYRIGHT: (C)1999,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、多層配線基板、特に絶縁基板内部にテープキャリアパッケージが内蔵されてなる多層配線基板とその製造方法に関するものである。 The present invention relates to a multilayer wiring board, it relates to a multilayer wiring board and a manufacturing method thereof comprising a built-in particular a tape carrier package inside the insulating substrate.

【0002】 [0002]

【従来技術】従来より、電子機器の小型化が進みつつあり、近年では、携帯情報端末の発達やコンピュータを持ち運んで操作する、いわゆるモバイルコンピューティングの普及によってさらに小型、薄型且つ高精細の多層配線基板が求められる傾向にある。 Of the Prior Art Conventionally, there progressing miniaturization of electronic devices in recent years, operating carrying your development and computer of the portable information terminal, more compact the spread of so-called mobile computing, thin and high-definition multi-layer wiring the substrate tends to be required.

【0003】また、従来の多層配線基板は、表裏に2次元的に半導体素子を実装するものであるために、配線基板の高密度実装化には自ずと限界があり、その結果、基板表面において配線に必要なスペースが確保できなくなるという問題が生じ、電子機器の軽量、小型化に伴うプリント基板の薄層化、小型化、軽量化に対しては、対応できないのが現状である。 [0003] In addition, the conventional multilayer wiring board, since it is intended to implement the two-dimensionally semiconductor element on both sides, there is a limit to high-density mounting of the wiring board, as a result, the wiring in the substrate surface there is a problem in that space required can not be ensured, the light weight of electronic devices, thinning of a printed circuit board with the miniaturization, size reduction, for weight reduction, can not correspond at present.

【0004】これに対して、種々の電気素子を高密度に実装する方法として、CSP(チップサイズパッケージ)やTSOP(Thin Small Outline Package) 、TC [0004] In contrast, the various electrical devices as a way to implement high density, CSP (chip size package) and TSOP (Thin Small Outline Package), TC
P等のパッケージを2段または3段に積み重ねた構造のものや、半導体素子そのものを積層すること等が、例えば、回路実装学会第23回セミナー(1997年10 Or anything stacked packages P such as two-stage or three-stage structure, or the like to stack the semiconductor device itself, for example, circuit mounting Society 23rd Seminar (1997 10
月)「半導体パッケージと実装技術の最新動向」において提案されている。 Month) have been proposed in the "latest trends in the semiconductor package and implementation technology."

【0005】 [0005]

【発明が解決しようとする課題】しかしながら、このようなパッケージを積み重ねる方法、半導体素子を積み重ねる方法では、半導体素子に信号を伝送するための信号線を引き回すための領域が非常に限られ、特に、今後の通信技術の発達に伴い、高周波信号を伝送するためのグランド層と中心導体を具備するマイクロストリップ線路等の複雑な高周波伝送線路等を形成することが非常に難しいものであった。 [SUMMARY OF THE INVENTION However, a method of stacking such packages, the method of stacking semiconductor element, region for routing the signal line for transmitting a signal to the semiconductor device is very limited, especially, with the development of future communication technology, to form a complex high-frequency transmission line such as a microstrip line or the like having a ground layer and the center conductor for transmitting a high frequency signal was very difficult.

【0006】しかも、単純にパッケージや半導体素子を積層する方法では、全体としての厚みが必然的に厚くなるために、小型軽量が必要なモバイル系機器に対しては適用できないものであった。 [0006] Moreover, in the method of simply stacking the packages and semiconductor devices, to the thickness of the entire inevitably becomes thick and was not applicable for small, lightweight mobile system equipment required.

【0007】本発明者らは、このような考えに基づき、 [0007] The present inventors have found that, based on this concept,
先に転写シートに金属箔からなる配線回路層を形成し、 Previously forming a wiring circuit layer made of a metal foil to the transfer sheet,
その配線回路層に半導体素子を接続した後に、絶縁層に転写して、1つまたは複数の半導体素子を内蔵する多層配線基板を作製する方法を考案した。 After connecting the semiconductor element to the wiring circuit layer, is transferred to the insulating layer, have devised a method of making a multi-layer wiring board with a built-in one or more of the semiconductor devices. しかし、この方法においては、ベア(裸) の半導体素子を金属箔に実装する作業は、高性能のクリーンルーム中にて行う必要があるために、容易に実施することが難しいものであった。 However, in this method, the work of mounting the semiconductor element of bare (bare) to the metal foil, since it is necessary to perform at during performance of the clean room, were those it is difficult to easily implemented.

【0008】従って、本発明は、半導体素子や電子部品(コンデンサ素子、抵抗素子、フィルター素子、発振素子など)を搭載する多層配線基板において、半導体素子を3次元的に内蔵して基板の小型化と、素子の実装密度を高めることのできる多層配線基板を提供することを目的とするものである。 Accordingly, the present invention relates to a semiconductor device and electronic component (a capacitor element, a resistor element, a filter element, an oscillation and an element) in the multilayer wiring board for mounting, miniaturization of the substrate incorporates a semiconductor device in three dimensions When, it is an object to provide a multilayer wiring board capable of enhancing the mounting density of the elements. さらに、本発明は、基板の内部に素子を3次元的に内蔵することのできる多層配線基板を容易に作製することのできる多層配線基板の製造方法を提供することを目的とするものである。 Furthermore, the present invention is an object to provide a method for manufacturing a multilayer wiring board capable of manufacturing a multilayer wiring board capable of incorporating the element in three dimensions in the substrate easily.

【0009】 [0009]

【課題を解決するための手段】本発明者は、半導体素子を搭載した配線基板の小型化について検討を重ねた結果、配線基板内に、テープキャリアパッケージ等の表面に電気素子が搭載された樹脂フィルムを、未硬化状態の絶縁層とともに積層一体化しその積層物を加熱処理して硬化させること、その際、樹脂フィルムとして熱硬化時の加熱温度において変形などの生じることのない耐熱性を有するフィルムによって形成されていることにより、 Means for Solving the Problems The present inventor has repeatedly studied miniaturization of a wiring board having semiconductor elements, a wiring board, an electrical element on a surface such as a tape carrier package is mounted resins the film, to be cured by heating the laminate integrated laminate thereof with an insulating layer of uncured, films with that time, that no heat resistance of occurrence of deformation at a heating temperature during thermal curing the resin film by being formed by,
電気素子の実装構造に悪影響を及ぼすことなく、多層配線基板内に内蔵せしめることができることを見いだし、 Without adversely affecting the mounting structure of the electric element, it found that can be allowed to built in the multilayer wiring substrate,
本発明に至った。 We have completed the present invention.

【0010】即ち、本発明の素子内蔵多層配線基板は、 [0010] In other words, the device built-in multi-layer wiring board of the present invention,
少なくとも熱硬化性樹脂を含む複数の絶縁層を積層してなる絶縁基板と、該絶縁基板の表面および内部に形成された配線回路層と、前記配線回路層間を電気的に接続するためのビアホール導体を具備する多層配線基板において、前記絶縁層間に、電気素子が搭載された樹脂フィルムを積層してなるとともに、前記樹脂フィルムのガラス転移点が、前記絶縁層の熱硬化温度よりも高いことを特徴とするものである。 A plurality of insulating layers and the insulating substrate formed by laminating a wiring circuit layer formed on the surface and inside of the insulating substrate, the via hole conductors for electrically connecting the wiring circuit layers including at least a thermosetting resin in the multilayer wiring board having a, the insulating interlayer, wherein with electric element formed by laminating a resin film mounted, the glass transition point of the resin film, higher than the thermal curing temperature of the insulating layer it is an.

【0011】また、前記電気素子としては、半導体素子、容量素子および抵抗素子等が上げられ、前記耐熱性を有する樹脂フィルムの材質としては、イミド樹脂、アラミド樹脂、フッ素樹脂、PET(ポリエチレンテレフタレート)樹脂、PEN(ポリエチレンナフタレート) [0011] As the electrical element, a semiconductor element, such as a capacitive element and the resistive element is raised, as a material of the resin film having the heat-resistant, imide resin, aramid resin, fluorine resin, PET (polyethylene terephthalate) resin, PEN (polyethylene naphthalate)
樹脂、ポリオレフィン樹脂等が好適に使用される。 Resins, polyolefin resins are preferably used.

【0012】また、電気素子が、基板内の空隙部に収納されることが望ましく、さらに、ビアホール導体は金属粉末の充填によって形成され、配線回路層が金属箔から形成されることが望ましい。 Further, the electric element, it is desirable to be housed in the gap portion in the substrate, further, the via-hole conductors are formed by filling the metal powder, it is preferable that the wiring circuit layer is formed from a metal foil.

【0013】また、本発明の素子内蔵多層配線基板の製造方法によれば、ビアホール導体および/または配線回路層が形成された未硬化状態の熱硬化性樹脂を含む複数の絶縁層を作製した後、これらの絶縁層間に、前記絶縁層中の熱硬化性樹脂の硬化温度よりも高いガラス転移点を有し、その表面に電気素子を搭載してなる樹脂フィルムを積層して一体化した後、該積層物を前記熱硬化性樹脂の硬化温度に加熱することを特徴とするものであり、 Further, according to the manufacturing method of the head protection multilayer wiring board of the present invention, after preparing a plurality of insulating layers containing a thermosetting resin in an uncured state via hole conductors and / or the wiring circuit layers are formed , in these insulating layers, after the having a high glass transition temperature than the curing temperature of the thermosetting resin of the insulating layer, and integrally laminating a resin film obtained by mounting the electrical device on the surface thereof, and characterized in that heating the laminate was the curing temperature of the thermosetting resin,
前記配線回路層が、金属箔からなること、前記ビアホール導体が、金属粉末を含むペーストを充填することによって形成されることが望ましい。 The wiring circuit layer be made of a metal foil, the via hole conductor is preferably formed by filling a paste containing a metal powder.

【0014】 [0014]

【発明の実施の形態】以下、本発明を図面をもとに説明する。 BEST MODE FOR CARRYING OUT THE INVENTION The following describes the present invention based on the drawings. 図1は、本発明の素子内蔵多層配線基板を製造するための製造工程を説明するための図である。 Figure 1 is a diagram for explaining a manufacturing process for manufacturing a device built multilayer wiring board of the present invention.

【0015】本発明の製造方法によれば、図1に示すように、ビアホール導体1および/または配線回路層2が形成された未硬化状態の熱硬化性樹脂を含む複数の絶縁層3を作製した後、これらの絶縁層3間に、電気素子4 According to the production method of the present invention, as shown in FIG. 1, producing a plurality of insulating layers 3 containing a thermosetting resin in an uncured state via hole conductors 1 and / or the wiring circuit layers 2 are formed after, between these insulating layers 3, the electric element 4
が形成されてなる樹脂フィルム5を挟持して積層して一体化する。 There sandwiching a resin film 5 formed formed to integrally laminated.

【0016】図1における絶縁層3a〜3dには、ビアホール導体1および配線回路層2が形成されたものであるが、ビアホール導体1は、熱硬化性樹脂を含む軟質(Bステージ状態)の絶縁層3a〜3dに、厚み方向に貫通するスルーホールを形成し、そのスルーホール内に金属粉末を含む導体ペーストをスクリーン印刷や吸引処理しながら充填することによりビアホール導体1を形成することができる。 [0016] insulating layer 3a~3d in FIG. 1, but in which the via hole conductors 1 and the wiring circuit layer 2 is formed, the via-hole conductors 1, insulation of soft (B stage state) containing a thermosetting resin the layer 3 a to 3 d, to form a through hole penetrating in the thickness direction, it is possible to form the via-hole conductors 1 by filling with a conductive paste by screen printing or suction process containing metal powder into the through-hole.

【0017】また、絶縁層3a〜3dの表面に配線回路層2を形成するには、1)絶縁層の表面に金属箔を貼り付けた後、エッチング処理して回路パターンを形成する方法、2)絶縁層表面にレジストを形成して、メッキにより形成する方法、3)転写フィルム表面に金属箔を貼り付け、金属箔をエッチング処理して回路パターンを形成した後、この金属箔からなる回路パターンを絶縁層表面に転写させる方法等が挙げられる。 Further, in order to form a wiring circuit layer 2 on the surface of the insulating layer 3a~3d is 1) after attaching a metal foil on the surface of the insulating layer, a method of forming a circuit pattern by etching, 2 ) by forming a resist on the insulating layer surface, a method of forming by plating, 3) transfer the film surface to paste metal foil, after forming a circuit pattern of the metal foil by etching, the circuit pattern made of a metal foil the method or the like to be transferred to the surface of the insulating layer.

【0018】なお、樹脂フィルムに形成された電気素子が嵩高い場合には、積層時に配線基板に対して変形が生じるために、そのような場合には、図1に示すように、 [0018] Incidentally, when the electric element formed on the resin film is bulky, since the deformation occurs for the wiring substrate during lamination, in such a case, as shown in FIG. 1,
表面に電気素子4が形成された樹脂フィルム5を積層する箇所の絶縁層3bに空隙部6を設け、積層時に電気素子4が空隙部6内に収納されるようにすることが望ましい。 The air gap 6 in the insulating layer 3b locations of laminating a resin film 5 to the electric element 4 are formed on the surface provided, it is desirable that the electric element 4 to be accommodated in the gap portion 6 during lamination.

【0019】なお、電気素子4が形成された樹脂フィルム5としては、例えば、図2に示すようなテープキャリアパッケージ(TCP)が挙げられる。 [0019] As the resin film 5 which electric element 4 is formed, for example, a tape carrier package (TCP) and the like as shown in FIG. 図2によれば、 According to FIG. 2,
樹脂フィルム5は、枠体状に形成されており、樹脂フィルム5の表面には、枠体内側から外側に導出された金属箔からなる配線回路層7が形成されており、その枠体内側の配線回路層7の表面に、半導体素子8が実装されている。 The resin film 5 is formed in a frame-like, on the surface of the resin film 5, a frame inside which the wiring circuit layer 7 made of a metal foil which is led to the outside is formed, of the frame body side the surface of the wiring circuit layer 7, the semiconductor device 8 is mounted. また、配線回路層7の枠体外側の端部は、樹脂フィルムを挟持する絶縁層のビアホール導体との接続を容易にするために直径30〜300μmの略円形のランドが形成されることが望ましい。 Further, the frame outer end of the wiring circuit layer 7 is preferably substantially circular land having a diameter of 30~300μm to facilitate the connection with the via hole conductors in the insulating layers sandwiching a resin film is formed . ランドがない場合はビア導体との接続、特に位置合わせが困難になったり、接続抵抗が増加する場合がある。 If land is not sometimes connected to the via conductor, or particularly difficult alignment and connection resistance increases. また、配線回路層7に実装された半導体素子8は、樹脂9によって樹脂封止されることが望ましい。 The semiconductor device 8 mounted on the wiring circuit layer 7 is preferably a resin 9 is sealed with a resin.

【0020】この封止樹脂9は、製造工程中、電気体素子表面を保護する役割と果たし、また絶縁層3a〜3d [0020] The sealing resin 9, during the manufacturing process, plays a role of protecting the electrical element surface and the insulating layer 3a~3d
と半導体素子8の熱膨張率の差を緩和するために用いられる。 Used to mitigate the difference in thermal expansion coefficient between the semiconductor device 8 with. 従って、樹脂中にSiO 2等のフィラーを50体積%以上含有する、熱膨張係数が半導体素子に近似した9〜13ppm/℃を有するエポキシ樹脂や、エラストマーのように、ゴムのように変形し、熱膨張差による応力を緩和するものが好適に使用される。 Thus, a filler such as SiO 2 50% by volume or more in the resin, the thermal expansion coefficient and an epoxy resin having a 9~13ppm / ℃ approximate to the semiconductor element, as elastomers, modified as rubber, which relax the stress due to thermal expansion difference is preferably used.

【0021】また、電気素子4が形成された樹脂フィルム5として、他の例としては、図3に示すような容量素子が形成されたものが挙げられる。 Further, as the resin film 5 which electric element 4 is formed, as another example, it includes those capacitive element as shown in FIG. 3 was formed. 図3(a)によれば、樹脂フィルム自体を高誘電率の粒子を混合して成形した高誘電率の樹脂フィルム10によって形成し、その両面に銅などの金属箔を電極11、11として被着形成し、電極11、11間にて容量を発生できるもの、あるいは図3(b)のように、樹脂フィルム12の表面に銅などの金属箔を電極13として形成し、その表面に誘電体薄膜14を形成し、さらに誘電体薄膜14表面に電極13を形成し、電極13、13間にて容量を発生できるもの等が挙げられる。 According to FIG. 3 (a), the resin film itself is formed of a resin film 10 of high dielectric constant which is formed by mixing particles of high dielectric constant, the metal foil such as copper on both surfaces as electrodes 11, 11 wear form, those capable of generating capacity in between electrodes 11 and 11, or as shown in FIG. 3 (b), forming a metal foil such as copper on the surface of the resin film 12 as an electrode 13, a dielectric on the surface thereof the thin film 14 is formed, further an electrode 13 is formed on the dielectric thin film 14 surface, such as those capable of generating capacity in between the electrodes 13 and 13 and the like.

【0022】図1によれば、これらの電気素子4を形成した樹脂フィルム5を絶縁層3a、3bの配線回路層2 According to FIG. 1, a resin film 5 formed of these electric elements 4 insulating layer 3a, 3b of the wiring circuit layer 2
やビアホール導体2と電気素子4の電極や端子と電気的に接続される箇所に配置し、3〜80kg/cm 2の圧力を印加することにより積層一体化することができる。 Place the locations to be connected and via conductors 2 and electrically to the electrode and the terminal of the electric element 4, can be laminated together by applying a pressure of 3~80kg / cm 2.
そして、上記の積層物を絶縁層3a〜3d中の熱硬化性樹脂が完全に硬化可能な温度に加熱し、これらの絶縁層を一括して熱硬化することにより、電気素子4を内蔵した多層配線基板を作製することができる。 The multilayer in which the laminate is thermosetting resin in the insulating layer 3a~3d heated to fully curable temperatures, by thermal curing at once these insulating layers, a built-in electric element 4 it can be manufactured wiring board.

【0023】本発明によれば、上記の製造過程において、多層配線基板内に内蔵される電気素子4が形成された樹脂フィルム5を、絶縁層3中の熱硬化性樹脂の硬化温度よりもガラス転移点の高い樹脂によって構成することが必要である。 According to the present invention, in the above production process, the resin film 5 which electric element 4 is formed that is built into the multilayer wiring board, a glass than the curing temperature of the thermosetting resin in the insulating layer 3 it is necessary to construct the high transition temperature resin. 樹脂フィルム5のガラス転移点が熱硬化性樹脂の硬化温度よりも低いと、前記製造過程における完全硬化時に、電気素子4が形成された樹脂フィルム5が変形してしまい、電気素子4との配線が断線してしまったり、多層配線基板との電気的な接続不良を来す虞がある。 When the glass transition point of the resin film 5 is lower than the curing temperature of the thermosetting resin, the time completely cured in the manufacturing process, the electric element 4 will be deformed resin film 5 is formed, the wiring between the electric element 4 there or accidentally disconnected, there is a possibility of causing an electrical connection failure between the multilayer wiring board. より具体的には、ガラス転移点が、熱硬化温度よりも10℃以上、特に20℃以上高いことが望まれる。 More specifically, the glass transition point, heat curing temperature 10 ° C. or higher than, greater it is desirable in particular 20 ° C. or higher.

【0024】このような耐熱性を有する樹脂フィルムとしては、前記樹脂フィルムが、イミド樹脂、アラミド樹脂、フッ素樹脂、ポリエチレンテレフタレート樹脂、ポリエチレンナフタレート樹脂、ポリオレフィン樹脂のうちの1種から選択することが望ましい。 [0024] As the resin films having such heat resistance, the resin film, an imide resin, an aramid resin, a fluorine resin, polyethylene terephthalate resin, polyethylene naphthalate resin, be selected from one of the polyolefin resin desirable.

【0025】上記の製造方法において、熱硬化性樹脂を含有する未硬化状態の絶縁層は、熱硬化性有機樹脂、または熱硬化性有機樹脂とフィラーなどの組成物を混練機や3本ロールなどの手段によって十分に混合し、これを圧延法、押し出し法、射出法、ドクターブレード法などによってシート状に成形することにより作製され、所望により熱処理して熱硬化性樹脂を半硬化させたものが使用される。 [0025] In the above manufacturing method, an insulating layer of uncured contains a thermosetting resin, a thermosetting organic resin, or a composition such as a thermosetting organic resin and a filler such as kneader or three-roll mixed thoroughly by means rolling method this extrusion method, an injection method, be made by molding into a sheet by a doctor blade method, those obtained by semi-curing the desired heat treated thermosetting resin used. 半硬化には、樹脂が完全硬化するに十分な温度よりもやや低い温度に加熱すればよい。 The semi-cured, it may be heated to a temperature slightly lower than a temperature sufficient resin is completely cured.

【0026】なお、絶縁層を形成する熱硬化性樹脂としては、絶縁材料としての電気的特性、耐熱性、および機械的強度を有する熱硬化性樹脂であれば特に限定されるものでなく、例えば、アラミド樹脂、フェノール樹脂、 [0026] As the thermosetting resin forming the insulating layer, the electrical properties of the insulating material, heat resistance, and not limited in particular as long as the thermosetting resin having mechanical strength, e.g. , aramid resin, phenol resin,
エポキシ樹脂、イミド樹脂、フッ素樹脂、フェニレンエーテル樹脂、ビスマイレイドトリアジン樹脂、ユリア樹脂、メラミン樹脂、シリコーン樹脂、ウレタン樹脂、不飽和ポリエステル樹脂、アリル樹脂等が、単独または組み合わせて使用できる。 Epoxy resin, imide resin, fluororesin, polyphenylene ether resin, bis Mai laid triazine resins, urea resins, melamine resins, silicone resins, urethane resins, unsaturated polyester resins, allyl resins, etc. can be used singly or in combination.

【0027】また、上記の絶縁シート3中には、絶縁基板あるいは配線基板全体の強度を高めるために、有機樹脂に対してフィラーを複合化させることもできる。 Further, in the insulating sheet 3 described above, in order to increase the strength of the entire insulating substrate or wiring board, fillers may also be conjugated to an organic resin. 有機樹脂と複合化されるフィラーとしては、SiO 2 、Al The filler with an organic resin is complexed, SiO 2, Al
23 、TiO 2 、AlN、SiC、BaTiO 3等の無機質フィラーが好適に用いられる。 2 O 3, TiO 2, AlN , SiC, inorganic fillers such as BaTiO 3 is preferably used. また、ガラスやアラミド樹脂からなる不織布、織布などに上記樹脂を含浸させて用いてもよい。 It may also be used in non-woven fabric made of glass or aramid resin, such as woven fabric impregnated with the resin.

【0028】なお、有機樹脂とフィラーとは、体積比率で15:85〜70:30の比率で複合化されるのが適当である。 [0028] Note that the organic resin and a filler, 15 in volume ratio: 85 to 70: it is suitable for being complexed with 30 ratio of.

【0029】また、絶縁層に対するスルーホール(ビアホール)および空隙部の形成は、ドリル、パンチング、 Further, formation of the through-hole (via hole) and the gap section for insulating layer, drills, punching,
サンドブラスト、あるいは炭酸ガスレーザ、YAGレーザ、及びエキシマレーザ等の照射による加工など公知の方法が採用される。 Sandblasting or carbon dioxide gas laser,, YAG laser, and a known method such as processing by the irradiation of an excimer laser or the like is employed. 特に、空隙部を形成する場合、絶縁層は、上記の種々の材質の中でもパンチング又はレーザーによる加工性の点から、エポキシ樹脂、イミド樹脂、 In particular, in the case of forming the void portion, the insulating layer is, among various materials of the above in terms of processability by punching or laser, epoxy resin, imide resin,
フェニレンエーテル樹脂と、シリカまたはアラミド不織布との混合物であることが最も望ましい。 A polyphenylene ether resin, and most preferably a mixture of silica or aramide nonwoven fabric.

【0030】一方、ビアホールに充填される金属ペーストは、銅粉末、銀粉末、銀被覆銅粉末、銅銀合金などの、平均粒径が0.5〜50μmの金属粉末を含む。 On the other hand, the metal paste filled in the via holes include copper powder, silver powder, silver-coated copper powder, such as copper-silver alloy, an average particle size of the metal powder 0.5 to 50 [mu] m. 金属粉末の平均粒径が0.5μmよりも小さいと、金属粉末同士の接触抵抗が増加してスルーホール導体の抵抗が高くなる傾向にあり、50μmを越えるとスルーホール導体の低抵抗化が難しくなる傾向にある。 If the average particle size of the metal powder is less than 0.5 [mu] m, the contact resistance of the metal powder particles is increased there is a tendency that the resistance is high in through-hole conductors, it is difficult to lower the resistance of the through-hole conductors exceeds 50μm there to tend.

【0031】また、導体ペーストは、前述したような金属粉末に対して、前述したような結合用有機樹脂や溶剤を添加混合して調製される。 Further, the conductive paste, the metal powder as described above, is prepared by adding and mixing a binding organic resins and solvents as described above. ペースト中に添加される溶剤としては、用いる結合用有機樹脂が溶解可能な溶剤であればよく、例えば、イソプロピルアルコール、テルピネオール、2−オクタノール、ブチルカルビトールアセテート等が用いられる。 The solvent added in the paste may be a solvent capable of bonding an organic resin is dissolved using, for example, isopropyl alcohol, terpineol, 2-octanol, butyl carbitol acetate or the like is used. また、エポキシ樹脂、トリアリルイソシアヌレート(TAIC)樹脂などの液状樹脂を用いた無溶剤で作製したペーストも良好に使用できる。 The epoxy resin, a paste made of solvent-free using a liquid resin, such as triallyl isocyanurate (TAIC) resin can be preferably used.

【0032】上記の導体ペースト中の結合用有機樹脂としては、前述した種々の絶縁シートを構成する有機樹脂の他、セルロースなども使用される。 [0032] bonding the organic resin in the above conductive paste, other organic resin constituting the various insulating sheet described above are also used, such as cellulose. この有機樹脂は、 The organic resin,
前記金属粉末同士を互いに接触させた状態で結合するとともに、金属粉末を絶縁シートに接着させる作用をなしている。 With bound being in contact with said metal powder particles to one another, and has a function of adhering the metal powder to the insulating sheet. この有機樹脂は、金属ペースト中において、 The organic resin is in a metal paste,
0.1乃至40体積%、特に0.3乃至30体積%の割合で含有されることが望ましい。 0.1 to 40 vol%, it is desirable that the content at a rate of preferably 0.3 to 30 vol%. これは、樹脂量が0. This is, the amount of resin is 0.
1体積%よりも少ないと、金属粉末同士を強固に結合することが難しく、低抵抗金属を絶縁層に強固に接着させることが困難となり、逆に40体積%を越えると、金属粉末間に樹脂が介在することになり粉末同士を十分に接触させることが難しくなり、スルーホール導体の抵抗が大きくなるためである。 When the amount is less than 1 vol%, it is difficult to strongly bond the metal powder particles, it is difficult to firmly bond the low-resistance metal in the insulating layer, exceeds 40 volume percent Conversely, the resin between the metal powder There it becomes difficult to sufficiently contact the powder particles will be interposed, because the resistance of the through-hole conductors increases.

【0033】配線回路層としては、銅、アルミニウム、 [0033] As the wiring circuit layer, copper, aluminum,
金、銀の群から選ばれる少なくとも1種、または2種以上の合金からなることが望ましく、特に、銅、または銅を含む合金が最も望ましい。 Gold, at least one selected from the group consisting of silver, or desirably composed of two or more alloys, in particular, an alloy containing copper or copper, is most preferable. また、配線層の低抵抗化のために、前記低抵抗金属よりも低融点の金属、例えば、 Further, in order to reduce the resistance of the wiring layers, than said low resistance metal having a low melting point metal, for example,
半田、錫などの低融点金属を導体組成物中の金属成分中に2〜20重量%の割合で含んでもよい。 Solder may contain a proportion of 2 to 20 wt% in the metal components of the low-melting-point metal conductors composition such as a tin.

【0034】配線回路層と絶縁層との密着強度を高める上では、絶縁層の配線回路層の形成箇所および/または転写フィルム表面の配線回路層表面の表面を0.1μm [0034] In order to enhance the adhesion strength between the wiring circuit layer and the insulating layer, 0.1 [mu] m to the surface of the wiring circuit layer surface of the forming portion and / or the transfer film surface of the wiring circuit layer of the insulating layer
以上、特に0.3μm〜3μm、最適には0.3〜1. Or more, and particularly 0.3μm~3μm, optimally 0.3 to 1.
5μmに粗面加工することが望ましい。 It is desirable to roughening to 5 [mu] m. また、ビアホール導体の両端を金属箔からなる配線回路層によって封止する上では、配線回路層4の厚みは、5〜40μmが適当である。 Further, on the both ends of the via-hole conductor is sealed by a wiring circuit layer made of a metal foil, the thickness of the wiring circuit layers 4, 5 to 40 m is appropriate.

【0035】このようにして、本発明によれば、従来の積層方法を用いて、複数の絶縁層が積層されてなる多層配線基板内に、テープキャリアパッケージ等の電気素子が形成された樹脂フィルムを実装収納することができ、 [0035] Thus, according to the present invention, using a conventional lamination method, a plurality of insulating layers are laminated multi-layer wiring substrate, a resin film electrical element, such as a tape carrier package is formed can be implemented housing the,
これにより多層配線基板の高密度化を可能とするとともに、多層配線基板の小型化を図ることができる。 Thus while allowing densification of a multilayer wiring board, it is possible to reduce the size of the multilayer wiring board.

【0036】 [0036]

【実施例】実施例1 (1) ガラス繊維の織布に対してエポキシ樹脂を50 EXAMPLE 1 (1) 50 epoxy resin relative to woven glass fiber
体積%の割合で含浸したFR5規格相当、厚さ100μ FR5 standard corresponds impregnated at a rate of volume%, thickness 100μ
mのプリプレグAに、炭酸ガスレーザで直径0.1mm The prepreg A of m, diameter 0.1mm in a carbon dioxide gas laser
のビアホールを形成し、そのホール内に銀をメッキした銅粉末を含む銅と、錫を主成分とし、少量の銀を含有する粉末に樹脂分を適量添加して作製したペーストを充填してビアホール導体を形成した。 A via hole is formed of a copper containing copper powder plated with silver in its hole, tin as a main component, is filled with a small amount of silver-containing powdered resin component was prepared by adding an appropriate amount pastes holes to form a conductor. また、このプリプレグに金型を用いて半導体素子や電子部品を設置するための12mm×12mmの大きさの空隙部を形成した。 Further, to form a void portion of the size of 12 mm × 12 mm for mounting the semiconductor devices and electronic components using a mold the prepreg.

【0037】(2) 一方、プリプレグAと同様な材質からなるプリプレグBにレーザでビアホールを形成し、 [0037] (2) On the other hand, to form a via hole with a laser prepreg B consisting of same material and the prepreg A,
そのホール内に銀をメッキした銅粉末を含む銅ペーストを充填してビアホール導体を形成した。 To form a via hole conductor by filling a copper paste containing copper powder plated with silver in its hole.

【0038】(3)また、一方、ポリエチレンテレフタレート(PET)樹脂からなる転写シートの表面に接着剤を塗布し、厚さ12μm、表面粗さ0.8μmの銅箔を一面に接着した。 [0038] (3) Further, whereas, an adhesive is applied to the surface of the transfer sheet made of polyethylene terephthalate (PET) resin was adhered thickness 12 [mu] m, a copper foil surface roughness 0.8μm on one side. そして、フォトレジスト(ドライフィルム)を塗布し露光現像を行った後、これを塩化第二鉄溶液中に浸漬して非パターン部をエッチング除去して配線回路層を形成した。 Then, after the coating is exposed and developed photoresist (dry film) was formed the wiring circuit layers which the pattern portion is immersed in a ferric chloride solution is removed by etching. なお、作製した配線回路層は、 The wiring circuit layer prepared is
線幅が20μm、配線と配線との間隔が20μmの微細なパターンである。 Line width 20 [mu] m, distance between the wiring and the wiring is a fine pattern of 20 [mu] m.

【0039】(4)そして、(1)で作製したプリプレグAに対して、(3)で作製された配線回路層が形成された転写シートを位置決めして50kg/cm 2の圧力を加えて圧着した後、転写フィルムを剥離して、テープキャリアパッケージと接続される配線回路層をプリプレグAに転写した。 [0039] (4) Then, crimping applies pressure against the prepreg A was prepared, (3) a transfer sheet fabricated wiring circuit layer is formed by positioning at 50 kg / cm 2 (1) after, by peeling off the transfer film, the wiring circuit layer to be connected to the tape carrier package has been transferred to the prepreg a.

【0040】(5)その後、(4)における空隙部に対して半導体素子が収納され、且つプリプレグA表面の配線回路層とテープキャリアパッケージのランドとを位置合わせして設置した。 [0040] (5) Then, (4) a semiconductor element is accommodated with respect to the gap portion of, and placed in and aligned with the lands of the wiring circuit layer and the tape carrier package of the prepreg A surface.

【0041】なお、用いたテープキャリアパッケージは、図2に示すように、ポリイミド樹脂からなり、ガラス転移点が450℃である厚さ32μmの樹脂フィルム5に厚さ18μmの銅箔からなる配線回路層7が形成され、さらにその配線回路層7に半導体素子8が実装されたものを使用した。 [0041] Incidentally, a tape carrier package using, as shown in FIG. 2, made of a polyimide resin, a wiring circuit having a glass transition point is made of copper foil having a thickness of 18μm on the resin film 5 having a thickness of 32μm is 450 ° C. layer 7 is formed, the semiconductor device 8 to the wiring circuit layer 7 is used which is mounted further. なお、半導体素子8の周囲はエポキシ系樹脂9を塗布して封止した。 Incidentally, around the semiconductor element 8 is sealed by coating the epoxy resin 9.

【0042】(6)次に、(3)と同様にして作製した金属箔からなる配線回路層を形成した転写シートによって、(2)で作製したプリプレグBの表面に配線回路層を転写した。 [0042] (6) Next, the transfer sheet to form a wiring circuit layer made of a metal foil was produced in the same manner as (3) to transfer the wiring circuit layer on the surface of the prepreg B prepared in (2).

【0043】(7)空隙部にテープキャリアパッケージが収納実装されたプリプレグAを中心に、その上下面に(6)のようにして配線回路層を形成したプリプレグを上下各2層づつ積層し10kg/cm 2の圧力で圧着し仮積層した。 [0043] (7) around a prepreg A tape carrier package is accommodated mounted in the gap portion, and the to form prepreg laminated upper and lower two layers at a time to the wiring circuit layer as (6) in its upper and lower surfaces 10kg / crimped at a pressure of cm 2 was tentatively laminated.

【0044】(8)(7)によって作製した積層体を、 [0044] The laminate was produced by (8) (7),
180℃で1時間加熱して一括硬化させてテープキャリアパッケージを内蔵した多層配線基板を作製した。 Was heated for 1 hour at 180 ° C. by simultaneously cured to produce a multilayer wiring board with a built-in tape carrier package.

【0045】得られた多層配線基板に対して、断面における配線回路層やビアホール導体の形成付近を観察した結果、テープキャリアパッケージIC素子と配線回路層、ビアホール導体と配線回路層とは良好な接続状態であり、各配線間の導通テストを行った結果、配線の断線も認められなかった。 [0045] the obtained multilayer wiring board, result of observation of the vicinity of the formation of the wiring circuit layers and via hole conductors in the cross section, good connection to the tape carrier package IC element wiring circuit layer, and the via-hole conductor and the wiring circuit layer a state, as a result of the continuity test between the wires, was not observed disconnection of the wiring. また、IC素子の動作においても何ら問題はなかった。 In addition, there was no any problem in the operation of the IC element. 得られた多層配線基板を湿度85 Humidity The resulting multi-layer wiring board 85
%、温度85℃の高温多湿雰囲気に100時間放置したが、目視で判別できる程度の劣化は生じていなかった。 %, It was allowed to stand for 100 hours in hot and humid atmosphere at 85 ° C., to the extent that can be distinguished visually deterioration did not occur.
また、比較として、テープキャリアパッケージとして、 For comparison, as a tape carrier package,
エポキシ樹脂からなる(ガラス転移点150℃)からなる厚さ32μmの樹脂フィルムに厚さ18μmの銅箔からなる配線回路層が形成され、さらにその配線回路層に半導体素子が実装されたものを使用して、上記と全く同様にして素子内蔵多層配線基板を作製し、同様の評価を行った結果、半導体素子と配線回路相間で断線が認められた。 An epoxy resin wiring circuit layer made of copper foil having a thickness of 18μm to a resin film having a thickness of 32μm consisting of (glass transition point 0.99 ° C.) is formed, further use what semiconductor element mounted on the wiring circuit layer to, to produce a device built multilayer wiring board in the same manner as described above, results of similar evaluation disconnection was observed between the semiconductor element wiring circuit phase.

【0046】実施例2 (1)ガラスクロスにPPE(ポリフェニレンエーテル)樹脂を含浸させた厚さ150μmの半硬化状態の絶縁層Aに、炭酸ガスレーザで直径0.1mmのビアホールを形成し、そのホール内に銀をメッキした銅粉末と錫を主成分とする粉末にTAIC樹脂を混合して作製した銅ペーストを充填してビアホール導体を形成した。 The insulating layer A in a semi-cured state of Examples 2 (1) thickness of 150μm impregnated with PPE (polyphenylene ether) resin in glass cloth, to form a via hole having a diameter of 0.1mm at a carbon dioxide gas laser, the holes to form a via-hole conductors are silver filled with plated copper powder and tin copper paste prepared by mixing the powder into TAIC resin composed mainly of the within. 一方、転写フイルムの表面に銅箔を接着した後、フォトレジスト(ドライフィルム)を塗布し露光現像を行った後、これを塩化第二鉄溶液中に浸漬して非パターン部をエッチング除去して配線回路層を形成し、この配線回路層を絶縁シートAに位置合わせして積層し、100kg Meanwhile, after bonding the copper foil on the surface of the transfer film, after the coating is exposed and developed photoresist (dry film), which was immersed in a solution of ferric chloride in a non-pattern portion is removed by etching forming a wiring circuit layer, and laminating the wiring circuit layer to align the insulating sheet a, 100 kg
/cm 2の圧力で圧着して転写フィルムを剥がし配線回路層を絶縁層Aに転写させた。 / And pressed at a pressure of cm 2 of the wiring circuit layers peeled transfer film was transferred to the insulating layer A.

【0047】(2)次に、高誘電体粉末を混合したポリイミドフィルム(ガラス転移点500℃)の両面に銅をメッキして作製したフィルムを所定形状にカットし、さらに銅をエッチングして容量を調整して、フィルム状コンデンサを作製した。 [0047] (2) Next, a film produced by plating copper on both surfaces of a polyimide film obtained by mixing a high dielectric constant powder (glass transition point 500 ° C.) was cut into a predetermined shape, volume and further etching the copper adjust to produce a film-shaped capacitor.

【0048】(3)(2)において作製したフィルム状コンデンサを絶縁層Aの所定箇所に設置した。 [0048] (3) a film-shaped capacitor produced was placed in a predetermined portion of the insulating layer A (2).

【0049】(4)その後、フィルム状コンデンサを設置した絶縁シートAの表面に、(1)と同様にしてビアホール導体および配線回路層を形成した絶縁層Bおよび絶縁層Cを順次を重ね合わせ、30kg/cm 2の圧力で積層圧着した。 [0049] (4) Thereafter, the surface of the insulating sheet A was placed film-shaped capacitor, sequentially superimposed insulating layers B and the insulating layer C was formed via hole conductor and the wiring circuit layer in the same manner as in (1), It was laminated crimped at a pressure of 30kg / cm 2.

【0050】(5)そして、絶縁シートA、B、Cの積層物を35kg/cm 2の圧力を印加しながら195℃ [0050] (5) The insulating sheet A, B, applied while 195 ° C. The pressure of 35 kg / cm 2 a stack of C
に加熱して完全硬化させて容量素子を内蔵した多層配線基板を作製した。 And heated to be completely hardened to produce a multilayer wiring board with a built-in capacitor element.

【0051】得られた多層配線基板に対して、断面における配線回路層やビアホール導体の形成付近を観察した結果、容量素子と配線回路層、ビアホール導体と配線回路層とは良好な接続状態であり、各配線間の導通テストを行った結果、配線の断線も認められなかった。 [0051] the obtained multilayer wiring board, result of observation of the vicinity of the formation of the wiring circuit layers and via hole conductors in the cross section, capacitive element and the wiring circuit layer, and the via-hole conductor and the wiring circuit layer has a good connection state , as a result of the continuity test between the wires, it was not observed disconnection of the wiring. また、 Also,
容量素子においても何ら問題なく、所定の容量を得ることができた。 Without any problems even in the capacitive element, it was possible to obtain a predetermined capacitance. 得られた多層配線基板を湿度85%、温度85℃の高温多湿雰囲気に100時間放置したが目視で判別できる程度の変化は生じていなかった。 The resulting 85% humidity a multilayer wiring board, a change in degree but was left for 100 hours in hot and humid atmosphere at 85 ° C. which can be determined by visual inspection did not occur.

【0052】また、比較のため、フィルム状コンデンサとして、エポキシ樹脂フィルム(ガラス転移点150 [0052] For comparison, a film-shaped capacitor, epoxy resin film (glass transition point 150
℃)の両面に銅をメッキして作製したものを使用し、上記と同様に容量素子内蔵多層配線基板を作製したところ、フィルム状コンデンサに変形が見られ、容量素子の静電容量が大きく変化した。 ° C.) copper using a disk produced by plating the both surfaces of, were manufactured capacitive element built multilayer wiring substrate in the same manner as described above, observed variations in the film-shaped capacitor, the capacitance of the capacitor is large changes did.

【0053】 [0053]

【発明の効果】以上詳述したとおり、本発明によれば、 As described above in detail, according to the present invention,
半導体素子や電子部品(コンデンサ素子、抵抗素子、フィルター素子、発振素子など)を搭載する多層配線基板において、耐熱性を有する樹脂フィルムに電気素子が形成されたテープキャリアパッケージやフィルム状電子部品を内部に実装収納することにより、半導体素子を3次元的に内蔵して基板の小型化と、素子の実装密度を高めることのでき、高密度、高精細、且つ多機能の配線基板を容易に形成できる。 Semiconductor devices and electronic components (capacitor element, a resistor element, a filter element, an oscillation and an element) inside the multilayer wiring board for mounting a tape carrier package or a film-shaped electronic component electrical elements are formed on a resin film having heat resistance by implementing housed, and downsizing of the substrate incorporates a semiconductor device in three dimensions, can of increasing the mounting density of devices, high density, high resolution, and a wiring board multifunctional readily formed .

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の素子内蔵多層配線基板の製造方法の一実施例を説明するための工程図である。 1 is a process diagram for explaining an embodiment of a manufacturing method of the head protection multilayer wiring board of the present invention.

【図2】電気素子が形成された樹脂フィルムの一例としてテープキャリアパッケージを説明するための平面図である。 2 is a plan view illustrating a tape carrier package as an example of a resin film electrical elements are formed.

【図3】電気素子が形成された樹脂フィルムの他の例として、容量素子が形成された樹脂フィルムの例を説明するための断面図である。 Other examples of Figure 3 resin film electrical element is formed is a cross-sectional view for explaining an example of a resin film capacitor element is formed.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 ビアホール導体 2,7 配線回路層 3,3a〜3d 絶縁層 4 電気素子 5,10,12 樹脂フィルム 6 空隙部 8 半導体素子 9 封止樹脂 11,13 電極 14 誘電体薄膜 1 via-hole conductors 2,7 wiring circuit layer 3,3a~3d insulating layer 4 electric element five, ten, twelve, the resin film 6 gap portion 8 semiconductor element 9 the sealing resin 11, 13 electrode 14 dielectric thin film

Claims (7)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】少なくとも熱硬化性樹脂を含む複数の絶縁層を積層してなる絶縁基板と、該絶縁基板の表面および内部に形成された配線回路層と、前記配線回路層間を電気的に接続するためのビアホール導体を具備する多層配線基板において、前記絶縁層間に、電気素子が搭載された樹脂フィルムを積層してなるとともに、前記樹脂フィルムのガラス転移点が、前記絶縁層の熱硬化温度よりも高いことを特徴とする素子内蔵多層配線基板。 Electrically connecting a plurality of insulating layers and the insulating substrate formed by laminating a wiring circuit layer formed on the surface and inside of the insulating substrate, the wiring circuit layers including claim 1, wherein at least a thermosetting resin in the multilayer wiring board having a via-hole conductors for, the insulating interlayer, with the electric element formed by laminating a resin film mounted, glass transition point of the resin film, than the thermal curing temperature of the insulating layer element built multilayer wiring board, characterized in that is also high.
  2. 【請求項2】前記電気素子が、半導体素子あるいは容量素子である請求項1記載の素子内容多層配線基板。 Wherein said electrical device is the element contents multilayer wiring board according to claim 1, wherein a semiconductor element or capacitive element.
  3. 【請求項3】前記樹脂フィルムが、イミド樹脂、アラミド樹脂、フッ素樹脂、、ポリエチレンテレフタレート樹脂、ポリエチレンナフタレート樹脂、ポリオレフィン樹脂のうちの1種からなる請求項1記載の素子内蔵多層配線基板。 Wherein the resin film, an imide resin, an aramid resin, a fluorine resin ,, polyethylene terephthalate resin, polyethylene naphthalate resin, the head protection multilayer wiring board according to claim 1, wherein comprising one of the polyolefin resin.
  4. 【請求項4】前記電気素子が、基板内に設けられた空隙部に収納されてなる請求項1記載の素子内蔵多層配線基板。 Wherein said electric element is an element built multilayer wiring board according to claim 1, wherein comprising housed in the gap portion provided in the substrate.
  5. 【請求項5】前記ビアホール導体が金属粉末の充填によって形成され、前記配線回路層が金属箔から形成されてなる請求項1記載の素子内蔵多層配線基板。 Wherein said via hole conductors are formed by filling the metal powder, the head protection multilayer wiring board according to claim 1, wherein said wiring circuit layer is formed from a metal foil.
  6. 【請求項6】ビアホール導体および/または配線回路層が形成された未硬化状態の熱硬化性樹脂を含む複数の絶縁層を作製した後、これらの絶縁層間に、前記絶縁層中の熱硬化性樹脂の硬化温度よりも高いガラス転移点を有し、その表面に電気素子を搭載してなる樹脂フィルムを積層して一体化した後、該積層物を前記熱硬化性樹脂の硬化温度に加熱して、一括硬化することを特徴とする素子内蔵多層配線基板の製造方法。 6. After producing a plurality of insulating layers including a via-hole conductors and / or thermosetting resin in an uncured state in which the wiring circuit layer is formed, in these insulating layers, thermosetting of the insulating layer It has a high glass transition temperature than the curing temperature of the resin and heated after integrally laminating a resin film obtained by mounting the electrical device on the surface thereof, the laminated material to the curing temperature of the thermosetting resin Te, the element built-in multilayer wiring board manufacturing method characterized by bulk curing.
  7. 【請求項7】前記ビアホール導体が、金属粉末を含むペーストを充填することによって形成され、前記配線回路層が金属箔から形成されてなる請求項6記載の素子内蔵多層配線基板の製造方法。 Wherein said via hole conductors are formed by filling a paste containing a metal powder, a manufacturing method of the head protection multilayer wiring board of the wiring circuit layer is formed from a metal foil according to claim 6, wherein.
JP11821498A 1998-04-28 1998-04-28 Manufacturing method of the head protection multilayer wiring board Expired - Lifetime JP3236818B2 (en)

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