JP2002270991A - Printed wiring board and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board where loop inductance can be reduced and to provide a manufacturing method for the printed wring board. SOLUTION: For arranging a chip capacitor 20 in the printed wiring board 10, the distance between an IC chip 90 and the chip capacitor 20 becomes short and the loop inductance can be reduced. Since conductive paste 26 is applied to surfaces of electrodes 21 and 22 formed by metallization, connection resistance on the surfaces of the electrodes 21 and 22 can be reduced, and projecting and recessing parts on the surfaces are eliminated. Thus, an adhesion property with a conductive adhesive 34 can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board on which electronic components such as IC chips are mounted, and more particularly to a printed wiring board having a built-in capacitor.

[0002]

2. Description of the Related Art Usually, inside a computer, a wiring distance between a power supply and an IC chip is long, and a loop inductance of this wiring portion is very large.
For this reason, the fluctuation of the IC drive voltage during the high-speed operation increases, which may cause the IC to malfunction. It is also difficult to stabilize the power supply voltage. For this reason, a capacitor is mounted on the surface of the printed wiring board to assist in power supply.

That is, the loop inductance that causes voltage fluctuation is generated from the power supply shown in FIG.
Power supply terminal 27 of IC chip 270
It depends on the wiring length up to 2P and the wiring length from the ground terminal 272E of the IC chip 270 to the power supply from the power supply via the ground wire in the printed wiring board 300. Further, the loop inductance can be reduced by reducing the distance between the wirings in which the current flows in the opposite direction, for example, the distance between the power supply line and the ground line. For this reason, as shown in FIG. 17B, by mounting a chip capacitor 298 on the printed wiring board 300, the printed wiring board 300 connecting the IC chip 270 and the chip capacitor 292 serving as a power supply source.
Shorten the wiring length between the power line and the ground line inside
It has been practiced to reduce the loop inductance by reducing the wiring interval.

[0004]

However, the magnitude of the voltage drop that causes the fluctuation of the IC driving voltage depends on the frequency. Therefore, as the driving frequency of the IC chip increases, the loop inductance cannot be reduced even if the chip capacitor is mounted on the surface as described above with reference to FIG. It became difficult to control.

For this reason, the present inventor has an idea of accommodating a chip capacitor in a printed wiring board. As a technique for embedding a capacitor in a substrate, see Japanese Unexamined Patent Publication No.
6472, JP-A-7-263619, JP-A-10-
No. 256429, JP-A-11-45555, JP-A-1
1-112678 and JP-A-11-31868.

Japanese Patent Application Laid-Open No. Hei 6-326472 discloses a technique for embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, power supply noise is reduced, and a space for mounting a chip capacitor is not required, and the size of the insulating substrate can be reduced. In addition, Japanese Patent Application Laid-Open
No. 263619 discloses a technique for embedding a capacitor in a substrate made of ceramic, alumina, or the like. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.

[0007] However, the above-described technique cannot make the distance between the IC chip and the capacitor very short, and cannot reduce the inductance as required at present in a higher frequency region of the IC chip.
In particular, in a resin-made multilayer build-up wiring board, disconnection between a terminal of a chip capacitor and a via hole due to a difference in thermal expansion coefficient between a capacitor made of ceramic and a core substrate made of resin and an interlayer resin insulating layer. Peeling occurred between the chip capacitor and the interlayer resin insulation layer, cracks occurred in the interlayer resin insulation layer, and high reliability could not be achieved for a long period of time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board which can reduce loop inductance and has high reliability, and a method of manufacturing the same. is there.

[0009]

According to a first aspect of the present invention, there is provided a printed wiring board having a resin insulating layer and a conductive circuit laminated on a core substrate, wherein the core substrate has at least A connection layer formed of at least one insulating resin layer and a housing layer housing a capacitor in a counterbore portion, and a conductive paste is applied to the surface of the electrode formed by metallizing the capacitor. Technical features.

A circuit formed by a build-up method in which an interlayer resin insulating layer is provided on a core substrate, a via hole or a through hole is formed in the interlayer resin insulating layer, and a conductive circuit as a conductive layer is formed. I have. They include
Either a semi-additive method or a full-additive method can be used.

According to the first aspect, since the capacitor is arranged in the printed wiring board, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced. Further, the core substrate includes at least one or more connection layers and a housing layer for housing the capacitor. Since the capacitor is housed in the thick housing layer, the core substrate does not become thick, and the interlayer resin is formed on the core substrate. Even when the insulating layer and the conductive circuit are laminated, the printed wiring board does not become thick.

In addition, since the conductive paste is applied to the surface of the metallized electrode of the capacitor, the electrical connectivity of the metallized electrode having a high surface resistance can be improved. Also, the electrode made of metallized
There is unevenness on the surface, and even if a direct connection is made with a conductive adhesive, it cannot be completely adhered, but the conductive paste can eliminate the unevenness, enhance the adhesion, and reduce the connection resistance. . In addition, since the metallized electrode is in contact with the surrounding resin layer via the conductive paste, the generation of stress due to the difference in thermal expansion between the electrode and the resin layer is suppressed, and cracks and peeling of the resin layer are eliminated.

In the second aspect, since the metal layer is provided on the conductive paste of the electrode of the capacitor, it is possible to prevent the occurrence of migration at the electrode and further reduce the connection resistance. The metallized electrode has irregularities on the surface and cannot be completely adhered even if it is directly connected with a conductive adhesive.However, applying a conductive paste and further providing a metal layer can reduce irregularities. It can be completely eliminated, adhesion can be enhanced, and connection resistance can be reduced.

According to a third aspect, the surface of the capacitor is subjected to a roughening treatment. Thereby, the adhesion between the chip capacitor made of ceramic and the adhesive layer made of resin and the interlayer resin insulating layer is increased, and the adhesive layer and interlayer resin insulating layer are separated at the interface even when the heat cycle test is performed. Nothing.

According to a fourth aspect of the present invention, the surface of the capacitor is subjected to a wettability improving treatment such as a seal coupling or a resin coating. Thereby, the adhesion between the chip capacitor made of ceramic and the adhesive layer made of resin and the interlayer resin insulating layer is increased, and the adhesive layer and interlayer resin insulating layer are separated at the interface even when the heat cycle test is performed. Nothing.

It is desirable to fill the recess with a resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if a stress originating from the capacitor is generated, the stress can be reduced by the filled resin. The resin also has the effect of reducing adhesion and migration between the capacitor and the core substrate.

According to the fifth aspect, the housing layer is made of a resin substrate in which a core material is impregnated with a resin, so that the core substrate can have sufficient strength.

According to the present invention, the connection layer and the capacitor housed in the housing layer are connected via a conductive adhesive.
Thereby, electrical connection with the capacitor and adhesion between the capacitor and the connection layer are ensured. Solder (Sn / Pb, Sn / Ag, Sn / Sb, Sn / Ag /
Cu), a conductive paste, or a resin having both conductivity and adhesiveness, such as a resin impregnated with metal particles, can be used.

It is desirable to fill the gap between the conductive adhesive and the capacitor with a resin. This is because the behavior caused by the capacitor can be reduced and migration of the conductive adhesive can be prevented.

According to the seventh aspect, since a circuit connected to the conductive adhesive is provided between the connection layer and the housing layer, the connection to the capacitor can be reliably established via the circuit. Further, by arranging a circuit formed of a metal layer between the connection layer and the housing layer, it is possible to prevent the core substrate from warping.

According to the present invention, the external board (daughter board, motherboard) connected to the back side of the printed wiring board and the terminal of the capacitor are connected to the via hole provided in the connection layer and the through hole formed in the core board. Connected via. That is, since the through holes are formed in the encasing layer provided with the core material and which are difficult to process and the terminals of the capacitor are not directly connected to the external substrate, the connection reliability can be improved.

In the ninth aspect, a wiring for connecting the IC chip and the external substrate is provided between the capacitors, and the signal lines do not pass through the capacitors. No propagation delay occurs due to passage. By providing a capacitor for power supply, IC
Large power can be easily supplied to the chip. Further, noise of signal propagation of the printed wiring board can be reduced.

Further, by arranging the connection wiring,
Wiring can also be provided below the capacitor.
Therefore, the degree of freedom of wiring is increased, and higher density and smaller size can be achieved.

In the tenth aspect, a capacitor is provided on the surface in addition to the capacitor housed in the substrate. Since the capacitor is housed in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance is reduced, and power can be supplied instantaneously. Because a capacitor is provided, a large-capacity capacitor can be attached.
Large power can be easily supplied to the IC chip.

In the eleventh aspect, since the capacitance of the capacitor on the surface is larger than the capacitance of the capacitor in the inner layer,
There is no shortage of power supply in the high frequency range, and the desired IC
The operation of the chip is ensured.

In the twelfth aspect, since the inductance of the capacitor on the surface is equal to or larger than the inductance of the capacitor in the inner layer, there is no shortage of power supply in a high frequency region, and a desired operation of the IC chip is ensured.

According to a thirteenth aspect, a resin is filled between the counterbore portion of the core substrate and the capacitor, and the coefficient of thermal expansion of the resin is determined by
It is set smaller than the core substrate, that is, close to a capacitor made of ceramic. For this reason, in the heat cycle test, even if internal stress is generated due to a difference in the coefficient of thermal expansion between the core substrate and the capacitor, cracks, peeling, and the like hardly occur on the core substrate, and high reliability can be achieved. Further, occurrence of migration can be prevented.

According to the fourteenth aspect, since a chip capacitor having an electrode formed inside the outer edge is used, a large external electrode can be obtained even when conduction is established through a via hole, and the allowable range of alignment is widened. Disappears.

According to the fifteenth aspect, since a capacitor having electrodes formed in a matrix is used, it is easy to accommodate a large chip capacitor in the core substrate. Therefore, the capacitance can be increased, so that an electrical problem can be solved. Further, even after various thermal histories, the printed wiring board is less likely to warp.

In the sixteenth aspect, a plurality of chip capacitors for multi-cavity may be connected to the capacitor. As a result, the capacitance can be adjusted appropriately, and I
The C chip can be operated.

According to a seventeenth aspect of the present invention, there is provided a method for manufacturing a printed wiring board, which comprises at least the following steps (a) to (c): (a) a resin board having a circuit pattern formed on one or both sides; Connecting a capacitor having a conductive paste applied on a metallized electrode to the circuit pattern via an adhesive material; and (b) attaching a resin substrate having a cavity for accommodating the capacitor to the resin plate. Forming a core substrate; and (c) forming an opening to the electrode of the capacitor in the resin plate to form a via hole.

According to the method of manufacturing a printed wiring board of the present invention, the chip capacitor can be accommodated in the core substrate, and a printed wiring board with reduced loop inductance can be provided.

Further, since the conductive paste is applied to the surface of the metallized electrode of the capacitor, the electrical connectivity of the metallized electrode having a high surface resistance can be improved. Also, the electrode made of metallized
There is unevenness on the surface, and even if a direct connection is made with a conductive adhesive, it cannot be completely adhered, but the conductive paste can eliminate the unevenness, enhance the adhesion, and reduce the connection resistance. . In addition, since the metallized electrode is in contact with the surrounding resin layer via the conductive paste, the generation of stress due to the difference in thermal expansion between the electrode and the resin layer is suppressed, and cracks and peeling of the resin layer are eliminated.

In the method for manufacturing a printed wiring board according to the eighteenth aspect, the resin substrate containing the capacitor and the resin plate are bonded to each other by applying pressure to both surfaces to form a core substrate. Can be laminated.

In the method for manufacturing a printed wiring board according to the nineteenth aspect, a through hole between the IC chip and the external substrate is provided between the capacitors, and the signal lines do not pass through the capacitors.
Reflection due to impedance discontinuity due to the high dielectric and propagation delay due to passage through the high dielectric do not occur. Providing a power supply capacitor makes it possible to easily supply large power to an IC chip.

In the present invention, the thermosetting resin sheet used as the interlayer resin insulating layer and the connection layer is made of a resin (hereinafter, referred to as a soluble particle) that is soluble in an acid or an oxidizing agent. , Hardly soluble resin). In addition, the "poorly soluble" used in the present invention
The term "soluble" refers to a substance having a relatively high dissolution rate when immersed in a solution containing the same acid or oxidizing agent for the same time as "soluble" for convenience, and a substance having a relatively low dissolution rate for convenience. Called "poorly soluble".

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and an acid or an oxidizing agent. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In the present invention, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

As the above-mentioned soluble resin particles, resin particles made of rubber can also be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

Examples of the soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

The soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin film can be ensured, and thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulating layer. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, a via opening can be formed in the interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin,
Examples thereof include a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolak type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolak type epoxy resin, alkylphenol novolak type epoxy resin, biphenol F type epoxy resin, and naphthalene type epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin film used in the present invention, it is preferable that the soluble particles are substantially uniformly dispersed in the hardly-soluble resin. A roughened surface having unevenness with a uniform roughness can be formed, and even when a via or a through hole is formed in a resin film, the adhesion of a metal layer of a conductive circuit formed thereon can be secured. Because. Alternatively, a resin film containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby, since the portions other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin film, the amount of the soluble particles dispersed in the poorly soluble resin is desirably 3 to 40% by weight based on the resin film. If the amount of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities. If the amount exceeds 40% by weight, the soluble particles may be dissolved using an acid or an oxidizing agent. In addition, there is a case where the resin film is melted to a deep portion of the resin film and the insulation between the conductor circuits via the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.

The resin film desirably contains a curing agent and other components in addition to the soluble particles and the hardly soluble resin. As the curing agent, for example,
Imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and microcapsules of these curing agents, and organic materials such as triphenylphosphine, tetraphenylphosphonium, and tetraphenylborate. Phosphine compounds and the like can be mentioned.

The content of the curing agent is desirably 0.05 to 10% by weight based on the resin film. 0.
If the amount is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidizing agent into the resin film is increased, and the insulating property of the resin film may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

Examples of the other components include fillers such as inorganic compounds or resins which do not affect the formation of a roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the printed wiring board can be improved by matching the thermal expansion coefficient, improving heat resistance and chemical resistance, and the like.

The resin film may contain a solvent. As the solvent, for example, acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Ethyl acetate, butyl acetate, cellosolve acetate, and aromatic hydrocarbons such as toluene and xylene. These may be used alone or in combination of two or more.

[0055]

Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a cross section of the printed wiring board 10, and FIG. 8 shows a state where the IC chip 90 is mounted on the printed wiring board 10 shown in FIG.

As shown in FIG. 7, the printed wiring board 10
The chip capacitor 20 includes a core substrate 30 that houses the chip capacitor 20, and an interlayer resin insulation layer 60 that forms the build-up layers 80A and 80B. Core substrate 30
Are a housing layer 31 for housing the capacitor 20 and a connection layer 40
Consists of Via holes 46 and conductor circuits 48 are formed in the connection layer 40, and via holes 66 and conductor circuits 68 are formed in the interlayer resin insulation layer 60. In the present embodiment, the build-up layer has one interlayer resin insulation layer 6.
However, the build-up layer may include a plurality of interlayer resin insulation layers.

As shown in FIG. 8, the upper build-up layer 8
Bumps 76 for connecting to pads 92S1, 92S2, 92P1, and 92P2 of IC chip 90 are formed in via hole 66 of 0A. On the other hand, pads 96S1, 96S2, 96P1, 96P2 of the daughter board 94 are provided in the via holes 66 of the lower buildup layer 80B.
A bump 76 is provided for connection to the substrate. A through hole 36 is formed in the core substrate 30.

As shown in FIG. 12, the chip capacitor 20 includes a first electrode 21 and a second electrode 22, and a dielectric 23 sandwiched between the first and second electrodes.
A plurality of first conductive films 24 connected to the first electrode 21 side and a plurality of second conductive films 25 connected to the second electrode 22 side are arranged facing each other. A conductive paste 26 covers the surfaces of the first electrode 21 and the second electrode 22.

Here, the first electrode 21 and the second electrode 22
Consists of metallization of Ni, Pb or Ag metal. The conductive paste 26 is made of a paste containing metal particles such as Cu, Ni or Ag. Here, the particle size of the metal particles is preferably 0.1 to 10 μm, particularly 1 to 5 μm.
Is optimal. As the conductive paste, metal particles,
An organic conductive paste to which a thermosetting resin such as an epoxy resin or a polyphenylene sulfide (PPS) resin is added is desirable. The thickness of the conductive paste 26 is 1 to 30.
μm is desirable. If the thickness is less than 1 μm, unevenness on the electrode surface cannot be eliminated, while if it exceeds 30 μm, the effect is not particularly improved. Here, a thickness of 5 to 20 μm is most desirable. Note that a paste containing two or more types of particles having different diameters can be used, and further, two or more types of different metal pastes can be coated.

In the first embodiment, since the conductive paste 26 is applied to the surfaces of the electrodes 21 and 22 made of metallized capacitor 20, the electrical connection between the electrodes 21 and 22 made of metallized and having high surface resistance is improved. can do. The electrodes 21 and 22 made of metallized
Even if the surface has irregularities and the direct connection is made with the conductive adhesive 34, it cannot be completely adhered. However, the irregularities can be eliminated by the conductive paste 26, and the adhesiveness can be improved.
Connection resistance can be reduced. In addition, the electrodes 21 and 22 made of metallization are used as the resin filler 32 and the core substrate 3.
0 through the conductive paste 26, the electrode 2
The generation of stress due to the difference in thermal expansion between the first and second resin fillers 32 and the core substrate 30 is suppressed.
The occurrence of cracks in the core substrate 30 is eliminated.

The signal pad 92S2 of the IC chip 90 shown in FIG. 8 is connected to the signal of the daughter board 94 via the bump 76, the conductor circuit 68, the via hole 66, the through hole 36, the via hole 66, and the bump 76. Pad 9
6S2. On the other hand, the signal pads 92S1 of the IC chip 90 are connected to the bumps 76 and the via holes 66.
It is connected to the signal pad 96S1 of the daughter board 94 via the through hole 36, the via hole 66, and the bump 76.

Power supply pad 92P1 of IC chip 90
Is connected to the first electrode 21 of the chip capacitor 20 via the bump 76-via hole 66-conductor circuit 48-via hole 46. On the other hand, the power supply pad 96P1 of the daughter board 94 is connected to the bump 76-via hole 66.
-Through hole 36-Conductor circuit 48-Via hole 46
To the first electrode 21 of the chip capacitor 20.

Power supply pad 92P2 of IC chip 90
Is connected to the second electrode 22 of the chip capacitor 20 via a bump 76-via hole 66-conductor circuit 48-via hole 46. On the other hand, the power supply pad 96P2 of the daughter board 94 is connected to the bump 76 and the via hole 66.
-Through hole 36-Conductor circuit 48-Via hole 46
Is connected to the second electrode 22 of the chip capacitor 20 via the.

In the printed wiring board 10 of this embodiment, I
Since the chip capacitor 20 is disposed immediately below the C chip 90, the distance between the IC chip and the capacitor is shortened, so that power can be instantaneously supplied to the IC chip. That is, the loop length that determines the loop inductance can be reduced.

Further, a through hole 36 is provided between the chip capacitors 20 so that a signal line does not pass through the chip capacitor 20. For this reason, it is possible to prevent reflection due to impedance discontinuity due to the high dielectric substance that occurs when passing through the capacitor, and propagation delay due to passage through the high dielectric substance.

The external board (daughter board) 94 connected to the back side of the printed wiring board and the first terminal 21 and the second terminal 22 of the capacitor 20 are connected to via holes provided in the connection layer 40 on the IC chip side. 46 and through a through hole 36 formed in the core substrate 30. That is, since a through hole is formed in the housing layer 31 having the core material and which is difficult to process, and the terminal of the capacitor is not directly connected to the external substrate, the connection reliability can be improved.

In this embodiment, as shown in FIG. 12, a roughened layer 23a is provided on the surface of a dielectric 23 made of ceramic of a chip capacitor 20. Therefore, the adhesion between the chip capacitor 20 made of ceramic and the adhesive layer 40 made of resin is high, and the adhesive layer 40 does not peel off at the interface even when the heat cycle test is performed. The roughened layer 23a can be formed by polishing the surface of the chip capacitor 20 after firing, or by performing a roughening process before firing.

In this embodiment, a resin filler 32 is interposed between the side surface of the cavity 31a of the core substrate 30 and the chip capacitor 20, as shown in FIG. Here, the coefficient of thermal expansion of the resin filler 32 is set to be smaller than that of the core substrate 30 and the adhesive layer 40, that is, close to the chip capacitor 20 made of ceramic. For this reason, in the heat cycle test, even if an internal stress is generated due to a difference in the coefficient of thermal expansion between the core substrate and the adhesive layer 40 and the chip capacitor 20, cracks, peeling, and the like hardly occur on the core substrate and the adhesive layer 40. , Can achieve high reliability. Further, occurrence of migration can be prevented.

Subsequently, a method of manufacturing the printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS. A connection layer, which is a resin layer forming the core substrate, is formed, and a circuit pattern made of a metal layer is formed on one surface thereof. Therefore, a resin film 40α having a metal film 41 laminated on one side is prepared (FIG. 1A). As the resin film 40α, a thermosetting resin such as epoxy, BT, polyimide, and olefin, or a mixture of a thermosetting resin and a thermoplastic resin can be used. Here, a film that does not include a core material to facilitate formation of through holes is desirable. This metal film 41 is pattern-etched to form a predetermined circuit pattern 42 (FIG. 1B). Next, the chip capacitor 20 is bonded to the circuit pattern 42 on the lower surface of the resin film 40α via the conductive adhesive 34 (FIG. 1).
(C)). Thereby, the electrical connection with the capacitor 20 and the adhesion between the capacitor 20 and the circuit pattern 42 are ensured. The conductive adhesive 34 is made of solder (Sn / Pb, Sn / Pb).
Sb, Sn / Ag, Sn / Ag / Cu), a conductive paste, or a resin having both conductivity and adhesiveness, such as resin impregnated with metal particles, can be used. It is better to fill the voids generated by the conductive adhesive and the capacitor with a resin.

On the other hand, an accommodation layer laminate 31α having a cavity 31a for accommodating a chip capacitor is prepared (FIG. 1C). The cavity 31a is formed by a counterbore. A laminate having a cavity can be formed by joining a prepreg having a through hole other than a counterbore and a prepreg having no through hole, or by injection molding. As the accommodation layer laminate 31α, a laminate formed by laminating prepregs in which a core material such as a glass cloth is impregnated with an epoxy resin can be used. Other than epoxy, B
Those generally used in printed wiring boards, such as those containing a reinforcing material such as T, phenolic resin or glass cloth, may be used. Note that a resin substrate having no core material such as a glass cloth can also be used. However, a substrate made of ceramic, AIN, or the like cannot be used as the core substrate. This is because the substrate has poor external formability, and may not be able to accommodate a capacitor, and may cause voids even when filled with resin. Since the melting point of the resin substrate is 300 ° C. or less, if a temperature exceeding 350 ° C. is applied, the resin substrate is melted, softened or carbonized.

Then, a resin film 40α on which the chip capacitor 20 is mounted, a resin laminate 30α for a core substrate having a capacitor accommodating portion, and another resin film 40α are laminated, and pressed from both sides to flatten the surface. (FIG. 1D). In the present embodiment, the capacitor 20
The housing layer 31 and the connection layer 40 that housed therein are bonded to each other by applying pressure to both surfaces to form the core substrate 30, so that the surface is flattened. Thereby, in a process described later, the interlayer resin insulating layer 60 and the conductor circuit 68 are provided so as to have high reliability.
Can be laminated. At this time, the gap between the capacitor 20 and the resin film 40α is filled with the resin that seeps out of the resin film 40α. here,
When the gap cannot be sufficiently filled, a filler 32α having a smaller coefficient of thermal expansion than the core substrate is disposed between the circuit patterns 42 on the resin film 40α side as shown in FIG. Filling as shown in FIG. 2 (D)
As shown in FIG. 2 (C), the filler 3
2α can be arranged and filled as shown in FIG. 2 (D).

Thereafter, by heating and curing, the core substrate 30 including the housing layer 31 for housing the chip capacitor 20 and the connection layer 40 is formed (FIG. 3A). It is preferable that the cavity 31a of the core substrate is filled with a resin filler 32 having a smaller coefficient of thermal expansion than that of the core substrate to improve airtightness. Also, here, the resin film 40α is laminated using a material without a metal layer, but a resin film (RCC) having a metal layer disposed on one side is laminated.
May be used. That is, a double-sided plate, a single-sided plate, a resin plate having no metal film, and a resin film can be used.

In the present embodiment, since the circuit pattern 42 connected to the conductive adhesive 34 is provided between the connection layer 40 forming the core substrate 30 and the encasing layer 31, the circuit pattern 42 is interposed therebetween. Thus, the connection to the capacitor 20 can be reliably obtained. In addition, by arranging the circuit pattern 42 made of a metal layer between the connection layer 40 and the housing layer 31, warpage of the core substrate 30 can be prevented.

Next, the connection layer 4 on the upper surface side is irradiated with a CO2 laser, a YAG laser, an excimer laser or a UV laser.
In FIG. 3, a non-through hole 43 serving as a via hole is formed (FIG. 3).
(B)). In some cases, an area mask having a through hole may be placed in correspondence with the position of the non-through hole to perform the area processing with a laser. Further, in the case where via holes having different sizes and diameters are formed, they may be formed by a mixed laser.

If necessary, the smear in the via hole is removed by a dry treatment such as a gas plasma treatment with oxygen or nitrogen, a corona treatment, or a treatment by immersion with an oxidizing agent such as permanganic acid. Is also good. Subsequently, the connection layer 40, the accommodation layer 31, and the connection layer 40
A through hole 33 for a through hole is formed in the core substrate 30 of 50 to 500 μm with a drill or a laser (FIG. 3C).

A metal film is formed in the surface layer of the connection layer 40 of the core substrate 30, the non-through holes 43 for via holes, and the through holes 33 for through holes. To this end, after applying a palladium catalyst to the surface of the connection layer 40, the core substrate 30 is immersed in an electroless plating solution to uniformly deposit an electroless copper plating film 44 (FIG. 4A). Here, electroless plating is used, but a metal layer of copper, nickel, or the like can be formed by sputtering. Sputtering is disadvantageous in cost, but has the advantage of improving the adhesion to the resin layer. In some cases, the electroless plating film may be formed after the formation by sputtering. This is because, depending on the resin, the catalyst application is not stable, and the formation of an electroless plating film provides more stable deposition of electrolytic plating. It is desirable that the metal film 44 be formed in a range of 0.1 to 3 mm.

Thereafter, a photosensitive dry film is stuck on the surface of the metal film 44, a mask is placed, exposure and development are performed, and a resist 51 having a predetermined pattern is formed. Then, the core substrate 30 is immersed in the electrolytic plating solution, and a current is passed through the electroless plating film 44 to deposit the electrolytic copper plating film 45 (FIG. 4B). Resist 50 and resist 51
Is removed with 5% KOH, the electroless plating film 44 under the resist 51 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and the via hole 46 and the conductive circuit 4 are formed in the connection layer 40.
8 to the through hole 33 of the core substrate 30.
6 (FIG. 4C).

A roughened layer is provided on the surface of the conductor layer of the conductor circuit 48, the via hole 46, and the through hole 36. The roughened layer is formed by an oxidation (blackening) -reduction treatment, an electroless plating film of an alloy made of Cu-Ni-P, or an etching treatment of an etching solution containing a cupric complex and an organic acid salt. The roughened layer has Ra (average roughness height) = 0.01 to
5 μm. Particularly desirable is a range of 0.5 to 3 μm. Although the roughened layer is formed here, it is also possible to directly fill the resin and attach a resin film as described later without forming the roughened layer.

Subsequently, the resin layer 3 is formed in the through hole 36.
8 is filled. As the resin layer, either a resin having no conductivity such as a resin such as an epoxy resin as a main component or a conductive resin containing a metal paste such as copper may be used. In this case, the thermosetting epoxy resin is filled with a material such as silica which is included for matching the coefficient of thermal expansion as a resin filler. After filling the through hole 36 with the resin 38,
The resin film 60α is attached (FIG. 5A). Note that a resin may be applied instead of attaching a resin film. After attaching the resin film 60α, the opening diameter 20 is formed in the insulating layer 60α by photo and laser.
A via hole 63 having a thickness of about 250 μm is formed and then thermally cured (FIG. 5B). Thereafter, a catalyst is applied to the core substrate, and the core substrate is immersed in the electroless plating to uniformly deposit an electroless plating film 64 having a thickness of 0.9 μm on the surface of the interlayer resin insulating layer 60. 70 (FIG. 5C).

Immersion in the electrolytic plating solution, and the electroless plating film 6
An electrolytic copper plating film 65 is formed on the portion where the resist 70 is not formed by passing a current through the substrate 4 (FIG. 6A). Resist 7
Then, the electroless plating film 64 under the plating resist is dissolved and removed, and the conductor circuit 68 including the electroless plating film 64 and the electrolytic copper plating film 65 and the via hole 6 are removed.
6 is obtained (FIG. 6B).

A roughened surface (not shown) was formed on the surfaces of the conductor circuit 68 and the via hole 66 by using an etching solution containing a second copper complex and an organic acid. In addition, Sn on the surface
Substitutions may be made.

A solder bump is formed on the above-mentioned printed wiring board. After applying a solder resist composition to both sides of the substrate and performing a drying process, a photomask film (not shown) on which a circular pattern (mask pattern) is drawn is placed in close contact with the substrate, and is exposed to ultraviolet light. And developing. Further, a heat treatment is further performed to form a solder resist layer (thickness: 20 μm) 72 having an opening 72a in a solder pad portion (including a via hole and its land portion) (FIG. 6C).

Then, the solder paste is filled into the openings 72a of the solder resist layer 72 (not shown). Thereafter, the solder filled in the opening 72a is reflowed at 200 ° C. to form a solder bump (solder body) 76 (see FIG. 7). In order to improve corrosion resistance, a metal layer such as Ni, Au, Ag, or Pd may be formed in the opening 72a by plating or sputtering.

Next, mounting of the IC chip on the printed wiring board and mounting on the daughter board will be described with reference to FIG. Solder pads 92S1, 9 of IC chip 90 are applied to solder bumps 76 of completed printed wiring board 10.
The IC chip 90 is mounted so that the 2S2, 92P1, and 92P2 correspond to each other, and the IC chip 90 is attached by performing reflow. Similarly, the pads 96S1 of the daughter board 94 are attached to the solder bumps 76 of the printed wiring board 10,
By reflowing 96S2, 96P1, 96P2,
The printed wiring board 10 is attached to the daughter board 94.

Next, a printed wiring board according to a first modification of the first embodiment of the present invention will be described with reference to FIG. The printed wiring board of the first modified example is the first modified example described above.
This is almost the same as the embodiment. However, in the printed wiring board of the first modified example, the conductive pins 84 are provided, and are formed so as to be connected to the daughter board via the conductive pins 84. In the embodiment described above with reference to FIG. 1A, the resin film 40α in which the metal film 41 is laminated on one side is used. However, in the first modified example, the resin film in which the metal film is laminated on both sides is used. The interlayer resin insulation layer 60 on the IC chip 90 side is manufactured. That is, the circuit pattern 42 is formed by pattern-etching the metal film on the upper surface. Further, using the opening 42a of the circuit pattern 42 as a conformal mask, a non-through hole 43 is formed by laser to form a via hole 46.

FIG. 12B shows a cross section of a chip capacitor 20 according to a first modification. In the first embodiment, the surface of the capacitor is subjected to a roughening treatment to improve the adhesiveness with the resin, but in a modified example, a polyimide film 23b is formed instead to improve the surface wettability. I have. Instead of the polyimide film, the surface of the capacitor may be subjected to a silane coupling treatment.

In the first modification, the conductive paste 2
6, a composite metal film 28 composed of an electroless copper plating film 28a and an electrolytic copper plating film 28b is formed. The thickness of the composite metal film 28 is desirably 0.1 to 10 μm.
５5 μm is optimal. Instead of a composite metal film, it is also possible to form a single-layer metal film.

In the first modification, the electrode 2 of the capacitor 20
Since the metal layer 28 is provided on the conductive pastes 1 and 22, the occurrence of migration at the electrodes 21 and 22 can be prevented, and the connection resistance can be further reduced. The electrodes 21 and 22 made of metallized
Even if the surface has irregularities and the direct connection is made with the conductive adhesive 34, it cannot be completely adhered. However, by applying the conductive paste 26 and further providing the metal layer 28, the irregularities are completely eliminated. This improves the adhesion and lowers the connection resistance.

Further, in the above-described first embodiment, only the chip capacitor 20 housed in the core substrate 30 is provided, but in the first modified example, a large-capacity chip capacitor 86 is mounted on the front and back surfaces. I have.

The IC chip instantaneously consumes large power and performs complicated arithmetic processing. Here, in order to supply a large power to the IC chip side, in the present embodiment, the chip capacitor 20 and the chip capacitor 8 for power supply are mounted on the printed wiring board.
6 is provided. The effect of this chip capacitor will be described with reference to FIG.

FIG. 13 shows the voltage supplied to the IC chip on the vertical axis and the time on the horizontal axis. Here, the two-dot chain line C
Indicates voltage fluctuation of a printed wiring board without a power supply capacitor. When the power supply capacitor is not provided, the voltage greatly decreases. A broken line A indicates a voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. Although the voltage does not drop much as compared with the two-dot chain line C, the rate-limiting power supply cannot be performed sufficiently because the loop length is long. That is, the voltage drops at the start of power supply. The two-dot chain line B indicates the voltage drop of the printed wiring board incorporating the chip capacitor described above with reference to FIG. Although the loop length has been shortened,
Since a large-capacity chip capacitor cannot be accommodated in the core substrate 30, the voltage fluctuates. here,
A solid line E indicates a voltage variation of the printed wiring board of the first modification in which the chip capacitor 20 in the core substrate described above with reference to FIG. 9 and the large-capacity chip capacitor 86 are mounted on the surface. By providing the chip capacitor 20 near the IC chip and the chip capacitor 86 having a large capacity (and a relatively large inductance), voltage fluctuation is minimized.

Next, a printed wiring board according to a second modification of the first embodiment of the present invention will be described with reference to FIG. The printed wiring board of the second modified example is almost the same as the above-described first embodiment. However, in the printed wiring board of the second modification, the first electrode 21 and the second electrode 22 of the chip capacitor 20 are directly connected to the power supply pads 92P1 and 92P2 of the IC chip 90 via the bumps 76. . In the second modification, the distance between the IC chip and the chip capacitor can be further reduced.

Next, a printed wiring board according to a third modification of the first embodiment of the present invention will be described with reference to FIG. The printed wiring board of the third modified example is substantially the same as the above-described first embodiment. However, in the printed wiring board of the third modification, the first pattern of the capacitor 20 is formed by the circuit pattern 42 provided between the housing layer 31 and the connection layer 40.
The electrode 21 and the second electrode 22 are directly connected to the through hole 36. In this third modification, the capacitor 20
The wiring length between the first electrode 21 and the second electrode 22 and the daughter board can be reduced.

Next, the configuration of the printed wiring board according to the second embodiment of the present invention will be described with reference to FIG. The configuration of the printed wiring board of the second embodiment is substantially the same as that of the above-described first embodiment. However, the core substrate 3
The chip capacitors 20 housed to 0 are different. Figure 1
4 shows a plan view of the chip capacitor. FIG.
(A) shows a chip capacitor for multi-piece cutting before cutting, and a dashed line in the drawing shows a cutting line. In the printed wiring board of the first embodiment described above, the first electrode 21 and the second electrode 22 are provided on the side edges of the chip capacitor as shown in the plan view of FIG. FIG. 14 (C)
Shows a chip capacitor for multi-cavity before cutting according to the second embodiment, and a dashed line in the drawing indicates a cutting line. In the printed wiring board of the second embodiment, FIG.
As shown in the plan view, a first electrode 21 and a second electrode 22 are provided inside the side edge of the chip capacitor. In addition,
A conductive paste is formed on the electrode as in the first embodiment, or a conductive paste and a composite metal layer are formed as in the first modification of the first embodiment.

In the printed wiring board of the second embodiment,
Since the chip capacitor 20 having the electrode formed inside the outer edge is used, a large-capacity chip capacitor can be used.

Next, a printed wiring board according to a first modification of the second embodiment will be described with reference to FIG. FIG.
Shows a plan view of the chip capacitor 20 housed in the core substrate of the printed wiring board according to the first modification. In the above-described first embodiment, a plurality of small-capacity chip capacitors are housed in the core substrate. In the first modification, a large-capacity large-format chip capacitor 20 is housed in the core substrate. Here, the chip capacitor 20 is connected to the first electrode 21.
, The second electrode 22, the dielectric 23, the first conductive film 24 connected to the first electrode 21, the second conductive film 25 connected to the second electrode 22, the first conductive film 24 and the first conductive film 24. 2 conductive film 25
And the connection electrodes 27 on the upper and lower surfaces of the chip capacitor not connected to the chip capacitor. The IC chip side and the daughter board side are connected via the electrodes 27.

In the printed wiring board of the first modified example, since the large-sized chip capacitor 20 is used, a large-capacity chip capacitor can be used. Further, since the large chip capacitor 20 is used, the printed wiring board does not warp even if the heat cycle is repeated. Note that a conductive paste is formed on the electrode as in the first embodiment, or a conductive paste and a composite metal layer are formed as in the first modification of the first embodiment.

A printed wiring board according to a second modification will be described with reference to FIG. FIG. 16A shows a chip capacitor before cutting for multi-cavity production, in which a dashed line indicates a normal cutting line, and FIG. 16B shows a plan view of the chip capacitor. . As shown in FIG. 16B, in the second modification, a plurality of (three in the example in the figure) multi-chip chip capacitors are connected and used in a large format.

In the second modification, a large-sized chip capacitor 20 is used, so that a large-capacity chip capacitor can be used. Further, since the large chip capacitor 20 is used, the printed wiring board does not warp even if the heat cycle is repeated. Note that a conductive paste is formed on the electrode as in the first embodiment, or a conductive paste and a composite metal layer are formed as in the first modification of the first embodiment.

In the above-described second embodiment, the chip capacitor is built in the printed wiring board. However, instead of the chip capacitor, it is also possible to use a plate-like capacitor in which a conductor film is provided on a ceramic plate. .

Here, with respect to the printed wiring board of the first embodiment, the chip capacitor 20 embedded in the core substrate is used.
And the inductance of the chip capacitor mounted on the back surface of the printed wiring board (the surface on the daughter board side) are shown. In case of single capacitor Embedded type 137pH Backside mounted type 287pH When 8 capacitors are connected in parallel Embedded type 60pH Backside mounted type 72pH As shown above, when using a single capacitor, it is connected in parallel to increase the capacity In addition, the inductance can be reduced by incorporating a chip capacitor.

Next, the result of the reliability test will be described. Here, the rate of change of the capacitance of one chip capacitor in the printed wiring board of the first embodiment was measured. Capacitance change rate (measuring frequency 100Hz) (measuring frequency 1kHz) Steam 168 hours: 0.3% 0.4% HAST 100 hours: -0.9% -0.9% TS 1000cycles: 1.1% 1.3%

In the Steam test, the humidity was set to 100% by applying steam. In the HAST test, the relative humidity was 100%,
It was left at an applied voltage of 1.3 V and a temperature of 121 ° C. for 100 hours. In the TS test, 30 minutes at -125 ° C and 30 minutes at 55 ° C
The test of standing for 1000 minutes was repeated 1000 times.

In the above reliability test, it was found that the same reliability as that of the existing capacitor surface mount type was achieved also in the printed wiring board having a built-in chip capacitor. As described above, in the TS test,
Due to the difference in the coefficient of thermal expansion between the capacitor 20 made of ceramic and the core substrate 30 made of resin and the adhesive layer 40, even if internal stress is generated, the chip capacitor 20 and the adhesive layer 4
It has been found that no peeling occurs between 0 and no cracks occur in the core substrate 30 and the adhesive layer 40, and high reliability can be achieved for a long period of time.

[0105]

According to the structure of the present invention, the electric characteristics caused by the inductance do not decrease. In addition, since the conductive paste is applied to the surface of the metallized electrode of the capacitor, the electrical connectivity of the metallized electrode having a high surface resistance can be improved. The metallized electrode has irregularities on the surface and cannot be completely adhered even if it is directly connected with a conductive adhesive.However, the irregularity can be eliminated by the conductive paste to improve the adhesion. , Connection resistance can be reduced. In addition, since the metallized electrode is in contact with the surrounding resin layer via the conductive paste, the generation of stress due to the difference in thermal expansion between the electrode and the resin layer is suppressed, and cracks and peeling of the resin layer are eliminated. Also, even when the capacitor is covered with copper, the occurrence of migration can be prevented.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a printed wiring board according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view of the printed wiring board according to the first embodiment.

FIG. 8 is a sectional view of the printed wiring board according to the first embodiment.

FIG. 9 is a cross-sectional view of a printed wiring board according to a first modification of the first embodiment.

FIG. 10 is a cross-sectional view of a printed wiring board according to a second modification of the first embodiment.

FIG. 11 is a sectional view of a printed wiring board according to a third modification of the first embodiment.

FIG. 12A is a cross-sectional view of a chip capacitor according to the first embodiment, and FIG. 12B is a cross-sectional view of a chip capacitor according to a first modification of the first embodiment.

FIG. 13 is a graph showing changes in supply voltage to an IC chip and time.

FIGS. 14A, 14B, 14C, and 14D are plan views of a chip capacitor of a printed wiring board according to a second embodiment.

FIG. 15 is a plan view of a chip capacitor of a printed wiring board according to a second embodiment.

FIG. 16 is a plan view of a chip capacitor of a printed wiring board according to a modification of the second embodiment.

FIGS. 17A and 17B are explanatory diagrams of a loop inductance of a printed wiring board according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Printed wiring board 20 Chip capacitor 21 1st electrode 22 2nd electrode 23 Dielectric 23a Roughened surface 23b Polyimide film 26 Conductive paste 28a Electroless copper plating film 28b Electrolytic copper plating film 28 Composite metal film 25 Housing layer 30 Core substrate 31 Housing Layer 31a Cavity 34 Conductive Adhesive 36 Through Hole 40 Connection Layer 42 Circuit Pattern 43 Non-through Hole 46 Via Hole 60 Interlayer Resin Insulating Layer 66 Via Hole 68 Conductor Circuit 84 Conductive Pin 90 IC Chip 94 Daughter Board

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 3/46 H05K 3/46 N H01L 23/12 BF Term (Reference) 5E314 AA24 AA27 BB06 FF05 FF08 FF21 GG05 GG19 5E319 AC02 BB20 CC03 CC70 CD29 GG11 5E336 AA04 AA08 AA12 AA16 BB03 BB16 BC26 BC34 CC37 CC53 CC55 GG11 GG16 5E346 AA02 AA12 CC04 CC08 CC09 CC13 CC32 CC37 CC39 CC41 CC42 FF07 FF10 HFF15 GG15 H

Claims (19)

[Claims] 1. A printed wiring board comprising a resin insulating layer and a conductive circuit laminated on a core substrate, wherein the core substrate comprises a connection layer formed of at least one insulating resin layer and a counterbore portion. And a housing layer that houses the capacitor, and the surface of the electrode formed by metallizing the capacitor,
A printed wiring board to which a conductive paste is applied. 2. The printed wiring board according to claim 1, wherein a metal layer is provided on the conductive paste of the electrodes of the capacitor. 3. The printed wiring board according to claim 1, wherein the surface of the capacitor is subjected to a roughening treatment. 4. The printed wiring board according to claim 1, wherein the surface of the capacitor is subjected to a surface wettability improving treatment. 5. The container according to claim 1, wherein the housing layer is formed of a resin substrate having a core material impregnated with a resin, and the connection layer is formed of a resin substrate having no core material. Printed wiring board. 6. The printed wiring board according to claim 1, wherein the connection layer and the capacitor are connected via a conductive adhesive. 7. The printed wiring board according to claim 6, wherein a circuit connected to the conductive adhesive is provided between the connection layer and the housing layer on the core substrate. 8. An I disposed on a front side of a printed wiring board.
The C chip and the terminals of the capacitor are connected via via holes provided in the connection layer, and the external substrate disposed on the back side of the printed wiring board and the terminals of the capacitor are connected to the via holes and The printed wiring board according to claim 6, wherein the printed wiring board is connected through a through hole formed in the core substrate. 9. The printed wiring according to claim 1, wherein a plurality of the capacitors are accommodated, and a wiring for connecting an IC chip and an external substrate is provided between the capacitors. Board. 10. The printed wiring board according to claim 1, wherein a capacitor is mounted on a surface of the printed wiring board. 11. The printed wiring board according to claim 10, wherein the capacitance of the chip capacitor on the surface is equal to or larger than the capacitance of the chip capacitor in the inner layer. 12. The printed wiring board according to claim 10, wherein the inductance of the chip capacitor on the front surface is equal to or greater than the inductance of the chip capacitor in the inner layer. 13. A resin having a smaller coefficient of thermal expansion than the core substrate is filled between the counterbore portion of the core substrate and the chip capacitor.
The printed wiring board according to any one of the above. 14. The printed wiring board according to claim 1, wherein a chip capacitor having an electrode formed inside an outer edge is used as the capacitor. 15. The printed wiring board according to claim 1, wherein a chip capacitor having electrodes formed in a matrix is used as said capacitor. 16. The printed wiring board according to claim 1, wherein a plurality of chip capacitors for multi-cavity are connected and used as said capacitor. 17. A method for producing a printed wiring board, comprising at least the following steps (a) to (c): (a) a resin board having a circuit pattern formed on one or both sides thereof, via an adhesive material; Connecting a capacitor having a conductive paste applied on a metallized electrode to the circuit pattern; (b) attaching a resin substrate having a cavity for accommodating the capacitor to the resin plate to form a core substrate. (C) forming a via hole in the resin plate by providing an opening to an electrode of the capacitor. 18. The method for manufacturing a printed wiring board according to claim 17, wherein pressure is applied to both sides of the substrate during the attaching in the step (c). 19. The method according to claim 19, wherein before and after the step (c), a through hole is formed in the core substrate obtained by attaching the resin substrate to the resin plate to form a through hole. A method for manufacturing a printed wiring board according to claim 17.