JP4585923B2 - Wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a wiring board including a core substrate in which a ceramic sub-core made of ceramic is accommodated, and a manufacturing method thereof.

  Conventionally, an organic package substrate is used as a wiring substrate on which a semiconductor integrated circuit element (hereinafter referred to as “IC chip”) is mounted. The organic package substrate has a dielectric layer made of a polymer material and a conductor layer made of a metal material alternately laminated on a core substrate mainly made of a polymer material such as an epoxy resin reinforced with glass fiber. It has a structure in which a wiring laminated portion is formed. However, organic package substrates are mainly made of polymer materials, so if thermal history such as solder reflow is added, there is a risk of problems such as disconnection due to differences in the linear expansion coefficient with IC chips mainly made of silicon. . Therefore, in Patent Document 1, in order to reduce the difference in linear expansion coefficient between the IC chip and the wiring board, a structure in which a sub-core made of ceramic having a smaller linear expansion coefficient than the core body made of a polymer material is accommodated in the core board. A wiring board having the following has been proposed.

JP 2005-39217 A

  By the way, the ceramic sub-core as described above usually has a through conductor penetrating between main surfaces, and a conductor pad connected to the through conductor is formed on the main surface (FIG. 3 of Patent Document 1). Since these through conductors and conductor pads are obtained by printing a metal paste on a green sheet obtained by molding ceramic powder together with a resin binder and firing them simultaneously, the firing temperature of the ceramic (alumina, silicon nitride, aluminum nitride, etc.) However, it is necessary to use a refractory metal that does not melt or flow out (for example, Mo or W) as the conductor material. For this reason, it is not possible to apply a roughening technique or the like used for forming the wiring laminated portion to the conductor pad of the ceramic secondary core, and when forming the wiring laminated portion on the core substrate containing the ceramic secondary core, Adhesiveness between the dielectric layer serving as the laminated portion and the via conductor formed through the dielectric layer and the conductor pad of the ceramic sub-core cannot be sufficiently obtained, and there is a risk of causing problems in manufacturing and products.

  The present invention has been made in view of the above problems, and when forming a wiring laminated portion on a core substrate containing a ceramic sub-core, a dielectric layer serving as a wiring laminated portion and a via formed therethrough It is an object of the present invention to provide a wiring board and a method for manufacturing the wiring board, in which sufficient adhesion between a conductor and a conductor pad of a ceramic sub-core can be obtained.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, the wiring board of the present invention is
A plate-shaped core body made of a polymer material is formed with a sub-core housing portion as a through-hole penetrating between the main surfaces or a recess opening in one of the main surfaces, and a plate-like shape made of ceramic inside A core substrate in which the ceramic sub-core is accommodated, and a wiring laminate formed by alternately laminating dielectric layers and conductor layers made of a polymer material on the main surface of the core substrate, A wiring board having a through conductor through which a ceramic sub-core penetrates between main surfaces and a conductor pad on the main surface connected thereto,
A Cu plated layer is formed on the surface of the conductor pad, and the surface of the Cu plated layer is a treated surface that has been subjected to a surface chemical treatment for improving adhesion to a polymer material. Ri Na and via conductor composed lowermost dielectric layer and Cu plating formed through that of the laminated wiring portion is in contact,
The treated surface is a roughened surface subjected to Cu roughening treatment as surface chemical treatment,
It is characterized in that a base plating layer having a stronger adhesion with each other is interposed between the conductor pad and the Cu plating layer than when the Cu plating layer is directly formed on the surface of the conductor pad .

In addition, in order to manufacture the wiring board, the manufacturing method of the wiring board of the present invention,
A sub core housing step of housing the ceramic sub core having the Cu plating layer formed on the surface of the conductor pad in the sub core housing portion;
A wiring laminating step of alternately laminating dielectric layers and conductor layers on the main surface of the core substrate containing the ceramic sub-core to form a wiring laminating portion;
In this order, and
Surface chemical treatment to improve adhesion to the polymer material on the Cu plating layer formed on the surface of the conductor pad before the sub-core housing process or between the sub-core housing process and the wiring lamination process a surface treatment step of applying seen including,
The surface chemical treatment in the surface treatment step is a Cu roughening treatment in which the surface of the Cu plating layer is a roughened surface,
In the wiring layering process, a via hole is drilled in the lowermost dielectric layer of the wiring layering part so that the roughened surface of the Cu plating layer formed on the surface of the conductor pad is exposed, and then the Cu plating is applied to the entire surface of the via hole. Including the step of filling the via hole to form a via conductor,
Prior to the sub-core housing step, the base plating layer and the Cu plating layer, which have stronger adhesion to each other than the case where the Cu plating layer is directly formed on the surface of the conductor pad of the ceramic sub-core, are formed. It includes a pad plating step that is formed in order .

  According to the present invention, by forming a Cu plating layer on the surface of the conductor pad, a via conductor (usually formed by the same Cu plating) formed through the lowermost dielectric layer of the wiring laminated portion. Improved adhesion. In addition, the surface of the Cu plating layer is treated with a surface chemical treatment to improve the adhesion to the polymer material, so that it adheres to the lowermost dielectric layer of the wiring laminate. Improves. In this way, the dielectric layer and the via conductor are in good contact with the conductor pad, so that it is possible to eliminate the possibility of problems in manufacturing and in the product.

  In the surface chemical treatment, as a first aspect, a Cu roughening treatment in which the surface of the Cu plating layer is a roughened surface (treated surface) can be applied. As the Cu roughening treatment, a known method such as microetching or blackening treatment can be used. When the surface of the Cu plating layer is roughened, the adhesion with the lowermost dielectric layer of the wiring laminated portion is sufficient due to the anchor effect.

  Alternatively, in the surface chemical treatment, as a second aspect, an adhesive layer forming process made of an alloy containing Cu and Sn, in which the surface of the Cu plating layer is the adhesive layer forming surface (processed surface), can be applied. According to this, the adhesiveness with the lowermost dielectric layer of the wiring laminated portion can be made sufficient without roughening the surface of the Cu plating layer. Specifically, the adhesive layer includes at least one selected from a third metal (Ag, Zn, Al, Ti, Bi, Cr, Fe, Co, Ni, Pd, Au, and Pt in addition to Cu and Sn. An alloy made of (metal).

  The plating structure of the conductor pad can be a structure in which the conductor pad is a metallized pad containing Mo or W as a main component and a Cu plating layer is directly formed on the surface thereof as a first aspect. Such a Cu plating layer can be obtained by directly forming a Cu plating layer on the surface of the conductor pad of the ceramic sub core before the sub core housing step (pad plating step). Thereby, the Cu plating layer for closely adhering the dielectric layer (by surface treatment) and the via conductor can be satisfactorily formed on the surface of the conductor pad.

  Or, as a second aspect, the plating structure of the conductor pad is a base having a stronger adhesion to each other than when the Cu plating layer is formed directly on the surface of the conductor pad between the conductor pad and the Cu plating layer. It can be set as the structure where the plating layer was inserted. For example, Ni plating, Pd plating, solder plating, or the like can be applied as the base plating layer. Among these, Ni plating is particularly suitable because of good adhesion and low cost. That is, the plating structure can be a metallized pad whose main component is Mo or W, and a structure in which a Ni plating layer and a Cu plating layer are formed in this order on the surface. The Ni plating layer and the Cu plating layer can be obtained by forming the Ni plating layer and the Cu plating layer in this order on the surface of the conductor pad of the ceramic sub core before the sub core housing step (pad plating step). . Thereby, the Cu plating layer for closely adhering the dielectric layer (by surface treatment) and the via conductor can be satisfactorily formed on the surface of the conductor pad.

  An embodiment of a wiring board of the present invention will be described with reference to the drawings. FIG. 1 schematically shows a cross-sectional structure of the wiring board 1. In the present embodiment, the plate-like member has a surface appearing on the upper side in the drawing as the first main surface MP1 and a surface appearing on the lower side as the second main surface MP2. The wiring substrate 1 has a ceramic sub-core 3 in the lower region of the solder bump 7 in the core substrate CB, reduces the difference in coefficient of linear expansion from the semiconductor integrated circuit element (IC chip) C, and breaks due to thermal stress. Etc. are less likely to occur. Detailed description will be given below.

  FIG. 2 is a diagram showing the wiring board 1 arranged between the IC chip C and the main board (motherboard or the like) GB. The IC chip C has a signal terminal, a power supply terminal, and a ground terminal on the second main surface (not shown), and solder bumps 7 (Pb-Sn series, Sn) formed on the first main surface MP1 of the wiring board 1. -Ag-based, Sn-Sb-based, Sn-Zn-based solder, etc.). Also, an underfill material (not shown) made of a thermosetting resin is filled between the IC chip C and the first main surface MP1 of the wiring board 1 in order to improve the thermal fatigue life of the solder bumps 7. Is done. On the other hand, the main board (motherboard or the like) GB is mainly composed of a polymer material reinforced with ceramic particles and fibers as fillers, and is connected via solder balls BL formed on the second main surface MP2 of the wiring board 1. Are connected to the terminal pads 56.

  FIG. 3 is a diagram illustrating the first main surface MP1 of the wiring board 1. FIG. The solder bumps 7 are arranged in a grid pattern (or may be a staggered pattern). Among these, the power terminals 7a and the ground terminals 7b are alternately arranged in the center, and the signal terminals surround the signal terminals. 7s is arranged. These correspond to the terminals of the IC chip C.

  The core body 2 is configured in a plate shape with a heat resistant resin plate (for example, bismaleimide-triazine resin plate), a fiber reinforced resin plate (for example, glass fiber reinforced epoxy resin), or the like. A sub-core accommodating portion 25 (through hole) penetrating between the main surfaces MP1 and MP2 is formed at a position including the lower region of the solder bump 7, and a plate-shaped ceramic sub-core 3 is accommodated therein. The core substrate CB is used.

  The ceramic sub-core 3 has a through conductor 32 penetrating between the main surfaces MP1 and MP2 and a conductor pad 31 on the main surfaces MP1 and MP2 connected thereto, which are respectively connected to the power supply terminal 7a and the ground terminal 7b. Correspond. By forming the power supply and ground through conductors 32 in parallel in the ceramic sub-core 3, it is possible to reduce the inductance of the power supply and ground paths and thereby reduce the impedance.

  The ceramic sub-core 3 can be obtained by forming a via hole in a ceramic green sheet containing a ceramic material powder by punching or laser drilling, and laminating and filling a metal powder paste. As a ceramic material constituting the ceramic sub-core 3, an inorganic ceramic filler such as alumina is added to 40 parts by weight or more and 60 parts by weight or less to alumina, silicon nitride, aluminum nitride or the like, borosilicate glass or lead borosilicate glass. Glass ceramic or the like can be used. The conductor pads 31 and the through conductors 32 are made of metallization mainly composed of Mo or W obtained by simultaneous firing with a ceramic material as a metal powder paste.

  A filling resin 4 made of a polymer material is filled in a space that forms a gap between the ceramic sub-core 3 and the core body 2 in the sub-core housing portion 25. The filling resin 4 is made of an epoxy-based resin containing an inorganic filler such as silica filler, and fixes the ceramic sub-core 3 to the core main body 2, and in-plane between the ceramic sub-core 3 and the core main body 2. It plays a role of absorbing the difference in linear expansion coefficient between the direction and the thickness direction by its own elastic deformation.

  As shown in FIGS. 8 to 11, the conductor pad 31 of the ceramic sub-core 3 has a Cu plating layer 31 c formed on the surface thereof, and the surface of the Cu plating layer 31 has adhesion to a polymer material. The treated surfaces CZ and FB are subjected to a Cu surface chemical treatment for improving the resistance. The processing layers CZ and FB are in contact with the lowermost dielectric layers B11 and B21 of the wiring laminated portions L1 and L2 and the via conductors 6 formed therethrough so that the dielectric layers B11 and B21 are in good contact with each other. is doing. Further, since the surface is composed of the Cu plating layer 31c, the adhesion to the via conductor 6 also composed of Cu plating is good. Each aspect will be described below.

  As a first aspect of the plating structure, as shown in FIGS. 10 and 11, a Cu plating layer 31 c is directly formed on the surface of the conductor pad 31. The Cu plating layer 31c is formed by electrolytic Cu plating (barrel plating) or electroless Cu plating with a thickness of about 2 μm to 4 μm. Note that when the roughened surface CZ shown in FIG. 10 is obtained, the surface of the Cu plating layer 31c is slightly etched by the Cu roughening process (described later), so that the roughened surface CZ is first formed with a thickness of about 5 μm. The thickness after the adjustment is adjusted to about 2 μm or more and 4 μm or less.

  As a second aspect of the plating structure, as shown in FIGS. 8 and 9, a Ni plating layer 31 n and a Cu plating layer 31 c are formed in this order on the surface of the conductor pad 31. The Cu plating layer 31c is the same as described above. The Ni plating layer 31 is a base plating layer that is interposed between the conductor pad 31 and the Cu plating layer 31c, and adheres well to each other so that the Cu plating layer 31c for the conductor pad 31 is better than in the case of the first embodiment. The adhesion is improved. In addition, the Ni plating layer 31n is formed by stacking about two layers of electroless Ni plating and subjected to sintering treatment, and has a thickness that does not cause pinholes, for example, 3.0 μm or more and 3.6 μm or less. It is adjusted to the degree. The electroless Ni plating can be Ni-B plating or Ni-P plating (or a plurality of layers may be formed in combination).

  As a 1st aspect of the processing surface by Cu surface chemical treatment, as shown in FIG.8 and FIG.10, it is set as the roughening surface CZ by which Cu roughening processing was performed as Cu surface chemical processing of the Cu plating layer 31c surface. be able to. As the Cu roughening treatment, a known method such as microetching or blackening treatment can be used. By making the surface of the Cu plating layer 31c the roughened surface CZ, the adhesion with the lowermost dielectric layers B11 and B21 of the wiring laminated portions L1 and L2 becomes sufficient due to the anchor effect. In order to obtain this effect, Cu roughening treatment is preferably performed so that the ten-point average roughness (Rz) defined in JIS-B-0601 is about 0.3 μm or more and 20 μm or less. Moreover, 0.5 micrometer or more and 1.0 micrometer or less are more preferable, and 0.5 micrometer or more and 5 micrometers or less are still more preferable.

  As a second aspect of the treatment surface by the Cu surface chemical treatment, as shown in FIGS. 9 and 11, the formation process of the adhesive layer FB made of an alloy containing Cu and Sn as the Cu surface chemical treatment on the surface of the Cu plating layer 31c. It can be set as the adhesive layer FB formation surface to which was given. According to the formation process of the adhesive layer FB, the adhesion with the lowermost dielectric layers B11 and B21 of the wiring laminated portions L1 and L2 is sufficient without roughening the surface of the Cu plating layer 31c. be able to. Specifically, the adhesive layer FB includes at least one selected from a third metal (Ag, Zn, Al, Ti, Bi, Cr, Fe, Co, Ni, Pd, Au, Pt in addition to Cu and Sn). Alloy). Further, for example, Cu is contained in an amount of about 1 to 50 atomic percent, Sn is contained in an amount of about 20 to 98 atomic percent, and a third metal is contained in an amount of about 1 to 50 atomic percent. The thickness of the adhesive layer FB is preferably 0.001 μm or more and 1 μm or less in order to obtain a sufficient adhesion effect.

  In the wiring laminated portions L1 and L2 provided on both main surfaces MP1 and MP2 of the core substrate CB, dielectric layers B11 to B14 and B21 to B24 and conductor layers M11 to M14 and M21 to M24 are alternately laminated. It has a structure. The conductor layers M11 to M14, M21 to M24 are configured by wirings 51 and 53 made of Cu plating, pads 55 and 56, and the like. Between the conductor layers M11 to M14 and M21 to M24, interlayer connection is made by the via conductor 6, thereby forming a conduction path (for signal, power supply, and ground) from the pad 55 to the pad 56. . The pads 55 and 56 are for forming the solder bumps 7 and the solder balls BL, and the surface thereof is Ni-Au plated.

  The dielectric layers B11 to B14 and B21 to B24 are made of a polymer material such as an epoxy resin, and appropriately include an inorganic filler such as silica powder that adjusts the dielectric constant and dielectric strength. Among these, the dielectric layers B11 to B13 and B21 to B23 are called buildup resin insulation layers and via layers, and insulate the conductor layers M11 to M14 and M21 to M24, and the via conductors 6 for interlayer connection are provided. It is formed through. On the other hand, the dielectric layers B14 and B24 are solder resist layers, and openings for exposing the pads 55 and 56 are formed.

  In addition, a through hole is formed in the core main body 2 and the dielectric layers B11 and B21 of the core substrate CB, and a through-hole conductor 21 is formed on the inner wall of the core substrate CB so as to establish conduction between the wiring laminated portions L1 and L2. . The through-hole conductor 21 corresponds to the signal terminal 7s. Inside the through-hole conductor 21, a resin hole filling material 23 made of an epoxy resin containing an inorganic filler such as a silica filler is filled and formed, and the end portion of the through-hole conductor 21 is a lid conductor made of Cu plating. 52 is formed. In addition, the area | region from the conductor layers M12 to M22 centering on a core board | substrate in which the through-hole conductor 21 and the cover conductor 52 were formed is called core area | region CR.

  Next, an embodiment of a method for manufacturing a wiring board according to the present invention will be described with reference to the drawings. 4-7 is a figure showing the manufacturing process of the wiring board 1. FIG.

  In step 1, a conductor pattern 54 (conductor layer M11) is formed on both main surfaces MP1 and MP2 of the core body 2. This is a pattern etching of copper foil using a mask material for a heat-resistant resin plate (for example, bismaleimide-triazine resin plate) or fiber reinforced resin plate (for example, glass fiber reinforced epoxy resin) having copper foil on both main surfaces. Can be obtained.

  In step 2, a through-hole penetrating between the main surfaces MP1 and MP2 is formed by drilling to provide the sub-core housing portion 25. Moreover, the adhesiveness with the filling resin 4 with which it fills later can be improved by performing a roughening process with the potassium permanganate etc. with respect to the side wall of the subcore accommodating part 25 (through-hole). Furthermore, an organic compound (coupling agent) may be applied.

In step 3 (blocking step), the opening on the second main surface MP2 side of the sub core housing part 25 (through hole) is made of the sheet material S having the adhesive ad on the surface, and the adhesive ad is in the sub core housing part 25. Close it so that it is exposed inside. The sheet material S preferably has an adhesive strength of the adhesive material ad of 8.0 N / 25 mm or more (180 ° peeling method (JIS
Z 0237)). The unit [N / 25 mm] means a force measured using a sheet material having a width of 25 mm as a sample. As the material (base material) of the sheet material S, for example, a resin sheet such as polyester, polyimide, or PET can be used. As the adhesive ad applied to the surface of the sheet material S, for example, a silicon adhesive, an acrylic adhesive, a thermoplastic rubber adhesive, or the like can be used.

  In step 4 (sub-core accommodating step), the ceramic sub-core 3 is accommodated from the opening on the first main surface MP1 side of the sub-core accommodating portion 25 and is fixed to the adhesive ad. This can accommodate the ceramic sub-core 3 with high accuracy by using a known mounting device. Here, a Cu plating layer 31c is formed in advance on the surface of the conductor pad 31 of the ceramic sub-core 3 (pad plating step). As described above, the plating structure on the surface of the conductor pad 31 is obtained by directly forming the Cu plating layer 31c on the surface of the conductor pad 31 (see FIGS. 10 and 11: first embodiment) or Ni on the surface of the conductor pad 31. What formed the plating layer 31n and the Cu plating layer 31c in this order (refer FIG.8 and FIG.9: 2nd aspect) is applicable. The formation method, thickness, and the like of the plating layers 31c and 31n are as described above.

  In step 5 (filling and curing step), the filling resin 4 is injected into the gap between the core body 2 and the ceramic sub-core 3 and cured. The filling resin 4 is injected while circulating a known dispenser DS. After the filling resin 4 is injected, the bubbles are extracted from the filling resin 4 by vacuum defoaming. Thereafter, the filling resin 4 is heated and dried to be cured (so-called curing). In addition, after the filling resin 4 is cured, the adhesion with the dielectric layers B11 and B21 to be formed later can be improved by performing a roughening treatment with potassium permanganate or the like.

  In step 6 (surface treatment step), a Cu surface chemical treatment is performed on the Cu plating layer 31c formed on the surface of the conductor pad 31 in order to improve adhesion to the polymer material. Further, by this treatment, the Cu surface chemical treatment is also performed on the surface of the conductor pattern 54 formed on both the main surfaces MP1 and MP2 of the core body 2. FIG. 5 shows a diagram in which a Cu roughening process (a known microetching method, a blackening process, etc.) is performed in which the surface of the Cu plating layer 31c is a roughened surface CZ. Further, the present invention is not limited to this, and the formation process of the adhesive layer FB made of the alloy containing Cu and Sn described above may be used. This step is performed in advance before step 4 (sub-core accommodation step), and the ceramic sub-core 3 in which the Cu pad chemical treatment is applied to the conductor pad 31 is accommodated in the sub-core accommodation portion 25. Also good.

  Step 7 and subsequent steps correspond to the wiring lamination step of the present invention. That is, the dielectric layers B11 to 14, B21 to 24 and the conductor layers M12 to M14 and M22 to M24 are alternately laminated on the main surfaces MP1 and MP2 of the core substrate CB in which the ceramic sub-core 3 is accommodated. Portions L1 and L2 are formed. This can be realized by using a known build-up process (semi-additive method, full additive method, subtractive method, formation of a dielectric layer by laminating a film-like resin material, photolithography technique, etc.).

  First, in step 7, dielectric layers B11 and B21 are laminated on the main surfaces MP1 and MP2 of the core substrate CB in which the ceramic sub-core 3 is accommodated. At this time, the surface of the conductor pad 31 of the ceramic sub-core 3 is subjected to the above-described Cu surface chemical treatment, so that the adhesion is good. Next, in step 8, via holes 6a are formed in the dielectric layers B11 and B21 by a technique such as a laser via process or a photo via process. As a result, the conductor pad 31 is exposed at the bottom of the via hole 6a. Further, after the via hole 6a is formed, a desmear process (resin residue removal process) is performed with potassium permanganate or the like, and the surface of the conductor pad 31 is cleaned.

  Next, in step 9, a through hole TH is drilled by a drill or the like so as to penetrate the core substrate CB and the dielectric layers B11 and B21 and the conductor layers M11 and M21 formed on the main surfaces MP1 and MP2 in the thickness direction. To do. In step 10, Cu plating (electrolytic Cu plating after electroless Cu plating) is applied to the entire surface to fill the inside of the via hole 6 a to form the via conductor 6, and the through hole conductor is formed on the inner surface of the through hole TH. 21 is formed. Then, the lid conductor 52 is formed by filling the inside of the through-hole conductor 21 with the resin filling material 23 and further applying Cu plating to the entire surface. In addition, by forming the via conductor 6 by the same Cu plating as the Cu plating layer 31c on the surface of the conductor pad 31, it is possible to relieve thermal stress that is likely to occur during solder reflow and to reduce the possibility of disconnection. Can do.

  Next, in step 12, the wiring 51 and the like are patterned by pattern etching of Cu plating covering the dielectric layers B11 and B21. Thus, the core region CR is obtained. Similarly, the dielectric layers B12 to B14 and B22 to B24 and the conductor layers M13, 14, M23, and M24 are alternately formed, and the dielectric layers B14 and B24 are opened by a technique such as a laser via process or a photo via process. And pads 55 and 56 are exposed. Further, Ni—Au plating is applied to the surfaces of the pads 55 and 56, and solder bumps 7 are formed on the pads 55. Thereafter, the wiring board 1 shown in FIG. 1 is completed through predetermined inspections such as electrical inspection and appearance inspection.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to these, In the range which does not lose the identity with the invention embodied in these, it can change suitably.

The figure which represents roughly the cross-section of the wiring board of this invention The figure showing the wiring board arrange | positioned between a semiconductor integrated circuit element (IC chip) and main boards (motherboard etc.) The figure showing the 1st principal surface of a wiring board The figure showing the manufacturing process of the wiring board of this invention Figure following Figure 4 Figure following Figure 5 Figure following Figure 6 First example of plating structure on conductor pad surface of ceramic sub-core Second example of plating structure on conductor pad surface of ceramic sub-core Third example of plating structure on conductor pad surface of ceramic sub-core Fourth example of plating structure on conductor pad surface of ceramic sub-core

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wiring board 2 Core main body 25 Sub core accommodating part 3 Ceramic sub core 4 Filling resin 6 Via conductor 7 Solder bump CB Core board L1, L2 Wiring lamination | stacking part

Claims (6)

A plate-shaped core body made of a polymer material is formed with a sub-core housing portion as a through-hole penetrating between the main surfaces or a recess opening in one of the main surfaces, and a plate-like shape made of ceramic inside A core substrate in which the ceramic sub-core is accommodated, and a wiring laminate formed by alternately laminating dielectric layers and conductor layers made of a polymer material on the main surface of the core substrate, The ceramic sub-core is a wiring board having a through conductor penetrating between main surfaces and a conductor pad on a main surface connected to the through conductor,
A Cu plating layer is formed on the surface of the conductor pad, and the surface of the Cu plating layer is a treated surface subjected to a surface chemical treatment for improving adhesion with a polymer material, and the treated surface. Ri Na and the by via conductor composed of the dielectric layer and the Cu plating formed through the its lowermost wiring laminated portion is in contact with,
The treated surface is a roughened surface subjected to Cu roughening treatment as the surface chemical treatment,
Between the conductor pad and the Cu plating layer, an underlying plating layer having stronger adhesion than each of the case where the Cu plating layer is directly formed on the surface of the conductor pad is interposed. Wiring board. The wiring board according to claim 1 , wherein the base plating layer is a Ni plating layer. The wiring board according to claim 1 , wherein the conductor pad is a metallized pad mainly composed of Mo or W, and a Ni plating layer and a Cu plating layer are formed on the surface thereof in this order. A plate-shaped core body made of a polymer material is formed with a sub-core housing portion as a through-hole penetrating between the main surfaces or a recess opening in one of the main surfaces, and a plate-like shape made of ceramic inside A core substrate in which the ceramic sub-core is accommodated, and a wiring laminate formed by alternately laminating dielectric layers and conductor layers made of a polymer material on the main surface of the core substrate, The ceramic sub-core is a method for manufacturing a wiring board having a through conductor penetrating between main surfaces and a conductor pad on the main surface connected to the through conductor,
A sub-core housing step of housing the ceramic sub-core having a Cu plating layer formed on the surface of the conductor pad in the sub-core housing portion;
A wiring laminating step of alternately laminating the dielectric layers and the conductor layers on the main surface of the core substrate in which the ceramic sub-core is accommodated to form the wiring laminating portion;
In this order, and
In order to improve the adhesion with the polymer material to the Cu plating layer formed on the surface of the conductor pad before the sub-core housing step or between the sub-core housing step and the wiring layering step. look including a surface treatment step of subjecting the surface chemical treatment of,
The surface chemical treatment in the surface treatment step is a Cu roughening treatment in which the surface of the Cu plating layer is a roughened surface,
In the wiring laminating step, after forming a via hole in the lowermost dielectric layer of the wiring laminating portion so that a roughened surface of the Cu plating layer formed on the surface of the conductor pad is exposed, Including the step of forming a via conductor constituted by Cu plating by filling the via hole by performing Cu plating on the entire surface,
Prior to the sub-core housing step, a base plating layer having a tighter adhesion with each other than when the Cu plating layer is directly formed on the surface of the conductor pad on the surface of the conductor pad of the ceramic sub-core, and A method of manufacturing a wiring board comprising a pad plating step of forming the Cu plating layer in this order . The method of manufacturing a wiring board according to claim 4 , wherein the base plating layer is a Ni plating layer . Before the sub-core housing step, the opening on the second main surface side of the sub-core housing portion formed as a through-hole penetrating between the main surfaces of the core body is a sheet material having an adhesive on the surface, Including a closing step of closing the adhesive so as to be exposed to the inside of the sub-core housing portion;
In the sub-core housing step, the ceramic sub-core is housed from the opening on the first main surface side of the sub-core housing portion and fixed to the adhesive,
The method for manufacturing a wiring board according to claim 4 , further comprising a filling and curing step of injecting and curing a filling resin into a gap between the core body and the ceramic sub-core after the sub-core housing step.

Images