JP2002100871A - Printed wiring board and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board together with its manufacturing method which incorporated capacitors in high density, for less occurrence of defectives. SOLUTION: A recess 32 is widely formed on a core substrate 30, and a plurality of capacitors 20 are housed in the recess 32. A plurality of capacitors 20 are allowed to be incorporated at high density in the recess 32. Since the heights of the plurality of capacitors 20 in the recess 32 are the same, the thickness of the resin layer on the upper surface of the capacitors 20 is constant, reducing the occurrence of defectives.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board on which electronic components such as an IC chip are mounted, and more particularly to a printed circuit board having a built-in capacitor.

[0002]

2. Description of the Related Art At present, in a printed wiring board for a package substrate, a chip capacitor is sometimes mounted on a surface in order to facilitate power supply to an IC chip.

[0003]

SUMMARY OF THE INVENTION Chip capacitors and I
Since the reactance with the C chip depends on the frequency, sufficient operation cannot be performed even when the chip capacitor is surface-mounted with the increase in the driving frequency of the IC chip. In order to solve the above-mentioned problem, the present applicant has proposed a technique for incorporating a capacitor in a printed wiring board in Japanese Patent Application No. 11-248313. Japanese Patent Application Laid-Open No. 6-326472 discloses a technique for embedding a capacitor in a substrate.
JP-A-7-263619, JP-A-10-2564
No. 29, JP-A-11-45555, JP-A-11-12
6978 and JP-A-11-313868.

Japanese Patent Application Laid-Open No. 6-326472 discloses a technique for embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, power supply noise is reduced, and a space for mounting a chip capacitor is not required, and the size of the insulating substrate can be reduced. In addition, Japanese Patent Application Laid-Open
No. 263619 discloses a technique for embedding a capacitor in a substrate made of ceramic, alumina, or the like. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.

[0005]

However, the above-mentioned Japanese Patent Application Laid-Open No. 6-326472 and Japanese Patent Application Laid-open No.
Cannot reduce the distance between the IC chip and the capacitor too much, and could not reduce the inductance as required at present in the higher frequency range of the IC chip. In particular, in a resin-made multilayer build-up wiring board, disconnection between a terminal of a chip capacitor and a via hole due to a difference in thermal expansion coefficient between a capacitor made of ceramic and a core substrate made of resin and an interlayer resin insulating layer. Peeling between chip capacitor and interlayer resin insulation layer,
Cracks occurred in the interlayer resin insulation layer, and high reliability could not be achieved for a long period of time.

In the invention of Japanese Patent Application No. 11-248313, since the concave portion is formed for each capacitor, the concave portion cannot be formed accurately when the precision of the counterbore processing is low. In some cases, it was not possible to enter the recess at an appropriate position. In addition, the depth of the concave portion becomes smaller than the height of the capacitor, and the capacitor sometimes protrudes from the concave portion. For this reason, the core substrate cannot be smoothed, and even if a printed wiring board is manufactured by forming an interlayer resin insulating layer and wiring on the core substrate, disconnection is likely to occur and the defective product occurrence rate is increased. found. Further, it has been difficult to increase the mounting density of the capacitor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to manufacture a printed wiring board and a printed wiring board having a built-in capacitor with a high density and a low rejection rate. It is to provide a method.

[Means for Solving the Problems]

In order to achieve the above object, according to the first aspect of the present invention, there is provided a printed wiring board in which a resin insulating layer and a conductive circuit are laminated on a core substrate, wherein a concave portion is formed in the core substrate. It is a technical feature that a plurality of capacitors are accommodated in the recess.

According to the first aspect, the recess is formed widely in the core substrate, and a plurality of capacitors are accommodated in the recess. for that reason,
It is possible to reliably arrange a plurality of capacitors in the core substrate. Since the capacitors can be arranged densely in the recess, the mounting density of the capacitors can be increased. In addition, since a plurality of capacitors are placed in the recess, the heights of the plurality of capacitors are uniform, so that the resin layer formed on the core substrate can have a uniform thickness, and the formation of via holes is stabilized. Further, since the concave portion is formed widely, the capacitor can be accurately positioned. Therefore, since the interlayer resin insulating layer and the conductive circuit can be appropriately formed on the core substrate, the defective product occurrence rate of the printed wiring board can be reduced.

It is desirable that the recess be filled with a resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if a stress originating from the capacitor is generated, the stress can be reduced by the filled resin. The resin also has the effect of reducing adhesion and migration between the capacitor and the core substrate.

According to the second aspect of the present invention, since the resin is filled between the capacitors in the concave portion, the capacitor can be positioned and fixed in the concave portion. The coefficient of thermal expansion of the resin is set smaller than that of the core substrate, that is, close to that of a capacitor made of ceramic. For this reason, in the heat cycle test, even if internal stress is generated due to a difference in the coefficient of thermal expansion between the core substrate and the capacitor, cracks, peeling, and the like hardly occur on the core substrate, and high reliability can be achieved. In addition, since no migration occurs, the connection with the capacitor is stabilized.

According to the third aspect of the present invention, since a through-hole is formed in the resin layer between the capacitors, the signal line does not pass through the capacitors, so that reflection due to impedance discontinuity due to the high dielectric substance and propagation delay due to passage through the high dielectric substance are reduced. Does not occur.

In addition, through-holes enable electrical connection between the front and back sides, wiring can be provided below the capacitor via a build-up layer, and pins and BGA of the capacitor can be provided. Can be.

According to the fourth and fifth aspects, the electrodes of the chip capacitor on which the metal film is formed are electrically connected to the via holes formed by plating. Here, the electrode of the chip capacitor is made of metallized and has irregularities on the surface, but the surface is smoothed by the metal film and the via hole is formed, so when the through hole is formed in the resin coated on the electrode As a result, no resin residue remains, and the connection reliability between the via hole and the electrode can be improved. Furthermore, since the via hole is formed by plating on the plated electrode, the connectivity between the electrode and the via hole is high, and even if a heat cycle test is performed, disconnection between the electrode and the via hole may occur. Absent.

It is desirable that the metal film of the electrode of the capacitor is provided with any one of copper, nickel and noble metal. This is because a layer of tin or zinc in the built-in capacitor easily induces migration at a connection portion with the via hole.

The surface of the chip capacitor may be subjected to a roughening treatment. Therefore, the adhesion between the ceramic chip capacitor, the resin adhesive layer, and the interlayer resin insulating layer is high, and the adhesive layer and the interlayer resin insulating layer may peel off at the interface even when the heat cycle test is performed. There is no.

According to a sixth aspect of the present invention, at least a part of the electrode of the chip capacitor is exposed and accommodated in the printed wiring board, and the electrode exposed from the coating layer is electrically connected. At this time, the main component of the metal exposed from the coating layer is desirably Cu. This is because the connection resistance can be reduced.

According to the present invention, the capacitor is provided on the surface in addition to the capacitor housed in the substrate. Since the capacitor is housed in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance is reduced, and power can be supplied instantaneously. Because a capacitor is provided, a large-capacity capacitor can be attached.
Large power can be easily supplied to the IC chip.

According to the present invention, since the capacitance of the capacitor on the surface is equal to or larger than the capacitance of the capacitor in the inner layer, there is no shortage of power supply in a high frequency region, and a desired operation of the IC chip is ensured.

In the ninth aspect, the inductance of the capacitor on the surface is greater than the inductance of the capacitor in the inner layer.
The desired operation of the IC chip is ensured.

According to the tenth aspect, since a chip capacitor having an electrode formed inside the outer edge is used, a large external electrode can be obtained even when conduction is established through a via hole, and the allowable range of alignment is widened. Disappears.

In the eleventh aspect, since a capacitor having electrodes formed in a matrix is used, it is easy to accommodate a large chip capacitor in the core substrate. Therefore, the capacitance can be increased, so that an electrical problem can be solved. Further, even after various thermal histories, the printed wiring board is less likely to warp.

In the twelfth aspect, a plurality of chip capacitors for multi-cavity may be connected to the capacitor. As a result, the capacitance can be adjusted appropriately, and I
The C chip can be operated.

According to a thirteenth aspect of the present invention, there is provided a method for manufacturing a printed wiring board, which comprises at least the following steps (a) to (c): (a) forming a recess in a core substrate; (B) placing a plurality of capacitors in the recess; (c) filling a resin between the capacitors.

According to the thirteenth aspect, since the concave portion is formed widely in the core substrate, a plurality of capacitors can be reliably disposed in the core substrate. Further, since a plurality of capacitors are placed in the recess, the heights of the plurality of capacitors are uniform, so that the core substrate can be smoothed. Further, since the concave portion is formed widely, the capacitor can be accurately positioned. Accordingly, the smoothness of the core substrate is not impaired, and the interlayer resin insulating layer and the conductive circuit can be appropriately formed on the core substrate, so that the defective product occurrence rate of the printed wiring board can be reduced. In addition, since the resin is filled between the capacitors, the capacitors can be positioned and fixed in the concave portions.

According to the fourteenth aspect of the present invention, the heights of the upper surfaces of the capacitors are made uniform by applying pressure or hitting the upper surfaces of the plurality of capacitors in the recess. Thereby, when the capacitors are provided in the recesses, the heights can be made uniform even if the sizes of the plurality of capacitors vary, and the core substrate can be made smooth. Therefore, the smoothness of the core substrate is not impaired, and the upper interlayer resin insulating layer and the conductive circuit can be appropriately formed, so that the defective product occurrence rate of the printed wiring board can be reduced.

According to the fifteenth aspect, since the signal line does not pass through the capacitor because the through hole is formed in the resin layer between the capacitors, reflection due to impedance discontinuity due to the high dielectric substance and propagation delay due to passage through the high dielectric substance are reduced. Does not occur. Further, through-holes enable electrical connection between the front and back sides, wiring can be provided below the capacitor via a build-up layer, and pins and BGA of the capacitor can be provided.

According to a sixteenth aspect of the present invention, there is provided a method for manufacturing a printed wiring board, which comprises at least the following steps (a) to (d): (a) containing a resin as a core material Forming a through hole in the resin material formed; (b) attaching a resin material to the resin material having the through hole to form a core substrate having a concave portion; (D) a step of filling the concave portions between the capacitors with a resin.

According to the sixteenth aspect, since the concave portion is widely formed in the core substrate, a plurality of capacitors can be securely disposed in the core substrate. Further, since a plurality of capacitors are placed in the recess, the heights of the plurality of capacitors are uniform, so that the core substrate can be smoothed. Further, since the concave portion is formed widely, the capacitor can be accurately positioned. Therefore, since the interlayer resin insulating layer and the conductive circuit can be appropriately formed on the core substrate, the defective product occurrence rate of the printed wiring board can be reduced. In addition, since the resin is filled between the capacitors, the capacitors can be positioned and fixed in the concave portions.

According to the seventeenth aspect of the present invention, the heights of the upper surfaces of the capacitors are made uniform by pushing or hitting the upper surfaces of the plurality of capacitors in the concave portion from above. Thereby,
When the capacitors are provided in the recesses, the heights can be made uniform even if the sizes of the plurality of capacitors vary. Therefore, the interlayer resin insulating layer and the conductive circuit can be appropriately formed on the core substrate without impairing the smoothness, and thus the defective product occurrence rate of the printed wiring board can be reduced.

According to the eighteenth aspect of the present invention, since the signal line does not pass through the capacitor because the through hole is formed in the resin layer between the capacitors, reflection due to impedance discontinuity due to the high dielectric substance and propagation delay due to passage through the high dielectric substance are reduced. Does not occur. In addition, through-holes enable electrical connection between the front and back surfaces, wiring can be provided below the capacitor via a build-up layer, and pins and BGA of the capacitor can be used.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a cross section of the printed wiring board 10, and FIG. 8 shows a state where the IC chip 90 is mounted on the printed wiring board 10 shown in FIG.

As shown in FIG. 7, the printed wiring board 10
Core substrate 30 accommodating a plurality of chip capacitors 20
And build-up wiring layers 80A and 80B. Build-up wiring layer 80A, build-up wiring layer 80B
Is composed of interlayer resin insulation layers 50 and 150. In the interlayer resin insulation layer 50, the via hole 160 and the conductor circuit 15
8, via holes 260 and conductive circuits 258 are formed in interlayer resin insulating layer 150. On the interlayer resin insulating layer 150, the solder resist layer 70 is provided.

The chip capacitor 20 includes a first electrode 21 and a second electrode 22 as shown in FIG.
A first conductive film 24 connected to the first electrode 21 side and a second conductive film 25 connected to the second electrode 22 side. A plurality of sheets are arranged facing each other.

As shown in FIG. 8, solder bumps 76U for connection to pads 92 of IC chip 90 are formed in via holes 260 of upper build-up wiring layer 80A. On the other hand, the via holes 260 of the lower build-up wiring layer 80B are provided with the pads 95 of the daughter board 94.
A solder bump 76D for connection to the substrate is formed.
Further, a through hole 46 is formed in the core substrate 30.

In the printed wiring board 10 of the present embodiment, since the concave portion 32 is formed widely, a plurality of chip capacitors 20 can be securely disposed on the substrate even if the precision of the counterboring process is low. Becomes Since the chip capacitors 20 can be arranged densely in the recesses 32, the mounting density of the capacitors can be increased. Also, the recess 32
Since the plurality of chip capacitors 20 have the same height, the resin layer formed on the core substrate can have a uniform thickness as described later, and the formation of via holes is stabilized. Therefore, since the interlayer resin insulating layers 50 and 150 and the conductor circuits 158 and 258 can be appropriately formed on the core substrate 30, the defective product generation rate of the printed wiring board 10 can be reduced.

As the core substrate, a substrate made of resin was used. For example, a resin material used for a general printed wiring board such as a glass epoxy resin-impregnated base material and a phenol resin-impregnated base material can be used. However, a substrate made of ceramic, AIN, or the like cannot be used as the core substrate. This is because the substrate has poor external formability, and may not be able to accommodate a capacitor, and may cause voids even when filled with resin.

Further, since the resin filler 36 is filled between the chip capacitors 20, the chip capacitors 20 arranged at accurate positions in the concave portions 32 can be positioned and fixed. Further, migration at the connection between the capacitor and the via hole can be prevented. Here, the resin filler 36 and the adhesive material 34 under the chip capacitor 20 are used.
Is smaller than that of the core substrate 30 and the resin insulating layer 40, that is, the chip capacitor 2 made of ceramic.
It is set to be close to 0. For this reason, in the heat cycle test, even if internal stress is generated due to a difference in thermal expansion coefficient between the core substrate 30 and the resin insulating layer 40 and the chip capacitor 20, cracks, peeling, etc. And high reliability can be achieved.

The resin layer 3 between the chip capacitors 20
6, since the signal line does not pass through the chip capacitor 20 made of ceramic because the through hole 46 is formed, reflection due to impedance discontinuity due to the high dielectric substance and propagation delay due to passage through the high dielectric substance do not occur. Since wiring can also be provided under the capacitor, the degree of freedom of wiring, external terminals such as pins is increased, and the density and size are reduced.

As shown in FIG. 17A, the surface of the metal layer 26 constituting the first electrode 21 and the second electrode 22 of the chip capacitor 20 is coated with a copper plating film 29. The coating of the plating film is formed by plating such as electrolytic plating and electroless plating. As shown in FIG. 7, the first and second electrodes 21 and 22 covered with the copper plating film 29 are electrically connected to each other through via holes 60 made of copper plating.
Here, the electrodes 21 and 22 of the chip capacitor are made of metallized and have irregularities on the surface. Therefore, the metal layer 26
If used in a state where the resin insulating layer 40 is exposed,
In the step of forming the opening 48 in the opening, resin may remain on the unevenness. In this case, the first,
Poor connection between the second electrodes 21 and 22 and the via holes 60 may occur. In contrast, in the present embodiment,
The surfaces of the first and second electrodes 21 and 22 are smoothed by the copper plating film 29, and when the opening 48 is formed in the resin insulating layer 40 coated on the electrodes, no resin residue remains and the via hole 60 is formed. Can improve the connection reliability with the electrodes 21 and 22 at the time of formation.

Further, the electrode 2 on which the copper plating film 29 is formed
Since the via holes 60 are formed by plating on the first and second electrodes 22, the connectivity between the electrodes 21 and 22 and the via holes 60 is high.
No disconnection occurs between the via hole 60 and the via hole 60.

The copper plating film 29 is provided after the nickel / tin layer coated on the surface of the metal layer 26 at the stage of manufacturing the chip capacitor is peeled off at the stage of mounting on the printed wiring board. Instead, the chip capacitor 20
It is also possible to cover the metal layer 26 with the copper plating film 29 directly at the manufacturing stage of the above. That is, in the present embodiment, after the laser is provided with an opening to the copper plating film 29 of the electrode,
Desmear processing is performed, and via holes are formed by copper plating. Therefore, even if an oxide film is formed on the surface of the copper plating film 29, the oxide film can be removed by the laser and desmear treatments, so that proper connection can be established.

As shown in FIG. 17B, the coating layer 2 of the first electrode 21 and the second electrode 22 of the chip capacitor 20 is formed.
From 8, the upper part can be exposed and housed in a printed wiring board, and can be electrically connected to the first electrode 21 and the second electrode 22 exposed from the covering layer 28. At this time, the main component of the metal exposed from the coating layer 28 is desirably Cu. This is because the connection resistance can be reduced.

Further, a roughened layer 23a may be provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. For this reason, the adhesion between the chip capacitor 20 made of ceramic and the resin insulating layer 40 made of resin is high, and the resin insulating layer 40 does not peel off at the interface even when the heat cycle test is performed. This roughened layer 23a
Can be formed by polishing the surface of the chip capacitor 20 after firing, and by performing a roughening process before firing. In the present embodiment, the surface of the capacitor is subjected to a roughening treatment to improve the adhesiveness with the resin, but instead, the surface of the capacitor may be subjected to a silane coupling treatment.

Subsequently, a method of manufacturing the printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.

(1) First, a core substrate 30 made of an insulating resin substrate is used as a starting material (see FIG. 1A). Next, a concave portion 32 for disposing a capacitor is formed on one surface of the core substrate 30 by counterbore processing (see FIG. 1B). At this time, the recess 32 is formed to be wider and larger than an area where a plurality of capacitors can be arranged. Thereby, a plurality of capacitors can be securely arranged on the core substrate 30.

(2) Thereafter, an adhesive material 34 is applied to the recess 32 using a printing machine (see FIG. 1C). At this time, potting may be performed in addition to the application. The adhesive material 34 has a smaller coefficient of thermal expansion than the core substrate 30 and the resin insulating layer 40. Next, a plurality of ceramic chip capacitors 20 (FIG.
Is mounted on the adhesive material 34 (see FIG. 1D). Here, as described later, by disposing a plurality of chip capacitors 20 in the recess 32 having a smooth bottom,
Since the plurality of chip capacitors 20 have the same height, the core substrate 30 can be smoothed. In addition, since the concave portion 32 is formed widely, the chip capacitor 20 can be accurately positioned and can be arranged at a high density.

(3) Then, the upper surfaces of the chip capacitors 20 are pressed or hit so that the upper surfaces of the plurality of chip capacitors 20 have the same height, and the heights are made uniform (FIG. 2).
(A)). By this step, when a plurality of chip capacitors 20 are arranged in the recess 32, even if the sizes of the plurality of chip capacitors 20 vary, the heights can be completely made uniform, and the core substrate 30 Can be smoothed.

(4) After that, a thermosetting resin is filled between the chip capacitors 20 in the concave portions 32, and heat-cured to form a resin layer 36 (see FIG. 2B). At this time, as the thermosetting resin, epoxy, phenol, polyimide, and triazine are preferable. Thus, the chip capacitor 20 in the recess 32 can be fixed. The resin layer 36 has a smaller coefficient of thermal expansion than the core substrate 30 and the resin insulating layer 40.

In addition, a resin such as a thermoplastic resin may be used. In addition, a filler may be impregnated in the resin in order to match the coefficient of thermal expansion. Examples of the filler include an inorganic filler, a ceramic filler, and a metal filler.

(5) Further, a resin made of an epoxy resin to be described later is applied from above using a printing machine to form a resin insulating layer 40 (see FIG. 2C). Note that a resin film may be attached instead of applying the resin.

Other than the above, a thermosetting resin, a thermoplastic resin, a photosensitive resin, a composite of a thermosetting resin and a thermoplastic resin,
One or more resins such as a composite of a photosensitive resin and a thermoplastic resin can be used. They may have a two-layer structure.

(6) Next, the resin insulating layer 40 is formed by laser.
Then, a via hole opening 48 is formed (see FIG. 2D). After that, desmear processing is performed. Exposure and development processing can be used instead of laser. Then, a through hole 46a for a through hole is formed in the resin layer 36 by a drill or a laser, and is cured by heating (see FIG. 3A).
Desmear treatment by a chemical solution such as permanganate or plasma treatment may be performed.

(7) Thereafter, a copper plating film 52 is formed on the surface of the resin insulating layer 40 by electroless copper plating (FIG. 3).
(B)). Instead of electroless plating, sputtering using a Ni-Cu alloy as a target is performed, and Ni-C
A u-alloy layer may be provided, and in some cases, an electroless plating film may be formed after being formed by sputtering.

(8) Next, a photosensitive dry film is stuck on the surface of the copper plating film 52, a mask is placed, exposure and development are performed, and a resist 54 having a predetermined pattern is formed. Then, the core substrate 30 is immersed in the electrolytic plating solution, and a current is passed through the copper plating film 52 to deposit the electrolytic plating film 56 (see FIG. 3C).

(9) Next, 5% of plating resist 54
After stripping and removing with NaOH, the copper plating film 52 under the plating resist 54 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and a conductor circuit 58 including the copper plating film 52 and the electrolytic copper plating film 56 is formed. (Including via holes 60) and through holes 46 are formed. Here, by forming the through hole 46, the chip capacitor 2 is formed.
Since the signal line does not pass through 0, reflection due to impedance discontinuity due to the high dielectric substance and propagation delay due to passage through the high dielectric substance do not occur. Next, by spraying an etchant on both surfaces of the substrate by spraying, and etching the surface of the conductor circuit 58 and the land surface of the through hole 46,
A roughened surface 58α is formed on the entire surface of the conductor circuit 58 (FIG. 3)
(D)).

(10) Thereafter, a resin filler 62 containing an epoxy resin as a main component is filled in the through hole 46 and dried (see FIG. 4A). A thermosetting resin, a thermoplastic resin, an ultraviolet curable resin, or the like can be used.
Among them, it is desirable to use a thermosetting resin. This is because when filling the through holes, it is easy to handle.

(11) A thermosetting epoxy resin sheet having a thickness of 50 μm is placed on both sides of the substrate having undergone the above steps at a temperature of 50 μm.
Vacuum compression bonding is performed at a pressure of 5 kg / cm ² while the temperature is raised to 150 ° C. to provide an interlayer resin insulating layer 50 made of an epoxy resin (see FIG. 4B). The degree of vacuum during vacuum compression is 10 mmHg. An olefin resin may be used instead of the epoxy resin.

(12) Next, CO ² having a wavelength of 10.4 μm is used.
Using a gas laser, beam diameter 5 mm, top hat mode, pulse width 5.0 μsec, mask hole diameter 0.5 mm,
Under the conditions of the shot, the interlayer resin insulating layer 50 has a diameter of 80 μm.
(See FIG. 4C). Thereafter, desmear treatment is performed using oxygen plasma.

(13) Next, plasma treatment is performed using SV-4540 manufactured by Japan Vacuum Engineering Co., Ltd. to roughen the surface of the interlayer resin insulation layer 50 to form a roughened surface 50α (FIG. 4D )reference). At this time, argon gas was used as the inert gas, electric power 200 W, gas pressure 0.6 Pa,
Plasma treatment is performed at a temperature of 70 ° C. for 2 minutes.
Roughening treatment may be performed with an acid or an oxidizing agent. Further, the thickness of the roughened layer is desirably 0.1 to 5 μm.

(14) Next, after replacing the argon gas inside using the same apparatus, sputtering using a Ni—Cu alloy as a target was performed at a pressure of 0.6 Pa and a temperature of 80 Pa.
Temperature, power 200W, time 5 minutes, Ni-C
The u alloy 152 is formed on the surface of the interlayer resin insulation layer 50.
At this time, the thickness of the formed Ni—Cu alloy layer 152 is 0.2 μm (see FIG. 5A).

(15) A commercially available photosensitive dry film is stuck on both surfaces of the substrate 30 after the above-mentioned processing, a photomask film is placed, and exposure is performed at 100 mJ / cm ^2. Develop with sodium, thickness 15
A μm plating resist 154 is provided. Next, electrolytic plating is performed under the following conditions to form an electrolytic plated film 156 having a thickness of 15 μm (see FIG. 5B). The electrolytic plating film 156 allows the conductor circuit 158 to be formed in a process described later.
That is, thickening of the portion to be formed and plating filling of the portion to be the via hole 160 are performed. The additive in the electrolytic plating aqueous solution is Capparaside HL manufactured by Atotech Japan.

[Electroplating aqueous solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (Capparaside HL, manufactured by Atotech Japan) 19.5 ml / l [Electroplating conditions] Current density 1 A / dm ² Time 65 minutes Temperature 22 ± 2 ℃

(16) The plating resist 154 is made of 5% Na
After stripping off with OH, the Ni-
The Cu alloy layer 152 is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide to form a 16 μm-thick conductor circuit 158 and a via hole 160 composed of the Ni—Cu alloy layer 152 and the electrolytic plating film 156. (See FIG. 5C).

(17) Next, the above (11) to (16)
Is repeated to form a further upper interlayer resin insulation layer 150 and conductive circuit 258 (via hole 260
(See FIG. 5D).

(18) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight was used. Oligomer for imparting properties (molecular weight 4000) 46.67
15 parts by weight, 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.), imidazole curing agent (trade name: 2E4MZ-CN manufactured by Shikoku Chemicals Co., Ltd.)
1.6 parts by weight, 3 parts by weight of a polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., trade name: R604) as a photosensitive monomer,
Also polyvalent acrylic monomer (Kyoei Chemical Co., Ltd., trade name:
1.5 parts by weight of DPE6A) and 0.71 part by weight of a dispersant antifoaming agent (manufactured by San Nopco, trade name: S-65) are placed in a container, stirred and mixed to prepare a mixed composition. Of benzophenone (manufactured by Kanto Kagaku) and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to give a viscosity of 25.
A solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s at ° C is obtained. The viscosity was measured using a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm and rotor No. 4 at 6 rpm.
According to

(19) Next, the solder resist composition is applied on both surfaces of the substrate 30 to a thickness of 20 μm.
After performing a drying process at 20 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a 5 mm-thick photomask on which a pattern of the solder resist resist opening is drawn is brought into close contact with the solder resist layer 70 to have a thickness of 1000 mJ / cm ^2. Exposure with ultraviolet light and development processing with a DMTG solution are performed to form openings 71U and 71D having a diameter of 200 μm (see FIG. 6A).
Further, a commercially available solder resist such as LPSR may be used.

(20) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 was formed was replaced with nickel chloride (2.3 × 10 ^-1 mol / l) and sodium hypophosphite (2.8 × 10 ^-1 mol / l). 10 ^-1 mol / l) and an electroless nickel plating solution having a pH of 4.5 containing sodium citrate (1.6 × 10 ^-1 mol / l) for 20 minutes.
A nickel plating layer 72 having a thickness of 5 μm is formed on U and 71D. Further, the substrate was coated with potassium potassium cyanide (7.
6 × 10 ⁻³ mol / l), ammonium chloride (1.9 × 10 ⁻³ mol / l)
10 ^-1 mol / l), sodium citrate (1.2 × 1
0 ^-1 mol / l), sodium hypophosphite (1.7 × 1
( ^0.1 mol / l) at 80 ° C. for 7.5 minutes to form a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 72. The solder pads 75 are formed in the holes 260 and the conductor circuits 258 (see FIG. 6B).

(21) Thereafter, the solder resist layer 70
The solder bumps (solder bodies) 76U and 76D are formed by printing a solder paste on the openings 71U and 71D of the solder paste and performing reflow at 200 ° C. Thereby, the printed wiring board 10 having the solder bumps 76U and 76D can be obtained (see FIG. 7).

Next, mounting of the IC chip on the printed wiring board 10 completed in the above-described steps and mounting on the daughter board will be described with reference to FIG. The IC chip 9 is placed so that the solder pads 92 of the IC chip 90 correspond to the solder bumps 76U of the completed printed wiring board 10.
The IC chip 90 is mounted by placing the “0” and performing reflow. Similarly, the printed wiring board 10 is attached to the daughter board 94 by reflowing so that the pads 95 of the daughter board 94 correspond to the solder bumps 76D of the printed wiring board 10.

The above-mentioned resin film includes a hardly soluble resin,
Contains soluble particles, hardeners and other components.
Each is described below.

The resin film used in the production method of the present invention comprises particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble particles”) in a resin which is hardly soluble in an acid or an oxidizing agent (hereinafter referred to as a “slightly soluble resin”). It is dispersed. The terms “sparingly soluble” and “soluble” as used in the present invention, when immersed in a solution containing the same acid or oxidizing agent for the same time, have a relatively high dissolution rate and are called “soluble” for convenience. Those having a relatively low dissolution rate are referred to as "poorly soluble" for convenience.

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and an acid or an oxidizing agent. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In the present invention, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

Further, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

The above-mentioned soluble inorganic particles include, for example, particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

The soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin film can be ensured, and thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed by using an acid or an oxidizing agent in the interlayer resin insulating layer. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, an opening for a via hole can be formed in an interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, polyimide resin,
Examples thereof include polyphenylene resin, polyolefin resin, and fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolak type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolak type epoxy resin, alkylphenol novolak type epoxy resin, biphenol F type epoxy resin, and naphthalene type epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin film used in the present invention, it is desirable that the soluble particles are substantially uniformly dispersed in the hardly-soluble resin. It is possible to form a roughened surface with unevenness of uniform roughness, and even if via holes and through holes are formed in the resin film, it is possible to secure the adhesion of the metal layer of the conductor circuit formed thereon. Because you can. Alternatively, a resin film containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby,
Since the portions other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin film, the amount of the soluble particles dispersed in the poorly soluble resin is desirably 3 to 40% by weight based on the resin film. If the amount of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities. If the amount exceeds 40% by weight, the soluble particles may be dissolved using an acid or an oxidizing agent. In addition, there is a case where the resin film is melted to a deep portion of the resin film and the insulation between the conductor circuits via the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.

The resin film desirably contains a curing agent and other components in addition to the soluble particles and the hardly soluble resin. As the curing agent, for example,
Imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and microcapsules of these curing agents, and organic materials such as triphenylphosphine, tetraphenylphosphonium, and tetraphenylborate. Phosphine compounds and the like can be mentioned.

The content of the curing agent is desirably 0.05 to 10% by weight based on the resin film. 0.
If the amount is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidizing agent into the resin film is increased, and the insulating property of the resin film may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

The other components include, for example, fillers such as inorganic compounds or resins which do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the printed wiring board can be improved by matching the thermal expansion coefficient, improving heat resistance and chemical resistance, and the like.

Further, the resin film may contain a solvent. As the solvent, for example, acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Ethyl acetate, butyl acetate, cellosolve acetate, and aromatic hydrocarbons such as toluene and xylene. These may be used alone or in combination of two or more.

Next, a printed wiring board 110 according to a second embodiment of the present invention will be described with reference to FIG. In the first embodiment described above, the case where the BGA is provided has been described. The second embodiment is almost the same as the first embodiment, but is configured as a PGA system in which connection is made via conductive connection pins 96 as shown in FIG.

Next, a method of manufacturing the printed wiring board described above with reference to FIG. 15 will be described with reference to FIGS.

(1) First, a through hole 37a for accommodating a chip capacitor is formed in a laminate 31α formed by laminating four prepregs 33 impregnated with epoxy resin. On the other hand, a laminate 3 formed by laminating two prepregs 33
1β is prepared (see FIG. 9A). Here, as the prepreg 33, a material containing a reinforcing material such as BT, phenol resin, or glass cloth in addition to epoxy can be used. By forming the through holes 37a for accommodating the chip capacitors widely, it becomes possible to securely accommodate the plurality of chip capacitors 20 in the concave portions 37 in a process described later.

(2) Next, the laminated plate 31α and the laminated plate 31β
The core substrate 31 provided with the concave portion 37 capable of accommodating the plurality of chip capacitors 20 is formed by press-bonding, heating, and curing (see FIG. 9B).

(3) Then, the adhesive material 34 is applied to the concave portion 37 at the position where the capacitor is provided by using a printing machine. Thereafter, the chip capacitor 20 made of a plurality of ceramics is accommodated in the recess 37 via the adhesive material 34 (FIG. 9).
(C)). Here, a plurality of chip capacitors 20
By disposing in the concave portion 37, the height of the plurality of chip capacitors 20 becomes uniform, so that the core substrate 31 can be smoothed. Further, since the concave portion 37 is formed widely, the chip capacitor 20 can be accurately positioned and can be arranged at a high density. Therefore, the resin layer can be formed to a uniform thickness on the core substrate, and the via holes can be appropriately formed on the core substrate 31 as described later. Becomes possible.

(4) Then, the upper surfaces of the chip capacitors 20 are pressed or hit so that the upper surfaces of the plurality of chip capacitors 20 have the same height, and the heights are made uniform. (FIG. 9
(D)). By this process, when a plurality of chip capacitors 20 are arranged in the recess 37, even if the sizes of the plurality of chip capacitors 20 vary, the heights can be made uniform and the core 31 substrate can be smoothed. Can be

(5) Thereafter, a space between the chip capacitors 20 in the recesses 37 is filled with a thermosetting resin, and heat-cured to form a resin layer 36 (see FIG. 10A). At this time,
As the thermosetting resin, epoxy, phenol, polyimide, and triazine are preferable. Thereby, the chip capacitor 20 in the concave portion 37 can be fixed.

(6) Further, the above-mentioned epoxy resin or polyolefin resin is applied thereon from above using a printing machine to form a resin insulating layer 40 (see FIG. 10B). Note that a resin film may be attached instead of applying the resin.

(7) Next, a via hole opening 48 is formed in the resin insulating layer 40 by exposure / development processing or laser (see FIG. 10C). Then, a through hole 46a for a through hole is formed in the resin layer 36 by a drill or a laser, and is cured by heating (see FIG. 10D).

(8) After applying a palladium catalyst to the substrate 31, the core substrate is immersed in an electroless plating solution.
The electroless plating film 53 is uniformly deposited (FIG. 11A)
reference). Here, electroless plating is used, but a metal layer such as copper or nickel may be formed by sputtering. In some cases, the electroless plating film may be formed after the formation by sputtering.

(9) Then, a photosensitive dry film is attached to the surface of the electroless plating film 53, a mask is placed, and exposure and development are performed to form a resist 54 having a predetermined pattern. Then, the core substrate 31 is immersed in the electrolytic plating solution, and a current is passed through the electroless plating film 53 to deposit the electrolytic plating film 56 (see FIG. 11B).

(10) After the above steps, the resist 54
% NaOH, the electroless plating film 53 under the resist 54 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and a conductor circuit 58 (electroless plating film 53 and electrolytic copper plating film 56) Via holes 60) and through holes 46 are formed. Here, the through hole 46
Is formed, the signal line does not pass through the chip capacitor 20, so that reflection due to impedance discontinuity due to the high dielectric substance and propagation delay due to passage through the high dielectric substance do not occur.

(11) Then, the substrate 31 is washed with water and acid degreased, and then soft-etched. Then, an etching solution is sprayed on both surfaces of the substrate 31 by spraying, and the conductive circuit 5
8 and the land surface and the inner wall of the through hole 46 are etched to form a roughened surface 58α on the entire surface of the conductor circuit 58 (see FIG. 11C). As an etching solution, an etching solution (Mec etch bond, manufactured by Mec Co.) consisting of 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride is used.

(12) Next, bisphenol F type epoxy
Simonomer (manufactured by Yuka Shell Co., molecular weight: 310, YL9
83U) 100 parts by weight, silane coupling agent on the surface
The average coated particle size is 1.6 μm and the largest particle
Having a diameter of 15 μm or less _Two Spherical particles (Adtech
CRS 1101-CE) 170 parts by weight and
Belling agent (Perenol S4 manufactured by San Nopco) 1.5
Put the parts by weight in a container, stir and mix to
Resin filler 62 having a degree of 23 ± 1 ° C. and 45-49 Pa · s
Is prepared. In addition, as a curing agent, an imidazole curing agent
(Shikoku Chemicals, 2E4MZ-CN) 6.5 parts by weight
Was. After that, the resin filler 62 is placed in the through hole 46.
Fill and dry (see FIG. 11D).

(13) Next, 30 parts by weight of a bisphenol A type epoxy resin (epoxy equivalent: 469, manufactured by Yuka Shell Epoxy Co., Ltd.) and a cresol novolak type epoxy resin (epoxy equivalent: 215, epicron manufactured by Dainippon Ink & Chemicals, Inc.) N-673) 40 parts by weight, triazine structure-containing phenol novolak resin (phenolic hydroxyl equivalent 120, phenolite KA-7052 manufactured by Dainippon Ink and Chemicals, Inc.) 30 parts by weight, ethyl diglycol acetate 20 parts by weight, solvent naphtha 20 parts by weight The mixture was heated and dissolved while stirring, and 15 parts by weight of a terminal epoxidized polybutadiene rubber (Denalex R-45EPT manufactured by Nagase Kasei Kogyo Co., Ltd.) and 2-phenyl-4,
5-bis (hydroxymethyl) imidazole pulverized product
5 parts by weight, 2 parts by weight of finely divided silica, and 0.5 part by weight of a silicon-based antifoaming agent are added to prepare an epoxy resin composition.
The resulting epoxy resin composition is applied on a 38 μm-thick PET film using a roll coater so that the thickness after drying becomes 50 μm, and then dried at 80 to 120 ° C. for 10 minutes to form an interlayer resin. A resin film for an insulating layer is produced.

(14) On both surfaces of the substrate, a resin film for an interlayer resin insulating layer slightly larger than the substrate 31 prepared in (13) is placed on the substrate 31, and the pressure is 4 kgf / cm ² , the temperature is 80 ° C., and the pressure is crimped. After temporarily compressing and cutting under the condition of a time of 10 seconds, the interlayer resin insulating layer 50 is formed by sticking using a vacuum laminator device by the following method (see FIG. 12A). That is, a resin film for an interlayer resin insulating layer is formed on the substrate 31 with a degree of vacuum of 0.5 Torr.
r, pressure 4 kgf / cm ² , temperature 80 ° C, pressure bonding time 60
The main bonding is performed under the condition of seconds, and then, the thermosetting is performed at 170 ° C. for 30 minutes.

(15) Next, on the interlayer resin insulation layer 50,
Mask 47 having a through hole 47a having a thickness of 1.2 mm
Through a CO ₂ gas laser with a wavelength of 10.4 μm,
A via hole opening 148 having a diameter of 80 μm is formed in the interlayer resin insulating layer 50 under the conditions of a beam diameter of 4.0 mm, a top hat mode, a pulse width of 8.0 μsec, a diameter of a through hole of the mask of 1.0 mm, and one shot. (See FIG. 12B).

(16) The substrate 31 having the via hole opening 148 formed thereon is washed with 80 g containing 60 g / l of permanganate.
C. for 10 minutes by dissolving and removing the epoxy resin particles present on the surface of the interlayer resin insulating layer 50, thereby making the surface of the interlayer resin insulating layer 50 including the inner wall of the via hole opening 148 a roughened surface 50α. (See FIG. 12C). Roughening treatment may be performed with an acid or an oxidizing agent. Further, the thickness of the roughened layer is desirably 0.1 to 5 μm.

(17) Next, the substrate 31 after the above processing is completed
Is immersed in a neutralizing solution (manufactured by Shipley) and then washed with water. Further, by applying a palladium catalyst to the surface of the substrate 31 which has been subjected to a surface roughening treatment (roughening depth: 3 μm),
Surface of interlayer resin insulation layer 50 and opening 1 for via hole
A catalyst nucleus is attached to the inner wall surface of 48.

(18) Next, the substrate is immersed in an electroless copper plating aqueous solution having the following composition to form an electroless copper plating film 153 having a thickness of 0.6 to 3.0 μm over the roughened surface 50α. (See FIG. 12D). [Electroless plating aqueous solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α'-bipyridyl 40 mg / l Polyethylene glycol (PEG) 0.10 g / l [Electroless plating conditions] 40 minutes at a liquid temperature of 35 ° C

(19) A commercially available photosensitive dry film is attached to the electroless copper plating film 153, and a mask is placed thereon.
Exposure is performed at 100 mJ / cm ² and development processing is performed using a 0.8% aqueous sodium carbonate solution to provide a plating resist 154 having a thickness of 30 μm (see FIG. 13A).

(20) Next, the substrate 31 is washed with water at 50 ° C., degreased, washed with water at 25 ° C., further washed with sulfuric acid, and then subjected to electrolytic plating under the following conditions to obtain a film having a thickness of 20 mm.
Forming a μm electrolytic copper plating film 156 (FIG. 13B)
reference). [Electroplating aqueous solution] sulfuric acid 2.24 mol / l copper sulfate 0.26 mol / l additive 19.5 ml / l (manufactured by Atotech Japan, Capparaside HL) [electroplating conditions] current density 1 A / dm ² hours 65 minutes Temperature 22 ± 2 ℃

(21) The plating resist 154 is made of 5% Na
After stripping off with OH, the electroless copper plating film 153 under the plating resist 154 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide.
3 and an electrolytic copper plating film 156 to form a conductor circuit 158 (including a via hole 160) having a thickness of 18 μm.
Thereafter, the same treatment as in (11) is performed, and the roughened surface 158 is formed by an etching solution containing a cupric complex and an organic acid.
is formed (see FIG. 13C).

(22) Subsequently, the above (14) to (21)
By repeating the above steps, the upper interlayer resin insulation layer 150 and the conductor circuit 258 (including the via hole 160) are further formed (see FIG. 13D).

(23) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight was used. Oligomer for imparting properties (molecular weight 4000) 46.67
15 parts by weight, 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.), imidazole curing agent (trade name: 2E4MZ-CN manufactured by Shikoku Chemicals Co., Ltd.)
1.6 parts by weight, 4.5 parts by weight of a photosensitive monomer, bifunctional acrylic monomer (manufactured by Kyoei Chemical Co., trade name: R604), and similarly polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., trade name: DPE6A) 5 parts by weight and 0.71 part by weight of a dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) are placed in a container, and the mixture is stirred and mixed to prepare a mixed composition. 2.0 parts by weight of benzophenone (manufactured by Kanto Kagaku) as a weight initiator and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to give a viscosity of 2 parts.
A solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s at 5 ° C. is obtained. In addition, the viscosity was measured by B
60 rpm with a type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.)
In the case of rotor No. 4 and in the case of 6 rpm the rotor No.
According to 3.

(24) Next, on both sides of the multilayer wiring board,
20 μm of the solder resist composition prepared in (23)
Apply with a thickness of Then, at 70 ° C for 20 minutes at 70 ° C
After performing a drying process under the condition of for 30 minutes, a 5 mm-thick photomask on which the pattern of the opening of the solder resist is drawn is brought into close contact with the solder resist composition, and the
The substrate is exposed to ultraviolet rays of mJ / cm ² and developed with a DMTG solution to form openings 71U and 71D having a diameter of 200 μm. Then, the solder resist composition is further cured by heating at 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours, and has openings 71U and 71D. Then, a solder resist layer 70 having a thickness of 20 μm is formed (see FIG. 14A).
As the solder resist composition, a commercially available solder resist composition can be used.

(25) Next, the substrate on which the solder resist layer 70 is formed is coated with nickel chloride (2.3 × 10 ^-1 mol).
/ L), sodium hypophosphite (2.8 × 10 ^-1 mol)
/ L), sodium citrate (1.6 × 10 ^-1 mol /
2) in the electroless nickel plating solution having pH = 4.5 containing l)
By immersing for 0 minute, a nickel plating layer 72 having a thickness of 5 μm is formed in the openings 71U and 71D. Furthermore, the substrate gold potassium cyanide ^{(7.6 × 10 -3 mol / l} ), ammonium chloride ^{(1.9 × 10 -1 mol / l} ), sodium citrate (1.2 × 10 ^-1 mol / l), immersed in an electroless gold plating solution containing sodium hypophosphite (1.7 × 10 ^-1 mol / l) at 80 ° C. for 7.5 minutes to form a layer having a thickness of A gold plating layer 74 of 0.03 μm is formed (see FIG. 14B).

(26) Thereafter, tin-tin is inserted into the opening 71U of the solder resist layer 70 on the surface of the substrate on which the IC chip is to be mounted.
Print solder paste containing lead. Further, a solder paste is printed as the conductive adhesive 97 in the opening 71D on the other surface. Next, the conductive connection pin 96 is attached to and supported by a suitable pin holding device, and the fixing portion 98 of the conductive connection pin 96 is brought into contact with the conductive adhesive 97 in the opening 71D. Then, reflow is performed to fix the conductive connection pins 96 to the conductive adhesive 97. Also, the conductive connection pins 9
As a method of attaching 6, the conductive adhesive 97 formed in a ball shape or the like is put into the opening 71D, or the conductive adhesive 97 is joined to the fixing portion 98 to attach the conductive connection pin 96. , And then reflow.

Thereafter, the opening 71 of the printed wiring board 110 is
Solder pad 9 of IC chip 90 is attached to U-side solder bump 76.
The IC chip 90 is mounted so that the two correspond to each other, and the IC chip 90 is mounted by performing reflow (FIG. 1).
5).

Subsequently, a manufacturing method according to a modification of the printed wiring board of the second embodiment will be described with reference to FIG. (1) First, a through hole 37a for accommodating a chip capacitor is formed in a laminated plate 31α in which four prepregs 33 impregnated with epoxy resin are laminated and cured. On the other hand, a sheet 31γ made of uncured prepreg 33,
A plate 31β obtained by curing the prepreg 33 is prepared (see FIG. 16A).

(2) Next, the laminated plate 31α and the plate 31β are pressure-bonded with a sheet 31γ, and the substrate 31
Is formed (see FIG. 16B).

(3) Then, the chip capacitors 20 made of a plurality of ceramics are housed on a sheet 31γ made of the uncured prepreg 33 (see FIG. 16C).

(4) Then, the upper surfaces of the chip capacitors 20 are pushed or hit so that the upper surfaces of the plurality of chip capacitors 20 have the same height, and the heights are made uniform (FIG. 2).
(A)). Then, heat and cure the uncured prepreg 3
A core substrate 31 for hardening 3 is formed. The following steps are the same as those in the second embodiment described above with reference to FIGS.

Subsequently, a printed wiring board according to a third embodiment of the present invention will be described with reference to FIG. In the first embodiment described above, only the chip capacitor 20 housed in the core substrate 30 is provided. In the third embodiment, a large-capacity chip capacitor 98 is mounted on the front and back surfaces.

The IC chip instantaneously consumes a large amount of power and performs complicated arithmetic processing. Here, in order to supply large power to the IC chip side, in the third embodiment, the printed circuit board is provided with a chip capacitor 20 and a chip capacitor 98 for power supply. The effect of this chip capacitor will be described with reference to FIG.

FIG. 19 shows the voltage supplied to the IC chip on the vertical axis and the time on the horizontal axis. Here, the two-dot chain line C
Indicates voltage fluctuation of a printed wiring board without a power supply capacitor. When the power supply capacitor is not provided, the voltage greatly decreases. A broken line A indicates a voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. Although the voltage does not drop much as compared with the two-dot chain line C, the rate-limiting power supply cannot be performed sufficiently because the loop length is long. That is, the voltage drops at the start of power supply. The two-dot chain line B indicates the voltage drop of the printed wiring board having the chip capacitor described above with reference to FIG. Although the loop length has been shortened,
Since a large-capacity chip capacitor cannot be accommodated in the core substrate 30, the voltage fluctuates. here,
The solid line E indicates the voltage fluctuation of the printed wiring board according to the third embodiment in which the chip capacitor 20 in the core substrate described above with reference to FIG. 18 and the large-capacity chip capacitor 98 are mounted on the surface. By providing the chip capacitor 20 near the IC chip and the chip capacitor 98 having a large capacity (and a relatively large inductance), voltage fluctuations are minimized.

Next, the configuration of a printed wiring board according to a fourth embodiment of the present invention will be described with reference to FIG. The configuration of the printed wiring board of the fourth embodiment is substantially the same as that of the above-described first embodiment. However, the core substrate 3
The chip capacitors 20 housed to 0 are different. FIG.
0 shows a plan view of the chip capacitor. FIG.
(A) shows a chip capacitor for multi-piece cutting before cutting, and a dashed line in the drawing shows a cutting line. In the printed wiring board of the first embodiment described above, the first electrode 21 and the second electrode 22 are provided on the side edges of the chip capacitor as shown in the plan view of FIG. FIG. 20 (C)
Indicates a chip capacitor for multi-cavity before cutting in the fourth embodiment, and a dashed line in the drawing indicates a cutting line. In the printed wiring board of the fourth embodiment, FIG.
As shown in the plan view, a first electrode 21 and a second electrode 22 are provided inside the side edge of the chip capacitor.

In the printed wiring board according to the fourth embodiment,
Since the chip capacitor 20 having the electrode formed inside the outer edge is used, a large-capacity chip capacitor can be used. Subsequently, a printed wiring board according to a first modification of the fourth embodiment will be described with reference to FIG.
FIG. 21 is a plan view of the chip capacitor 20 housed in the core substrate of the printed wiring board according to the first modification. In the above-described first embodiment, a plurality of small-capacity chip capacitors are housed in the core substrate. In the first modification, a large-capacity large-format chip capacitor 20 is housed in the core substrate. Here, the chip capacitor 20 is
The electrode 21, the second electrode 22, the dielectric 23, and the first electrode 2
1, the first conductive film 24 connected to the first conductive film 24, the second conductive film 25 connected to the second electrode 22 side, and the upper and lower surfaces of the chip capacitor not connected to the first conductive film 24 and the second conductive film 25. And a connection electrode 27. The IC chip side and the daughter board side are connected via the electrodes 27.

In the printed wiring board of the first modification, a large-sized chip capacitor 20 is used, so that a large-capacity chip capacitor can be used. Further, since the large chip capacitor 20 is used, the printed wiring board does not warp even if the heat cycle is repeated.

A printed wiring board according to a second modification will be described with reference to FIG. FIG. 22 (A) shows a chip capacitor before cutting for multi-cavity cutting, in which a dashed line shows a normal cutting line, and FIG. 22 (B) shows a plan view of the chip capacitor. . As shown in FIG. 22B, in the second modification, a plurality of (three in the example in the figure) multi-chip chip capacitors are connected and used in a large format.

In the second modification, a large-sized chip capacitor 20 is used, so that a large-capacity chip capacitor can be used. Further, since the large chip capacitor 20 is used, the printed wiring board does not warp even if the heat cycle is repeated.

In the above-described fourth embodiment, the chip capacitor is built in the printed wiring board. However, instead of the chip capacitor, a plate-like capacitor in which a conductor film is provided on a ceramic plate can be used. .

Here, with respect to the printed wiring board of the first embodiment, the chip capacitor 20 embedded in the core substrate is used.
And the inductance of the chip capacitor mounted on the back surface of the printed wiring board (the surface on the daughter board side) are shown below. In case of single capacitor Embedded type 137pH Backside mounted type 287pH When 8 capacitors are connected in parallel Embedded type 60pH Backside mounted type 72pH As shown above, when using a single capacitor, it is connected in parallel to increase the capacity In addition, the inductance can be reduced by incorporating a chip capacitor.

Next, the result of the reliability test will be described. Here, the rate of change of the capacitance of one chip capacitor in the printed wiring board of the first embodiment was measured. Capacitance change rate (measuring frequency 100Hz) (measuring frequency 1kHz) Steam 168 hours: 0.3% 0.4% HAST 100 hours: -0.9% -0.9% TS 1000cycles: 1.1% 1.3%

In the Steam test, steam was applied and the humidity was kept at 100%. In the HAST test, the relative humidity was 100%,
It was left at an applied voltage of 1.3 V and a temperature of 121 ° C. for 100 hours. In the TS test, 30 minutes at -125 ° C and 30 minutes at 55 ° C
The test of standing for 1000 minutes was repeated 1000 times.

In the above reliability test, it was found that a printed wiring board having a built-in chip capacitor could achieve the same reliability as the existing surface mount type capacitor. As described above, in the TS test,
Due to the difference in the coefficient of thermal expansion between the capacitor made of ceramic and the core substrate 30 made of resin and the resin insulating layer 40, even if internal stress is generated, the first terminal 2
1. No disconnection between the second terminal 22 and the via hole 60, separation between the chip capacitor 20 and the resin insulation layer 40, no cracks in the resin insulation layer 40, and high reliability can be achieved for a long period of time. There was found.

[0137]

According to the present invention, as described above, since a plurality of recesses are formed and a plurality of capacitors are accommodated in the recesses, the plurality of capacitors can be accurately positioned even if the precision of counterboring is low. Thus, it is possible to dispose them at high density in the core substrate. In addition, since a plurality of capacitors are placed in the recess, the heights of the plurality of capacitors are uniform, so that the insulating layer on the capacitors can be made uniform in thickness. Therefore, the via hole and the conductor circuit can be appropriately formed, so that the defective product occurrence rate of the printed wiring board can be reduced.

Since the resin is filled between the core substrate and the capacitor, even if a stress caused by the capacitor or the like is generated, the stress is reduced and no migration occurs. Therefore, there is no influence such as peeling or melting of the connection portion between the electrode of the capacitor and the via hole. Therefore, desired performance can be maintained even if a reliability test is performed. Also, even when the capacitor is covered with copper, the occurrence of migration can be prevented.

[Brief description of the drawings]

FIGS. 1A, 1B, 1C, and 1D are manufacturing process diagrams of a printed wiring board according to a first embodiment of the present invention.

FIGS. 2A, 2B, 2C, and 2D are manufacturing process diagrams of a printed wiring board according to the first embodiment of the present invention.

FIGS. 3A, 3B, 3C, and 3D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 4A, 4B, 4C, and 4D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 5A, 5B, 5C, and 5D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 6A and 6B are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a sectional view of the printed wiring board according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a state in which an IC chip is mounted on the printed wiring board according to the first embodiment of the present invention.

FIGS. 9A, 9B, 9C, and 9D are manufacturing process diagrams of a printed wiring board according to the second embodiment of the present invention.

FIG. 10A, FIG. 10B, FIG. 10C, FIG.
It is a manufacturing process figure of the printed wiring board concerning a 2nd embodiment of the present invention.

FIG. 11A, FIG. 11B, FIG. 11C, and FIG.
It is a manufacturing process figure of the printed wiring board concerning a 2nd embodiment of the present invention.

FIGS. 12 (A), (B), (C), (D)
It is a manufacturing process figure of the printed wiring board concerning a 2nd embodiment of the present invention.

13 (A), (B), (C), (D)
It is a manufacturing process figure of the printed wiring board concerning a 2nd embodiment of the present invention.

FIGS. 14A and 14B are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a state in which an IC chip is mounted on a printed wiring board according to a second embodiment of the present invention.

FIG. 16A, FIG. 16B, FIG. 16C, FIG.
It is a manufacturing process figure of the printed wiring board concerning the modification of a 2nd embodiment of the present invention.

FIG. 17 is a sectional view of the chip capacitor according to the first embodiment of the present invention.

FIG. 18 is a sectional view of a printed wiring board according to a third embodiment.

FIG. 19 is a graph showing changes in supply voltage to an IC chip and time.

FIGS. 20A, 20B, 20C, and 20D are plan views of a chip capacitor of a printed wiring board according to a fourth embodiment.

FIG. 21 is a plan view of a chip capacitor of a printed wiring board according to a fourth embodiment.

FIG. 22 is a plan view of a chip capacitor of a printed wiring board according to a modification of the fourth embodiment.

[Explanation of symbols]

 Reference Signs List 20 chip capacitor 30 core substrate 31 core substrate 32 concave portion 36 resin layer 37 concave portion 40 interlayer resin insulating layer 46 via hole 50 interlayer resin insulating layer 58 conductive circuit 60 via hole 70 solder resist layer 71U, 71D opening 72 nickel plating layer 74 gold Plating layer 76 Solder bump 90 IC chip 92 Solder pad (IC chip side) 94 Daughter board 95 Solder pad (Daughter board side) 96 Conductive connection pin 97 Conductive adhesive 98 Fixing part 150 Interlayer resin insulation layer 158 Conductor circuit 160 Via hole 258 Conductor circuit 260 Via hole

Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court II (Reference) H05K 1/18 H01G 1/035 E 3/40 4/38 A (72) Inventor Wang East Winter Ibikawa-cho, Ibi-gun, Gifu Prefecture 1-1 Ibiden Co., Ltd. Ogaki-Kita Plant (72) Inventor Hideo Yabashi 1-1 Ibiden Ogigaki-Kita Plant, Gifu Pref. 1-1 F-term in the Ogaki-Kita Plant of Ibiden Co., Ltd. (Reference) CD27 CD32.

Claims (18)

[Claims] 1. A printed wiring board comprising a resin insulating layer and a conductor circuit laminated on a core substrate, wherein a concave portion is formed in the core substrate, and a plurality of capacitors are accommodated in the concave portion. A printed wiring board, characterized in that: 2. The method according to claim 1, wherein the plurality of capacitors in the concave portion include:
The printed wiring board according to claim 1, wherein the printed wiring board is filled with a resin having a smaller coefficient of thermal expansion than the core substrate. 3. A through hole is formed in the resin layer by forming a through hole.
A printed wiring board according to claim 1. 4. The printed wiring according to claim 1, wherein a metal film is formed on the electrode of the capacitor, and the electrode on which the metal film is formed is electrically connected to the electrode by plating. Board. 5. The printed wiring board according to claim 4, wherein the metal film formed on the electrode of the chip capacitor is a plating film mainly composed of copper. 6. The capacitor according to claim 1, wherein at least a part of the coating layer of the electrode of the capacitor is exposed, and the electrode exposed from the coating layer is electrically connected by plating. 2. The printed wiring board according to item 1. 7. A printed circuit board according to claim 1, wherein a capacitor is mounted on a surface of said printed wiring board.
A printed wiring board according to claim 1. 8. The printed wiring board according to claim 7, wherein the capacitance of the chip capacitor on the front surface is equal to or larger than the capacitance of the chip capacitor in the inner layer. 9. The printed wiring board according to claim 7, wherein the inductance of the chip capacitor on the front surface is equal to or larger than the inductance of the chip capacitor in the inner layer. 10. The printed wiring board according to claim 1, wherein a chip capacitor having an electrode formed inside an outer edge is used as the capacitor. 11. The printed wiring board according to claim 1, wherein a chip capacitor having electrodes formed in a matrix is used as said capacitor. 12. The printed wiring board according to claim 1, wherein a plurality of chip capacitors for multi-cavity are connected and used as the capacitor. 13. A method for manufacturing a printed wiring board, comprising at least the following steps (a) to (c): (a) forming a concave portion in a core substrate; (C) filling a resin between the capacitors. 14. After the step (b), pressure is applied from above to the upper surfaces of the plurality of capacitors in the concave portion,
14. The method for manufacturing a printed wiring board according to claim 13, further comprising a step of adjusting the height of the upper surface of the capacitor. 15. The method according to claim 13, further comprising, after the step (c), forming a through hole by forming a through hole in the resin layer. 16. A method for manufacturing a printed wiring board, comprising at least the following steps (a) to (d): (a) forming through holes in a resin material containing a resin as a core material; (B) attaching a resin material to the resin material having the through holes to form a core substrate having a concave portion; (c) placing a plurality of capacitors in the concave portion of the core substrate. (D) filling a resin between the capacitors. 17. After the step (c), a pressure is applied from above to an upper surface of the plurality of capacitors in the concave portion,
17. The method for manufacturing a printed wiring board according to claim 16, further comprising a step of adjusting the height of the upper surface of the capacitor. 18. The method according to claim 16, further comprising, after the step (d), forming a through hole by forming a through hole in the resin layer.