JP2003008239A - Multilayer printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board whose electrical connection properties and reliability are superior, without increasing an inductance portion or without causing supply shortage of electric power. SOLUTION: When terminals (electrodes) 98 for power supply are extracted from the side face of the multilayer printed wiring board 10, distances from an IC chip 112 to the terminals 98 can be shortened, an inductance is not increased, and an unstable operation and a malfunction which are caused by the shortage of the electric power are reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board in which interlayer resin insulation layers and conductor layers are alternately laminated on a core board and external board connecting terminals are arranged.
The present invention relates to a multilayer printed wiring board that can be used as a package substrate on which an IC chip is placed.

[0002]

2. Description of the Related Art Conventionally, build-up multilayer printed wiring boards have been manufactured, for example, by the method disclosed in JP-A-9-130050. A roughened layer is formed on the surface of the conductor circuit of the printed wiring board by electroless plating or etching. Thereafter, an interlayer insulating resin is applied by a roll coater or printing, exposed and developed to form a via hole opening for interlayer conduction, and UV curing and main curing are performed to form an interlayer resin insulating layer. Furthermore, in the interlayer resin insulation layer,
A catalyst such as palladium is attached to the roughened surface that has been roughened with an acid or an oxidizing agent. Then, a thin electroless plating film is formed, a pattern is formed on the plating film with a dry film, and after thickening with electrolytic plating, the dry film is peeled off with an alkali and etched to create a conductor circuit. . By repeating this, a build-up multilayer printed wiring board is obtained.

As a technique corresponding thereto, it has been considered to form a via hole with a laser by pressing a resin film obtained by semi-curing an interlayer insulating layer. An IC chip is mounted on the surface layer of the multilayer printed wiring board, and on the opposite surface, a BGA or PG that is an external board connection terminal.
A is provided.

[0004]

At present, as the frequency of IC chips increases, the power supply supplied to the multilayer printed wiring boards also increases proportionately. Therefore, there is a concern that power supply shortage may occur. In particular, it requires a large amount of power instantly at startup. It takes time for the electric power to make up for the shortage. The shortfall is compensated with the passage of time, but the time lag makes the operation unstable,
This causes a problem that the performance of the IC chip is not fully exhibited. In order to compensate for them, by mounting a capacitor on the surface layer of a multilayer printed wiring board, supplying the electric power charged in the capacitor and compensating for the shortage, the unstable operation due to the power shortage is eliminated. I was letting it. This will be described with reference to the figure. In FIG. 10, the vertical axis represents the voltage supplied to the IC chip and the horizontal axis represents time. If the capacitor is not mounted as shown by the dotted line A, the power is rapidly depleted at the same time as the operation of the IC chip, resulting in large attenuation. After that, with the lapse of time, the supply of the power supply catches up, so that the unstable operation is eliminated. In order to compensate for this, the instability of the operation caused by the power shortage that may occur during the initial operation is eliminated by discharging the electric power stored in the capacitor (see dotted line B).

However, the IC chip is 2 GHz, 3
In the high frequency region of GHz, a large amount of electric power is required to start up the computer, which causes a shortage of power supply, which may cause instability during operation. A dotted line C in FIG. 10 shows a case where a multilayer printed wiring board including a capacitor is operated at a high frequency. In particular, when the power supply is insufficient during the initial operation,
This will freeze the device itself such as a personal computer or mobile because it will hinder the startup of software.

In order to efficiently supply power to the multilayer printed wiring board, it is necessary to reduce the inductance. Therefore, the present inventor examined two methods. One is to increase the total capacitance of the capacitors.
The other is to shorten the distance from the IC chip to the capacitor to the power supply.

In the former method, in order to secure the total capacitance of the capacitors mounted on the surface of the multilayer printed wiring board, the number of capacitors mounted is increased or the capacitance of a single capacitor is increased. I did that. However, in order to do so, it is necessary to secure a space for mounting the capacitor C as shown in FIG. 9A, and the space for mounting the capacitor C is the area of the external board connecting terminal for drawing out the signal line L. Therefore, the wiring length of the signal line L also becomes long, which easily causes signal delay and the like, and there is a concern that the inductance may increase due to the wiring length.

In the latter method, as shown in FIG. 9 (B), the thickness of the multilayer printed wiring board 110 is reduced to shorten the wiring length for interlayer conduction, or as shown in FIG. 9 (C). The capacitor C is embedded in the printed wiring board 110 to reduce the inductance. However, as shown in FIG. 9C, if the insulating layer is thinned in order to reduce the thickness of the multilayer printed wiring board, it becomes difficult to secure the interlayer insulation and the strength of the substrate itself is reduced, which causes warpage and the like. There is a concern that the electrical connectivity and reliability will deteriorate. Further, when the capacitor is embedded as shown in FIG. 9C, it is feared that the necessary capacitance cannot be secured because the technique for embedding and the repair of the capacitor become impossible.

The present invention has been made in order to solve the above-mentioned problems, and an object of the present invention is to improve the electrical connectivity and reliability without increasing the inductance and causing a power supply shortage. It is to provide an excellent multilayer printed wiring board.

[0010]

To achieve the above object, in a multilayer printed wiring board according to a first aspect of the present invention, interlayer resin insulation layers and conductor layers are alternately laminated and external board connection terminals are provided. Another technical feature of the multilayer printed wiring board is that terminals or electrodes for power supply are provided on the side surface of the substrate.

In order to achieve the above object, in the multilayer printed wiring board according to the present invention, an interlayer resin insulating layer and a conductor layer are alternately laminated, and an external substrate connecting terminal is provided. A technical feature is that a through hole or a via hole is exposed on a side surface of the substrate and the exposed through hole or via hole is used as a terminal or an electrode for power supply.

In order to achieve the above-mentioned object, in a multilayer printed wiring board according to a third aspect of the present invention, an interlayer resin insulating layer and a conductor layer are alternately laminated and an external substrate connecting terminal is provided. The technical feature is that a through hole or a via hole filled with a conductive metal is exposed on the side surface of the substrate, and the exposed through hole or via hole is used as a terminal or an electrode for power supply. .

Since the distance from the IC chip to the capacitor (power supply terminal) can be shortened by pulling out the terminal or electrode for power supply from the side surface of the substrate, the inductance does not increase and the power is insufficient. The instability and erroneous operation caused by are reduced. It should be noted that the terminals or electrodes that require power supply are also formed on at least one surface, and may be formed on two or more surfaces.

The conductor layer of the terminal or electrode for power supply formed on the side surface of the substrate is formed by plating, conductive paste, or sputtering. On top of that, gold, silver,
A corrosion resistant metal such as nickel may be formed.

The through hole or the via hole may be exposed. As shown in FIG. 1, only the through hole 36 is used as a terminal (electrode) 98 for power supply. Alternatively, as shown in FIG. 3, only the via hole 60 is used as a terminal (electrode) 98 for power supply. Further, as shown in FIG. 4, it may be used as a terminal (electrode) 98 for power supply in a composite of the through hole 36 and the via hole 60.

At this time, a filling resin may be filled in the through hole or the via hole. The filling resin may be an insulating material or a conductive material. As the insulating material, any of thermosetting resin, photosensitive resin, and thermoplastic resin can be used. For example, an epoxy resin, a phenol resin, an olefin resin, a polyimide resin, or the like can be used. As the conductive material,
It is possible to use plating, a conductive paste, an insulating resin containing solder or metal particles, or the like. They may be used alone or as a composite resin layer of two or more kinds.

The interlayer connection is preferably made by a via hole. That is, via holes are formed in the interlayer insulating layer by laser or photo etching, a roughening layer is provided on the surface layer of the insulating layer to form a conductor layer, and the build-up multilayer printed wiring board is formed by repeating the formation of the conductor layer. It is what Either the semi-additive method or the full-additive method may be used.

Particularly, it is desirable that the conductor layers are provided on both surfaces of the substrate to be the core. As a result, the conductor layer of the terminals or electrodes for power supply formed on the side surface of the substrate can be formed on one side or both sides of the core substrate, and as shown in FIG. You can also do it. This is because the degree of freedom in design increases.

It is desirable that the terminals or electrodes for power supply are connected to the power supply layer provided on the inner layer of the wiring board. It is desirable that the core substrate be provided with terminals or electrodes for power supply. Furthermore, as shown in FIG. 2, it is more desirable that the core substrate 30 is connected to the power supply layer 52.

As a result, the distance from the power supply to the power supply terminal or electrode can be shortened, and the inductance is not increased. Since the power is supplied in the same layer, the concentration of electric power does not occur because it does not pass through the through holes and the via holes. Therefore, even if a large amount of electric power is supplied, no problem occurs. Therefore, unstable operation and malfunction do not occur.

It is desirable that a capacitor be mounted on the side surface. This makes it possible to supply electric power in the middle of the IC chip to the capacitor, and to reduce the amount of reduction when the voltage drops.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION A multilayer printed wiring board according to embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a perspective view of a multilayer printed wiring board according to the first embodiment. In the multilayer printed wiring board 10 of the first embodiment, the IC chip 112 is mounted on the upper surface by the flip chip, and the conductive connection pins 96 are mounted on the back surface. The multilayer printed wiring board 10 is provided with buildup layers 80A and 80B formed by laminating a plurality of interlayer resin insulation layers and conductor layers on both surfaces of the core substrate 30.
The upper and lower buildup layers 80A and 80B are connected to each other through the through holes provided in the. Through holes 36 are exposed on one or more side surfaces of the multilayer printed wiring board, and the through holes 36 form terminals (or electrodes) 98 for power supply.

FIG. 2A shows a power supply layer (solid layer) 52 formed on the upper surface of the core substrate 30 of the multilayer printed wiring board 10 shown in FIG. The power supply layer 52 is formed with through holes 52a for passing signal lines up and down.
The power supply layer 52 is connected to the terminal 98.

FIG. 2B shows a BB cross section of FIG. 2A. The power supplied from the terminal 98 is the power supply layer 5
2 and via the via hole 60 formed in the buildup layer 80A to the IC chip 112 at a short distance.

Subsequently, a method of manufacturing the multilayer printed wiring board of the first embodiment will be described. (1) 0.8mm thick glass epoxy resin, FR4, FR
The starting material was a copper clad laminate in which 18 μm copper foil was laminated on both sides of a substrate made of 5, or BT (bismaleimide triazine) resin. First, the copper clad laminate is patterned to form inner layer copper patterns on both surfaces of the substrate.

(2) After the substrate having the inner layer copper pattern formed thereon is washed with water, an etching solution containing a cupric complex and an organic acid is allowed to act under the oxygen coexisting conditions such as spraying and bubbling to make copper of the conductor circuit. A roughening layer is provided on the surface of the inner layer copper pattern by the process of melting the conductor to form voids.

Besides, a roughening layer may be provided by an oxidation-reduction treatment or an electroless plating alloy. The roughened layer formed is preferably in the range of 0.1 to 5 μm. This is because if it is within this range, the conductor circuit and the interlayer resin insulation layer are less likely to be peeled off, and even if the metal layer is removed by etching, it does not easily remain.

(3) On the surface of the substrate, a semi-cured resin film to be a lower interlayer resin insulation layer is placed at a temperature of 50 to 15
While heating up to 0 ° C., it is vacuum pressure-bonded and laminated at a pressure of 5 kgf / cm ² . Alternatively, it may be formed by applying a resin whose viscosity has been adjusted in advance to a state in which it can be applied by a roll coater, a caten coater or the like.

Specific examples of the interlayer resin insulation layer include, for example, epoxy resin, phenol resin, polyimide resin,
Examples thereof include polyphenylene resin, polyolefin resin, fluororesin, polyether sulfone, and phenoxy resin. These resins may be used alone or in combination of two or more.

In the resin film used in the present invention, it is desirable that the soluble particles are substantially uniformly dispersed in the sparingly soluble resin. It is possible to form a roughened surface having unevenness with a uniform roughness, and even if a via hole or a through hole is formed in the resin film, it is possible to secure the adhesion of the metal layer of the conductor circuit formed thereon. Because you can. Moreover, you may use the resin film which contains a soluble particle only in the surface layer part which forms a roughened surface. Thereby,
Since the parts other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulation layer is surely maintained.

It is desirable that the resin film contains a curing agent and other components in addition to the soluble particles and the poorly soluble resin.

(4) Subsequently, a through hole for a through hole having a diameter of 350 μm is formed by drilling in the core substrate to which the resin film is attached. A laser may be used instead of the drill.

(5) Then, an opening for via hole having a diameter of 80 μm is formed in the resin film by carbonic acid, excimer, YAG, or UV laser. Then, the resin film is thermoset to form a lower interlayer resin insulation layer. The via hole may be formed by laser area processing, or by mounting a mask and performing laser area processing. A mixed laser (meaning a combination of a carbon dioxide laser and an excimer laser) may be used. Both the through hole and the via hole may be formed by laser.

(6) Next, chromic acid or permanganate (potassium permanganate, sodium permanganate)
The through-hole through-holes formed in the core substrate and the lower interlayer resin insulation layer are desmeared by the oxidizer consisting of, and at the same time, the surface of the lower interlayer resin insulation layer is roughened.

(7) A palladium catalyst is applied to the surface of the roughened interlayer resin insulation layer to form an electroless copper plating film in an electroless plating aqueous solution. Although the electroless copper plating film is formed here, it is also possible to form a copper or nickel film by using sputtering. In addition, before forming the metal layer, plasma, as a dry treatment on the surface layer,
UV or corona treatment may be performed. This modifies the surface.

(8) After the substrate on which the electroless copper plating film is formed is washed with water, a plating resist having a predetermined pattern is formed. << Aqueous electroless plating solution >> EDTA: 150 g / l Copper sulfate: 20 g / l HCHO: 30 ml / l NaOH: 40 g / l Additive: 50 mg / l << Electroless plating conditions >> Liquid temperature 30 ° C., 45 minutes

(9) Then, the substrate is immersed in an electrolytic plating solution, and an electric current is passed through the electroless copper plated film to form an electrolytic copper plated film. <Electrolytic plating aqueous solution> Sulfuric acid: 150 g / l Copper sulfate: 160 g / l Leveling agent (polyoxyethylene compound): 30
ml / l Brightener (amine sulfonate compound): 0.8ml / l << Electrolytic plating conditions >> Current density: 1A / dm2 Time: 78min Temperature: 23 +/- 2 ℃

(10) The plating resist is stripped and removed with KOH, and the electroless copper plating film under the plating resist is stripped by light etching to form a via hole and a through hole formed of the electroless copper plating film and the electrolytic copper plating film. To form. The via hole has a field shape.

(11) The via hole and the through hole are formed by oxidation-reduction treatment. Instead of this oxidation-reduction treatment, etching (eg, etching by spraying or dipping with a solution containing a cupric complex and an organic acid salt) or a roughened layer (Cu-Ni- It is also possible to form a roughened layer by electroless plating of an alloy made of P).

(12) A resin filler is filled in the through holes and dried in a drying oven at a temperature of 100 ° C. for 20 minutes. Here, the following raw material composition can be used as the resin filler. [Resin composition] 100 parts by weight of bisphenol F-type epoxy monomer (Made by Yuka Shell, molecular weight 310, YL983U), SiO2 spherical particles with an average particle size of 1.6 μm coated with a silane coupling agent on the surface (Admatech, CRS
1101-CE, where the maximum particle size is not more than the thickness (15 μm) of the inner layer copper pattern described below) 170 parts by weight, and 1.5 parts by weight of a leveling agent (Panenol S4 manufactured by San Nopco) are mixed by stirring to obtain The viscosity of the mixture is 23 ±
It was obtained by adjusting to 360,000 to 49,000 cps at 1 ° C. [Curing agent composition] Imidazole curing agent (manufactured by Shikoku Kasei,
2E4MZ-CN) 6.5 parts by weight.

Further, the through hole used as the power source was filled with a conductive resin instead of the resin filler. A resin paste containing a conductive metal such as gold, silver, or copper, the viscosity of which was adjusted, was used. The filling was performed by printing in the same manner as the resin filler.

(13) One side of the substrate that has been subjected to the treatment of (12) is polished so as to smooth the surface of the resin filler protruding from the opening of the through hole 36, and then to remove scratches due to polishing. Buffing and polishing with a belt sander. Such a series of polishing is similarly performed on the other surface of the substrate. The polishing is carried out in a semi-cured state, but it may be carried out after it is completely cured. Then 100
The resin filler and the conductive paste were completely cured by heat treatment at 1 ° C. for 1 hour and at 150 ° C. for 1 hour.

The resin constituting the resin filler means an epoxy resin, a phenol resin, a fluororesin, a triazine resin, a polyolefin resin, a polyphenylene ether resin, etc., and is a thermosetting resin, a thermoplastic resin, or a composite thereof. Alternatively, an inorganic filler such as silica or alumina may be contained in the resin to adjust the coefficient of thermal expansion. Alternatively, a paste mainly containing a conductive resin, a conductive metal filler such as gold, silver, or copper may be used. Further, each of the above-mentioned composite materials may be used.

(14) A palladium catalyst is applied to the surface of the interlayer resin insulation layer to form an electroless copper plating film in an electroless plating aqueous solution. Although the electroless copper plating film is formed here, it is also possible to form the copper or nickel film by using sputtering.

(15) After forming a plating resist of a predetermined pattern, forming an electrolytic copper plating film, peeling and removing the plating resist, and removing the electroless copper plating film under the plating resist by etching, Lid plating composed of an electroless copper plating film and an electrolytic copper plating film is formed at the opening of the through hole. At this time, a power supply layer is formed and a terminal or an electrode portion that can be connected to the power supply layer is formed.

(16) Etching (an etching solution containing a cupric complex and an organic acid) is applied to the lid plating of the openings of the conductor circuit, the via holes and the through holes. Instead of this etching, a roughened layer (Cu-Ni-P) can be formed by electroless plating, or a roughened layer can be formed by an oxidation-reduction treatment.

(17) By repeating the above steps (3) to (11), an upper interlayer resin insulation layer is formed, and an electroless copper plating film and an electrolytic copper plating film are formed on the upper interlayer resin insulation layer. To form a field-shaped via hole. Therefore, in this case, the process is repeated three times to form the via hole on the through hole on the stack of three stages. Further, the land diameter of the stacked via hole, which is the uppermost conductor layer, was 150 μm, but the land diameter of the lower via hole was 250 μm, and the gap between the uppermost stacked via hole and its conductor circuit was It was formed to fill up.

(18) Subsequently, a solder resist and a solder bump are formed. The raw material composition of the solder resist consists of the following. 46.67 g of a photosensitizing oligomer (molecular weight 4000) obtained by acrylating 50% of epoxy groups of 60 wt% cresol novolac type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG was dissolved in methyl ethyl ketone.
80% by weight of bisphenol A type epoxy resin (Yukaka Shell, Epicoat 1001) 15.0 g, imidazole curing agent (Shikoku Kasei, 2E4MZ-CN) 1.6 g, polyvalent acrylic monomer as a photosensitive monomer (Nippon Kayaku) , R604) 3g,
Similarly polyvalent acrylic monomer (Kyoeisha Chemical Co., Ltd., DPE6A)
1.5 g, dispersion type antifoaming agent (S-65, manufactured by San Nopco) 0.71
2 g of benzophenone (manufactured by Kanto Kagaku) as a photoinitiator and 0.2 g of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to the mixture, and the viscosity was 2.0 Pa at 25 ° C. -A solder resist composition adjusted to s is obtained. Various resins can be used for the solder resist layer, for example, bisphenol A type epoxy resin,
A bisphenol A type epoxy resin acrylate, a novolac type epoxy resin, or a resin obtained by curing an acrylate of a novolac type epoxy resin with an amine curing agent or an imidazole curing agent can be used. Especially when forming solder bumps by forming openings in the solder resist layer,
It is preferable to use a "novolac type epoxy resin or an acrylate of a novolac type epoxy resin" and include an "imidazole curing agent" as a curing agent. The solder resist composition having a thickness of 30 μm is applied to both surfaces of the multilayer printed wiring board obtained in (17) above. Also, a commercially available solder resist layer can be used.

(19) Then, at 80 ° C. for 20 minutes at 100 ° C.
After drying for 30 minutes, a 5mm-thick photomask film with a circular pattern (mask pattern) was placed in close contact with it, exposed to 1000mJ / cm ² of ultraviolet light, and DMT was applied.
G Develop. And then at 80 ℃ for 1 hour, 100 ℃
1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours to form a solder resist layer 70 (thickness 20 μm) having openings (opening diameter 200 μm).

(20) After that, the sheet-shaped printed wiring board was cut into individual pieces. A router or dicing can be used for the cutting. At that time, a through hole to be a terminal or an electrode portion on the side surface was cut into two equal parts. As a result, exposed terminals or electrodes were formed on the side surfaces of the multilayer printed wiring board.

(21) was added to nickel chloride 2.3 × 10 ^-1 mol /
pH consisting of 1, sodium hypophosphite 2.8 × 10 ⁻¹ mol / l, sodium citrate 1.6 × 10 ⁻¹ mol / l =
It is dipped in an electroless nickel plating solution of 4.5 for 20 minutes to form a nickel plating layer 72 having a thickness of 5 μm in the opening. Further, potassium gold cyanide 7.6 × 10 ^-3 mol /
80% in an electroless gold plating solution consisting of 1, ammonium chloride 1.9 × 10 ⁻¹ mol / l, sodium citrate 1.2 × 10 ⁻¹ mol / l, sodium hypophosphite 1.7 × 10 ⁻¹ mol / l
It is immersed for 7.5 minutes under the condition of ° C to form a gold plating layer of 0.03 µm thickness on the nickel plating layer of 5 µm thickness.

In the above-mentioned example, the intermediate layer is formed of nickel and the noble metal layer is made of gold. However, in addition to nickel, it may be formed of palladium, titanium, or the like. In addition to gold, silver, platinum, or the like may be used. Further, the noble metal layer may be formed of two or more layers. Surface treatment is dry treatment, plasma,
UV or corona treatment may be performed. Thereby, the filling property of the underfill can be improved.

(22) Then, solder paste is printed in the openings of the solder resist layer and reflowed at 230 ° C. to form solder bumps (solder bodies) in the via holes on the upper surface, and on the lower surface side. Conductive connection pins 96, which are external board connection terminals, are attached to the via holes via solder. It is also possible to form a BGA instead of the conductive connection pin.

(Second Embodiment) This is almost the same as the multilayer printed wiring board of the first embodiment. As shown in FIG. 3, the terminal (electrode) 98 on the side surface of the multilayer printed wiring board was formed by a stacked via that forms the via hole 60 directly above the via hole 60.

(Third Embodiment) This is almost the same as the multilayer printed wiring board of the first embodiment. As shown in FIG. 4, the terminal (electrode) 98 on the side surface of the multilayer printed wiring board was formed by a stack via that also forms the via hole 60 immediately above the through hole 36.

(Fourth Embodiment) This is almost the same as the multilayer printed wiring board of the first embodiment. As shown in FIG. 5, the terminals (electrodes) on the side surface of the multilayer printed wiring board are formed by stack vias forming the via holes 60 immediately above the through holes 36, and the terminals (electrodes) are staggered in each row. Composed of.

(Fifth Embodiment) This is almost the same as the multilayer printed wiring board of the first embodiment. The capacitor C was mounted on the terminal (electrode) on the side surface.

(Sixth Embodiment) The second embodiment is almost the same as the multilayer printed wiring board. The capacitor C was mounted on the terminal (electrode) on the side surface.

(Seventh Embodiment) As shown in FIG. 8, terminals (electrodes) 98 were formed on the side surfaces of a multilayer printed wiring board. The electrode 98 was formed by disposing a conductive paste 98 on the metal film 92 formed in the recess.

(Comparative Example) A multilayer printed wiring board is manufactured which is almost the same as in Example 1 except that terminals for power supply or electrodes are formed from external terminals on the lower surface of the board from the back surface of the board. In the multilayer printed wiring boards of Examples 1 to 6, the inductance did not increase and the voltage drop width was smaller than that of the multilayer printed wiring boards of the comparative examples. Further, the operation of the IC chip was not confirmed to be unstable or malfunction. In the example, it was found that a multilayer printed wiring board with improved electrical connectivity can be obtained.

[0061]

As described above, according to the present invention, the distance from the IC chip to the capacitor (power supply terminal) can be shortened by drawing out the terminal or electrode for power supply from the side surface of the substrate. Therefore, the inductance does not increase, and the instability or malfunction of the operation due to the power shortage is reduced.

[Brief description of drawings]

FIG. 1 is a perspective view showing an appearance of a multilayer printed wiring board according to a first embodiment of the present invention.

2 (A) shows a power supply layer (solid layer) 52 formed on the upper surface of the core substrate of the multilayer printed wiring board shown in FIG. 1, and FIG. 2 (B) shows FIG. 2 (A). 7B shows a cross section taken along line BB of FIG.

FIG. 3 is a perspective view showing an appearance of a multilayer printed wiring board according to a second embodiment of the present invention.

FIG. 4 is a perspective view showing an appearance of a multilayer printed wiring board according to a third embodiment of the present invention.

FIG. 5 is a perspective view showing an appearance of a multilayer printed wiring board according to a fourth embodiment of the present invention.

FIG. 6 is a perspective view showing an appearance of a multilayer printed wiring board according to a fifth embodiment of the present invention.

FIG. 7 is a perspective view showing an appearance of a multilayer printed wiring board according to a sixth embodiment of the present invention.

FIG. 8 is a perspective view showing an appearance of a multilayer printed wiring board according to a seventh embodiment of the present invention.

9 (A), (B), and (C) are explanatory views showing a configuration of a conventional multilayer printed wiring board.

FIG. 10 is a graph showing changes over time in the voltage supplied to the IC chip.

[Explanation of symbols]

10 Multilayer printed wiring board 30 core substrate 52 power layer 80A, 80B build-up layer 96 conductive connection pin 98 Power supply terminal (electrode) 112 IC chip C chip capacitor

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5E317 AA22 AA24 BB02 BB03 BB12                       BB13 BB14 BB15 CC25 CC32                       CC33 CD12 CD27 CD32 GG11                 5E338 AA03 BB02 EE14                 5E346 AA42 BB06 CC04 CC08 CC09                       CC10 CC13 CC14 CC32 DD12                       FF03 FF15 FF18 FF45 HH02                       HH06

Claims (7)

[Claims] 1. In a multilayer printed wiring board in which interlayer resin insulation layers and conductor layers are alternately laminated and external board connection terminals are provided, terminals or electrodes for power supply are provided on the side surface of the board. A multilayer printed wiring board characterized by being made. 2. In a multilayer printed wiring board in which interlayer resin insulation layers and conductor layers are alternately laminated and external board connecting terminals are arranged, a through hole or a via hole is exposed at a side surface of the board, and A multilayer printed wiring board, wherein the exposed through hole or via hole is used as a terminal or an electrode for power supply. 3. A multilayer printed wiring board in which interlayer resin insulation layers and conductor layers are alternately laminated and external board connection terminals are arranged, wherein a through hole or a side surface of the board is filled with a conductive metal. A multilayer printed wiring board, wherein a via hole is exposed, and the exposed through hole or via hole is used as a terminal or an electrode for power supply. 4. The multilayer printed wiring board according to claim 1, wherein interlayer connection is performed by via holes. 5. The terminal or electrode for power supply is
The multilayer printed wiring board according to any one of claims 1 to 3, which is connected to a power supply layer provided on an inner layer of the wiring board. 6. The interlayer resin insulation layer and the conductor layer are laminated on a core substrate, and terminals or electrodes for power supply are arranged on the core substrate. Multilayer printed wiring board. 7. The multilayer printed wiring board according to claim 1, wherein a capacitor is mounted on the side surface.