JPH02143587A - Feed structure of multilayer interconnection substrate - Google Patents
Feed structure of multilayer interconnection substrateInfo
- Publication number
- JPH02143587A JPH02143587A JP63298528A JP29852888A JPH02143587A JP H02143587 A JPH02143587 A JP H02143587A JP 63298528 A JP63298528 A JP 63298528A JP 29852888 A JP29852888 A JP 29852888A JP H02143587 A JPH02143587 A JP H02143587A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- pins
- power feeding
- multilayer interconnection
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title abstract description 8
- 238000000034 method Methods 0.000 abstract description 5
- 239000010409 thin film Substances 0.000 abstract description 5
- 239000000919 ceramic Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＬＳＩチップ等を高密度実装する場合に使用し
て好適な多層配線基板の給電構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power supply structure for a multilayer wiring board suitable for use when mounting LSI chips and the like at high density.
一般に、多層配線基板は、一方の側の面に露呈する多数
の入出力ピンと、この入出力ピンに接続する内部配線層
を含み、入出力ピンと反対側の面に多数のＬＳＩチップ
が実装されている。従来、この多層配線基板上に実装す
るＬＳＩチップへの給電は、入出力ピンの一部を信号入
出力用のピンに残りの一部を電源供給用のピンに割り当
て、電源供給用のピンから内層配線層を介して行なわれ
ていた。Generally, a multilayer wiring board includes a large number of input/output pins exposed on one side, an internal wiring layer connected to the input/output pins, and a large number of LSI chips mounted on the side opposite to the input/output pins. There is. Conventionally, power was supplied to LSI chips mounted on this multilayer wiring board by assigning some of the input/output pins to signal input/output pins and the remaining part to power supply pins. This was done via an inner wiring layer.
上述した従来の多層配線基板の給電構造においては、入
出力ピンの一部を信号入出力用のピンとしてまた残りの
ものを電源供給用のピンとして割り当てているため、信
号入力用の電極及び電源供給用の電極を多く設けること
ができず、近年のＬＳＩチップの高密度実装化に応じる
ことができないという問題とピンが小さい為、１ピン当
りの電流量を大きくすることが出来ないという問題があ
った。In the power supply structure of the conventional multilayer wiring board described above, some of the input/output pins are assigned as signal input/output pins, and the remaining pins are assigned as power supply pins. There is a problem that it is not possible to provide many electrodes for supply, and it is not possible to respond to the high density packaging of LSI chips in recent years.As the pins are small, there is a problem that the amount of current per pin cannot be increased. there were.
本発明はこのような事情に鑑みなされたもので、多層配
線基板における信号入出力用の電極および電源供給用の
電極の個数を増加させることができ、しかも電源供給用
の端子を設けることにより、大電流を確実に供給できる
様になり、もって近年のＬＳＩチップの高密度実装化に
応じることができる多層配線基板の給電構造を提供する
ものである。The present invention was made in view of the above circumstances, and it is possible to increase the number of signal input/output electrodes and power supply electrodes in a multilayer wiring board, and by providing power supply terminals, The present invention provides a power supply structure for a multilayer wiring board that can reliably supply a large current and thus meet the recent high-density packaging of LSI chips.
本発明の多層配線基板の給電構造は、内部に電源層が形
成され信号入出力用のピン及び電源供給用のピンを有す
る多層配線基板の側面に前記電源層を露呈させ、前記電
源層の露呈端面に電源供給用のパッドを設け、前記パッ
ドに電源供給用の端子を固着したことを特徴とする。The power supply structure of the multilayer wiring board of the present invention has a power supply layer formed inside and has pins for signal input/output and power supply pins, and the power supply layer is exposed on the side surface of the multilayer wiring board, and the power supply layer is exposed on the side surface of the multilayer wiring board. A power supply pad is provided on the end face, and a power supply terminal is fixed to the pad.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。１はセラミ
ック製の多層配線基板でタングステン。FIG. 1 is a sectional view of an embodiment of the present invention. 1 is a ceramic multilayer wiring board made of tungsten.
金、銀、銅、銀−パラジウム等を導体成分とし、内部電
源層２とスルーホール３が設けられている。内部電源層
２にスルーホール３を介して接続される電源供給用のピ
ン５と、信号入出力用のピン４が多層配線基板１の裏面
に設けられている。The conductor component is gold, silver, copper, silver-palladium, etc., and an internal power supply layer 2 and through holes 3 are provided. A power supply pin 5 connected to the internal power supply layer 2 via a through hole 3 and a signal input/output pin 4 are provided on the back surface of the multilayer wiring board 1.
ピン４．５にスルーホール３を介して接続される配線網
６を内部に有する薄膜層７が多層配線基板１の表面に設
けられている。薄膜層７の上面には配線網６に接続する
リード８を有するＬＳＩチップ９が実装されている。こ
の多層配線基板１は側面に内部電源層２が露呈されてい
る。薄膜層７に於ける各層間の絶縁材はポリイミド系の
合成樹脂によって形成されている。A thin film layer 7 having therein a wiring network 6 connected to pins 4.5 via through holes 3 is provided on the surface of multilayer wiring board 1. An LSI chip 9 having leads 8 connected to the wiring network 6 is mounted on the upper surface of the thin film layer 7 . This multilayer wiring board 1 has an internal power supply layer 2 exposed on the side surface. The insulating material between each layer in the thin film layer 7 is made of polyimide-based synthetic resin.
１０は電源供給用の端子で内部電源層２の外部露呈端面
に形成された電源供給用のパッド１１に固着され、セラ
ミック多層配線基板１の内部電源Ｎ２と実装用プリント
基板１２の電源バス１３を接続する。これら端子を固着
する電源供給用のパッド１１は多層配線基板１の製作後
に内部電源層２の外部露呈端面にスパッタ膜を施してレ
ジストを塗布し、フォトリソグラフィ技術によりレジス
トを溶解して所望の寸法の導体膜にした後、銅メツキも
しくは金メツキを施すことにより形成することができる
。電源供給用の端子１０とセラミック基板１の接続は半
田付もしくはロー付けにより行なわれる。また、セラミ
ック基板１の端子１０は半田付あるいは第２図に示す様
なボルト方式によりプリント板１２の電源バス１３に接
続されている。Reference numeral 10 denotes a power supply terminal, which is fixed to a power supply pad 11 formed on the externally exposed end surface of the internal power supply layer 2, and connects the internal power supply N2 of the ceramic multilayer wiring board 1 and the power supply bus 13 of the printed circuit board 12 for mounting. Connecting. The power supply pads 11 for fixing these terminals are formed by sputtering a resist film on the externally exposed end face of the internal power supply layer 2 after manufacturing the multilayer wiring board 1, and dissolving the resist using photolithography technology to obtain the desired dimensions. It can be formed by forming a conductive film and then applying copper plating or gold plating. The power supply terminal 10 and the ceramic substrate 1 are connected by soldering or brazing. Further, the terminals 10 of the ceramic substrate 1 are connected to the power supply bus 13 of the printed board 12 by soldering or by a bolt method as shown in FIG.
薄膜層７の配線網６は、フォトリソグラフィ技術を用い
て形成される。なお、配線網６の幅員は約２５μｍの寸
法に、スルーホール３の口径は約２００μｍの寸法に、
また、内部配線Ｎ２の厚さは約１００μｍの寸法に設定
されている。この様に構成された多層配線基板の給電構
造においては、多層配線基板１の裏面に突出する入出力
ピンのうち電源供給用のピン５の割り当て数を削減させ
、信号入出力用ピン４の割り当て数を増加させることが
でき、多層配線基板１における信号入出力用の電極及び
電源供給用の電極の個数を増加させることができる。し
かもロー付けされた端子１０により内部電源層２に大電
流をロスが少ない形で供給することができる。The wiring network 6 of the thin film layer 7 is formed using photolithography technology. Note that the width of the wiring network 6 is approximately 25 μm, the diameter of the through hole 3 is approximately 200 μm,
Further, the thickness of the internal wiring N2 is set to approximately 100 μm. In the power supply structure of the multilayer wiring board configured in this way, the number of pins 5 for power supply among the input/output pins protruding from the back surface of the multilayer wiring board 1 is reduced, and the number of pins 4 for signal input/output is allocated. The number of signal input/output electrodes and power supply electrodes on the multilayer wiring board 1 can be increased. Furthermore, the soldered terminals 10 can supply a large current to the internal power supply layer 2 with little loss.
他に、第３図、第４図に示す様なＬＳＩチップ９を多層
配線基板１の両面に配置する様な実装方式では電源供給
用に基板１の面上にピンを配置することができない為、
基板１の端面から給電する方式は特に有用である。In addition, in a mounting method such as arranging the LSI chip 9 on both sides of the multilayer wiring board 1 as shown in FIGS. 3 and 4, it is not possible to arrange pins on the surface of the board 1 for power supply. ,
A method of feeding power from the end surface of the substrate 1 is particularly useful.
第３図は端子１０を実装用プリント基板１２の電源バス
１３に半田付もしくはロー付した場合、第４図はこれら
をボルト方式により接続した場合である。FIG. 3 shows the case where the terminal 10 is soldered or brazed to the power supply bus 13 of the printed circuit board 12 for mounting, and FIG. 4 shows the case where these are connected by a bolt method.
なお、本発明においては電源供給用の電極が電源供給用
端子１０および電源供給用のピン５からなるが、これら
電極は使用する電源の種類に応じて使い分けられる。Incidentally, in the present invention, the power supply electrode is composed of the power supply terminal 10 and the power supply pin 5, but these electrodes can be used depending on the type of power supply used.
また、本発明における内部電源層２の層数および電源供
給用パッド１０の個数を前述した実施例に限定されず、
例えば５個６個・・・とじてもよくその個数は適宜変更
することができる。Further, the number of layers of the internal power supply layer 2 and the number of power supply pads 10 in the present invention are not limited to the above-mentioned embodiments,
For example, 5, 6, etc. may be used, and the number can be changed as appropriate.
以上説明したように本発明は、多層配線基板に設けた電
源供給用のパッドに電源供給用の端子を固着することに
より、多層配線基板の入出力ピンのうち電源供給用のピ
ンの割り当て数を削減させ、信号入出力用のピンの割り
当て数を増加させることができ、電源供給用の端子をロ
ー付けし、しかも電圧ドロップの少ない安定した大電流
供給を可能にすることができる。As explained above, the present invention reduces the number of power supply pins allocated among the input/output pins of the multilayer wiring board by fixing the power supply terminals to the power supply pads provided on the multilayer wiring board. The number of pins assigned for signal input/output can be increased, power supply terminals can be soldered, and a stable large current supply with little voltage drop can be made possible.
第１図は本発明の一実施例の断面図、第２図〜第４図は
本発明の他の実施例の断面図である。
１・・・多層配線基板、２・・・内部電源層、３・・・
スルーホール、４・・・信号用ピン、５・・・電源用ピ
ン、６・・・配線網、７・・・薄ｐＡ層、８・・・リー
ド、９・・・ＬＳＩチップ、１０・・・電源供給用端子
、１１・・・電源供給用パッド、１２・・・プリント板
、１３・・・電源バス。FIG. 1 is a sectional view of one embodiment of the invention, and FIGS. 2 to 4 are sectional views of other embodiments of the invention. 1...Multilayer wiring board, 2...Internal power supply layer, 3...
Through hole, 4... Signal pin, 5... Power supply pin, 6... Wiring network, 7... Thin pA layer, 8... Lead, 9... LSI chip, 10... - Power supply terminal, 11... Power supply pad, 12... Printed board, 13... Power supply bus.
Claims (1)
給用のピンを有する多層配線基板の側面に前記電源層を
露呈させ、前記電源層の露呈端面に電源供給用のパッド
を設け、前記パッドに電源供給用の端子を固着したこと
を特徴とする多層配線基板の給電構造。The power supply layer is exposed on the side surface of a multilayer wiring board which has a power supply layer formed therein and has signal input/output pins and power supply pins, and a power supply pad is provided on the exposed end surface of the power supply layer. A power supply structure for a multilayer wiring board characterized by a power supply terminal fixed to a pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63298528A JP2629908B2 (en) | 1988-11-25 | 1988-11-25 | Power supply structure of multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63298528A JP2629908B2 (en) | 1988-11-25 | 1988-11-25 | Power supply structure of multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02143587A true JPH02143587A (en) | 1990-06-01 |
| JP2629908B2 JP2629908B2 (en) | 1997-07-16 |
Family
ID=17860892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63298528A Expired - Lifetime JP2629908B2 (en) | 1988-11-25 | 1988-11-25 | Power supply structure of multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2629908B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07263824A (en) * | 1994-03-18 | 1995-10-13 | Nec Corp | Interconnection board |
| US5728974A (en) * | 1994-06-17 | 1998-03-17 | Sumitomo Wiring Systems, Ltd. | Sealing grommet |
| US5739475A (en) * | 1994-04-21 | 1998-04-14 | Inoac Corporation | Grommet for protecting a wire harness with structure for ensuring flush seating |
| JP2003008239A (en) * | 2001-06-21 | 2003-01-10 | Ibiden Co Ltd | Multilayer printed wiring board |
-
1988
- 1988-11-25 JP JP63298528A patent/JP2629908B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07263824A (en) * | 1994-03-18 | 1995-10-13 | Nec Corp | Interconnection board |
| US5739475A (en) * | 1994-04-21 | 1998-04-14 | Inoac Corporation | Grommet for protecting a wire harness with structure for ensuring flush seating |
| US5728974A (en) * | 1994-06-17 | 1998-03-17 | Sumitomo Wiring Systems, Ltd. | Sealing grommet |
| JP2003008239A (en) * | 2001-06-21 | 2003-01-10 | Ibiden Co Ltd | Multilayer printed wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2629908B2 (en) | 1997-07-16 |
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