JPH0629443A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPH0629443A
JPH0629443A JP4178729A JP17872992A JPH0629443A JP H0629443 A JPH0629443 A JP H0629443A JP 4178729 A JP4178729 A JP 4178729A JP 17872992 A JP17872992 A JP 17872992A JP H0629443 A JPH0629443 A JP H0629443A
Authority
JP
Japan
Prior art keywords
lead
lead frame
ceramic substrate
integrated circuit
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4178729A
Other languages
Japanese (ja)
Inventor
Kazuyuki Yamada
和行 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4178729A priority Critical patent/JPH0629443A/en
Publication of JPH0629443A publication Critical patent/JPH0629443A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To decrease the lead pitch of a hybrid integrated circuit to achieve high mounting density by grasping a ceramic substrate between two lead frames and fixing the grasped part using high temperature melting solder. CONSTITUTION:A lead frame with a required lead pitch is produced by punching a metal sheet, which is thinner than one used for the conventional lead frame. The ends of the leads 18 and 19 of the lead frame are bent by 1/2 of the thickness of a ceramic substrate 1 so that they can grasp the substrate as shown in the Figure. The grasped part is fixed by high-melting solder and molded with resin 9. According to this method, it is possible to produce a lead frame with a lead pitch of 0.5mm and thus realize a hybrid integrated circuit that enables high-density mounting of surface mount devices.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はリードピッチを短縮した
混成集積回路の製造方法に関する。情報処理装置を構成
する電子機器を小型化するには半導体集積回路の集積度
の向上と共に搭載する回路部品の小型化および配線基板
の小型化と高密度化が必要である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a hybrid integrated circuit having a reduced lead pitch. In order to miniaturize the electronic equipment which constitutes the information processing apparatus, it is necessary to improve the degree of integration of the semiconductor integrated circuit, and to miniaturize the circuit components to be mounted and miniaturize and increase the density of the wiring board.

【0002】そのため、配線基板に搭載する半導体部品
および回路部品にはチップ部品が多く用いられており、
また、配線基板も当初の単層プリント板より、多層プリ
ント板、表面実装プリント板へと集積度の向上が行なわ
れている。
Therefore, chip parts are often used for semiconductor parts and circuit parts to be mounted on a wiring board.
In addition, the wiring board has been improved in integration degree from the initial single-layer printed board to a multilayer printed board and a surface-mounted printed board.

【0003】[0003]

【従来の技術】LSI やVLSIなど半導体集積回路の実装法
としては従来のリード挿入部品実装に代わってチップ部
品を配線基板上に接着剤や共晶合金などを用いて固定し
た後、半田やワイヤボンディングにより回路接続を行な
う表面実装技術(Surface Mounting Technology略称SMT)
が主流になっており、フラットパッケージが多く使用さ
れている。
2. Description of the Related Art As a method for mounting semiconductor integrated circuits such as LSI and VLSI, instead of the conventional lead insertion component mounting, chip components are fixed on a wiring board with an adhesive or a eutectic alloy, then solder or wire. Surface Mounting Technology for connecting circuits by bonding (SMT)
Has become the mainstream, and flat packages are often used.

【0004】さて、発明者等は混成集積回路(Hybrid I
C)についても表面実装型の要求が高まっていることから
QFP(Quarter Flat Package) タイプの表面実装混成集積
回路( 略称SMD-HYB)を開発し使用している。
By the way, the inventors of the present invention have proposed a hybrid integrated circuit (Hybrid I
With regard to (C) as well, there is an increasing demand for surface mount type
QFP (Quarter Flat Package) type surface mount hybrid integrated circuit (abbreviated as SMD-HYB) has been developed and used.

【0005】図3はこの構成を示す模式断面図である。
すなわち、アルミナなどのセラミック基板1の表裏面に
厚膜HYB 製造技術を用いて厚膜抵抗器2やランド,ボン
ディングパッド,導体線路3,スルーホール4などの配
線パターンを形成すると共に、半導体チップ5, チップ
コンデンサ6などを搭載し、半導体チップ5については
ワイヤ7を用いてボンデングパッドに回路接続し、ま
た、チップコンデンサ6については半田付けにより導体
線路3に設けてあるパッドに溶着している。
FIG. 3 is a schematic sectional view showing this structure.
That is, a wiring pattern such as a thick film resistor 2, a land, a bonding pad, a conductor line 3 and a through hole 4 is formed on the front and back surfaces of a ceramic substrate 1 made of alumina or the like by using a thick film HYB manufacturing technique, and a semiconductor chip 5 is formed. Then, the chip capacitor 6 and the like are mounted, the semiconductor chip 5 is connected to the bonding pad by using the wire 7, and the chip capacitor 6 is welded to the pad provided on the conductor line 3 by soldering. .

【0006】このように、スルーホール4を用いてセラ
ミック基板1の両面に混成集積回路を形成した後、リー
ド端子8とセラミック基板1の端面にパターン形成して
あるランド部とを高温半田などを用いて溶着する。
After the hybrid integrated circuits are formed on both surfaces of the ceramic substrate 1 by using the through holes 4 as described above, the lead terminals 8 and the land portions patterned on the end surface of the ceramic substrate 1 are subjected to high-temperature soldering or the like. Use to weld.

【0007】そして、最後にトランスフアモールド法に
より樹脂外装9を行なって混成集積回路が完成してい
る。また、図4はこのようにして形成されたQFP タイプ
樹脂パッケージの平面図(A)と側面図(B)である
が、高密度実装を行なっているために膨大な数のリード
端子8を備えている。
Finally, the resin exterior 9 is applied by the transfer molding method to complete the hybrid integrated circuit. Further, FIG. 4 is a plan view (A) and a side view (B) of the QFP type resin package formed in this way, which has a huge number of lead terminals 8 for high-density mounting. ing.

【0008】例えば、現在使用しているパッケージ寸法
が横32 mm ,縦28,高さ4.4 mm のSMD-HYB について、
リード端子の数は104 本、また、横44 mm ,縦40,高さ
4.4mm のSMD-HYB について、リード端子の数は168 本に
及んでいるが、後者のパッケージ寸法について200 本以
上( 例えば256 本) のリード端子を備えたSMD-HYBの実
用化が要望されている。
[0008] For example, regarding the SMD-HYB whose package size currently used is 32 mm in width, 28 in height, and 4.4 mm in height,
104 lead terminals, 44 mm wide, 40 vertical, height
With respect to the 4.4 mm SMD-HYB, the number of lead terminals reaches 168, but for the latter package size, there is a demand for the practical application of SMD-HYB with more than 200 (for example, 256) lead terminals. There is.

【0009】こゝで、このような要求を満たすための対
策としてはセラミック回路基板にパターン形成されてい
る導体線路やチップを微小化することが必要であるが、
これ以外にリード端子の構造を変更する必要がある。
Here, as a measure for satisfying such requirements, it is necessary to miniaturize the conductor lines and chips formed on the ceramic circuit board by patterning.
In addition to this, it is necessary to change the structure of the lead terminal.

【0010】すなわち、従来のリード端子は図5に示す
ようにしてセラミック回路基板1と接合していた。すな
わち、先端に挟持部11をもつクリップリード12からな
り、挟持部11にセラミック基板1を挿入し、高温半田や
金錫共晶合金などを用いて溶着する方法が採られてい
た。
That is, the conventional lead terminal is joined to the ceramic circuit board 1 as shown in FIG. That is, a method is used in which a clip lead 12 having a sandwiching portion 11 at the tip is formed, the ceramic substrate 1 is inserted into the sandwiching portion 11, and welding is performed using high-temperature solder, a gold-tin eutectic alloy, or the like.

【0011】こゝで、従来はリード端子の材料としては
厚さが0.2 〜0.3mm の銅合金を用い、図6に示すように
クリップリード型の構造をとり、リードピッチ13の寸法
として0.8 mm を採っていたが、多ピン化を進めるため
にはリードピッチを0.5 mmに縮小する必要がある。
Here, conventionally, a copper alloy having a thickness of 0.2 to 0.3 mm is used as the material of the lead terminal, and a clip lead type structure is adopted as shown in FIG. 6, and the lead pitch 13 is 0.8 mm. However, in order to increase the number of pins, it is necessary to reduce the lead pitch to 0.5 mm.

【0012】然し、クリップリード型の構造をとる場
合、挟持部の間隙14として0.1mm が必要であり、また、
リード片15の幅として0.2mm が必要であり、また、リー
ド端子の相互間隔16として少なくとも0.1mm が必要であ
る。
However, in the case of the clip lead type structure, 0.1 mm is required as the gap 14 between the holding portions, and
The width of the lead pieces 15 must be 0.2 mm, and the mutual spacing 16 between the lead terminals must be at least 0.1 mm.

【0013】そのため、クリップリード型の構造をとる
場合のリードピッチは0.6mm が限界であり、また、実際
に板厚が0.15 mm の銅合金を使用する場合でも上記の寸
法が加工限界である。
Therefore, the lead pitch in the case of the clip lead type structure is limited to 0.6 mm, and the above dimension is the processing limit even when a copper alloy having a plate thickness of 0.15 mm is actually used.

【0014】[0014]

【発明が解決しようとする課題】情報処理装置を構成す
る電子機器を小型化する必要から、発明者等が開発した
表面実装混成集積回路(SMD-HYB)は更に実装密度を向上
する必要があり、従来のパッケージ面積でリード端子数
の増加が要望されている。
The surface mount hybrid integrated circuit (SMD-HYB) developed by the inventor and the like needs to have a higher packing density because it is necessary to miniaturize the electronic equipment that constitutes the information processing apparatus. There is a demand for an increase in the number of lead terminals in the conventional package area.

【0015】そこで、従来のリードピッチ0.8mm を0.5m
m にして多ピン化を実現したいが、従来のクリップリー
ド型では実現できないことが問題であり、この解決が課
題である。
Therefore, the conventional lead pitch of 0.8 mm is changed to 0.5 m
We would like to realize multiple pins with m, but there is a problem that it cannot be realized with the conventional clip lead type, and this solution is a problem.

【0016】[0016]

【課題を解決するための手段】上記の課題は、今までリ
ードフレーム用として使用してきた金属板に較べて厚さ
が薄い金属板に打抜き加工を施して、必要とするリード
ピッチを備えたリードフレームを形成する工程と、この
リードフレームの先端を少なくともセラミック基板の1/
2 の厚さの段差をもつように曲げ加工する工程と、二枚
のリードフレームを用い、先端部でセラミック基板を挟
持した状態で高融点半田を用い、セラミック基板のラン
ドとリードフレームの先端部とを溶着し固定する工程と
を少なくとも含むことを特徴として混成集積回路の製造
方法を形成することにより解決することができる。
SUMMARY OF THE INVENTION The above-mentioned problems are solved by providing a lead having a required lead pitch by punching a metal plate having a thickness smaller than that of a metal plate used for a lead frame. The step of forming the frame and the tip of this lead frame should be at least 1 / of the ceramic substrate.
Bending process so that there is a difference in thickness of 2 and using two lead frames, using high melting point solder with the ceramic substrate sandwiched between the tips, the land of the ceramic substrate and the tip of the lead frame It can be solved by forming a method for manufacturing a hybrid integrated circuit, characterized by including at least a step of welding and fixing.

【0017】[0017]

【作用】本発明は従来のクリップリードではリードピッ
チを0.5mm にすることは不可能なことから、セラミック
基板を従来のように一個のリード端子で挟持するのでは
なく、図2に示すように先端を曲げ加工したリード片1
8,19 を備えたリードフレームを準備し、このリード片1
8,19 によりセラミック基板のランドを挟持するように
したものである。
In the present invention, since it is impossible to set the lead pitch to 0.5 mm in the conventional clip lead, as shown in FIG. 2, the ceramic substrate is not sandwiched by one lead terminal as in the conventional case. Lead piece with bent tip 1
Prepare a leadframe with 8,19 and this lead piece 1
The land of the ceramic substrate is sandwiched by 8,19.

【0018】図1は本発明を適用したSMD-HYB の構成を
示す断面図であって、リード片18と19によりセラミック
基板1を挟持し、高温半田を用いて挟持部を溶着固定し
た後、樹脂外装9を施した状態を示している。
FIG. 1 is a sectional view showing the structure of an SMD-HYB to which the present invention is applied. The ceramic substrate 1 is sandwiched by lead pieces 18 and 19, and the sandwiched portion is welded and fixed by using high temperature solder. The figure shows a state where a resin sheath 9 is applied.

【0019】このような方法をとることにより従来のク
リップリード構造をとる場合の0.6mm のリードピッチ限
界をクリヤーすることができ、0.5mm のリードピッチを
実現することができる。
By adopting such a method, it is possible to clear the lead pitch limit of 0.6 mm when the conventional clip lead structure is adopted, and it is possible to realize a lead pitch of 0.5 mm.

【0020】こゝで、リード端子のセラミック基板への
装着法としては、導電性ペーストのスクリーンプリント
によりパターン形成されているセラミック基板のランド
に二組のリードフレームを固定して一体化した状態で挿
入し、従来と同様に高温半田あるいは金錫(Au-Sn) 共晶
半田を用いて溶着する。
Here, as a method of mounting the lead terminals on the ceramic substrate, two sets of lead frames are fixed and integrated to the lands of the ceramic substrate which are patterned by screen printing of conductive paste. Insert it and weld it using high temperature solder or gold-tin (Au-Sn) eutectic solder as before.

【0021】そして、樹脂モールド後にリード端子に対
して半田付け性を向上するためにメッキ処理を行なう
が、この際に厚めにメッキを行なうことにより、二枚の
リード端子を完全に一体化することができる。
Then, after the resin molding, a plating process is performed on the lead terminals to improve solderability. At this time, the two lead terminals are completely integrated by performing a thick plating. You can

【0022】そのために、本発明に係る製造工程におい
て使用するリードフレームの厚さは少なくとも従来の1/
2 で足りる。なお、その他の製造工程については従来と
全く同様である。
For this reason, the thickness of the lead frame used in the manufacturing process according to the present invention is at least 1 / the conventional thickness.
2 is enough. The other manufacturing steps are exactly the same as the conventional one.

【0023】[0023]

【実施例】従来のリードフレームは厚さが0.25 mm のCu
合金を使用しているが、本発明の実施においては0.1mm
の厚さのCu合金を使用し、打抜き加工により図2に示す
ように先端部が反対方向に曲げ加工してしてあるリード
フレームを準備した。
[Example] A conventional lead frame has a thickness of 0.25 mm of Cu.
Alloy is used, but in the practice of the present invention 0.1 mm
A Cu alloy having a thickness of 1 was used to prepare a lead frame in which the tip end was bent in the opposite direction as shown in FIG. 2 by punching.

【0024】さて、SMD-HYD については従来と全く同じ
工程で形成した。すなわち、所定位置に貫通孔を設けて
あるセラミック基板の表裏面に厚膜ペーストを印刷して
ランド,ボンディングパッド,導体線路,スルーホール
などの配線パターンを形成した後、この基板面の所定位
置に半導体チップとチップコンデンサなどのチップ部品
を接着固定した後、半導体チップについてはワイヤボン
ディング法で、また、コンデンサについては半田付けに
より回路接続を行なった。
The SMD-HYD was formed by the same process as the conventional process. That is, a thick film paste is printed on the front and back surfaces of a ceramic substrate having through holes at predetermined positions to form wiring patterns such as lands, bonding pads, conductor lines, and through holes, and then at predetermined positions on this substrate surface. After the semiconductor chip and a chip component such as a chip capacitor were bonded and fixed, the semiconductor chip was connected by the wire bonding method, and the capacitor was connected by soldering.

【0025】次に、二枚のリードフレームを用い、先端
部でセラミック基板を挟持した状態で高融点半田を用い
てセラミック基板のランドとリードフレームの先端部と
を溶着し固定した。
Next, two lead frames were used, and the land of the ceramic substrate and the leading end of the lead frame were welded and fixed to each other by using high melting point solder with the leading end sandwiching the ceramic substrate.

【0026】次に、リードフレームの先端部を溶着固定
したセラミック基板にエポキシ樹脂のトランスファモー
ルドを施して樹脂モールドした後、樹脂モールドを行な
ったリードフレームのリード部に半田メッキを10μm の
厚さに施した後にリードの曲げ加工を行い、引き続いて
リードフレームより切断することにより混成集積回路素
子が完成した。
Next, transfer molding of epoxy resin is performed on the ceramic substrate with the tip end of the lead frame welded and fixed, and then the lead portion of the resin-molded lead frame is solder-plated to a thickness of 10 μm. After the application, the leads are bent and subsequently cut from the lead frame to complete the hybrid integrated circuit element.

【0027】[0027]

【発明の効果】以上記したように本発明の実施によりリ
ードピッチが0.5mm 程度と小さく実装密度の大きなQFP
タイプのSMD-HYB を実用化することができる。
As described above, according to the present invention, a QFP having a small lead pitch of about 0.5 mm and a large mounting density is provided.
A type of SMD-HYB can be put to practical use.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を適用したSMD-HYB の構成を示す断面図
である。
FIG. 1 is a cross-sectional view showing a configuration of SMD-HYB to which the present invention is applied.

【図2】本発明に係るリード端子の構成を示す斜視図で
ある。
FIG. 2 is a perspective view showing a configuration of a lead terminal according to the present invention.

【図3】表面実装混成集積回路(SMD-HYB )の構成を示
す模式断面図である。
FIG. 3 is a schematic cross-sectional view showing a configuration of a surface mount hybrid integrated circuit (SMD-HYB).

【図4】表面実装混成集積回路(SMD-HYB )の平面図
(A)と側面図(B)である。
FIG. 4 is a plan view (A) and a side view (B) of a surface mount hybrid integrated circuit (SMD-HYB).

【図5】従来のリード端子の構造を示す平面図(A)と
側面図(B)である。
FIG. 5 is a plan view (A) and a side view (B) showing a structure of a conventional lead terminal.

【図6】クリップリード型をとるリード端子の平面図で
ある。
FIG. 6 is a plan view of a lead terminal of a clip lead type.

【符号の説明】[Explanation of symbols]

1 セラミック基板 8 リード端子 12 クリップリード 13 リードピッチ 14 間隙 15,18,19 リード片 16 相互間隔 1 Ceramic substrate 8 Lead terminals 12 Clip leads 13 Lead pitch 14 Gap 15,18,19 Lead pieces 16 Mutual spacing

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 所定位置に貫通孔を設けてあるセラミッ
ク基板の表裏面に厚膜ペーストを印刷してランド,ボン
ディングパッド,導体線路,スルーホールなどの配線パ
ターンを形成する工程と、 該基板面の所定位置にチップ部品を接着固定した後、回
路接続する工程と、 従来、リードフレーム用として使用してきた金属板に較
べて厚さが薄い金属板に打抜き加工を施して、必要とす
るリードピッチを備えたリードフレームを形成する工程
と、 該リードフレームの先端を少なくともセラミック基板の
1/2 の厚さの段差をもつように曲げ加工する工程と、 二枚のリードフレームを用い、先端部でセラミック基板
を挟持した状態で高融点半田を用い、該セラミック基板
のランドとリードフレームの先端部とを溶着し固定する
工程と、 リードフレームの先端部を溶着固定したセラミック基板
に樹脂のトランスファモールドを施して樹脂モールドす
る工程と、 樹脂モールドを行なったリードフレームのリード部にメ
ッキを施した後にリードの曲げ加工を行い、引き続いて
該リードフレームより切断する工程と、 を少なくとも含むことを特徴とする混成集積回路の製造
方法。
1. A step of printing a thick film paste on the front and back surfaces of a ceramic substrate having through holes at predetermined positions to form wiring patterns such as lands, bonding pads, conductor lines, and through holes, and the substrate surface. After the chip parts are bonded and fixed to the prescribed positions, the circuit connection is performed, and the required lead pitch is obtained by punching a metal plate that is thinner than the metal plate used conventionally for lead frames. And a tip of the lead frame is formed on the ceramic substrate.
Bending process so that there is a step with a thickness of 1/2, using two lead frames, using a high melting point solder with the ceramic substrate clamped at the tip, the land of the ceramic substrate and the lead frame Of the lead frame is welded and fixed, the ceramic substrate with the tip of the lead frame is welded and fixed, is resin-molded by resin transfer molding, and the lead part of the resin-molded lead frame is plated. A method for manufacturing a hybrid integrated circuit, comprising the following steps: bending the leads after applying the leads, and subsequently cutting the leads from the lead frame.
JP4178729A 1992-07-07 1992-07-07 Manufacture of hybrid integrated circuit Withdrawn JPH0629443A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4178729A JPH0629443A (en) 1992-07-07 1992-07-07 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4178729A JPH0629443A (en) 1992-07-07 1992-07-07 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPH0629443A true JPH0629443A (en) 1994-02-04

Family

ID=16053560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4178729A Withdrawn JPH0629443A (en) 1992-07-07 1992-07-07 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPH0629443A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002343922A (en) * 2001-05-18 2002-11-29 Nec Kyushu Ltd Method for manufacturing semiconductor device
JP2016134620A (en) * 2015-01-20 2016-07-25 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic electronic component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002343922A (en) * 2001-05-18 2002-11-29 Nec Kyushu Ltd Method for manufacturing semiconductor device
JP2016134620A (en) * 2015-01-20 2016-07-25 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic electronic component

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