JP2784248B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor chip and a circuit component are integrally provided with resin sealing.

(Prior Art) The present applicant has previously proposed a method of manufacturing a semiconductor device in which a semiconductor chip and circuit components are integrally encapsulated and mounted (Japanese Patent Application No. 1-231134).

This method of manufacturing a semiconductor device includes forming a wiring pattern on a metal base using a non-etching metal such as gold, bonding a semiconductor chip to the metal base, and wire bonding the wiring pattern and the semiconductor chip, A method of sealing one side of a metal base on which is mounted a resin, further etching away the metal base part exposed from the resin sealing part to leave the wiring pattern, and only a wire bonding part on the metal base. After mounting the semiconductor chip in advance and performing wire bonding, one side of the metal base on which the semiconductor chip is mounted is resin-sealed,
This is a method of forming a wiring pattern on the metal base by etching the metal base in a predetermined pattern from the exposed surface side.

(Problem to be Solved by the Invention) The method of using the metal base as the mounting base of the semiconductor chip has a merit that a normal metal etching method can be used since the product is obtained by etching the metal base.

However, the conventional method has the following problems.

In the case of a method in which the metal base is finally completely removed by etching to leave only the wiring pattern made of a non-etching metal such as gold, the remaining wiring pattern needs to have a certain strength. A certain thickness or more is required. Since an expensive metal such as gold is used as the non-etching metal, the cost is high.

In the case of a method of forming a wiring pattern using the metal base itself as a conductor by etching the metal base, it is difficult to position the pattern because the wire bonding portion and the wiring pattern must be formed separately.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to enable a semiconductor chip and circuit components to be easily and integrally mounted, and to reduce the number of manufacturing steps and to manufacture the semiconductor chip. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of reducing costs and forming a wiring pattern with high accuracy.

(Means for Solving the Problems) The present invention has the following configuration to achieve the above object.

That is, a plating layer whose surface layer is made of a non-etching metal is provided on the surface opposite to the metal-based semiconductor chip mounting surface in accordance with a wiring pattern to be formed, and a required circuit component such as a semiconductor chip is mounted on the metal base. Then, one side on which the circuit component of the metal base is mounted is resin-sealed, and the circuit component is resin-sealed by etching the metal base as a protective film at the time of etching the plating layer. A semiconductor device having a wiring pattern formed thereon.

Further, on the metal-based semiconductor chip mounting surface,
According to a feature of the present invention, the required circuit components are mounted after a plating layer whose surface layer is made of a non-etching metal is provided according to a required wiring pattern such as a die attaching portion and a wire bonding portion.

Further, one or more conductor layers are further provided on the wiring pattern via an electrical insulating layer.

Also, on the opposite side of the metal-based semiconductor chip mounting surface,
According to the wiring pattern to be formed, a plating layer whose surface layer is made of a non-etching metal is provided, a required circuit component such as a semiconductor chip is mounted on the metal base, and one side of the metal base on which the circuit component is mounted is externally mounted. Providing an insertion hole for inserting the connection pin and sealing the resin, forming a conductive thin film on the surface of the sealing resin opposite to the surface to which the metal base is joined,
The metal base is etched as a protective film at the time of etching the plating layer and the conductive thin film is etched according to a predetermined pattern, and the pins are inserted into the insertion holes to electrically connect the metal base and the conductive thin film. By connecting, the circuit component is sealed with a resin to obtain a semiconductor device having pins for external connection.

Also, the end of the wiring pattern is extended to the side of the sealing resin for external connection, and after forming the wiring pattern, the pin is erected as an external connection terminal by being electrically connected to the wiring pattern. After forming the wiring pattern, it is useful to form a bump by electrically connecting to the wiring pattern as an external connection terminal.

As a method of connecting the semiconductor chip and the wiring pattern, a method of electrically connecting by wire bonding and a method of electrically connecting by a flip chip method are useful.

Further, an electrolytic copper foil is used as a metal base, and a rough surface side of the electrolytic copper foil is a mounting surface of the circuit component.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The manufacturing method according to the present invention can be applied to the manufacture of various types of semiconductor devices. Hereinafter, the manufacturing method will be described for some types.

<Flat Package Type> FIG. 1 shows an example in which the present invention is applied to a flat package type semiconductor device.

The manufacturing method of the present invention is characterized in that after a required wiring pattern is formed on a metal base in advance using a non-etching metal, resin sealing with a semiconductor chip mounted thereon is performed.

FIG. 1A shows a metal base 10 used in manufacturing. The material of the metal base 10 is not particularly limited as long as it can be easily dissolved and removed by etching. In the embodiment, an electrolytic copper foil is used as the metal base 10. The electrolytic copper foil has a rough surface on which copper grows and has an uneven shape. The rough surface is used on the side to be joined to the sealing resin. This is for improving the adhesion to the sealing resin.

First, a plating layer for forming a predetermined wiring pattern using a non-etching metal is provided on the metal base 10. Here, the wiring pattern is a die attaching portion for joining the semiconductor chip to the metal base 10, a wire bonding portion for connecting the semiconductor chip to the metal base,
It refers to a conductor layer portion such as a circuit pattern portion for connecting a semiconductor device to a lead frame or a mounting board.

The non-etching metal may be any metal that is not affected by an etchant used for dissolving and removing the metal base 10. In the embodiment, gold is used as the non-etching metal. Note that the plating layer 14 may be a laminate of a plurality of layers. In this case, the surface layer of the plating layer may be formed of a non-etching metal.

FIG. 1B shows a state in which a resist pattern 12 is formed on a metal base 10 in accordance with a wiring pattern. Since the wiring pattern is formed in a predetermined pattern on the metal base 10 as described above, the resist pattern 12 covers the surface of the metal base 10 except for the part where the wiring pattern is formed.
By plating the non-etching metal with the resist pattern 12 formed on the front and back surfaces of the metal base 10, a wiring pattern can be formed on the metal base 10.

In the embodiment, since the metal base 10 is used, after the resist pattern 12 is formed, the metal base 10 is etched to make the rough surface of the metal base 10 smooth before etching. Gold is used as the non-etching metal.

FIG. 1C shows a state in which the gold plating layer 14 is formed on the metal base 10 as described above.

Subsequently, the semiconductor chip 16 is mounted on the metal base 10.
Therefore, the resist pattern 12 is peeled and removed, the semiconductor chip 16 is bonded to the die attaching portion 18, and the wire bonding portion is removed.
20 and the semiconductor chip 16 are wire-bonded. The wire bonding part 20 smoothes the rough surface of the metal base 10,
Good bonding properties due to gold plating.

Next, the semiconductor chip 16 is sealed with a resin. Fig. 1 (d)
Is a state after resin sealing. In the case of resin sealing, only one side on which the semiconductor chip 16 of the metal base 10 is mounted as shown in the figure. 22 is a sealing resin.

After resin sealing, the metal base 10 exposed from the sealing resin 22 is etched. At this time, since the gold plating layer 14 exposed on the outer surface of the metal base 10 acts as an etching pattern, the gold plating layer 14, that is, the metal base 10 is etched according to the wiring pattern, and a semiconductor device having a predetermined wiring pattern is obtained. .

FIG. 1 (e) shows the semiconductor device thus obtained.
In the semiconductor device of this embodiment, the connection leads 24 extend outside the sealing resin 22. For example, as shown in the drawing, the connection leads 24 are connected to the inner leads 26 of the lead frame.
Can be connected and used.

FIG. 1 (f) shows a resist coating for protecting the wiring pattern while connecting the lead 25 formed in a gull wing shape, which is formed as a type to be mounted on a substrate.
This is an example in which 27 is provided.

FIG. 2 shows an example in which bumps are formed as external connection terminals.

A resist pattern 12 is provided on a metal base 10, and after etching, gold plating is applied and a gold plating layer is formed in a predetermined pattern.
14 are formed (FIG. 2A), and the semiconductor chips 16 are connected by wire bonding and sealed with a resin (FIG. 2B).

Next, the metal base 10 is etched to form a predetermined wiring pattern.

When bumps are formed, the exposed surface of the wiring pattern is subjected to protective coating, the bump forming portion of the protective coating 28 is etched to form a hole leading to the wiring pattern, and formed by solder plating or solder reflow, or a screen. There is a method in which holes are formed at bump formation locations by a printing method, a protective coating 28 is applied, and bumps 30 are formed.

FIG. 3 shows a type in which bumps are formed as external connection terminals similarly to FIG. 2, but bumps 30 can also be arranged on the back side of the mounting portion of the semiconductor chip 16 by a wiring pattern. There is an advantage that the flat space of the above can be effectively used as a bump forming portion and the overall size of the semiconductor device can be reduced.

In each of the semiconductor devices of the above embodiments, the semiconductor chip and the metal base are connected by wire bonding, but the same applies to the case of connection by the flip chip method.

FIG. 4 shows an embodiment in which the semiconductor chips 16 are connected by the flip chip method. It is obtained by forming a gold plating layer 14 on the metal base 10 (FIG. 4A), connecting the semiconductor chip 16, sealing with a resin, and etching the metal base 10 (FIG. 4B). ). FIG. 4 shows a state where the connection lead 24 is connected to the lead frame.

FIG. 5 shows an example of a semiconductor device in which the semiconductor chip 16 is mounted by the flip chip method and the bump 30 is formed.

There are various methods for mounting a semiconductor device, such as a method of using a connection lead as in the above example, forming a connection bump, and providing an exposed terminal for external connection. An appropriate type can be manufactured according to the mounting method.

The semiconductor device shown in each of the above embodiments has the following features from the manufacturing method.

In other words, by sealing the resin on one side of the metal base 10, it can be formed thinner and more compact than the conventional resin-sealed semiconductor device including the protective coating 28.

Since the gold plating layer 14 is used as an etching pattern and the main part of the conductor layer becomes the metal base 10, the thickness of the gold plating layer 14 does not need to be so large, which is advantageous in terms of cost.

When providing the gold plating layer 14 on the metal base 10,
Since the front and rear surfaces of the ten surfaces can be simultaneously patterned, the pattern can be accurately formed by eliminating the pattern deviation as compared with the case where the front and rear surfaces are patterned in separate steps.

In the case of a semiconductor device in which the connection lead 24 extends from the sealing resin 22, the connection lead 24 is bent into a predetermined shape before the metal base 10 is etched, and then the metal base 10 is etched. You may. According to this method, deformation of the connection lead 24 can be prevented.

<PGA Package Type> FIG. 6 shows a method of manufacturing a PGA package type. PGA
In the package type, a gold plating layer 14 is provided on the metal base 10, the semiconductor chip 16 is mounted, and then the resin is sealed (6th.
(FIG. 6 (a)), the metal base 10 is etched to form a wiring pattern, and the pins 32 are soldered (FIG. 6 (b)). A pattern for etching and forming a hole for connecting the pin 32 is formed in the gold plating layer 14 in advance.

FIG. 7 shows another embodiment of the PGA package type.
In this embodiment, the pins 32 are provided to penetrate the sealing resin 22 side. The semiconductor device of this embodiment has a semiconductor chip 16
A method of molding the pin 32 integrally with the sealing resin 22 by insert molding when sealing the resin, forming an insertion hole for inserting the pin 32 at the time of resin sealing, and inserting the pin 32 in a later process You can use the connection method.

After connecting the pins 32, the metal base 10 is etched to form a predetermined wiring pattern.

<Multilayer Package Type> Although the semiconductor device of each of the above embodiments has a single wiring pattern (conductor layer), the semiconductor device can also be used for manufacturing a multilayer package type semiconductor device having a multilayered conductor layer.

FIG. 8 shows an example of manufacturing a multilayer package type semiconductor device.

FIG. 8A shows a state in which the semiconductor chip 16 is wire-bonded, sealed with a resin, and the metal base 10 is etched to form a wiring pattern. The manufacturing method up to this point is the same as in the above embodiment. As a result, a first conductor layer is formed.

Next, an insulating layer 34 is formed on the first conductive layer by using an electrically insulating material, and the insulating layer 34 is etched to provide a hole for forming a via, or a via forming portion is formed by a screen printing method. A via 36 is formed by filling the hole with a conductive material (FIG. 8 (b)).

Next, a conductor layer 38 is formed on the insulating layer 34, and a predetermined pattern is formed by etching or the like. As a method for forming the conductor layer 38, a known method for forming a conductor layer, sputtering, vapor deposition, plating, or the like can be used.

As shown in FIG. 8 (a), a semiconductor device having a multi-layered conductor layer can be formed in such a manner as to be exposed to the outside on the back side of the semiconductor chip 16 according to the method of the present invention, as shown in FIG. This is because an arbitrary wiring pattern can be formed. Therefore, according to the above method, it is possible to easily provide a further multilayered conductor layer by interposing an insulating layer in the middle.

In the case where a terminal for external connection is provided, the above-described method such as bump formation may be used.

FIG. 9 is an example of a semiconductor device having two conductor layers.

In manufacturing this semiconductor device, first, the ninth
As shown in FIG. 1A, when the gold plating layer 14 is formed, a non-plated portion 39 for forming a through hole for inserting the pin 32 is provided. An insertion hole 40 for inserting the 32 is provided and molding is performed.

Next, a conductive thin film 42 is formed on the lower surface of the sealing resin 22, a predetermined resist pattern is formed on the conductive thin film 42, and then the conductive thin film 42 and the metal base 10 are etched to form a conductive layer having a predetermined wiring pattern. It is formed on the front and back surfaces of the sealing resin 22.

Next, the pin 32 is inserted into the insertion hole 40, and the sealing resin 22 is inserted.
Electrical connection is made between the conductor layers on the front and back surfaces. This allows
As shown in FIG. 9B, a semiconductor device having two conductor layers is obtained.

FIG. 10 shows another embodiment of the semiconductor having the conductor layers on the front and back surfaces of the sealing resin 22, respectively. In the semiconductor device of this embodiment, a gold plating layer 14 is provided in a predetermined pattern on the metal base 10 on which the semiconductor chip 16 is mounted, and the semiconductor chip 16 is mounted and wire-bonded, and the gold plating layer 14 in a predetermined pattern is provided. After forming the metal base 10 as a separate body, inserting the two metal bases into a molding die and integrally sealing with resin (FIG. 10 (a)), the conductor layers on the front and back sides are plated with a gold plating layer 14. By etching as an etching pattern.

In the case of a semiconductor device in which two conductor layers are provided, the conductor layer on one or both sides can be further formed in multiple layers in the same manner as in the example shown in FIG. .

In the above description, an example is shown in which the semiconductor chips 16 are connected by wire bonding. However, the same applies to the case where the semiconductor chips 16 are mounted by the flip chip method as shown in FIG.

Further, in each of the above embodiments, the example in which the semiconductor chip is sealed with a resin is shown, but the wiring pattern is formed by using a metal base using a plating layer formed of a non-etching metal provided on the surface opposite to the semiconductor chip mounting surface. Since it is formed by etching, an arbitrary wiring pattern can be formed. Therefore, it is very easy to mount other required circuit components together with the semiconductor chip. By mounting other circuit components, various electronic components according to various applications can be manufactured.

As described above, the present invention has been described variously with reference to the preferred embodiments. However, the present invention is not limited to these embodiments, and it goes without saying that many modifications can be made without departing from the spirit of the invention. That is.

(Effects of the Invention) According to the method of manufacturing a semiconductor device according to the present invention, the following significant effects are obtained.

Since the semiconductor chip is bonded to the metal base and resin-molded, the metal base is etched to form a wiring pattern, so that deformation of leads and the like can be prevented.

Because the metal base is held by the sealing resin,
A thin metal base can be used, and as a result, a fine pattern can be formed with high accuracy.

Since etching is performed after resin sealing, a tie bar becomes unnecessary.

Since the pattern is simultaneously formed on the front and back surfaces of the metal base, it is possible to eliminate the pattern shift between the front and back surfaces of the metal base.

Since the non-etching metal is used as an etching pattern, it does not need to be formed so thick, and the cost can be reduced when an expensive metal such as gold is used.

The entire planar space of the semiconductor device can be effectively used as a space for external connection such as a bump.

The present invention can be applied to the manufacture of various types of semiconductor devices, and can also be applied to a multilayer semiconductor device having a plurality of conductor layers.

Other circuit components can be simultaneously mounted in addition to the semiconductor chip, so that various electronic devices can be manufactured.

When an electrolytic copper foil is used as the metal base, the adhesion between the sealing resin and the wiring pattern is improved, and peeling or the like can be prevented, thereby improving the reliability of the device.

[Brief description of the drawings]

1 to 5 are flat package type semiconductor devices manufactured by the manufacturing method according to the present invention, and FIGS.
PGA package type semiconductor device, FIGS. 8 and 9
FIG. 10 is an explanatory view showing an example of manufacturing a multilayer package type semiconductor device. 10: Metal base, 12: Resist pattern, 14: Gold plating layer, 16: Semiconductor chip, 20: Wire bonding part, 22: Sealing resin, 28: Protective coating, 29
…… Adhesive, 30 …… Bump, 31 …… Insulating film, 34…
... insulating layer, 36 via, 38 ... conductor layer, 40 ... insertion hole,
42 ... Conductor thin film.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-94431 (JP, A) JP-A-3-94430 (JP, A) JP-A-2-151496 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H01L 21/50 H01L 23/12-23/14 H01L 21/60 301 H01L 21/60 311

Claims (10)

(57) [Claims] A plating layer having a surface layer made of a non-etching metal is provided on a surface opposite to a metal-based semiconductor chip mounting surface according to a wiring pattern to be formed, and a required circuit such as a semiconductor chip is provided on the metal base. A component is mounted, and one side of the metal base on which the circuit component is mounted is resin-sealed, and the circuit component is resin-sealed by etching the metal base as a protective film when etching the plating layer. A method for manufacturing a semiconductor device, comprising: obtaining a semiconductor device having a wiring pattern formed on a resin. 2. A method according to claim 1, further comprising: providing a plating layer whose surface layer is made of a non-etching metal on the semiconductor chip mounting surface of the metal base in accordance with a required wiring pattern such as a die attaching portion and a wire bonding portion. 2. The method according to claim 1, further comprising mounting a circuit component. 3. The method of manufacturing a semiconductor device according to claim 1, wherein one or two or more conductor layers are further provided on the wiring pattern via an electrical insulating layer. 4. A plating layer having a surface layer made of a non-etching metal according to a wiring pattern to be formed on a surface opposite to a metal-based semiconductor chip mounting surface, and a required circuit such as a semiconductor chip is provided on the metal base. A component is mounted, and one side of the metal base on which the circuit component is mounted is provided with an insertion hole through which an external connection pin is inserted, and is resin-sealed. On a surface of the sealing resin opposite to the surface to which the metal base is joined Forming a conductive thin film, etching the metal base as a protective film when etching the plating layer, etching the conductive thin film according to a predetermined pattern, fitting the pin into the insertion hole, and connecting the metal base and the conductor. The circuit device according to claim 1, wherein the circuit component is resin-sealed by electrically connecting the thin film to the thin film to obtain a semiconductor device having pins for external connection. Manufacturing method 5. An end of a wiring pattern extending to a side of a sealing resin for external connection.
4. The method for manufacturing a semiconductor device according to 2 or 3. 6. The method for manufacturing a semiconductor device according to claim 1, wherein after forming the wiring pattern, pins are electrically connected to the wiring pattern as external connection terminals and pins are erected. 7. The method of manufacturing a semiconductor device according to claim 1, wherein after forming the wiring pattern, a bump is formed as an external connection terminal by being electrically connected to the wiring pattern. 8. The method according to claim 1, wherein the semiconductor chip and the wiring pattern are electrically connected by wire bonding. 9. The method according to claim 1, wherein the semiconductor chip and the wiring pattern are electrically connected by a flip chip method. 10. The method according to claim 1, wherein an electrolytic copper foil is used as a metal base, and a rough surface side of the electrolytic copper foil is used as a mounting surface of the circuit component. 10. The method for manufacturing a semiconductor device according to 7, 8, or 9.