JP2001291800A - Package for electronic component - Google Patents
Package for electronic componentInfo
- Publication number
- JP2001291800A JP2001291800A JP2000145720A JP2000145720A JP2001291800A JP 2001291800 A JP2001291800 A JP 2001291800A JP 2000145720 A JP2000145720 A JP 2000145720A JP 2000145720 A JP2000145720 A JP 2000145720A JP 2001291800 A JP2001291800 A JP 2001291800A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- package
- metal circuit
- concave shape
- circuit layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本考案は、半導体チップ等の電子
部品を収容する電子部品用パッケージ、特に電子部品を
収容するための凹形状を有することを特徴とする電子部
品用パッケージ及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for an electronic component containing an electronic component such as a semiconductor chip, and more particularly to a package for an electronic component having a concave shape for containing an electronic component and a method of manufacturing the same. About.
【０００２】[0002]
【従来の技術】通常、半導体チップ等の電子部品（以
下、電子部品という）を収容する凹形状を有する電子部
品用パッケージ（以下、パッケージという）において、
電子部品と絶縁層を介した他の金属回路層とを電気的に
接続させる場合は、搭載した電子部品側の接続端子とワ
イヤーボンディングするための金属回路を電子部品の周
囲に設ける方法が用いられている。2. Description of the Related Art Generally, in a package for an electronic component having a concave shape for accommodating an electronic component such as a semiconductor chip (hereinafter referred to as an electronic component) (hereinafter referred to as a package),
When electrically connecting an electronic component to another metal circuit layer via an insulating layer, a method of providing a metal circuit around the electronic component for wire bonding with a connection terminal on the mounted electronic component is used. ing.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、図１１
に示す上記に記した従来のパッケージにおいては、搭載
した電子部品の接続端子とワイヤーボンディング（８
０）するためのワイヤーボンディング用金属回路（９
０）を電子部品の周囲に設ける必要があるので、電子部
品を収容する凹形状は該ワイヤーボンディング用金属回
路を設けるエリアを確保して大きくしなければならない
ことからパッケージの小型化を阻害する。本発明はこの
ような問題点を鑑みてなされ、凹形状の底部に薄い絶縁
層、該絶縁層の裏面に金属回路層、該絶縁層の上面より
裏面の金属回路層に至る穴、及び、該穴の上に電気的導
通性を有する接続端子を有し、該接続端子により、該凹
形状内に収容された電子部品と該金属回路層を電気的に
接続して、パッケージの小型化を実現することを目的と
している。また、凹形状内に収容した電子部品の直上に
他の電子部品を搭載することで、小型パッケージの部品
実装密度を向上し、パッケージの多機能化を実現するこ
とを目的としている。However, FIG.
In the conventional package described above, the connection terminal of the mounted electronic component is connected to the wire bonding (8).
0) metal circuit for wire bonding (9
Since it is necessary to provide (0) around the electronic component, the concave shape for accommodating the electronic component needs to secure an area where the metal circuit for wire bonding is to be provided and be large, which hinders miniaturization of the package. The present invention has been made in view of such problems, a thin insulating layer at the bottom of the concave shape, a metal circuit layer on the back surface of the insulating layer, a hole extending from the upper surface of the insulating layer to the metal circuit layer on the back surface, and A connection terminal having electrical conductivity is provided on the hole, and the connection terminal electrically connects the electronic component housed in the concave shape to the metal circuit layer, thereby realizing a compact package. It is intended to be. It is another object of the present invention to increase the component mounting density of a small package and realize multifunctional package by mounting another electronic component directly above the electronic component housed in the concave shape.
【０００４】[0004]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明のパッケージは次の構成を備える。すなわ
ち、凹形状の底部に薄い絶縁層、該絶縁層の裏面に金属
回路層、該絶縁層の上面より裏面の金属回路層に至る
穴、及び、該穴の上に電気的導通性を有する接続端子を
有し、該接続端子により、前記凹形状内に収容された電
子部品と該金属回路層を電気的に接続することを特徴と
する。また、凹形状内に収容した電子部品の直上に他の
電子部品を搭載することを特徴とする。In order to achieve the above object, a package according to the present invention has the following configuration. That is, a thin insulating layer at the bottom of the concave shape, a metal circuit layer on the back surface of the insulating layer, a hole extending from the upper surface of the insulating layer to the metal circuit layer on the back surface, and a connection having electrical conductivity on the hole. And a metal circuit layer electrically connected to the electronic component housed in the concave shape by the connection terminal. Further, another electronic component is mounted immediately above the electronic component housed in the concave shape.
【０００５】[0005]
【作用】本発明によれば、凹形状の底部に薄い絶縁層、
該絶縁層の裏面に金属回路層、該絶縁層の上面より裏面
の金属回路層に至る穴、及び、該穴の上に電気的導通性
を有する接続端子を有し、該接続端子により、該凹形状
内に収容された電子部品と該金属回路層を電気的に接続
して、パッケージの小型化を可能とする。また、凹形状
内に収容した電子部品の直上に他の電子部品を搭載する
ことで、小型パッケージの部品実装密度を向上し、パッ
ケージの多機能化を可能とする。According to the present invention, a thin insulating layer is provided on the concave bottom,
A metal circuit layer on the back surface of the insulating layer, a hole extending from the upper surface of the insulating layer to the metal circuit layer on the back surface, and a connection terminal having electrical conductivity on the hole; The electronic component housed in the concave shape and the metal circuit layer are electrically connected, and the package can be reduced in size. In addition, by mounting another electronic component directly above the electronic component housed in the concave shape, the component mounting density of a small package can be improved, and the package can be multifunctional.
【０００６】[0006]
【実施例】以下、本発明に係るパッケージ及びその製造
方法に関する好適な実施例について添付図面とともに説
明する。図では、説明上一部のみ示す。また、収容する
電子部品としては半導体チップを例示する。 図１は、通常のプリント配線基板の製造工程を経
て、所要の金属回路層（３０）を形成した後、ザグリ工
法を用いて、電子部品を収容する凹形状を形成した本発
明に係る電子部品用パッケージの断面図である。図２
は、あらかじめ電子部品を収容する所要の大きさの窓明
け加工した基材と該基材の下方に位置する金属回路層
（３０）と、該基材と該金属回路層を接着するためのあ
らかじめ電子部品を収容する所要の大きさの窓明け加工
した接着性絶縁層（２０）を張り合わせる工法、即ち張
り合わせ工法にて凹形状を形成した、本発明に係る電子
部品用パッケージの断面図である。図３は、あらかじめ
半導体チップ等の電子部品を収容する所要の大きさの窓
明け加工した基材と、該基材の下方に位置するあらかじ
め所要の部位にソルダーレジスト層（２５）を被着した
金属回路層（３０）と、該基材と該金属回路層を接着す
るためのあらかじめ半導体チップ等の電子部品を収容す
る所要の大きさの窓明け加工した接着性を有する絶縁層
（２０）を張り合わせて凹形状を形成した本発明に係る
電子部品用パッケージの断面図である。図４は、あらか
じめ半導体チップ等の電子部品を収容する所要の大きさ
の窓明け加工した基材と、該基材の下方に金属回路層を
被着した接着性絶縁層（２０）を張り合わせて形成した
凹形状を有する電子部品用パッケージ。凹形状底部の絶
縁層の厚さは、１０μｍから１００μｍとすることがで
き、後工程で設ける接続端子間の電気的短絡を防止する
作用を有する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a package according to the present invention and a manufacturing method thereof will be described below with reference to the accompanying drawings. In the figure, only a part is shown for explanation. A semiconductor chip is exemplified as an electronic component to be housed. FIG. 1 shows an electronic component according to the present invention in which a required metal circuit layer (30) is formed through a normal printed wiring board manufacturing process, and then a concave shape for housing the electronic component is formed by using a counterbore method. FIG. FIG.
Is a window-processed base material of a required size for accommodating an electronic component in advance, a metal circuit layer (30) located below the base material, and a pre-bonding method for bonding the base material and the metal circuit layer. FIG. 2 is a cross-sectional view of an electronic component package according to the present invention, in which a concave shape is formed by a method of bonding a window-formed adhesive insulating layer (20) having a required size for housing an electronic component, that is, a bonding method. . FIG. 3 shows a window-processed base material of a required size for accommodating electronic components such as a semiconductor chip in advance, and a solder resist layer (25) applied to a predetermined site below the base material in advance. A metal circuit layer (30) and an insulating layer (20) having an adhesive property and having a window of a required size for accommodating an electronic component such as a semiconductor chip in advance for bonding the substrate and the metal circuit layer. It is sectional drawing of the package for electronic components which concerns on this invention and formed the concave shape by sticking together. FIG. 4 shows a base material having a window of a required size for accommodating an electronic component such as a semiconductor chip in advance, and an adhesive insulating layer (20) having a metal circuit layer adhered below the base material. An electronic component package having a formed concave shape. The thickness of the insulating layer at the bottom of the concave shape can be set to 10 μm to 100 μm, and has an effect of preventing an electric short circuit between connection terminals provided in a later step.
【０００７】 図５は、図１に示す本実施例の製造方
法を説明するための断面図である。図５（ａ）は、通常
のプリント配線基板の製造工程を経て、所要の金属回路
層（３０）を形成した後、ザグリ工法を用いて電子部品
を収容する凹形状底部の薄い絶縁層（１０）を形成した
状態を示す。図５（ｂ）は、凹形状底部の薄い絶縁層
（１０）に、レーザー加工によって下方の金属回路層
（３０）に至る所要の穴（４０）を設けた後、該穴（４
０）の開口により露出した金属回路層及び他の露出した
金属回路層にメッキ処理を施してメッキ層（５０）を被
着形成した状態を示す。このレーザー加工は、ビルドア
ップ工法等に採用されているものを適用できる。また、
メッキ処理は、通常のプリント配線基板の製造工程で採
用されるニッケル・金メッキ等の金属メッキが適用でき
る。メッキ処理を施すことにより、耐湿性・耐腐食性・
接続の信頼性が向上する点で望ましい。図５（ｃ）は、
前記穴（４０）の上に電気的導通性を有する接続端子を
設けた状態を示す。本実施例は、該接続端子として半田
ボール（６０）を採用した。該半田ボールは、絶縁層
（１０）に設けられた所要の穴（４０）に位置決めして
搭載された後、リフロー等により加熱加工されてメッキ
処理を施された下方の金属回路層（３０）に固着され
る。FIG. 5 is a cross-sectional view for explaining the manufacturing method of the embodiment shown in FIG. FIG. 5 (a) shows that after forming a required metal circuit layer (30) through a normal printed wiring board manufacturing process, a thin insulating layer (10) having a concave bottom for accommodating an electronic component by using a counterbore method. ) Is shown. FIG. 5 (b) shows that a required hole (40) reaching the lower metal circuit layer (30) is formed in the thin insulating layer (10) at the concave bottom by laser processing, and then the hole (4) is formed.
A state in which a plating process is applied to the metal circuit layer exposed through the opening 0) and the other exposed metal circuit layer to form a plating layer (50) thereon. For this laser processing, those employed in the build-up method or the like can be applied. Also,
As the plating process, metal plating such as nickel and gold plating employed in a normal printed wiring board manufacturing process can be applied. By applying plating, moisture resistance, corrosion resistance,
This is desirable in that connection reliability is improved. FIG. 5 (c)
A state in which a connection terminal having electrical conductivity is provided on the hole (40) is shown. In this embodiment, a solder ball (60) is employed as the connection terminal. The solder balls are positioned and mounted in required holes (40) provided in the insulating layer (10), and then heated and processed by reflow or the like and plated to form a lower metal circuit layer (30). To be fixed.
【０００８】 図６は、図２に示す本実施例の製造方
法を説明するための断面図である。図６（ａ）は、あら
かじめ電子部品を収容する所要の大きさの窓明け加工し
た基材と、該基材の下方に位置する金属回路層（３０）
と、該基材と該金属回路層を接着するためのあらかじめ
電子部品を収容する所要の大きさの窓明け加工した接着
性絶縁層（２０）を張り合わせる工法、即ち張り合わせ
工法にて凹形状を形成した状態を示す。図６（ｂ）は、
凹形状底部の薄い絶縁層（１０）に、レーザー加工によ
って下方の金属回路層（３０）に至る所要の穴（４０）
を設けた後、該穴（４０）の開口により露出した金属回
路層及び他の露出した金属回路層にメッキ処理を施して
メッキ層（５０）を被着形成した状態を示す。このレー
ザー加工は、ビルドアップ工法等に採用されているもの
を適用できる。また、メッキ処理は、通常のプリント配
線基板の製造工程で採用されるニッケル・金メッキ等の
金属メッキが適用できる。メッキ処理を施すことによ
り、耐湿性・耐腐食性・接続の信頼性が向上する点で望
ましい。図６（ｃ）は、前記穴（４０）の上に電気的導
通性を有する接続端子を設けた状態を示す。本実施例
は、該接続端子として半田ボール（６０）を採用した。
該半田ボールは、絶縁層（１０）に設けられた所要の穴
（４０）に位置決めして搭載された後、リフロー等によ
り加熱加工されてメッキ処理を施された下方の金属回路
層（３０）に固着される。FIG. 6 is a cross-sectional view for explaining the manufacturing method of the present embodiment shown in FIG. FIG. 6A shows a window-processed base material of a required size for housing electronic components in advance, and a metal circuit layer (30) located below the base material.
And a method of bonding an adhesive insulating layer (20) having a window of a required size for accommodating an electronic component in advance for bonding the substrate and the metal circuit layer, that is, forming a concave shape by a bonding method. This shows the formed state. FIG. 6 (b)
The required holes (40) leading to the lower metal circuit layer (30) by laser machining in the thin insulating layer (10) at the bottom of the concave shape
After plating, the metal circuit layer exposed through the opening of the hole (40) and the other exposed metal circuit layer are subjected to a plating treatment to form a plating layer (50). For this laser processing, those employed in the build-up method or the like can be applied. Further, as the plating process, metal plating such as nickel and gold plating employed in a normal printed wiring board manufacturing process can be applied. Plating is desirable in that moisture resistance, corrosion resistance, and connection reliability are improved. FIG. 6C shows a state in which a connection terminal having electrical conductivity is provided on the hole (40). In this embodiment, a solder ball (60) is employed as the connection terminal.
The solder balls are positioned and mounted in required holes (40) provided in the insulating layer (10), and then heated and processed by reflow or the like and plated to form a lower metal circuit layer (30). To be fixed.
【０００９】 図７は、図３に示す本実施例の製造方
法を説明するための断面図である。図７（ａ）は、あら
かじめ半導体チップ等の電子部品を収容する所要の大き
さの窓明け加工した基材と、該基材の下方に位置するあ
らかじめ所要の部位に接続端子を設けるための開口を有
するソルダーレジスト層（２５）を被着した金属回路層
（３０）と、該基材と該金属回路層を接着するためのあ
らかじめ半導体チップ等の電子部品を収容する所要の大
きさの窓明け加工した接着性を有する絶縁層（２０）を
張り合わせて凹形状を形成した状態を示す。図７（ｂ）
は、ソルダーレジスト開口（４５）により露出した金属
回路層及び他の露出した金属回路層にメッキ処理を施し
てメッキ層（５０）を被着形成した状態を示す。メッキ
処理を施すことにより、耐湿性・耐腐食性・接続の信頼
性が向上する点で望ましい。このメッキ処理は、通常の
プリント配線基板の製造工程で採用されるニッケル・金
メッキ等の金属メッキが適用できる。図７（ｃ）は、前
記ソルダーレジスト開口（４５）の上に電気的導通性を
有する接続端子を設けた状態を示す。本実施例は、該接
続端子として半田ボール（６０）を採用した。該半田ボ
ールは、所要の部位に設けられたソルダーレジスト開口
（４５）に位置決めして搭載された後、リフロー等によ
り加熱加工されてメッキ処理を施された下方の金属回路
層（３０）に固着される。FIG. 7 is a cross-sectional view for explaining the manufacturing method of the present embodiment shown in FIG. FIG. 7 (a) shows a window-processed base material of a required size for accommodating an electronic component such as a semiconductor chip in advance, and an opening for providing a connection terminal at a predetermined site below the base material. A metal circuit layer (30) on which a solder resist layer (25) having the following is applied, and a window of a required size for accommodating an electronic component such as a semiconductor chip in advance for bonding the substrate and the metal circuit layer. The state where the processed insulating layer (20) having adhesiveness is bonded to form a concave shape is shown. FIG. 7 (b)
Shows a state where the metal circuit layer exposed through the solder resist opening (45) and the other exposed metal circuit layer are subjected to plating to form a plating layer (50). Plating is desirable in that moisture resistance, corrosion resistance, and connection reliability are improved. For this plating process, metal plating such as nickel and gold plating employed in a normal printed wiring board manufacturing process can be applied. FIG. 7C shows a state in which a connection terminal having electrical conductivity is provided on the solder resist opening (45). In this embodiment, a solder ball (60) is employed as the connection terminal. The solder ball is positioned and mounted in a solder resist opening (45) provided at a required portion, and then is fixed to a lower metal circuit layer (30) which has been subjected to a heating process such as a reflow process and plated. Is done.
【００１０】 図８は、図４に示す本実施例の製造方
法を説明するための断面図である。図８（ａ）は、あら
かじめ電子部品を収容する所要の大きさの窓明け加工し
た基材と、該基材の下方に金属回路層（３０）を被着し
た接着性絶縁層（２０）を張り合わせる工法、即ち張り
合わせ工法にて凹形状を形成した状態を示す。図８
（ｂ）は、凹形状底部の薄い絶縁層（１０）に、レーザ
ー加工によって下方の金属回路層（３０）に至る所要の
穴（４０）を設けた後、該穴（４０）の開口により露出
した金属回路層及び他の露出した金属回路層にメッキ処
理を施してメッキ層（５０）を被着形成した状態を示
す。このレーザー加工は、ビルドアップ工法等に採用さ
れているものを適用できる。また、メッキ処理は、通常
のプリント配線基板の製造工程で採用されるニッケル・
金メッキ等の金属メッキが適用できる。メッキ処理を施
すことにより、耐湿性・耐腐食性・接続の信頼性が向上
する点で望ましい。図８（ｃ）は、前記穴（４０）の上
に電気的導通性を有する接続端子を設けた状態を示す。
本実施例は、該接続端子として半田ボール（６０）を採
用した。該半田ボールは、絶縁層（１０）に設けられた
所要の穴（４０）に位置決めして搭載された後、リフロ
ー等により加熱加工されてメッキ処理を施された下方の
金属回路層（３０）に固着される。FIG. 8 is a cross-sectional view for explaining the manufacturing method of the present embodiment shown in FIG. FIG. 8A shows a window-processed base material of a required size for housing electronic components in advance, and an adhesive insulating layer (20) having a metal circuit layer (30) applied below the base material. The state in which the concave shape is formed by the bonding method, that is, the bonding method is shown. FIG.
(B) shows a case in which a required hole (40) reaching the lower metal circuit layer (30) is provided in a thin insulating layer (10) at the bottom of the concave shape by laser processing, and then exposed through the opening of the hole (40). This shows a state in which a plating process is performed on the metal circuit layer thus formed and the other exposed metal circuit layers to form a plating layer (50). For this laser processing, those employed in the build-up method or the like can be applied. In addition, the plating process is performed by using nickel or
Metal plating such as gold plating can be applied. Plating is desirable in that moisture resistance, corrosion resistance, and connection reliability are improved. FIG. 8C shows a state in which a connection terminal having electrical conductivity is provided on the hole (40).
In this embodiment, a solder ball (60) is employed as the connection terminal. The solder balls are positioned and mounted in required holes (40) provided in the insulating layer (10), and then heated and processed by reflow or the like and plated to form a lower metal circuit layer (30). To be fixed.
【００１１】図９は、本発明に係る多層パッケージの実
施例を示す。多層化は通常のプリント配線基板の工程で
容易に製造することができ、本発明に係るパッケージの
他の実施例においても、多層化は同様に可能であり、本
発明はパッケージの層数に関わらず適用できる。FIG. 9 shows an embodiment of a multilayer package according to the present invention. Multilayering can be easily manufactured in a normal printed wiring board process, and in other embodiments of the package according to the present invention, multilayering is also possible, and the present invention is not limited to the number of layers of the package. Applicable.
【００１２】図１０は、本発明に係るパッケージにおい
て、凹形状内に収容した電子部品の直上に他の電子部品
を搭載したパッケージの例を示す。凹形状内に収容した
電子部品は、リフロー等の加熱処理により半田ボールと
接続される。その後、該電子部品の直上に他の電子部品
を固着する。このとき、通常の接着性を有する銀ペース
ト等で容易に接着することができる。該直上に固着され
た電子部品は、ワイヤーボンディングにより所要の金属
回路と接続される。こうして、凹形状内に収容した電子
部品の直上に他の電子部品を搭載することで小型パッケ
ージの部品実装密度を向上することができる。FIG. 10 shows an example of a package according to the present invention in which another electronic component is mounted immediately above an electronic component housed in a concave shape. The electronic component housed in the concave shape is connected to the solder ball by a heat treatment such as reflow. Thereafter, another electronic component is fixed just above the electronic component. At this time, it can be easily bonded with a silver paste or the like having a normal adhesive property. The electronic component fixed immediately above is connected to a required metal circuit by wire bonding. In this manner, by mounting another electronic component immediately above the electronic component housed in the concave shape, the component mounting density of the small package can be improved.
【００１３】[0013]
【発明の効果】本発明によれば、凹形状の底部に薄い絶
縁層、該絶縁層の裏面に金属回路層、該絶縁層の表裏を
貫通する穴、及び、該穴の上方に電気的導通性を有する
接続端子を有し、該接続端子により、該凹形状内に収容
された電子部品と該金属回路層を電気的に接続してパッ
ケージの小型化を実現する。また、凹形状内に収容した
電子部品の直上に他の電子部品を搭載することで、小型
パッケージの部品実装密度を向上し、パッケージの多機
能化を実現する。According to the present invention, a thin insulating layer is provided at the bottom of the concave shape, a metal circuit layer is provided at the back surface of the insulating layer, a hole penetrating the front and back of the insulating layer, and an electrical connection is provided above the hole. A connection terminal having electrical characteristics, and the connection terminal electrically connects the electronic component housed in the concave shape to the metal circuit layer, thereby realizing a compact package. In addition, by mounting another electronic component directly above the electronic component housed in the concave shape, the component mounting density of a small package is improved, and the multifunctionality of the package is realized.
【図１】ザグリ工法により凹形状を形成した本発明によ
るパッケージの断面図。FIG. 1 is a sectional view of a package according to the present invention in which a concave shape is formed by a counterbore method.
【図２】張り合わせ工法により凹形状を形成した本発明
によるパッケージの断面図。FIG. 2 is a cross-sectional view of a package according to the present invention in which a concave shape is formed by a bonding method.
【図３】ソルダーレジスト層を有する張り合わせ工法に
より凹形状を形成した本発明によるパッケージの断面
図。FIG. 3 is a cross-sectional view of a package according to the present invention in which a concave shape is formed by a bonding method having a solder resist layer.
【図４】接着層を兼ねた絶縁層を有する張り合わせ工法
により凹形状を形成した本発明によるパッケージの断面
図。FIG. 4 is a sectional view of a package according to the present invention in which a concave shape is formed by a bonding method having an insulating layer also serving as an adhesive layer.
【図５】ザグリ工法により凹形状を形成した本発明によ
るパッケージの製造方法を説明する断面図。FIG. 5 is a sectional view for explaining a method of manufacturing a package according to the present invention in which a concave shape is formed by a counterbore method.
【図６】張り合わせ工法により凹形状を形成した本発明
によるパッケージの製造方法を説明する断面図。FIG. 6 is a cross-sectional view illustrating a method of manufacturing a package according to the present invention in which a concave shape is formed by a bonding method.
【図７】ソルダーレジスト層を有する張り合わせ工法に
より凹形状を形成した本発明によるパッケージの製造方
法を説明する断面図。FIG. 7 is a cross-sectional view illustrating a method of manufacturing a package according to the present invention in which a concave shape is formed by a bonding method having a solder resist layer.
【図８】接着層を兼ねた絶縁層を有する張り合わせ工法
により凹形状を形成した本発明によるパッケージの製造
方法を説明する断面図。FIG. 8 is a cross-sectional view illustrating a method for manufacturing a package according to the present invention in which a concave shape is formed by a bonding method having an insulating layer also serving as an adhesive layer.
【図９】多層化した本発明によるパッケージ実施例の断
面図。FIG. 9 is a cross-sectional view of a multilayered package embodiment according to the present invention.
【図１０】凹形状内に収容した電子部品の直上に他の電
子部品を搭載した本発明によるパッケージ実施例の断面
図。FIG. 10 is a sectional view of an embodiment of a package according to the present invention in which another electronic component is mounted immediately above an electronic component housed in a concave shape.
【図１１】パッケージの小型化を阻害する状態を示し
た、従来のパッケージの断面図。FIG. 11 is a cross-sectional view of a conventional package showing a state in which miniaturization of the package is impeded.
１０ 絶縁層 ２０ 接着性絶縁層 ２５ ソルダーレジスト層 ３０ 金属回路層 ４０ 穴 ４５ ソルダーレジスト開口 ５０ メッキ層 ６０ 半田ボール ７０ 半導体チップ ８０ ワイヤーボンディング ９０ ワイヤーボンディング用金属回路 DESCRIPTION OF SYMBOLS 10 Insulating layer 20 Adhesive insulating layer 25 Solder resist layer 30 Metal circuit layer 40 Hole 45 Solder resist opening 50 Plating layer 60 Solder ball 70 Semiconductor chip 80 Wire bonding 90 Metal circuit for wire bonding
Claims (8)
の凹形状を有する電子部品用パッケージにおいて、凹形
状の底部に薄い絶縁層、該絶縁層の裏面に金属回路層、
該絶縁層の上面より裏面の金属回路層に至る穴、及び、
該穴の上に電気的導通性を有する接続端子を有し、該接
続端子により、該凹形状内に収容された半導体チップ等
の電子部品と該金属回路層を電気的に接続する電子部品
用パッケージ。An electronic component package having a concave shape for accommodating an electronic component such as a semiconductor chip, wherein a thin insulating layer is provided on the bottom of the concave shape, and a metal circuit layer is provided on a back surface of the insulating layer.
A hole extending from the upper surface of the insulating layer to the metal circuit layer on the back surface, and
An electronic component having a connection terminal having electrical conductivity on the hole and electrically connecting the metal circuit layer with an electronic component such as a semiconductor chip housed in the concave shape by the connection terminal. package.
おいて、ザグリ工法を用いて形成した凹形状を有する電
子部品用パッケージ。2. The electronic component package according to claim 1, wherein the electronic component package has a concave shape formed by a counterbore method.
おいて、あらかじめ半導体チップ等の電子部品を収容す
る所要の大きさの窓明け加工した基材と、該基材の下方
に位置する金属回路層と、該基材と該金属回路層を接着
するためのあらかじめ半導体チップ等の電子部品を収容
する所要の大きさの窓明け加工した接着性性を有する絶
縁層層を張り合わせて形成した凹形状を有する電子部品
用パッケージ。3. A package for an electronic component according to claim 1, wherein a base material having a required size for receiving an electronic component such as a semiconductor chip is preliminarily opened, and a metal circuit located below the base material. A concave shape formed by laminating a layer and an insulating layer having an adhesive property in which a window of a required size for accommodating an electronic component such as a semiconductor chip in advance for bonding the substrate and the metal circuit layer is formed. An electronic component package having:
おいて、あらかじめ半導体チップ等の電子部品を収容す
る所要の大きさの窓明け加工した基材と、該基材の下方
に位置するあらかじめ所要の部位にソルダーレジスト層
を被着した金属回路層と、該基材と該金属回路層を接着
するためのあらかじめ半導体チップ等の電子部品を収容
する所要の大きさの窓明け加工した接着性を有する絶縁
層を張り合わせて形成した凹形状を有する電子部品用パ
ッケージ。4. A package for an electronic component according to claim 1, wherein a base material having a window of a required size for accommodating an electronic component such as a semiconductor chip is formed in advance, and a base material located below the base material is provided in advance. And a metal circuit layer having a solder resist layer adhered to a portion thereof, and an adhesive having a predetermined size for opening an electronic component such as a semiconductor chip for bonding the substrate and the metal circuit layer. Electronic component package having a concave shape formed by laminating insulating layers having the same.
おいて、あらかじめ半導体チップ等の電子部品を収容す
る所要の大きさの窓明け加工した基材と、該基材の下方
に金属回路層を被着した接着性を有する絶縁層を張り合
わせて形成した凹形状を有する電子部品用パッケージ。5. A package for an electronic component according to claim 1, wherein a base material having a predetermined size for receiving an electronic component such as a semiconductor chip and having a window formed therein in advance is provided, and a metal circuit layer is provided below the base material. An electronic component package having a concave shape formed by laminating an adhered insulating layer having adhesion.
パッケージにおいて、接続端子として半田ボールを用い
た電子部品用パッケージ。6. The electronic component package according to claim 1, wherein solder balls are used as connection terminals.
パッケージにおいて、凹形状内に収容した電子部品の直
上に他の電子部品を搭載した電子部品用パッケージ。7. The electronic component package according to claim 1, wherein another electronic component is mounted immediately above the electronic component housed in the concave shape.
パッケージの製造方法。8. A method for manufacturing an electronic component package according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000145720A JP2001291800A (en) | 2000-04-10 | 2000-04-10 | Package for electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000145720A JP2001291800A (en) | 2000-04-10 | 2000-04-10 | Package for electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001291800A true JP2001291800A (en) | 2001-10-19 |
Family
ID=18652184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000145720A Pending JP2001291800A (en) | 2000-04-10 | 2000-04-10 | Package for electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001291800A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007027155A (en) * | 2005-07-12 | 2007-02-01 | Nichicon Corp | Solder supply method to minute soldering land |
| JP2010521818A (en) * | 2007-03-12 | 2010-06-24 | マイクロン テクノロジー， インク． | Semiconductor device packaging apparatus, packaged semiconductor component, manufacturing method of semiconductor device packaging apparatus, and manufacturing method of semiconductor component |
| CN107872925A (en) * | 2016-09-27 | 2018-04-03 | 奥特斯奥地利科技与系统技术有限公司 | Part is embedded in the core on conductive foil |
-
2000
- 2000-04-10 JP JP2000145720A patent/JP2001291800A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007027155A (en) * | 2005-07-12 | 2007-02-01 | Nichicon Corp | Solder supply method to minute soldering land |
| JP2010521818A (en) * | 2007-03-12 | 2010-06-24 | マイクロン テクノロジー， インク． | Semiconductor device packaging apparatus, packaged semiconductor component, manufacturing method of semiconductor device packaging apparatus, and manufacturing method of semiconductor component |
| CN107872925A (en) * | 2016-09-27 | 2018-04-03 | 奥特斯奥地利科技与系统技术有限公司 | Part is embedded in the core on conductive foil |
| US10743422B2 (en) | 2016-09-27 | 2020-08-11 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Embedding a component in a core on conductive foil |
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