JPS6350862B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing electronic circuit boards, such as chip carrier boards for ICs and LSIs, and circuit boards for watches, using printed circuit boards.

Conventional configurations and their problems Generally, in double-sided or multilayer printed circuit boards,
So-called through holes are formed on both sides of the substrate, and connection conductors are provided in a direction perpendicular to the surface of the substrate. However, in chip carrier boards for ICs and LSIs, circuit boards for watches, etc. that use printed circuit boards, conductors are formed on the sides of the board for purposes such as connection, contact, and soldering.
Among these, a conventional example will be explained with reference to FIGS. 1 to 4, taking a chip carrier board as an example.

FIG. 1 is a top view of a conventional example after completion, FIG. 2 is a sectional view, FIG. 3 is a sectional view after an IC chip is mounted, and FIG. 4 is a sectional view of each process.

First, the structure of the chip carrier board and the method of incorporating IC and LSI chips into the board will be explained with reference to FIGS. 1 to 3. For a chip carrier board consisting of an insulating substrate 1, a die pad 2, a wire bonding pad 3, a conductor wiring 4, a side conductor 5, a side groove 6, and an external electrode 7 as shown in FIGS. 1 and 2, FIG. As shown, an IC chip 8 is die-bonded to a die pad 2, wire-bonded using a bonding wire 9, and sealed using a resin 10 and a frame 11. The external electrode 7 and the side conductor 5 are parts that will be soldered later when connecting to the motherboard.

Next, a method of manufacturing the above conventional chip carrier substrate will be explained with reference to FIG. 4.

First, as shown in FIG.
A through hole 13 is formed in the substrate 2 formed thereon by drilling or the like. Next, as shown in FIG. 4c, an electroless copper plating film 14 and an electrolytic copper plating film 15 are formed on the inner wall of the through hole 13 and the conductor foil 12. At this time, the conductor foil 12 on both sides
are electrically connected by plating films 14 and 15 formed on the inner wall of the through hole 13. Usually, the thickness of the electroless copper plating film 14 is about 0.25 to 1 μm, and the thickness of the electrolytic copper plating film 15 is about 10 to 25 μm. Next, as shown in FIG. 4d, conductor foil 1
2. Electroless copper plating film 14, electrolytic copper plating film 15
The unnecessary parts of the die pad 2, wire bonding pad 3, conductor wiring 4,
External electrodes 7 are formed. Next, as shown in FIG. 4e, an unnecessary portion is cut off approximately at the center of the through hole 13 to obtain a chip carrier substrate. The side groove 6 is a portion where about half of the through hole 13 remains. FIG. 4d shows a sectional view taken along line A-A' in FIG. The unnecessary parts are removed in the process shown in Figure 4 e.
A method of punching out a press using a mold, or
This is done by cutting with a die sig saw or the like.

The disadvantages of the conventional example are as follows.

(1) If unnecessary parts are separated by punching with a press using a mold, a 10 to 25 μm thick and flexible electrolytic copper plating film 15 is already formed on the inner wall of the through hole at the time of punching. is formed, so if shear force during pressing is applied to the electrolytic copper plating film 15 on the inner wall of the through hole, the electrolytic copper plating film 15 may peel off or the adhesion strength of the electrolytic copper plating film on the inner wall of the through hole may decrease. There is. The smaller the through-hole pitch and through-hole diameter, the greater the rate of peeling, which is very disadvantageous for high density, poor yield, and reduced reliability.

(2) Another method for cutting off unnecessary parts is to use a dicing saw or the like, but since it is not possible to cut all four sides of the chip carrier board at once, productivity is low and costs are high. Also, in this case, the electrolytic copper plating film 15 has already been applied to the inner wall of the through hole.
is formed, the electrolytic copper plating film 15 on the inner wall of the through-hole may be peeled off, although the extent is smaller than in the pressing method. Further, in this method, burrs are generated in the electrolytic copper plating film. Since these burrs break easily, they fall onto the board and cause short circuits, resulting in poor quality and low reliability.

(3) If the diameter of the through-hole is made smaller in order to achieve higher density, the circulation of the plating liquid into the through-hole during non-resolved copper plating becomes very poor, and the plating coverage becomes poor. The thickness of the copper plating in the holes is thin and uneven, making the side conductors of the chip carrier board very unreliable.

OBJECTS OF THE INVENTION The present invention eliminates the drawbacks of the above-mentioned conventional examples, and aims to obtain a highly reliable electronic circuit board such as a chip carrier board without peeling off the electrolytic copper plating film on the inner wall of the through hole. It is something to do.

Structure of the Invention In order to achieve the above object, the present invention is a method in which after drilling a through hole, electroless copper plating is performed on the inner wall of the through hole, unnecessary parts are punched out using a press, and then electrolytic copper plating is performed. be.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 5 and 6. This embodiment is a chip carrier board intended for mounting IC, LSI chips, etc.
i is a sectional view for each step, and FIG. 6 is a top view for each step. Further, FIG. 5b and FIG. 6a, FIG. 5d and FIG. 6b, and FIG. 5g and FIG. 6c correspond, respectively.

First, as shown in Figure 5a, glass epoxy,
Conductor foils 32 made of copper or the like are fixed to both sides of an insulating substrate 21 made of polyamide or the like. Insulating substrate 21
The thickness is usually about 0.2 to 1.6 μm. Further, the thickness of the conductor foil 32 is approximately 9 to 35 μm.

Next, as shown in FIGS. 5B and 6A, a through hole 33 is formed in a portion that will later become the side surface of the chip carrier substrate by drilling, laser processing, punching, or the like. The diameter of the through hole 33 is
Although it is selected depending on the pitch of the external electrodes of the chip carrier substrate, it is usually about 0.2 to 1.0 mmφ. The number of through holes 33 to be formed depends on the IC to be mounted,
Determined by the number of pins on the LSI chip. The pitch of the through holes 33 is approximately 0.3 to 2.54 mm, and is determined based on the number of pins and chip size of the IC or LSI chip, the external dimensions of the chip carrier board, etc.

Next, as shown in FIG. 5c, an electroless copper plating film 34 is formed on the inner wall of the through hole 33 and the conductive foil 32. At this time, the conductor foils 32 on both sides are electrically connected via the electroless copper plating film. Electroless copper plating is generally done by the method used for manufacturing through-hole boards, and the thickness is usually 0.25 to 1μ.
That's about it.

Next, as shown in FIGS. 5 d and 6 b, the through hole 33 is punched out using a press at approximately the center thereof, and unnecessary parts are cut off. At this time, a part of the through hole 33 becomes the groove 26 on the side surface of the chip carrier board. Also, as shown in Figure 6b,
The chip carrier substrate 41 is connected to the insulating substrate 21 on the outer periphery by the support portion 40, and a plurality of chip carrier substrates 41 are formed on one insulating substrate 21. Support part 40
After the chip carrier board is completed, or the IC,
Disconnect after mounting the LSI chip. Since the chip carrier substrate 41 is usually very small, about 5 to 20 mm square, by connecting a plurality of them to the insulating substrate 21 using the support portion 40, handling becomes easier and productivity is improved. Electroless copper plating film is 0.25~1μ
Because it is extremely thin and extremely brittle, even if shearing force is applied to the plating film on the inner wall of the through hole during punching using a press, the electroless copper plating film on the inner wall of the through hole may peel off. There isn't.

Next, as shown in FIG. 5e, an electrolytic copper plating film 35 is formed on the side grooves 26 and the electroless copper plating film 34. The thickness of the electrolytic copper plating film 35 is approximately 10 to 25 μm. At this time, the through hole 33 has already been
Since the groove 26 on the side is continuous with the large hole 36, the circulation of the plating liquid to the groove 26 on the side is very good, and even if the through hole diameter is small, there are no pinholes and the thickness is uniform. It is possible to form a highly reliable electrolytic copper plating film.

Next, as shown in FIG. 5f, a plating resist film 37 is formed by photo-etching on the portion to be removed later, and using the plating resist film 37 as a mask, an etching resist film 38 is formed. As the etching resist film 38, a solder plating film or the like is used. Thereafter, as shown in FIG. 5g and FIG. 6c, after removing the plating resist 37, using the etching resist film 38 as a mask, unnecessary parts are removed by etching, and the die pad 22, wire bonding pad 23, and conductor wiring are removed. 24, external electrode 27,
A conductor layer 25 of side grooves is formed. Etching is
This is done using a solution such as ammonium persulfate. In this embodiment, a method is described in which a plating film such as solder is used as the etching resist film 38, but Drac film, liquid resist, etc. may also be used. However, in this case, it is necessary to fill the side grooves 26 and the large holes 36 formed by cutting off unnecessary parts with resin or the like to protect the conductor portions of the side grooves during etching.

Next, after removing the etching resist film 38 as shown in FIG.
form 9. Au plating is performed by electrolytic plating, and its thickness is approximately 0.1 to 1.5 μm. In addition, when normally performing Au plating, 1 to 4μ Ni plating is applied to the base.

An Au plating film may be used as the etching resist film when unnecessary parts are removed by etching.In that case, the etching resist film does not need to be removed, and the etching resist film is as shown in Figure 5i. This becomes an Au plating film 39.

Effects of the Invention The present invention has the following effects because unnecessary parts are separated after electroless copper plating.

(1) Even when punched with a press, the electroless copper plating film inside the through hole is extremely thin (0.25 to 1μ) and brittle, so even if shear force is applied during punching, the electroless copper plating inside the through hole will The copper plating film does not peel off, and an extremely reliable electronic circuit board such as a chip carrier board can be obtained.

(2) For the reason shown above, even if the through-hole pitch is very small, such as 0.4 mm, 0.51 mm, or 0.635 mm, it can be easily separated, resulting in a high-density electronic circuit board such as a chip carrier board. be able to.

(3) As the cutting method is performed by pressing using a mold, productivity is extremely high and costs are low.

(4) When performing electrolytic copper plating, the through-hole area is already in the groove state and is connected to the large hole formed by cutting off the unnecessary part, so it is difficult to plate the side groove. Even if the diameter of the through-hole is made small in order to achieve good circumference and high density, the electrolytic copper plating film in the side groove has no pinholes and has a uniform thickness, making it possible to obtain a highly reliable conductor in the side groove. Can be done.

[Brief explanation of drawings]

Figure 1 is a top view after completing a conventional chip carrier board, Figure 2 is a sectional view taken along line A-A' in Figure 1, Figure 3 is a sectional view after an IC chip is mounted on the chip carrier board, and Figure 4 a. - e are cross-sectional views of each step in a conventional manufacturing method, FIGS. It is a top view according to process in . 21...Insulating substrate, 22...Die pad, 23
... wire bonding pad, 24 ... conductor wiring, 25 ... conductor in side groove, 26 ... side groove,
27...External electrode, 32...Conductor foil, 33...Through hole, 34...Electroless copper plating film, 35...
... Electrolytic copper plating film, 36 ... Large hole, 37 ... Plating resist film, 38 ... Etching resist film,
39... Au plating, 40... Support part, 41...
Chip carrier board.

Claims (1)

[Claims] 1. After forming a through hole in an insulating substrate having conductive foil on one or both sides, electroless plating is performed on the conductive foil including the inner wall of the through hole, and then cutting off unnecessary parts leaving a part of the through hole. , comprising a part of the inner wall of the through hole, electroplating is performed on the conductor foil, and a conductor wiring is formed using the conductor foil and the plating film of the part of the inner wall of the through hole. Method of manufacturing circuit boards.