JP3383597B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3383597B2 JP3383597B2 JP31126098A JP31126098A JP3383597B2 JP 3383597 B2 JP3383597 B2 JP 3383597B2 JP 31126098 A JP31126098 A JP 31126098A JP 31126098 A JP31126098 A JP 31126098A JP 3383597 B2 JP3383597 B2 JP 3383597B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor element
- semiconductor
- outer lead
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子の機能
面に回路基板が貼着され、半導体素子のアウターリード
パッドと回路基板の回路パターンが電気導体により接続
された半導体装置の製造方法に係わり、特に、アウター
リードパッドがファインピッチで列設されたチップスケ
ールサイズの半導体パッケージの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a circuit board is attached to a functional surface of a semiconductor element and an outer lead pad of the semiconductor element and a circuit pattern of the circuit board are connected by an electric conductor. In particular, the present invention relates to a method for manufacturing a chip scale size semiconductor package in which outer lead pads are arranged in a fine pitch.
【０００２】[0002]
【従来の技術】近年、半導体パッケージの小型化の要請
に対してアウターリードパッドを半導体素子の中央部に
配置したチップスケールサイズの半導体パッケージ（Ｃ
ＳＰ）が注目されている。2. Description of the Related Art In recent years, in response to a demand for miniaturization of a semiconductor package, a chip scale size semiconductor package (C
SP) is drawing attention.
【０００３】このチップスケールサイズの半導体パッケ
ージは、半導体素子の機能面に、該半導体素子のアウタ
ーリードパッドと対応する位置に窓部を設けた回路基板
を貼着し、この窓部を介して、半導体素子のアウターリ
ードパッドと回路基板のボンディングパッドをボンディ
ングワイヤにより電気接続して構成されている。In this semiconductor package of chip scale size, a circuit board having a window portion at a position corresponding to an outer lead pad of the semiconductor element is attached to a functional surface of the semiconductor element, and the window portion is provided through the window portion. The outer lead pad of the semiconductor element and the bonding pad of the circuit board are electrically connected by a bonding wire.
【０００４】図９は、このようなチップスケールサイズ
の半導体パッケージの一例の断面を模式的に示したもの
である。FIG. 9 schematically shows a cross section of an example of such a chip scale size semiconductor package.
【０００５】この半導体パッケージ１は、中央部にアウ
ターリードパッド２を２列（紙面の上下方向に）に配置
した半導体素子３の上に、テープ状の回路基板４の絶縁
フィルム側を接着剤層５を介して貼着させて構成されて
いる。回路基板４には、ワイヤボンディング用の窓部６
が形成され、その縁部にはアウターリードパッド２に対
応するボンディングパッド７ａが形成され、窓部６から
離れた位置には外部入出力パッド７ｂが形成され、ボン
ディングパッド７ａと外部入出力パッド７ｂは回路パタ
ーン７ｃにより電気的に接続されている。In this semiconductor package 1, a tape-shaped circuit board 4 on an insulating film side is provided with an adhesive layer on a semiconductor element 3 in which outer lead pads 2 are arranged in two rows in the central portion (in the vertical direction of the paper). It is configured to be attached via 5. The circuit board 4 has a window 6 for wire bonding.
Is formed, a bonding pad 7a corresponding to the outer lead pad 2 is formed on the edge thereof, and an external input / output pad 7b is formed at a position away from the window portion 6. The bonding pad 7a and the external input / output pad 7b are formed. Are electrically connected by the circuit pattern 7c.
【０００６】半導体素子３のアウターリードパッド２と
回路基板４のボンディングパッド７ａは、ボンディング
ツールを用いてボンディングワイヤ８により電気的に接
続され、外部入出力パッド７ｂには、半田ボール９がリ
フローされて固定されている。 なお、図示を省略した
が、ボンディング終了後、窓部６上には、例えばシリコ
ーン樹脂のような耐湿性で電気絶縁性の硬化性樹脂がポ
ッティングされて封止される。The outer lead pad 2 of the semiconductor element 3 and the bonding pad 7a of the circuit board 4 are electrically connected by a bonding wire 8 using a bonding tool, and the solder ball 9 is reflowed to the external input / output pad 7b. It is fixed. Although illustration is omitted, after the bonding is completed, a moisture-resistant and electrically insulating curable resin such as silicone resin is potted and sealed on the window portion 6.
【０００７】ところで、ファインピッチのアウターリー
ドパッド２を有する半導体素子では、図１０に示すよう
に、アウターリードパッド２の間隔が例えば１００μｍ
程度と狭くなっている。これに対してアウターリードパ
ッド２の周りには、ワイヤボンディングのために、パッ
ド２を中心として半径０．３ｍｍ程度（３００μｍ程
度）のボンディングツールが干渉しないための動作空間
Ｓ（実際には動作空間に金型の抜きの精度、パターンの
精度、貼着の誤差等を加味した空間）が必要であり、全
てのボンディングパッドについて、動作空間Ｓを設ける
と、結局、幅が０．７ｍｍ（７００μｍ）の連続した窓
部６がパッド２の列に沿って形成されることになる。By the way, in the semiconductor element having the fine pitch outer lead pads 2, as shown in FIG. 10, the outer lead pads 2 are spaced by 100 μm, for example.
It is getting narrower. On the other hand, around the outer lead pad 2, an operation space S (actually, the operation space S) is provided so that a bonding tool having a radius of about 0.3 mm (about 300 μm) centering on the pad 2 does not interfere due to wire bonding. Requires a space for taking into account the precision of die removal, the precision of the pattern, the error of sticking, etc.). If the operation space S is provided for all bonding pads, the width will eventually be 0.7 mm (700 μm). The continuous window portions 6 of 6 are formed along the row of the pads 2.
【０００８】半導体素子３上に素子を横切る形でアウタ
ーリードパッド２が列設されている場合には、窓部６も
それに応じて半導体素子３を横切る形で形成される。ま
た、半導体ウエハに半導体チップがマトリックス状に多
数形成された状態でテープ状の回路基板を、この半導体
ウエハ上のダイシング前の半導体素子３に貼着する場合
には、窓部６の一部のものは殆ど半導体ウエハの最大直
径を横切るような状態に形成されるようになる。When the outer lead pads 2 are arranged in a row across the semiconductor element 3, the window portion 6 is also formed correspondingly across the semiconductor element 3. In addition, when a tape-shaped circuit board having a large number of semiconductor chips formed in a matrix on a semiconductor wafer is attached to the semiconductor element 3 on the semiconductor wafer before dicing, a part of the window 6 is to be attached. Most of the objects are formed so as to cross the maximum diameter of the semiconductor wafer.
【０００９】このように長い連続した窓部６が形成され
ると、回路基板４を半導体ウエハに貼着する際に「寄
り」を発生する原因となり、歩留まりを劣化させるとい
う問題があった。When such a long continuous window portion 6 is formed, there is a problem in that when the circuit board 4 is attached to a semiconductor wafer, a "deviation" occurs and the yield is deteriorated.
【００１０】このような問題を回避するためには、「窓
部」が長くなる場合に、回路基板の適当な位置に窓部を
横切って回路基板４に補強用のブリッジを形成すること
が考えられる。In order to avoid such a problem, it is considered to form a reinforcing bridge on the circuit board 4 across the window portion at an appropriate position on the circuit board when the "window portion" becomes long. To be
【００１１】しかしながら、回路基板の打ち抜きにより
形成されるブリッジでは、打ち抜き誤差とパターンの誤
差を考慮して少なくとも４００μｍ程度の幅のブリッジ
が必要であり、回路基板の歩留まりが低くなるという問
題があった。However, in a bridge formed by punching a circuit board, a bridge having a width of at least about 400 μm is required in consideration of punching error and pattern error, which causes a problem of low yield of the circuit board. .
【００１２】また、半導体ウエハに多数マトリックス状
に形成された半導体素子に直接回路基板テープを貼着
し、この状態でワイヤボンディングを行う方法では、ブ
リッジ幅の分だけ半導体ウエハに使用不能部分が生じる
ため１ウエハあたりのＩＣ取り数が減少するという問題
があった。Further, in a method in which a circuit board tape is directly adhered to semiconductor elements formed in a matrix on a semiconductor wafer and wire bonding is performed in this state, an unusable portion is produced in the semiconductor wafer by the bridge width. Therefore, there is a problem that the number of ICs taken per wafer is reduced.
【００１３】[0013]
【発明が解決しようとする課題】上述したとおり、従来
公知の、半導体素子の機能面に回路基板が貼着され半導
体素子のアウターリードパッドと回路基板の回路パター
ンが、アウターリードパッドの周囲に形成した回路基板
の窓部において電気導体で接続される形式の半導体装置
では、アウターリードパッドの間隔が非常に狭くなって
いる。このため、回路基板のボンディング用の窓部には
ボンディングツールが干渉しない動作空間を必要とし、
連続した窓部がアウターリードパッドの列に沿って形成
されることになる。As described above, a conventionally known circuit board is attached to the functional surface of a semiconductor element, and an outer lead pad of the semiconductor element and a circuit pattern of the circuit board are formed around the outer lead pad. In the semiconductor device of the type in which the electric conductors are connected in the window portion of the circuit board, the outer lead pads are very narrow. Therefore, the bonding window of the circuit board requires an operating space where the bonding tool does not interfere,
A continuous window will be formed along the row of outer lead pads.
【００１４】回路基板に長い連続した窓部が形成される
と、この回路基板を半導体ウエハに貼着する際に「寄
り」を発生する原因となり、歩留まりを劣化させるとい
う問題があった。If a long continuous window portion is formed on the circuit board, it causes a "closer" when the circuit board is attached to the semiconductor wafer, and there is a problem that the yield is deteriorated.
【００１５】この問題を回避するために、窓部を横切っ
て絶縁フィルムによるブリッジを形成することも考えら
れるが、この場合、回路基板全体によるブリッジでは、
打ち抜き誤差と寸法誤差を考慮して少なくとも４００μ
ｍ程度の幅のブリッジが必要であり、回路基板の歩留ま
りが低くなるという問題があった。In order to avoid this problem, it is conceivable to form a bridge made of an insulating film across the window, but in this case, the bridge made of the entire circuit board is
At least 400μ in consideration of punching error and dimensional error
Since a bridge having a width of about m is required, there is a problem that the yield of the circuit board is reduced.
【００１６】また、半導体ウエハに直接回路基板テープ
を貼着しこの状態でワイヤボンディングを行う方法で
は、ブリッジ幅の分だけ半導体ウエハに使用不能部分が
生じるため１ウエハあたりのＩＣ取り数が減少するとい
う問題があった。Further, in the method in which the circuit board tape is directly adhered to the semiconductor wafer and the wire bonding is performed in this state, the semiconductor wafer has an unusable portion by the width of the bridge, so that the number of ICs to be taken per wafer is reduced. There was a problem.
【００１７】本発明は、かかる従来の問題を解決するた
めになされたもので、半導体素子の機能面に回路基板が
貼着され、半導体素子のアウターリードパッドと回路基
板の回路パターンが回路基板に形成した窓部において電
気導体で接続された半導体装置を製造するにあたって、
回路基板を半導体ウエハに貼着する際の「寄り」の発生
を防止するとともに、半導体素子の歩留まりを改善した
半導体装置及びその製造方法を提供することを目的とす
る。The present invention has been made to solve such a conventional problem. A circuit board is attached to a functional surface of a semiconductor element, and an outer lead pad of the semiconductor element and a circuit pattern of the circuit board are formed on the circuit board. In manufacturing a semiconductor device connected by an electric conductor in the formed window,
An object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device, in which a "deviation" when sticking a circuit board to a semiconductor wafer is prevented and a yield of semiconductor elements is improved.
【００１８】[0018]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体素子の機能面に回路基板が貼着され、
前記半導体素子のアウターリードパッドと前記回路基板
の回路パターンが電気導体により接続された半導体装置
の製造方法において、金属箔と絶縁フィルムとを接合さ
せた積層板の前記金属箔にエッチングを施して、貼着す
べき半導体素子のアウターリードパッドと対応する領域
を外して回路パターンを形成するとともに前記アウター
リードパッドと対応する領域に該領域を横切るブリッジ
パターンを形成して回路基板とする工程と、前記回路基
板の貼着すべき半導体素子のアウターリードパッドと対
応する領域の絶縁フィルムを除去して該領域に窓部を形
成する工程と、前記回路基板の絶縁フィルム側を前記半
導体素子に接着する工程と、前記回路基板の回路パター
ンと前記半導体素子のアウターリードパッドを電気導体
により接続する工程とを有することを特徴としている。According to a method of manufacturing a semiconductor device of the present invention, a circuit board is attached to a functional surface of a semiconductor element,
In a method for manufacturing a semiconductor device in which an outer lead pad of the semiconductor element and a circuit pattern of the circuit board are connected by an electric conductor, etching is performed on the metal foil of a laminated plate in which a metal foil and an insulating film are joined, Forming a circuit pattern by removing a region corresponding to the outer lead pad of the semiconductor element to be attached and forming a bridge pattern across the region in a region corresponding to the outer lead pad to form a circuit board; A step of removing an insulating film in a region corresponding to an outer lead pad of a semiconductor element to be attached on a circuit board to form a window portion in the region; and a step of adhering the insulating film side of the circuit board to the semiconductor element And a process for connecting the circuit pattern of the circuit board and the outer lead pad of the semiconductor element with an electric conductor. It is characterized by having and.
【００１９】半導体素子は、半導体ウエハの主面にマト
リックス状に多数形成されたダイシング前の半導体素子
であってもよい。The semiconductor element may be a semiconductor element before dicing, which is formed in a matrix on the main surface of the semiconductor wafer.
【００２０】さらに、ブリッジパターンは、半導体ウエ
ハにおけるダイシングラインに形成されることが望まし
い。この場合、ブリッジパターンはダイシングの際に除
去される。なお、ブリッジパターンがメッキ用引出し線
を兼ねていることがより望ましい。Further, it is desirable that the bridge pattern is formed on the dicing line on the semiconductor wafer. In this case, the bridge pattern is removed during dicing. It is more desirable that the bridge pattern also serves as the lead wire for plating.
【００２１】また、回路基板のボンディングパッドは、
回路基板の窓部に沿って形成される。 本発明の半導体
パッケージに用いられるテープ状の絶縁基板としては、
ポリイミドフィルムその他のイミド系フィルム、ポリエ
ステルフィルム等が例示されるが、電気絶縁特性、耐熱
性、機械的特性に優れていることからポリイミド系フィ
ルムが適している。The bonding pads on the circuit board are
It is formed along the window of the circuit board. The tape-shaped insulating substrate used for the semiconductor package of the present invention includes:
Examples of the polyimide film include other imide-based films, polyester films, and the like. The polyimide-based film is suitable because it has excellent electrical insulation properties, heat resistance, and mechanical properties.
【００２２】なお、ブリッジパターンの幅は０．３ｍｍ
未満であることが望ましい。The width of the bridge pattern is 0.3 mm.
It is desirable to be less than.
【００２３】[0023]
【発明の実施の形態】以下、本発明の実施態様を、図１
乃至図８を参照しながら説明する。なお、これらの図に
おいて図９及び図１０と共通する部分には同一の符号を
付す。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIG.
It will be described with reference to FIGS. In these figures, the same parts as those in FIGS. 9 and 10 are designated by the same reference numerals.
【００２４】［実施例１］図１は、本発明の第１の実施
例を説明するための図である。[Embodiment 1] FIG. 1 is a view for explaining a first embodiment of the present invention.
【００２５】この実施例のテープ状回路基板４は、ポリ
イミドからなる絶縁フィルムと銅箔を接着させた積層板
をフォトリソグラフィの技法によりパターニングして得
られたものである。回路基板４における半導体素子１の
アウターリードパッド２と対応する領域には、ワイヤボ
ンディング用の矩形の窓部６が形成されており、この窓
部６を横切って銅箔のエッチングにより形成された幅
０．０４ｍｍ程度のブリッジパターン１０が形成されて
いる。なお、図示は省略したが、ボンディグパッド７
ａ、外部入出力パッド７ｂ及び回路パターン７ｃ上には
電解メッキによるＡｕ／Ｎｉメッキ層が形成されてい
る。The tape-shaped circuit board 4 of this embodiment is obtained by patterning a laminated plate to which an insulating film made of polyimide and a copper foil are adhered by a photolithography technique. A rectangular window portion 6 for wire bonding is formed in a region of the circuit board 4 corresponding to the outer lead pad 2 of the semiconductor element 1, and a width formed by etching a copper foil across the window portion 6. A bridge pattern 10 of about 0.04 mm is formed. Although not shown, the bonding pad 7
On the a, the external input / output pad 7b and the circuit pattern 7c, an Au / Ni plating layer is formed by electrolytic plating.
【００２６】また、窓部６は、銅箔のエッチング及びＡ
ｕ／Ｎｉメッキの後、貼着すべき半導体素子のアウター
リードパッド２に対応する領域をレーザービームで除去
して形成されたものである。Further, the window 6 is formed by etching the copper foil and
After u / Ni plating, the region corresponding to the outer lead pad 2 of the semiconductor element to be attached is removed by a laser beam.
【００２７】回路基板４はテープ状をなしており、通常
は、図２に示すごとく、個々の半導体チップに対応する
単位区画１１（点線で囲まれた部分）を、幅方向に数個
（同図では３個の例を示している。）並列して長手方向
に繰り返し多数連続させて形成するとともに、貼着すべ
き半導体チップのアウターリードパッドの位置に形成し
た窓部６を各区画１１の境界部で横切って銅箔からなる
ブリッジパターン１０を設けて構成されている。The circuit board 4 is in the form of a tape, and normally, as shown in FIG. 2, several unit sections 11 (portions surrounded by dotted lines) corresponding to individual semiconductor chips are arranged in the width direction (the same). In the drawing, three examples are shown.) A plurality of windows are formed in parallel in the longitudinal direction so that a large number of them are continuously formed, and the window portion 6 formed at the position of the outer lead pad of the semiconductor chip to be attached is provided in each section 11. A bridge pattern 10 made of copper foil is provided across the boundary portion.
【００２８】回路基板４の窓部６を横切るブリッジパタ
ーン１０は、一方の側に沿わせて形成したメッキ用引出
し母線１２を介して互いに電気的に連結されており、Ａ
ｕ／Ｎｉ電解メッキの際に、このブリッジパターン１０
を介してボンディグパッド７ａ、外部入出力パッド７ｂ
及び回路パターン７ｃ等のメッキ対象領域に給電され
る。なお、この回路基板（テープ）４ａの両側に自動給
送のためのスプロケット１３が形成されている。The bridge patterns 10 that cross the window portion 6 of the circuit board 4 are electrically connected to each other via a plating drawing busbar 12 formed along one side.
When u / Ni electroplating, this bridge pattern 10
Bonding pad 7a, external input / output pad 7b
Also, power is supplied to the area to be plated such as the circuit pattern 7c. Incidentally, sprockets 13 for automatic feeding are formed on both sides of the circuit board (tape) 4a.
【００２９】この実施例のテープ状回路基板４ａには、
接着剤を介して、半導体チップ１がブリッジパターン１
２と点線で囲まれた領域内に位置するように貼着され
る。In the tape-shaped circuit board 4a of this embodiment,
The semiconductor chip 1 has a bridge pattern 1 via an adhesive.
It is affixed so that it may be located in the area surrounded by 2 and the dotted line.
【００３０】そして回路基板４ａに形成した窓部６に露
出する半導体チップのアウターリードパッド２と、回路
基板４のボンディングパッド７ａがボンディングワイヤ
（図示せず）により電気的に接続され、外部入出力端子
７ｂには半田ボール９が搭載されリフローにより固定さ
れる。また、ワイヤボンディングの済んだ半導体チップ
１のアウターリードパッド部には硬化性樹脂によるポッ
ティングが施される。、 しかる後、回路基板４は各区
画１１の境界部で切断分離され、このときブリッジパタ
ーン１０も同時に除去されて半導体パッケージが完成す
る。The outer lead pad 2 of the semiconductor chip exposed in the window 6 formed on the circuit board 4a and the bonding pad 7a of the circuit board 4 are electrically connected by a bonding wire (not shown), and external input / output is performed. Solder balls 9 are mounted on the terminals 7b and fixed by reflow. Further, potting with a curable resin is applied to the outer lead pad portion of the semiconductor chip 1 after wire bonding. After that, the circuit board 4 is cut and separated at the boundary of each section 11, and at this time, the bridge pattern 10 is also removed at the same time to complete the semiconductor package.
【００３１】なお、ブリッジパターン１０は、半導体チ
ップの境界間に形成するだけでは足りないようであれ
ば、ボンディングツールの干渉を受けるアウターリード
パッド領域内に形成してもよい。半導体素子のアウター
リードパッド領域内に形成されたブリッジパターンは、
ワイヤボンディング時にボンディングツールにより切断
される。この場合、切断をブリッジパターンの所定の箇
所で行わせるため、切断箇所に切り込み（ノッチ）を設
けておくことが望ましい。Note that the bridge pattern 10 may be formed in the outer lead pad region which is subject to the interference of the bonding tool if it is not enough to form it between the boundaries of the semiconductor chips. The bridge pattern formed in the outer lead pad area of the semiconductor element is
It is cut by a bonding tool during wire bonding. In this case, it is desirable to provide a cut (notch) at the cut position in order to cut at a predetermined position of the bridge pattern.
【００３２】［実施例２］図３は、回路基板４に形成し
たリード６を半導体素子３のアウターリードパッド２上
に圧着させるタイプの半導体パッケージに本発明を適用
した一実施例の製造過程における断面を模式的に示した
ものである。[Embodiment 2] FIG. 3 shows a manufacturing process of an embodiment in which the present invention is applied to a semiconductor package of a type in which leads 6 formed on a circuit board 4 are pressure-bonded onto outer lead pads 2 of a semiconductor element 3. 3 is a schematic view of a cross section.
【００３３】この実施例は、中央部にアウターリードパ
ッド２を２列に配置した半導体素子３の上に、テープ状
の回路基板４の銅箔４ａ側をエラストマー層１４を介し
て貼着し、ブリッジパターン１０を残したまま回路基板
４に形成したリード７ｄを、ボンディングツールを用い
て半導体素子３のアウターリードパッド２上に圧着させ
て電気的に接続したものである。In this embodiment, the copper foil 4a side of the tape-shaped circuit board 4 is attached via the elastomer layer 14 onto the semiconductor element 3 in which the outer lead pads 2 are arranged in two rows in the central portion, The leads 7d formed on the circuit board 4 while leaving the bridge pattern 10 left are electrically connected to the outer lead pads 2 of the semiconductor element 3 by pressure bonding using a bonding tool.
【００３４】この後、図示はしないが、ブリッジパター
ン１０が切断され、リード７ｄの接続部上に、例えばシ
リコーン樹脂のような耐湿性で電気絶縁性の硬化性樹脂
をポッティングしてリード７ｄの部分を封止し、外部入
出力パッド上に半田ボールがリフローにより搭載されて
半導体パッケージとされる。Thereafter, although not shown, the bridge pattern 10 is cut, and a moisture-resistant and electrically insulating curable resin such as a silicone resin is potted on the connecting portion of the lead 7d to form a portion of the lead 7d. And the solder balls are mounted on the external input / output pads by reflow to form a semiconductor package.
【００３５】この半導体パッケージ１は、例えば、図４
及び図５に示す工程により製造される。This semiconductor package 1 is, for example, as shown in FIG.
And the process shown in FIG.
【００３６】図４は、この半導体パッケージに用いる回
路基板４のリード部分の製造工程を示している。FIG. 4 shows the manufacturing process of the lead portion of the circuit board 4 used in this semiconductor package.
【００３７】まず、銅箔４ａとポリイミドのような絶縁
フィルム４ｂが、接着剤を介して接着される（図４
ａ）。銅箔４ａ上にはフォトレジストが塗布され、回路
パターンやリードなどの金メッキの必要な部分を抜いた
マスク、又は金メッキの不要な部分を抜いたマスクを用
いて露光現像が行われてレジストパターン１５が形成さ
れる（図４ｂ）。電解メッキにより銅箔の露出した部分
のみにＡｕ／Ｎｉメッキ層１６が形成される（図４
ｃ）。次に、レジストパターン１５が除去され、絶縁フ
ィルム４ｂに外部出力パッド（ボール搭載パッド）を形
成するための穴１７とボンディング用の窓６がレーザビ
ームの照射により形成される（図４ｄ）。穴１７には導
電性のペースト１８が充填されて外部入出力端子７ｂが
形成され（図４ｅ）、レジストパターンを形成して銅箔
不要部を除去して導体パターン、ブリッジパターン（図
示せず）を形成するとともに窓部６に露出しているＡｕ
／Ｎｉメッキ層１６の施された銅箔４ｂが除去されてＡ
ｕ／Ｎｉメッキ層１６によるリード部１９が形成される
（図４ｆ）。First, the copper foil 4a and the insulating film 4b such as polyimide are adhered via an adhesive (FIG. 4).
a). A photoresist is applied on the copper foil 4a, and exposure and development are performed using a mask from which a portion such as a circuit pattern or lead that requires gold plating is removed, or a mask from which an unnecessary portion of gold plating is removed. Are formed (Fig. 4b). The Au / Ni plating layer 16 is formed only on the exposed portion of the copper foil by electrolytic plating (see FIG. 4).
c). Next, the resist pattern 15 is removed, and holes 17 for forming external output pads (ball mounting pads) and windows 6 for bonding are formed in the insulating film 4b by laser beam irradiation (FIG. 4d). The holes 17 are filled with a conductive paste 18 to form the external input / output terminals 7b (FIG. 4e), a resist pattern is formed to remove unnecessary portions of the copper foil, and a conductor pattern and a bridge pattern (not shown). Au that is exposed to the window 6 while forming the
/ Ni plating layer 16 applied copper foil 4b is removed
The lead portion 19 is formed by the u / Ni plated layer 16 (FIG. 4f).
【００３８】以上の各工程を経ることにより回路基板４
が完成する。Through the above steps, the circuit board 4
Is completed.
【００３９】図５は、このようにして得られた回路基板
４を用いてた半導体パッケージを製造する工程を示した
ものである。FIG. 5 shows steps of manufacturing a semiconductor package using the circuit board 4 thus obtained.
【００４０】回路基板４のＡｕ／Ｎｉメッキ層１６側に
は、ボンディングのためのリード部１９を残してスクリ
ーン印刷によりエラストマー層２０が形成され（図５
ａ）、このエラストマー層２０を介して半導体素子３が
回路基板４の対応する位置に接着される（図５ｂ）。そ
して、ボンディングツール２１によりリード部１６の先
端部が切り離されつつ、その先端部が半導体素子３の対
応するアウターリードパッドに接続される（図５ｃ）。
また、外部入出力端子７ｂには半田ボール９が搭載さ
れ、リフローによりバンプが形成され（同）、ボンディ
ングパッド部には硬化性樹脂がポッティングされて（図
示せず）、半導体パッケージが完成する。An elastomer layer 20 is formed on the Au / Ni plating layer 16 side of the circuit board 4 by screen printing, leaving a lead portion 19 for bonding (FIG. 5).
a), the semiconductor element 3 is adhered to the corresponding position of the circuit board 4 through the elastomer layer 20 (FIG. 5b). Then, the tip portion of the lead portion 16 is separated by the bonding tool 21, and the tip portion is connected to the corresponding outer lead pad of the semiconductor element 3 (FIG. 5c).
Further, the solder balls 9 are mounted on the external input / output terminals 7b, bumps are formed by reflow (the same), and a curable resin is potted on the bonding pad portion (not shown) to complete the semiconductor package.
【００４１】この実施例におけるブリッジパターン１０
は、ワイヤボンデング時にボンディングツールにより切
断されるか、又は半導体素子３に対応する寸法線に沿っ
て回路基板４を切断する際に同時に切断される。Bridge pattern 10 in this embodiment
Are cut by a bonding tool at the time of wire bonding or at the same time when the circuit board 4 is cut along a dimension line corresponding to the semiconductor element 3.
【００４２】［実施例３］図６は、マトリックス状に複
数形成されたウエハ２２半導体形成面に貼着して用いら
れるテープ状回路基板４を概略的に示したもので、図７
及び図８は図６の円で囲まれた部分Ａの異なる態様を示
したものである。[Embodiment 3] FIG. 6 schematically shows a tape-shaped circuit board 4 to be used by adhering it to a semiconductor formation surface of a wafer 22 formed in a matrix.
8 and 9 show different aspects of the circled portion A of FIG.
【００４３】図７、図８において、半導体チップの各単
位におけるボンディングパッドに対応する領域Ｂは連続
した穴部とされており、この穴部Ｂを横切って、ブリッ
ジパターン１０が形成されている。図において７ａはア
ウターリードパッド、Ｃは半導体素子搭載領域である。
この実施例では、半導体素子の搭載、ワイヤボンディン
グ、ポッティング等は、ウエハの状態で行われ、最終的
に点線に沿ってダイシングされ、Ｄの部分が半導体パッ
ケージの１単位となる。In FIGS. 7 and 8, the region B corresponding to the bonding pad in each unit of the semiconductor chip is a continuous hole, and the bridge pattern 10 is formed across the hole B. In the figure, 7a is an outer lead pad, and C is a semiconductor element mounting region.
In this embodiment, mounting of semiconductor elements, wire bonding, potting, etc. are performed in a wafer state and finally diced along the dotted line, and the portion D becomes one unit of the semiconductor package.
【００４４】図７の、窓部６のほぼ中央にブリッジパタ
ーン１０が形成された例では、ワイヤボンディングの際
にボンディングツールによりブリッジパターン１０が切
断され、図８のダイシングラインに沿ってブリッジパタ
ーン１０が形成された例では、ダイシングの際に、ブリ
ッジパターン１０も同時に切断除去される。In the example of FIG. 7 in which the bridge pattern 10 is formed substantially in the center of the window portion 6, the bridge pattern 10 is cut by a bonding tool during wire bonding, and the bridge pattern 10 is cut along the dicing line of FIG. In the example in which the bridge pattern 10 is formed, the bridge pattern 10 is cut and removed at the same time during dicing.
【００４５】[0045]
【発明の効果】本発明によれば、半導体素子の機能面に
回路基板が貼着され、前記半導体素子のアウターリード
パッドと前記回路基板の回路パターンが電気導体により
接続された半導体装置を製造するにあたり、回路基板の
ボンディングパッドと対応する領域にブリッジパターン
を形成して窓部の間隔を一定に保持するようにしたの
で、回路基板を半導体ウエハに貼着する際の「寄り」の
発生が防止されて回路基板、半導体素子の歩留まりが改
善される。According to the present invention, a circuit board is attached to the functional surface of a semiconductor element, and an outer lead pad of the semiconductor element and a circuit pattern of the circuit board are connected by an electric conductor to manufacture a semiconductor device. At this time, a bridge pattern is formed in the area corresponding to the bonding pad of the circuit board to keep the window interval constant, so that the "deviation" when sticking the circuit board to the semiconductor wafer is prevented. As a result, the yield of circuit boards and semiconductor devices is improved.
【図１】 本発明の一実施例を説明するための拡大断面
図。FIG. 1 is an enlarged cross-sectional view for explaining an embodiment of the present invention.
【図２】 本発明の他の実施例を説明するためのテープ
状回路基板の平面図。FIG. 2 is a plan view of a tape-shaped circuit board for explaining another embodiment of the present invention.
【図３】 本発明の他の実施例を説明するための拡大断
面図。FIG. 3 is an enlarged sectional view for explaining another embodiment of the present invention.
【図４】 図３に示した実施例の製造過程を示す拡大断
面図。FIG. 4 is an enlarged cross-sectional view showing the manufacturing process of the embodiment shown in FIG.
【図５】 図３に示した実施例の製造過程を示す拡大断
面図。5 is an enlarged cross-sectional view showing a manufacturing process of the embodiment shown in FIG.
【図６】 本発明のさらに他の実施例を概略的に示す平
面図。FIG. 6 is a plan view schematically showing still another embodiment of the present invention.
【図７】 図６に示した実施例の一態様の要部の拡大平
面図。FIG. 7 is an enlarged plan view of a main part of one aspect of the embodiment shown in FIG.
【図８】 図６に示した実施例の他の態様を示す拡大平
面図。8 is an enlarged plan view showing another aspect of the embodiment shown in FIG.
【図９】 半導体パッケージを模式的に示した断面図。FIG. 9 is a sectional view schematically showing a semiconductor package.
【図１０】 ファインピッチのボンディングパッドを有
する半導体素子をワイヤボンディングする際にボンディ
ングツールにより干渉される領域を示した平面図。FIG. 10 is a plan view showing a region interfered by a bonding tool when wire-bonding a semiconductor element having fine-pitch bonding pads.
１……半導体パッケージ、２……アウターリードパッ
ド、３……半導体素子、４……テープ状の回路基板、５
……接着剤層、６……ボンディング用の窓部、７ａ……
ボンディングパッド、７ｂ……外部入出力パッド、７ｃ
……回路パターン、７ｄ……リード、８……ボンディン
グワイヤ、９……半田ボール、１０……ブリッジパター
ン、１２……メッキ用引出し母線、１３……スプロケッ
ト、１４……エラストマー層、１５……レジストパター
ン、１６……Ａｕ／Ｎｉメッキ層、１７……穴、１８…
…外部出力パッド、１９……リード部、２０……エラス
トマー層、２１……ボンディングツール。1 ... semiconductor package, 2 ... outer lead pad, 3 ... semiconductor element, 4 ... tape-shaped circuit board, 5
...... Adhesive layer, 6 ...... Bonding window, 7a ......
Bonding pad, 7b ... External input / output pad, 7c
...... Circuit pattern, 7d ...... Lead, 8 ...... Bonding wire, 9 ...... Solder ball, 10 ...... Bridge pattern, 12 ...... Drawing busbar for plating, 13 ...... Sprocket, 14 ...... Elastomer layer, 15 ...... Resist pattern, 16 ... Au / Ni plating layer, 17 ... Hole, 18 ...
External output pad, 19 lead, 20 elastomer layer, 21 bonding tool.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 23/12 ─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/60 H01L 23/12
Claims (4)
れ、前記半導体素子のアウターリードパッドと前記回路
基板の回路パターンが電気導体により接続された半導体
装置の製造方法において、 金属箔と絶縁フィルムとを接合させた積層板の前記金属
箔にエッチングを施して、貼着すべき半導体素子のアウ
ターリードパッドと対応する領域を外して回路パターン
を形成するとともに前記アウターリードパッドと対応す
る領域に該領域を横切るブリッジパターンを形成して回
路基板とする工程と、 前記回路基板の貼着すべき半導体素子のアウターリード
パッドと対応する領域の絶縁フィルムを除去して該領域
に窓部を形成する工程と、 前記回路基板を前記半導体素子に接着する工程と、 前記回路基板の回路パターンと前記半導体素子のアウタ
ーリードパッドを電気導体により接続する工程とを有す
ることを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device, wherein a circuit board is attached to a functional surface of a semiconductor element, and an outer lead pad of the semiconductor element and a circuit pattern of the circuit board are connected by an electric conductor. Etching the metal foil of the laminated plate bonded to the film, removes the area corresponding to the outer lead pad of the semiconductor element to be adhered to form a circuit pattern and to the area corresponding to the outer lead pad. Forming a bridge pattern across the area to form a circuit board, and removing an insulating film in an area corresponding to the outer lead pad of the semiconductor element to be attached to the circuit board to form a window in the area A step of adhering the circuit board to the semiconductor element, a circuit pattern of the circuit board and an outer layer of the semiconductor element The method of manufacturing a semiconductor device characterized by having a step of connecting the electrical conductors of lead pads.
にマトリックス状に多数形成されたダイシング前の半導
体素子であることを特徴とする請求項１記載の半導体装
置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor element is a semiconductor element before dicing, which is formed in a matrix on the main surface of a semiconductor wafer.
におけるダイシングライン上に形成されていることを特
徴とする請求項２記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 2, wherein the bridge pattern is formed on a dicing line on a semiconductor wafer.
線を兼ねていることを特徴とする請求項１乃至３のいず
れか１項記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the bridge pattern also serves as a lead wire for plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31126098A JP3383597B2 (en) | 1998-10-30 | 1998-10-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31126098A JP3383597B2 (en) | 1998-10-30 | 1998-10-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000138258A JP2000138258A (en) | 2000-05-16 |
| JP3383597B2 true JP3383597B2 (en) | 2003-03-04 |
Family
ID=18015010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31126098A Expired - Fee Related JP3383597B2 (en) | 1998-10-30 | 1998-10-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3383597B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114189995A (en) * | 2021-12-02 | 2022-03-15 | 广州得尔塔影像技术有限公司 | Manufacturing method of circuit board and circuit board |
-
1998
- 1998-10-30 JP JP31126098A patent/JP3383597B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000138258A (en) | 2000-05-16 |
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