JPH0982752A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable multiple pins and improve the mounting efficiency without increasing in size a device. SOLUTION: The semiconductor device comprises a semiconductor chip 1 having salient-poles 4 formed on a plurality of electrode pads 3 arranged on the peripheral edge of a main surface 1a side, and a film board 2 made of an insulating film 4 having slit-like openings 6 perforated corresponding to the electrode forming positions of the chip 1 as a base material and a wiring pattern 7 formed on the surface at the opposite side to the chip abutting surface abutted with the main surface 1a of the chip 1 of both surfaces of the film 4. The salient-poles 4 of the chip 1 are connected to the one end side of the pattern 7 via the opening 6. External connection salient-poles 8 are arranged in a two-dimensional array at the other end of the pattern 7 on the surface at the opposite side to the abutted surface of the board 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a film substrate having an insulating film such as polyimide, epoxy containing glass fiber or polyester as a base material.

[0002]

2. Description of the Related Art Generally, as a semiconductor device using a film substrate, a TCP (Tape Carrier Psckage) using a TAB (Tape Automated Bonding) technique is widely known. FIG. 5 is a plan view showing the structure of a conventional semiconductor device of this type. In the semiconductor device shown in FIG. 5, a tape-shaped film carrier 51 is provided with a sprocket hole 52 for carrying the carrier and a device hole 53 larger than the chip size (punching). In the film carrier 51, a desired lead pattern 54 is formed by adhering (laminating) a metal foil such as copper foil to an insulating film such as polyimide and patterning the metal foil using a photoresist technique or an etching technique. It is a thing. On the other hand, a bump electrode 56 is formed on the electrode pad (not shown) of the semiconductor chip 55, and the bump electrode 56 and the device hole 5 are formed.
The lead portions (inner leads) projecting inside 3 are bonded (inner lead bonding: ILB) by a eutectic alloy method or a thermocompression bonding method.

When the conventional semiconductor device having the above structure is mounted on a printed circuit board, the lead pattern 54 is cut to a desired length, and a forming die is used to perform lead processing. The protruding lead portion (outer lead) is bonded to the land pattern on the printed circuit board (outer lead bonding:
OLB).

[0004]

However, in the above-mentioned conventional semiconductor device, the lead pattern 5 for the OLB is used.
Since 4 is thin and thin, it is very soft, and the leads are deformed even by a light stress, so there is a problem that it is difficult to handle and mount it on a printed circuit board. Also,
Since the lead pattern 54 extends outward from each side of the semiconductor chip 55, if the number of leads increases,
As a result, the size of the device was enlarged, and there was a difficulty in achieving high-density mounting. In particular, recently, in addition to the performance improvement of semiconductor devices and the increase in the number of pins in accordance with the increase in functions, a narrow lead pitch has been remarkably used in order to improve the mounting density. In order to avoid a short circuit, it was not possible to adopt a bonding method by batch solder reflow, which is called surface mounting. Therefore, it is necessary to individually mount using an OLB device equipped with a dedicated bonding tool, which causes a problem that the overall efficiency of the mounting work is reduced.

The present invention has been made in order to solve the above problems, and its main purpose is to provide a semiconductor device capable of increasing the number of pins and improving the mounting efficiency without increasing the device size. Especially.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to achieve the above object, and is a semiconductor chip having protruding electrodes formed on a plurality of electrode pads arranged at the peripheral portion on the main surface side. And an insulating film having a slit-shaped opening corresponding to the electrode forming position of the semiconductor chip as a base material, and on both sides of the insulating film, at least a main surface of the semiconductor chip is abutted with a chip abutting surface. With a film substrate having a wiring pattern formed on the opposite surface, the protruding electrode of the semiconductor chip is connected to one end of the wiring pattern through an opening,
On the surface of the film substrate opposite to the chip abutting surface, the protruding electrodes for external connection are two-dimensionally arranged at the other end of the wiring pattern.

Therefore, according to the semiconductor device of the present invention,
Since the area for arranging the protruding electrodes that will be the external connection terminals is expanded over the entire in-plane area of the film substrate, the number of pins can be increased without increasing the device size. It is possible to arrange the protruding electrodes with a wider terminal pitch. Further, when mounting on a printed circuit board or the like, it is possible to preferably adopt a bonding method by batch reflow heating without causing a short circuit between electrodes.

[0008]

1 is a view for explaining a first embodiment of a semiconductor device according to the present invention, in which (a) is a side sectional view thereof and (b) is a bottom view thereof. The semiconductor device of this embodiment shown in FIG. 1 is mainly composed of a semiconductor chip 1 and a film substrate 2.

Of these, a plurality of electrode pads 3 are arranged at a predetermined pitch on the peripheral portion of the semiconductor chip 1 on the main surface 1a side. On each electrode pad 3, a bump electrode 4 is formed by, for example, gold plating using the existing bump forming technique.

On the other hand, the film substrate 2 is made of a heat-resistant insulating film 5 made of, for example, polyimide as a base material, and has a slit-shaped opening corresponding to the electrode forming position of the semiconductor chip 1 in the central area thereof. The part 6 is perforated.
Further, of both surfaces of the insulating film 5, the surface opposite to the chip abutting surface (the upper surface of the film in the illustrated example) with which the main surface 1a of the semiconductor chip 1 is abutted (the lower surface of the film in the illustrated example) is, for example, copper foil. A wiring pattern 7 is formed by patterning the above by etching. One end side of each wiring pattern 7 is fixed to the insulating film 5 while straddling the slit-shaped opening 6, and the other end side thereof extends in a predetermined direction toward the external connection electrode formation position. I have put it out. In addition, the wiring pattern 7 straddling the opening 6
The exposed surface is subjected to gold plating, and the pattern arrangement pitch at that portion is set to be the same as the arrangement pitch of the protruding electrodes 4 (electrode pads 3) on the semiconductor chip 1.

Incidentally, when manufacturing the above-mentioned film substrate 2, the same material as that of the film carrier for TAB described in the conventional example and the same manufacturing method can be adopted.

Here, the semiconductor chip 1 is butted against the film substrate 2 via its main surface 1a, and in this state, the protruding electrodes 4 on the side of the semiconductor chip 1 pass through the openings 6 of the insulating film 5 to form the wiring pattern 7. It is electrically and mechanically connected to one end side, that is, the pattern exposed surface that straddles the opening 6. Further, the protruding electrode 8 for external connection is formed at the other end position of the wiring pattern 7 extending in the predetermined direction as described above, and the protruding electrode 8 is arranged on the film substrate 2 by drawing the wiring pattern 7. Two-dimensionally arranged on the lower surface, that is, the surface opposite to the chip abutting surface. Further, a heat-resistant solder resist 9 is laminated on the film substrate 4 in such a manner that the formation position of the protruding electrode 8 is opened, and the heat-resistant solder resist 9 causes the wiring pattern 7 to cover the pattern area of the opening 6. Except coated.

The protruding electrode 8 used in this embodiment
Is a so-called “solder ball” in which solder plating is selectively applied to a thickness of about 20 μm by a photomask method, and then the solder is melted by reflow heating and hardened into a spherical shape. The shape may be other than the "solder ball". Further, the array form of the projecting electrodes 8 in the plane of the film substrate 2 may be a grid pattern as shown in FIG. 1B, or a zigzag pattern (not shown), and is not particularly limited. Not something.

In addition to this, the region from the periphery of the semiconductor chip 1 to the abutting portion with the film substrate 2 is made of resin 1.
It is sealed with 0. The resin 10 is injected and cured by potting using, for example, a dispenser, and is used for purposes other than the purpose of protecting the main surface 1a of the semiconductor chip 1 and the connection between the protruding electrode 4 and the wiring pattern 7 from the external environment. It also serves to firmly bond the semiconductor chip 1 and the film substrate 2 to each other to increase the mechanical strength of the entire device.

FIG. 2 is a side sectional view showing a mounted state of the semiconductor device of the first embodiment. In FIG. 2, the projecting electrodes 8 arranged in the in-plane area of the film substrate 2 are bonded to the land pattern 12 of the printed circuit board 11 by reflow heating, whereby the semiconductor device and the printed circuit board 11 are joined.
The electrical connection with is obtained.

In the semiconductor device having the above structure,
The protruding electrode 4 formed on the semiconductor chip 1 is connected to one end side of the wiring pattern 7 through the opening 6 formed in the insulating film 5, and the protruding electrode 8 for external connection is formed into a film by drawing the wiring pattern 7. Since the terminals are arranged two-dimensionally on the substrate 2, the area for arranging the terminals for external connection is greatly expanded, and the terminal pitch for external connection is set wider than in the conventional case even with the same device size. be able to.

Therefore, in the past, a dedicated OLB device had to be used for reasons such as a narrow terminal pitch and easy lead deformation, but in the present embodiment, the mounting efficiency is excellent as described above. Even if the bonding method by batch reflow heating is adopted, a wide terminal pitch is ensured, so that highly reliable and highly accurate bonding can be easily performed without causing a short circuit between electrodes.

Further, since the protruding electrodes 8 for external connection are two-dimensionally arranged in the in-plane area of the film substrate 2, the pattern length can be set shorter than in the conventional case. As a result, it is possible to improve the transmission characteristics when handling high-speed signals and increase the heat dissipation efficiency of the entire device, so that it is possible to mount the semiconductor chip 1 with high power consumption.

Furthermore, since one end side of the wiring pattern 7 is fixed to the insulating film 4 while straddling the opening 6,
Even if some stress is applied during the manufacturing process, the arrangement pitch in the pattern portion can be kept constant. Therefore, the protruding electrode 4 of the semiconductor chip 1 and the film substrate 2
When connecting with the wiring pattern 7 of No. 2, stable ILB can be performed by accurately matching the positions of both.

FIG. 3 is a side sectional view showing a second embodiment of the semiconductor device according to the present invention. The semiconductor device shown in FIG. 3 is different from the first embodiment in that wiring patterns 7a and 7b are formed on both surfaces of the film base material 4, respectively.

In the second embodiment, one of the two-layer wiring patterns 7a, 7b is used as a signal line wiring pattern and the other is used as a ground wiring pattern, so that crosstalk noise It is possible to obtain the effect that the transmission characteristics of the electric signal including the above are improved.

FIG. 4 is a side sectional view showing a third embodiment of the semiconductor device according to the present invention. In the semiconductor device shown in FIG. 4, the difference from the second embodiment is that an insulator 13 made of glass epoxy or the like is adhered onto the film substrate 2 having the two-layer wiring patterns 7a and 7b. The insulator 13 has a frame-shaped structure with an opening larger than the outer diameter of the chip. By setting the thickness dimension of the insulator 13 to be substantially the same as the chip thickness, the upper surface of the insulator 13 and the chip back surface 1b are substantially flat. It is located in one. Furthermore, insulator 1
A heat radiating plate 14 made of a highly heat conductive material such as copper is adhered to the upper surface of the chip 3 and the chip back surface 1b.

In the semiconductor device of the third embodiment, since the heat dissipation plate 14 having high thermal conductivity is directly surface-bonded to the back surface 1b of the semiconductor chip 1, the heat generated in the semiconductor chip 1 is used. Can be efficiently exhausted not only from the main surface 1a side but also from the chip back surface 1b side. This makes it possible to reduce the thermal resistance of the entire semiconductor device, which is particularly suitable for semiconductor devices that generate high heat. Further, since the surface of the heat dissipation plate 14 has a concavo-convex structure, the heat transfer area on the side of the chip back surface 1b can be increased, so that a semiconductor device having a higher heat dissipation effect can be obtained.

[0024]

As described above, according to the semiconductor device of the present invention, the protruding electrode formed on the semiconductor chip is connected to one end side of the wiring pattern through the opening formed in the insulating film, and the film substrate is further connected. By arranging the projecting electrodes for external connection located on the other surface of the wiring pattern at the other end of the wiring pattern two-dimensionally, the projecting electrode arrangement area can be expanded over the entire in-plane area of the film substrate. This allows
The number of pins can be increased without increasing the device size, and the protruding electrodes can be arranged at a wider terminal pitch even with the same device size. Therefore,
When mounting on a printed circuit board or the like, higher density mounting can be realized, and since the bonding method by collective reflow heating can be adopted by increasing the terminal pitch, it is possible to improve the mounting efficiency.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a side sectional view showing a mounted state of the semiconductor device according to the first embodiment.

FIG. 3 is a side sectional view showing a second embodiment of the semiconductor device according to the present invention.

FIG. 4 is a side sectional view showing a third embodiment of the semiconductor device according to the present invention.

FIG. 5 is a plan view showing a configuration of a conventional semiconductor device.

[Explanation of symbols]

 1 Semiconductor Chip 2 Film Substrate 3 Electrode Pad 4 Projection Electrode 5 Insulation Film 6 Opening 7 Wiring Pattern 8 Projective Electrode

Claims (2)

[Claims] 1. A semiconductor chip having projecting electrodes formed on a plurality of electrode pads arranged at a peripheral portion on the main surface side, and a slit-shaped opening corresponding to an electrode forming position of the semiconductor chip. And a film substrate having a wiring pattern formed on a surface opposite to the chip abutting surface on which at least the main surfaces of the semiconductor chips are abutted, on both sides of the insulating film, The protruding electrode of the semiconductor chip is connected to one end of the pattern through the opening, and the surface of the film substrate opposite to the chip abutting surface is located at the other end of the wiring pattern and is externally connected. A semiconductor device in which projecting electrodes for use in a two-dimensional array. 2. The semiconductor device according to claim 1, wherein one end side of the wiring pattern is fixed to the insulating film while straddling the opening.