JP2600898B2 - Thin package device - Google Patents
Thin package deviceInfo
- Publication number
- JP2600898B2 JP2600898B2 JP1099327A JP9932789A JP2600898B2 JP 2600898 B2 JP2600898 B2 JP 2600898B2 JP 1099327 A JP1099327 A JP 1099327A JP 9932789 A JP9932789 A JP 9932789A JP 2600898 B2 JP2600898 B2 JP 2600898B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- substrate
- leads
- package device
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔概 要〕 IC等半導体装置で特に薄型パッケージ装置に関し、 ICとしての特性を損なうことなく小型，薄型化を実現
することを目的とし、 基板表面の中央に形成された凹部に素子が搭載され、
該凹部の周囲の基板上に外部導出用リードが配置され、
該素子と外部導出用リードが接続用リードにより接続さ
れ、該基板表面側の素子，接続用リードおよび外部導出
用リードが樹脂で覆われ且つ該凹部の形成された部分の
基板裏面が樹脂で覆われずに封止されて構成する。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a semiconductor device such as an IC, and particularly to a thin package device, which is formed at the center of the substrate surface with the aim of realizing a small size and a thin shape without deteriorating the characteristics of the IC. The element is mounted in the recess,
An external lead is arranged on the substrate around the concave portion,
The element and the lead for external lead-out are connected by a lead for connection, the element on the front surface side of the substrate, the lead for connection and the lead for lead-out are covered with resin, and the back surface of the substrate where the recess is formed is covered with resin. It is configured without being sealed.
本発明はIC等の薄型パッケージ装置に係り、特に特性
を損なうことなく小型，薄型化を実現して適用分野の拡
大を図った薄型パッケージ装置に関する。The present invention relates to a thin package device such as an IC, and more particularly, to a thin package device which realizes reduction in size and thickness without impairing characteristics and expands application fields.
近年、LSIの高集積化につれて多ピン化，表面実装化
の傾向が益々強まっているが、最近では特に薄型化を図
るためにフラットパッケージICが使用されるようになっ
ている。In recent years, as the integration of LSIs has become higher, the trend toward more pins and surface mounting has been increasing. Recently, however, flat package ICs have come to be used especially for thinning.
第３図は従来のフラットパッケージICの構成を示す断
面図である。FIG. 3 is a sectional view showing the configuration of a conventional flat package IC.
図で、11はICチップ（以下素子とする）,12はリード
フレームの素子搭載用ステージであり、13は上記素子11
上の複数の電極とそれぞれ対応するように該ステージ12
の周囲に放射状に形成されている複数のリードを示し,1
4は上記素子11上の各バンプ電極と該各バンプ電極に対
応する上記リード14の間を接続しているワイヤ,15は該
素子11をステージ12,リード13およびワイヤ14と共に封
入して一体化させているエポキシ樹脂を示している。In the figure, 11 is an IC chip (hereinafter referred to as an element), 12 is a stage for mounting an element of a lead frame, and 13 is the element 11
The stage 12 corresponds to each of the upper electrodes.
Indicates multiple leads radially formed around
Reference numeral 4 denotes a wire connecting between each bump electrode on the element 11 and the lead 14 corresponding to the bump electrode. Reference numeral 15 encloses the element 11 together with the stage 12, the lead 13, and the wire 14 to integrate them. An epoxy resin is shown.
構成の工程を簡単に説明すると、リードフレームの素
子搭載用ステージ12の所定位置に素子11を搭載してダイ
スボンディングによって該素子11をステージ12に固定し
た後、該素子11上の複数の各パンプ電極と該ステージの
周囲に形成されている各対応リード13の間をワイヤボン
ディングマシーンによってワイヤ14で自動的に接続す
る。In brief, the steps of the configuration are as follows. After mounting the element 11 at a predetermined position on the element mounting stage 12 of the lead frame and fixing the element 11 to the stage 12 by die bonding, a plurality of pumps on the element 11 are mounted. The wires and the corresponding leads 13 formed around the stage are automatically connected by wires 14 by a wire bonding machine.
その後、該素子11を含むリード13の所定位置までの領
域を上記ステージごと埋没させるようにエポキシ樹脂で
封入してフラットパッケージICを構成している。Thereafter, an area up to a predetermined position of the lead 13 including the element 11 is sealed with an epoxy resin so as to be buried together with the stage, thereby forming a flat package IC.
かかる構成になるパッケージICでは、 ステージ12の裏面からステージ12の樹脂との接触面を
伝わって水分が素子11に浸入し易いため、ステージ12の
裏面まで耐湿不良が生じない厚さの樹脂で被覆する必要
がある。In the package IC having such a configuration, since moisture easily penetrates into the element 11 from the back surface of the stage 12 through the contact surface with the resin of the stage 12, the back surface of the stage 12 is covered with a resin having a thickness that does not cause poor moisture resistance. There is a need to.
ワイヤボンディングマシーンによる接続の場合にはワ
イヤ14に余長を持たせて接続するため、素子11の表面よ
り更に図示ａ寸法だけパッケージICとしての厚さを厚く
する必要がある。In the case of connection using a wire bonding machine, since the wires 14 are connected with an extra length, it is necessary to further increase the thickness of the package IC by a dimension a shown in the drawing from the surface of the element 11.
等の理由によってパッケージICとしての厚さを薄くする
ことに制約が生じ、最低でも1mm程度になることから特
に薄いICを必要とする分野には適用できない欠点があ
る。For these reasons, there is a restriction in reducing the thickness of the package IC, and since it is at least about 1 mm, there is a drawback that it cannot be applied particularly to a field requiring a thin IC.
従来のフラットパッケージタイプのICではその薄型化
に制約があるため適応分野に制限が生じ、特に薄型を必
要とする高密度実装用プリント板やICカード等には使用
できないと言う問題があった。Conventional flat package type ICs have limitations in their application field due to restrictions on their thickness reduction, and there is a problem that they cannot be used especially for high-density mounting printed boards and IC cards that require a thin type.
上記問題点は、基板表面の中央に形成された凹部に素
子が搭載され、 該凹部の周囲の基板上に外部導出用リードが配置さ
れ、 該素子と外部導出用リードが接続用リードにより接続
され、 該基板表面側の素子，接続用リードおよび外部導出用
リードが樹脂で覆われ且つ該凹部の形成された部分の基
板裏面が樹脂で覆われずに封止されてなる薄型パッケー
ジ装置によって解決される。The above problem is that an element is mounted in a recess formed in the center of the substrate surface, an external lead is arranged on the substrate around the concave, and the element and the external lead are connected by a connection lead. The problem is solved by a thin package device in which the element, the connection lead and the external lead-out on the front surface side of the substrate are covered with a resin, and the back surface of the substrate where the concave portion is formed is sealed without being covered with the resin. You.
従来のフラットパッケージタイプのICに使用されてい
る素子搭載用ステージ裏面側の絶縁樹脂層が除去できれ
ば該樹脂層分の厚さを削減することができる。If the insulating resin layer on the back side of the element mounting stage used in the conventional flat package type IC can be removed, the thickness of the resin layer can be reduced.
また素子のバンプ電極と周囲リード線との接続を従来
のワイヤボンディングのワイヤからテープリードボンデ
ィングによる接続用リード変えると、余長すなわち撓み
が必要なくなって表面側の樹脂の厚さが削減できる。Further, when the connection between the bump electrode of the element and the peripheral lead wire is changed from the conventional wire bonding wire to the connection lead by tape lead bonding, the extra length, that is, the bending is not required, and the thickness of the resin on the surface side can be reduced.
本発明では、素子搭載部分に凹みが形成され，その凹
みの周囲にリードが配置される基板をベースとして使用
することによってステージ裏面側の絶縁樹脂層の除去を
可能とし、更にテープ・オートメイテッド・ボンディン
グ手段等によるリード接続を併用することによってICと
して耐湿特性を良好に薄型化の実現を図っている。According to the present invention, it is possible to remove the insulating resin layer on the back side of the stage by using a substrate having a recess formed in an element mounting portion and a lead disposed around the recess as a base. The use of lead connection by bonding means and the like is also used to achieve a thin IC with good moisture resistance.
従って、特性を落とすことなくICとしての小型，薄型
化を実現することができる。Therefore, the size and thickness of the IC can be reduced without lowering the characteristics.
第１図は本発明になる薄型パッケージ装置の製造方法
を示す工程図であり、第２図は他の実施例を示す図であ
る。FIG. 1 is a process diagram showing a method for manufacturing a thin package device according to the present invention, and FIG. 2 is a diagram showing another embodiment.
以下図に従って説明する。 This will be described below with reference to the drawings.
第１図（Ａ）で、１は鉄（Fe），銅（Cu），アルミニ
ウム（Al）またはこれらの合金等からなる例えば厚さが
100μｍ程度の基板であり、その中央部の少なくとも素
子面積より多少大きいステージ1a部分は板厚とほぼ等し
い段差ｄ（100μｍ）の凹平面に形成されている。なお
素子を搭載しまた外部導出用のリードを配置する基板を
このように金属材料によって形成すれば、薄く且つ高い
強度に形成できると共に素子からの熱の放散もよい。In FIG. 1 (A), 1 is made of iron (Fe), copper (Cu), aluminum (Al) or an alloy thereof, for example, and has a thickness of 1 mm.
The stage 1a, which is a substrate having a size of about 100 μm and at least slightly larger than the element area at the center, is formed on a concave plane having a step d (100 μm) substantially equal to the plate thickness. If the substrate on which the elements are mounted and the leads for external lead-out are formed of such a metal material, the substrate can be formed thin and with high strength, and heat can be radiated from the elements.
そこで該基板１の上記ステージ1aの中央部の搭載素子
とほぼ同じ面積領域に厚さ10μｍ程度の半田や接着剤の
如き接合固定膜1bを被着形成すると共に該領域を除く該
基板１の表裏ほぼ全面に同じ厚さの例えばホーローの如
き絶縁膜1cをコーティング処理して形成した後，上記ス
テージ1aの全周辺に沿う凸面上の該絶縁膜1cの所定幅領
域に厚さ10μｍ程度の例えば鉛ガラスの如き低融点ガラ
スやポリイミドの様な耐熱性樹脂からなる絶縁層接着剤
層1dを上記同様のコーティング処理で被着形成する。Therefore, a bonding and fixing film 1b such as solder or an adhesive having a thickness of about 10 μm is formed on a region of the substrate 1 having substantially the same area as the mounting element at the center of the stage 1a, and the front and back of the substrate 1 excluding the region are removed. After forming an insulating film 1c such as an enamel having the same thickness on almost the entire surface by coating, the lead film having a thickness of about 10 μm is formed on a predetermined width region of the insulating film 1c on a convex surface along the entire periphery of the stage 1a. An insulating adhesive layer 1d made of a low-melting glass such as glass or a heat-resistant resin such as polyimide is applied and formed by the same coating process as described above.
図（Ｂ）はこの状態を示している。 FIG. (B) shows this state.
一方図（Ｃ）の外リード２は、鉄（Fe），銅（Cu），
アルミニウム（Al）またはこれらの合金等からなる厚さ
50μｍの金属板をエッチング等の手段で形成したもの
で、所定の被搭載素子上の複数のバンプ電極に対応して
幅40μｍ程度の複数の外部導出用リード2a,2b,2c,2d…
を周辺連結部（2z）から中心に向かう逆放射の櫛刃状に
なっており、該外リード２の外部導出用リード2a,2b,2
c,2d…の各先端部が上記図（Ｂ）の絶縁層1d上の所定位
置になるように例えばポリイミドのような耐熱性接着材
で接着固定して図（Ｃ）に示すリードベース３を形成し
ている。On the other hand, the outer lead 2 in FIG. (C) is made of iron (Fe), copper (Cu),
Thickness made of aluminum (Al) or their alloys
A metal plate of 50 μm is formed by etching or the like, and a plurality of leads 2a, 2b, 2c, 2d having a width of about 40 μm corresponding to a plurality of bump electrodes on a predetermined mounted element.
Are formed in a comb blade shape of reverse radiation from the peripheral connecting portion (2z) toward the center, and leads 2a, 2b, 2
The lead base 3 shown in FIG. 7C is fixed by bonding with a heat-resistant adhesive such as polyimide so that the respective tips of c, 2d... are located at predetermined positions on the insulating layer 1d in FIG. Has formed.
他方平面図（Ｄ）に示す５は、例えば上記基板１とほ
ぼ同じ大きさの角孔6aを備えたポリイミド等からなる樹
脂フィルム６の片面に、上記角孔6aから該角孔6aの内側
に向かって突出する内側端部E1が所定の素子上の複数の
電極位置に対応しまた該角孔6aの端部E2が図（Ｃ）に示
すリードベース３の各外部導出用リード2a,2b,2c,2d…
の先端部に対応するようにパターニング形成した銅（C
u）またはその合金からなる複数の接続用リード5a,5b,5
c,5d…を持つ回路基板を示したものである。On the other hand, reference numeral 5 shown in a plan view (D) shows one side of a resin film 6 made of polyimide or the like having square holes 6a having substantially the same size as the substrate 1, for example, from the square holes 6a to the inside of the square holes 6a. toward the inner end portion E 1 which projects corresponds to the plurality of electrode locations on a given device and each external lead leads 2a of the lead base 3 end E 2 of the angular hole 6a is shown in Figure (C), 2b, 2c, 2d…
Copper (C) patterned to correspond to the tip of
u) or a plurality of connection leads 5a, 5b, 5 made of an alloy thereof or
This shows a circuit board having c, 5d...
そこで、破線L1で示す所定領域に素子７を載置した上
で該素子７上の各バンプ電極と上記回路基板５の各接続
用リードの内側端部E1を半田付け等の手段でボンディン
グ接続すると図（Ｅ）に示すチップ完成体８を得ること
ができる。Therefore, bonding the inner end E 1 of the connecting lead of each bump electrode and the circuit board 5 on the element 7 in terms of placing the element 7 in a predetermined region indicated by the broken line L 1 by a means such as soldering When connected, a completed chip 8 shown in FIG.
かかる回路基板５を使用したチップ完成体８の場合に
は、テープ状の各接続用リード5a,5b,5c,5d…は平面的
に形成されるためワイヤボンディング手段におけるワイ
ヤのようにボンディング時に余長を持たせる必要がな
く、結果的に薄型化に対して効果的な接続を実現するこ
とができる。In the case of the completed chip 8 using such a circuit board 5, the tape-shaped connection leads 5a, 5b, 5c, 5d... There is no need to provide a length, and as a result, an effective connection can be realized for thinning.
次いで、該チップ完成体８の素子７の裏面側を前記リ
ードベース３の接合固定膜1b面上に載置してダイス付け
を行うと共に、該チップ完成体８の各接続用リード5a,5
b,5c,5d…の図（Ｄ）および図（Ｅ）におけるE2部分を
それぞれ対応する外リード２の各外部導出用リード2a,2
b,2c,2d…の内側端部にボンディング接続すると共に図
（Ｄ）および図（Ｅ）の一点鎖線L2で示す線上で各接続
用リードを切断すると図（Ｆ）に示す如き状態とするこ
とができる。Next, the back surface of the element 7 of the completed chip 8 is placed on the surface of the bonding fixing film 1b of the lead base 3 and diced, and the connection leads 5a and 5 of the completed chip 8 are connected.
b, 5c, 5d ... in FIG. (D) and FIG respective external lead lead 2a of the outer leads 2 corresponding respectively to E 2 moiety in (E), 2
b, 2c, figures (D) and on a line indicated by a chain line L 2 in FIG. (E) when cutting each connecting lead between state as shown in FIG. (F) as well as bonding connection to the inner end of the 2d ... be able to.
ここで、基板１の裏面側を露出させた状態で少なくと
も上記チップ完成体８が埋没するように図の一点鎖線L3
で示す領域を通常の低圧トランスファーモールディング
方法によってエポキシ樹脂等で封入してパッケージ化す
ると共に、図（Ｃ）の二点鎖線L4で示すｃ〜c1線で外リ
ード２の周辺連結部2zを切断除去することによって図
（Ｇ）に示すような所要の薄型パッケージ装置９を構成
することができる。Here, the one-dot chain line L 3 shown in the drawing is such that at least the chip completed body 8 is buried with the back surface side of the substrate 1 exposed.
With packaging and sealed with an epoxy resin or the like by a conventional low-pressure transfer molding method an area indicated by a peripheral connecting portion 2z of the outer leads 2 in C～c 1 line indicated by the two-dot chain line L 4 in FIG. (C) By cutting and removing, a required thin package device 9 as shown in FIG.
なお、従来と同様の素子を使用した場合に、パッケー
ジ装置としての全体の厚さが約0.5mm以下で構成できる
ことを実験的に確認している。It has been experimentally confirmed that when the same device as in the related art is used, the entire thickness of the package device can be configured to be about 0.5 mm or less.
第２図は特に素子の発熱量が多い場合に適用される例
を示したものである。FIG. 2 shows an example applied particularly when the heat generation amount of the element is large.
この場合には第１図（Ｂ）の工程で基板１の紙面下側
すなわち裏面の所定領域にエポキシ樹脂の如き絶縁性接
着剤膜1eを介して半田膜1fを形成すると共に他の部分を
第１図で説明した如くに形成して図（ａ）に示す状態と
する。In this case, in the step shown in FIG. 1 (B), a solder film 1f is formed on the lower side of the paper surface of the substrate 1, that is, on a predetermined region on the back surface of the substrate 1 via an insulating adhesive film 1e such as epoxy resin, and the other portions are formed in the same manner. 1 is formed as described with reference to FIG.
次いで、第１図で説明した工程を経て所要の薄型パッ
ケージ装置を構成した後、上記半田膜1fの面に通常の放
熱フィン10を添着して図（ｂ）に示すような放熱フィン
が装着された薄型パッケージ装置を得ることができる。Next, after a required thin package device is formed through the steps described in FIG. 1, a normal radiating fin 10 is attached to the surface of the solder film 1f, and a radiating fin as shown in FIG. A thin package device can be obtained.
上述の如く本発明により、ICとしての特性を損なうこ
となく小型，薄型化を実現して適用分野の拡大を図った
薄型パッケージ装置を提供することができる。As described above, according to the present invention, it is possible to provide a thin package device which can be reduced in size and thickness without impairing the characteristics of an IC and which can be applied to a wider range of applications.
第１図は本発明になる薄型パッケージ装置の製造方法を
示す工程図、 第２図は他の実施例を示す図、 第３図は従来のフラットパッケージICの構成を示す断面
図である。 である。図において、 １は基板、、1aは凹部（ステージ）、 1bは接合固定膜、1cは絶縁膜、 1dは接着剤層、1eは絶縁性接着剤膜、 1fは半田膜、２は外リード、 2a,2b…は外部導出用リード、2zは連結部、 ３はリードベース、５は回路基板、 5a,5b…は接続用リード、６は樹脂フィルム、 ７はICチップ（素子）、８はチップ完成体、 ９は薄型パッケージ装置、10は放熱フィン、 をそれぞれ表わす。FIG. 1 is a process diagram showing a method of manufacturing a thin package device according to the present invention, FIG. 2 is a diagram showing another embodiment, and FIG. 3 is a cross-sectional view showing a configuration of a conventional flat package IC. It is. In the figure, 1 is a substrate, 1a is a concave portion (stage), 1b is a bonding fixing film, 1c is an insulating film, 1d is an adhesive layer, 1e is an insulating adhesive film, 1f is a solder film, 2 is an outer lead, 2a, 2b ... are external leads, 2z is a connecting part, 3 is a lead base, 5 is a circuit board, 5a, 5b ... are connection leads, 6 is a resin film, 7 is an IC chip (element), and 8 is a chip. 9 indicates a thin package device, and 10 indicates a radiating fin.
Claims (1)
（1a）に素子（７）が搭載され、 該凹部（1a）の周囲の基板（１）上に外部導出用リード
（2a,2b,2c,2d）が配置され、 該素子（７）と外部導出用リード（2a,2b,2c,2d）が接
続用リード（5a,5b）により接続され、 該基板（１）表面側の素子（７），接続用リード（5a,5
b）および外部導出用リード（2a,2b,2c,2d）が樹脂で覆
われ且つ該凹部（1a）の形成された部分の基板（１）裏
面が樹脂で覆われずに封止されてなることを特徴とする
薄型パッケージ装置。An element (7) is mounted in a concave portion (1a) formed at the center of the surface of a substrate (1), and leads for external lead-out (2a, 2a) are mounted on the substrate (1) around the concave portion (1a). 2b, 2c, 2d) are arranged, and the element (7) and the lead-out leads (2a, 2b, 2c, 2d) are connected by connection leads (5a, 5b). Element (7), connection lead (5a, 5
b) and the leads (2a, 2b, 2c, 2d) for external lead-out are covered with resin, and the back surface of the substrate (1) where the concave portion (1a) is formed is sealed without being covered with resin. A thin package device characterized by the above-mentioned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1099327A JP2600898B2 (en) | 1989-04-19 | 1989-04-19 | Thin package device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1099327A JP2600898B2 (en) | 1989-04-19 | 1989-04-19 | Thin package device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02278753A JPH02278753A (en) | 1990-11-15 |
| JP2600898B2 true JP2600898B2 (en) | 1997-04-16 |
Family
ID=14244541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1099327A Expired - Lifetime JP2600898B2 (en) | 1989-04-19 | 1989-04-19 | Thin package device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2600898B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5293301A (en) * | 1990-11-30 | 1994-03-08 | Shinko Electric Industries Co., Ltd. | Semiconductor device and lead frame used therein |
-
1989
- 1989-04-19 JP JP1099327A patent/JP2600898B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02278753A (en) | 1990-11-15 |
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