JPS59124794A - Method of producing electronic circuit board - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing electronic circuit boards, such as chip carrier boards for ICs and LSIs, and circuit boards for watches, using printed circuit boards.

Conventional Structures and Problems Generally, in double-sided or multilayer printed circuit boards, so-called through holes are formed on both sides of the board, and connecting conductors are provided in a direction perpendicular to the surface of the board.

However, in chip carrier boards for TO1LSTs, circuit boards for watches, etc. that use printed circuit boards, conductors are formed on the side surfaces of the boards for purposes such as connection, contact, and soldering.

Among these, a conventional example will be explained with reference to FIGS. 1 to 4, taking a chip carrier substrate as an example.

Figure 1 is a top view of the conventional example after completion, Figure 2 is a cross-sectional view, Figure 3 is a cross-sectional view after IC chip mounting, and Figure 4 is a cross-sectional view of each process. .

The structure of the chip carrier substrate and the method of incorporating IC and LST chips into the substrate will be explained with reference to FIGS. 1 to 3. An insulating substrate 1, a die pad 2, a wire bonding pad 3, and a conductor wiring 4 as shown in FIG. 1 and FIG.
As shown in FIG. 3, a chip 8 is firmly bonded to the die pad 2 on a chip carrier substrate consisting of a side conductor 5, a side groove 6, and an external electrode 7, and then wire bonded using a bonding wire 9. and resin 10
and a frame 11 for sealing.

3. The external electrode 7 and side conductor 5 are parts that will be soldered later when connecting to the motherboard.

Next, a method of manufacturing the conventional chip carrier substrate will be described with reference to FIG. 4.

First, as shown in FIGS. 4a and 4b, through-holes 13 are formed by drilling or the like on an insulating substrate 1 made of glass epoxy, etc., on which conductor foils 12 made of copper or the like are formed on both sides. . Next, as shown in FIG. 4C, an electroless copper plating film 14 is applied to the inner wall of the through hole 13 and the conductor foil 12.
An electrolytic copper plating film 15 is formed. At this time, the conductor foils 12 on both sides are electrically connected by the plating films 14 and 15 formed on the inner walls of the through holes 13. Usually, the thickness of the electroless copper plating film 14 is about 0.25 to 1/2,
The thickness of the electrolytic copper plating film 15 is approximately 10 to 25 μm. Next, as shown in FIG. 4 (I), unnecessary parts of the conductor foil 12, electroless copper plating film 14, and electrolytic copper plating film 15 are removed by etching, and the die pad 2, wire bonding pad 3, conductor wiring 4, Form the external electrode 7. Next, the fourth
As shown in Figure e, the unnecessary portion is cut off approximately at the center of the through hole 13 to obtain a chip carrier substrate. The side groove 6 is a portion where about half of the through hole 13 remains.

FIG. 4d shows a sectional view taken along line AA' in FIG. The unnecessary portions are removed in the step shown in FIG. 4e by punching with a press using a mold, or by cutting a cutting board.

The disadvantages of the conventional example are as follows.

(1) If unnecessary parts are cut off by punching with a press using a mold, there is already a thick and flexible electrolytic film on the inner wall of the through hole at the time of punching. Since the copper plating film 15 is formed, the shear force during pressing is applied to the electrolytic copper plating film 15 on the inner wall of the through hole.
If this occurs, the electrolytic copper plating film 15 may peel off or the adhesion strength of the electrolytic copper plating film on the inner wall of the through hole may decrease. The smaller the through-hole pitch and through-hole diameter, the greater the rate of peeling, which is extremely disadvantageous for higher density, resulting in poor yield and lower reliability.

Page 5 (2) Another method of removing unnecessary parts is using a guising tool.
If the chip carrier board is cut using a method such as the above, it is not possible to cut all four sides of the chip carrier board at once, resulting in poor productivity and high cost.

Also, in this case, since the electrolytic copper plating film 15 has already been formed on the inner wall of the through hole, the electrolytic copper plating film 15 on the inner wall of the through hole is
It may be torn off. Further, in this method, burrs occur in the electrolytic copper plating film. Since this material is easily broken, it falls onto the board and causes a short circuit, resulting in poor quality and low reliability.

(3) If the diameter of the through-hole is made smaller in order to achieve higher density, the circulation of the plating solution into the through-hole during electrolytic copper plating will be very poor, and the coverage of the plating will be poor. The copper plating thickness is thin and uneven, making the side conductors of the chip carrier substrate very unreliable.

Purpose of the Invention The present invention eliminates the drawbacks of the above-mentioned conventional example.
The purpose of this method is to obtain a highly reliable electronic circuit board such as a chip carrier board without peeling off the electrolytic copper plating film on the inner wall of the through hole.

Structure of the Invention In order to achieve the object described in item 1, the present invention provides a method in which, after drilling a through hole, electroless copper plating is applied to the inner wall of the through hole, unnecessary parts are punched out using a press, and then electrolytic copper plating is applied. It is something to do.

Description of examples An embodiment of the present invention will be described with reference to FIGS. 5 and 6.

This embodiment is a chip carrier board for mounting a T01LSI chip, etc., and FIGS. 5A to 5I are cross-sectional views of each step, and FIG. 6 is a top view of each step. Figure 5 1) and 6
Figures a, 5d, 51, 5g, and 6c correspond to each other, respectively.

First, as shown in FIG. 5a, conductor foils 32 made of copper or the like are fixed on both sides of an insulating substrate 21 made of glass epoxy, polyamide, or the like. The thickness of the insulating substrate 21 is usually 0.
It is about 2 to 16 μm. The thickness of the conductor foil 32 is 9 to 35 degrees.

Next, as shown in FIG. 51) and FIG. 6a, a through hole 33 is formed in a portion that will later become the side surface of the chip carrier substrate by drilling, laser processing, punching, or the like. The diameter of the through hole 33 is selected depending on the pitch of the external electrodes of the chip carrier substrate, etc., but is usually 0.2 to 1.
It is about 01m 0. The number of through holes 33 to be formed is determined by the number of pins of the 'IC1r, sr chip to be mounted. Further, the pitch of the through hole 33 is 0.
3 to 2.54, and is determined from the number of pins and chip size of the TO, T, and ST chips, external dimensions of the chip carrier board, etc.

Next, as shown in FIG. 5C, an electroless copper plating film 34 is formed on the inner wall of the through hole 33 and the conductive foil 32. At this time, the conductor foils 32 on both sides are electrically connected via the electroless copper plating film. Electroless copper plating is performed by a method generally used for manufacturing through-hole boards, and the thickness is usually about 0.25 to 1 μm.

Next, as shown in FIG. 5d1 and 6 [FIG. 1], the through hole 33 is punched out using a press at approximately the center thereof, and unnecessary parts are cut off. At this time, a part of the through hole 33 becomes the groove 26 on the side surface of the chip carrier substrate. Moreover, as shown in FIG. 6 1), the chip carrier substrate 41 is
They are connected to the insulating substrate 21 on the outer periphery by the support portion 40, and a plurality of strips are formed on a single insulating substrate 21. The support part 40 is installed after the chip carrier board is completed or after the chip carrier board is installed.
T, S■ Separate after mounting the chip. Usually, the chip carrier substrate 41 is very small, about 5 to 201111 squares, so by connecting a plurality of them to the insulating substrate 21 using the support part 40, handling becomes easier and productivity is improved. The electroless copper plating film is extremely thin at 0.25 to 1μ.
Because the trench is extremely brittle, even if shearing force is applied to the plating film on the inner wall of the through-hole during punching using a press, as in conventional methods, the electroless copper plating film on the inner wall of the through-hole will not peel off.

Next, as shown in FIG. 5e, an electrolytic copper plating film 35 is formed on the side groove 26 and the electroless copper plating film 34. As shown in FIG. The thickness of the electrolytic copper plating film 35 is about 10 to 25 μm. At this time, the through hole 33 has already become the groove 26 on the side surface and is connected to the large hole 36, so the groove 26 on the side surface
The circulation of the plating solution is very good, and even when the through-hole diameter is small, it is possible to form a highly reliable electrolytic copper plating film with no pinholes and a uniform thickness.

Next, as shown in Fig. 5f, in the part to be removed later,
A plating resist film 37 is formed by photoetching, and using the plating resist film 37 as a mask, an etching resist film 38 is formed. As the etching resist film 38, a solder plating film or the like is used. After that, Figures 5g and 6
After removing the plating resist 37 as shown in FIG. A conductor layer 25 is formed. Etching is performed using a solution such as ammonium persulfate. Actual Example 10 ·-' On the male side, a method using a plating film such as solder as the etching resist film 38 has been described, but it is also possible to use a drag film, a liquid resist, or the like. However, in this case, the groove 26 on the side surface and the large hole 3 formed by cutting off unnecessary parts
It is necessary to fill the portion 6 with resin or the like to protect the conductor portion of the side groove during etching.

Next, as shown in FIG. 5 h11, the etching resist film 3 is etched.
After removing 8, in order to improve the bonding performance of wire bonding when mounting IC, LS chip,
U plating is performed to form an Au plating film 39. Au plating is performed by electrolytic plating, and the thickness uo is 1 to 1
．． It is about 51z.

Further, when performing normal Au plating, 1 to 4/j N1 plating is performed on the base.

An Au plating film may be used as the etching resist film when unnecessary parts are removed by etching. In that case, the etching resist film does not need to be removed. The Au plating film 39 is shown in
becomes.

11. Effects of the Invention In the present invention, unnecessary parts are separated after electroless copper plating, and therefore the following effects are achieved.

(1) Even when punched out with a press, the electroless copper plating film inside the through hole is extremely thin at 0.25 to 1 μm.
Due to its extremely brittle nature, the electroless copper plating film inside the through holes will not peel off even when shearing force is applied during punching, making it possible to obtain extremely reliable electronic circuit boards such as chip carrier boards. can.

(2) Due to the reasons shown above, the through hole pitch is
Even if the size is very small, such as 0.04 mm, 0.51 mm, or 0.635 mm, it can be easily separated, making it possible to obtain a high-density electronic circuit board such as a chip carrier board.

(3) As the cutting method is performed by pressing using a mold, the productivity is very high and the cost is low.

(4) When performing electrolytic copper plating, the through-hole part is already in the groove state and is connected to the large hole formed by cutting off the unnecessary part, so it is difficult to plate the side groove. Even if the diameter of the through hole is made small in order to achieve high density, the electrolytic copper plating film in the side groove has no pinholes and has a uniform thickness, making it possible to obtain a highly reliable conductor in the side groove. I can do that.

[Brief explanation of drawings]

Figure 1 is a top view of a conventional chip carrier board after completion, Figure 2 is a sectional view taken along line A-A' in Figure 1, Figure 3 is a sectional view of a conventional chip carrier board after the C chip is mounted, Figure 4a
-e is a cross-sectional view of each step in a conventional manufacturing method, FIGS. It is a top view according to process in . 21... Insulating substrate, 22... Die pad, 23...
・Wire bonding pad, 24... Conductor wiring, 2
5...Conductor in side groove, 26...Groove in side surface, 27...
External electrode, 32... Conductor foil, 33... Through hole, 34... Electroless copper plating film, 35... Electrolytic copper plating film,
36...Large pore, 37. Metsukire cyst membrane, 38...
Etching 13 Baler resist film, 39...Au plating, 40...Supporting part, /II...Chip carrier substrate. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 4 Figure 5 Figure 6 Figure 6 (b) Figure 6 (ω

Claims (1)

[Claims] A through hole is formed in an insulating substrate having conductive foil on one or both sides, electroless plating is performed on the conductive foil including the inner wall of the through hole, and unnecessary parts are cut off, leaving a part of the through hole. An electronic circuit comprising a part of the inner wall of the through hole, electrolytically plated on the conductor foil, and forming a conductor wiring using the conductor foil and the plating film on the part of the inner wall of the through hole. Substrate manufacturing method.