JPS63240093A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPS63240093A JPS63240093A JP7463387A JP7463387A JPS63240093A JP S63240093 A JPS63240093 A JP S63240093A JP 7463387 A JP7463387 A JP 7463387A JP 7463387 A JP7463387 A JP 7463387A JP S63240093 A JPS63240093 A JP S63240093A
- Authority
- JP
- Japan
- Prior art keywords
- electrolytic plating
- circuit
- outline
- printed wiring
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000009713 electroplating Methods 0.000 claims description 51
- 239000004020 conductor Substances 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 18
- 238000007747 plating Methods 0.000 claims description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 238000003486 chemical etching Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000004080 punching Methods 0.000 claims description 3
- 238000007772 electroless plating Methods 0.000 claims description 2
- 238000007796 conventional method Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010297 mechanical methods and process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- -1 etc. is not attached Chemical compound 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000000275 quality assurance Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体および集積回路チップを直接搭載しチ
ップそのものをワイヤボンディング、フリップチップ（
ＦＬＩＰ ＣＨＩＰ：チップの下にはんだめっきやは
んだ蒸着により接着パッドを作り、配線板の導体と結合
する方法）やＴａｐｅムｕｔｏｍａｔｅｄ Ｂｏｎｄ
ｉｎｇ （Ｔ Ａ Ｂ ）などの方法で直接実装するの
に使われるプリント配線板の製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to directly mounting semiconductor and integrated circuit chips and bonding the chips themselves by wire bonding, flip chip (
FLIP CHIP: A method of creating adhesive pads under the chip by solder plating or solder evaporation and bonding it to the conductor of the wiring board) and Tape Mutomated Bond
The present invention relates to a method for manufacturing a printed wiring board used for direct mounting using a method such as ing (T A B ).
従来の技術
従来、チップはセラミック基板もしくけ金属板リードフ
レーム上に突出した状態で搭載されパッケージされてプ
リント配線板に実装されていた。BACKGROUND OF THE INVENTION Conventionally, chips have been mounted on ceramic substrates or metal plate lead frames in a protruding state, packaged, and mounted on printed wiring boards.
一方最近ダイボンディングおよびワイヤボンディング等
の技術進歩により、プラスチック基板のプリント配線板
上にも直接チップを搭載する方法が開発され実施が可能
となってきた。プリント配線板も実装技術の進歩により
その実装方法にマツチング出来るよう改良がなされてき
ている。On the other hand, recent technological advances in die bonding, wire bonding, etc. have made it possible to develop and implement methods for directly mounting chips on printed wiring boards made of plastic substrates. With advances in mounting technology, printed wiring boards have also been improved to match the mounting methods.
従来のこのようにチップを搭載するプリント配線板の製
造の一つの方法としては、あらかじめプリント配線板上
に導体回路を形成した後、電解ニッケルメッキ、電解金
メッキ等の電解メッキが施される。この方法は比較的高
い精度と信頼性のある電子回路製品が得られるので、特
にチップを直接搭載するプリント配線板に社良く応用さ
れる方法である。この際、プリント配線板上に導体回路
を形成した後、電解メッキを施すために全ての導体回路
をあらかじめ導通線で導通した後、該導通線を外部リー
ド線につないで電解メッキを施し、更に、電解メッキの
終了後にあっては、不要となる導通線のうち実際に使用
される時に導体回路として必要な部分以外の不要な回路
部分を何らかの方法で除去する必要がある。この場合、
通常は導通線をプリント配線板の外形線の外に導き出し
て電解メッキ終了後は、プレスなどによる打抜き加工に
よって除去することが一般的に行われている。One conventional method for manufacturing a printed wiring board on which a chip is mounted is to form a conductor circuit on the printed wiring board in advance, and then apply electrolytic plating such as electrolytic nickel plating or electrolytic gold plating. Since this method produces electronic circuit products with relatively high precision and reliability, it is a method that is often applied particularly to printed wiring boards on which chips are directly mounted. At this time, after forming conductor circuits on the printed wiring board, all the conductor circuits are connected in advance with conductive wires in order to perform electrolytic plating, and then the conductive wires are connected to external lead wires and electrolytic plating is applied. After the electrolytic plating is completed, it is necessary to remove unnecessary circuit parts other than those necessary as conductor circuits when actually used among the unnecessary conductive wires by some method. in this case,
Normally, the conductive wire is guided outside the outline of the printed wiring board, and after electrolytic plating is completed, it is generally removed by punching using a press or the like.
また外形線の内側の孤立した導体回路を電解メッキする
ために、電解メッキ用導体回路を形成し、電解メッキが
終了した後でドリル等機械的な方法で不要回路を切断し
所望の回路を得る技術、さらには実公昭６０−３８２９
１号公報にみられるように、打抜き外形線の内側の電解
メッキ用導体回路を集中配置し電解メッキ用導体回路部
分をザグリ切削加工によシ除去する方法もあった。In addition, in order to electrolytically plate isolated conductor circuits inside the outline, a conductor circuit for electrolytic plating is formed, and after electrolytic plating is completed, unnecessary circuits are cut using a mechanical method such as a drill to obtain the desired circuit. Technology, and even Jikko Sho 60-3829
As seen in Publication No. 1, there was a method in which the conductor circuit for electrolytic plating was centrally arranged inside the punched outline and the conductor circuit for electrolytic plating was removed by counterbore cutting.
発明が解決しようとする問題点 このような従来の技術の問題点について述べる。The problem that the invention seeks to solve Problems with such conventional technology will be described.
（１）上記の導通線をプリント配線板の外形線の外に導
き出して電解メッキ終了後にプレスなどによって打抜き
加工によって除去する方法は、導体回路が複雑になると
導通線の全てを外形線の外側に設定することはできず、
またこのような場合には外形線の内側に孤立した導体回
路が残り、この部分には電解メッキが施されないという
問題点があった。したがってこの従来方法では高い精度
と信頼性のあるプリント配線板を製造することができな
いのであった。(1) The above-mentioned method of leading the conductive wires outside the outline of the printed wiring board and removing them by punching using a press or the like after electrolytic plating is completed will lead all the conductive wires outside the outline when the conductor circuit becomes complex. cannot be set,
Further, in such a case, there is a problem in that an isolated conductor circuit remains inside the outline, and this portion is not electrolytically plated. Therefore, this conventional method cannot produce printed wiring boards with high precision and reliability.
（２）次に第２の従来技術である外形線の内側の孤立し
た導体回路を電解メッキするために、電解メッキ用導体
回路を形成し、電解メッキが終了した後でドリル等機械
的な方法で不要回路を切断し所望の回路を得る技術は、
配線密度が高くなればドリル等機械的な切断では生産性
、回路の信頼性（切削時の銅箔等のヒゲによるショート
など）などに問題があり、高密度配線のプリント配線板
には適用できないという問題点を有していた。(2) Next, in order to electrolytically plate an isolated conductor circuit inside the outline line, which is the second conventional technique, a conductor circuit for electrolytic plating is formed, and after electrolytic plating is completed, a mechanical method such as a drill is used. The technology to cut unnecessary circuits and obtain the desired circuit is
As wiring density increases, mechanical cutting using drills and other tools has problems with productivity and circuit reliability (such as short circuits caused by whiskers in copper foil, etc. during cutting), and cannot be applied to printed wiring boards with high-density wiring. There was a problem.
（３次に第３の従来技術である打抜き外形線の内側の電
解メッキ用導体回路を集中配置し、電解メッキ用導体回
路部分をザグリ切削加工により除去し、所望の回路を得
る技術は、電解メッキ用導体回路部分が集中配置されて
いるため切削加工時金属箔のヒゲによるショートを皆無
にすることは非常に困難であシ、また最近のように回路
が高密度化されればされるほど生産時の品質保証ができ
ないという問題点を有していた。(Thirdly, the third conventional technique is to concentrate the conductor circuit for electrolytic plating inside the punched outline and remove the conductor circuit for electrolytic plating by counterbore cutting to obtain the desired circuit. Because the conductor circuit parts for plating are arranged in a concentrated manner, it is extremely difficult to completely eliminate short circuits caused by whiskers in the metal foil during cutting, and as circuits become more dense these days, The problem was that quality assurance during production was not possible.
またこの方法では基板が座ぐられるためザグリを必要と
しないものまた最近のようにプリント配線板が薄いもの
、あるいはフレキシブル配線板のようなものには適さな
いものであった。In addition, this method does not require counterboring because the board is seated, and is not suitable for products such as thin printed wiring boards or flexible wiring boards, which have been developed recently.
本発明はこのような問題点を解決するもので、高密度の
プリント配線板であっても、生産性に優れた工法で、電
解メッキをほどこした高品質のプリント配線板の製造方
法を提供するものである。The present invention solves these problems, and provides a method for manufacturing high-quality electrolytic plated printed wiring boards using a method with excellent productivity even for high-density printed wiring boards. It is something.
問題点を解決するだめの手段
以上のような問題点を除去、改善するために、本発明は
、電解メッキにより導体回路が形成されたプリント配線
板において、打抜き外形線の内側と外側に電解メッキの
リード線として使用した後は不要となる電解メッキ用導
体回路を形成し、このうち特に打抜き外形線の内側にあ
る不用な電解メッキ用導体回路を化学的エツチング法で
除去して所望の回路パターンを有するプリント配線板の
製造方法を提供するものである。Means for Solving the Problems In order to eliminate and improve the above-mentioned problems, the present invention provides electrolytic plating on the inside and outside of the punched outline lines in printed wiring boards on which conductor circuits are formed by electrolytic plating. A conductor circuit for electrolytic plating that becomes unnecessary after being used as a lead wire is formed, and the unnecessary conductor circuit for electrolytic plating inside the punched outline is removed by chemical etching to create the desired circuit pattern. The present invention provides a method for manufacturing a printed wiring board having the following.
作用
この構成により導体回路が複雑になり導通線の全てを外
形線の外側に設定することのできないようなプリント配
線板でも、外形線の内側にも電解メッキ用の導通線を設
定することができ、高密度、薄型のプリント配線板でも
自由に設計でき量産性に優れた高品質のプリント配線板
を得ることができる。Effect: This configuration makes it possible to set conductive lines for electrolytic plating inside the external lines even on printed wiring boards where the conductor circuit is complicated and it is impossible to set all of the conductive lines outside the external lines. , high-density, thin printed wiring boards can be freely designed, and high-quality printed wiring boards with excellent mass productivity can be obtained.
なお、本発明のプリント配線板は、片面、両面および多
層基板あるいはチップを凹部に搭載させてグイボンディ
ングにより凹部の底部にチップを固定しワイヤボンディ
ングその他の方法でチップ回路とプリント配線板とを電
気的に接続するためザグリ加工を必要とするプリント配
線板であっても何れもなんの問題もなく適用できる。The printed wiring board of the present invention has a single-sided, double-sided, and multilayer board or chip mounted in a recess, and the chip is fixed to the bottom of the recess by wire bonding, and the chip circuit and the printed wiring board are electrically connected by wire bonding or other methods. The present invention can be applied to any printed wiring board that requires counterbore processing for direct connection without any problems.
実施例
以下本発明の一実施例について、図面を参照しながら説
明する。EXAMPLE An example of the present invention will be described below with reference to the drawings.
第１図はプレスによる外形線打抜き前であるが、本発明
で得られた電解メッキにより導体回路が形成されたチッ
プ搭載用のプリント配線板の一実施例の平面図である。FIG. 1 is a plan view of an embodiment of a printed wiring board for mounting a chip on which a conductive circuit is formed by electrolytic plating obtained according to the present invention, although before the outline is punched out by a press.
第１図で示すように、導体回路が複雑であり、電解メッ
キ用の導通線の全てを外形線の外側に設定することがで
きないようなプリント配線板であり、打抜き外形線の内
側（例えば第１図の３の部分）にも電解メッキ用の導通
線が必要なプリント配線板の場合特に有効である。As shown in Figure 1, this is a printed wiring board whose conductor circuit is complex and it is impossible to set all of the conductive lines for electrolytic plating outside the outline of the punched outline (for example, inside the outline of the punched outline). This is particularly effective in the case of a printed wiring board that requires a conductive wire for electrolytic plating even in the portion 3 in Figure 1).
１はプリント配線板の打抜き外形線、２は打抜き外形線
の外側の電解メッキ用導通線、３は打抜き外形線の内側
にある孤立した導体回路であυ、４はチップ搭載箇所、
６の部分はチップとワイヤボンディングするために電解
ニッケルメッキと電解金メッキが必ず必要な部分である
。６は本発明を実施した結果形成されたニッケル、金等
の電解メッキが付着していない部分であり銅が表面にあ
られれている。以下順をおって本発明で得られるプリン
ト配線板（第１図）の製造過程を説明する。1 is the punched outline of the printed wiring board, 2 is the conductive wire for electrolytic plating outside the punched outline, 3 is an isolated conductor circuit inside the punched outline, 4 is the chip mounting location,
Part 6 is a part where electrolytic nickel plating and electrolytic gold plating are absolutely necessary for wire bonding with the chip. Reference numeral 6 denotes a portion formed as a result of implementing the present invention to which electrolytic plating of nickel, gold, etc. is not attached, and copper is deposited on the surface. The manufacturing process of the printed wiring board (FIG. 1) obtained by the present invention will be explained in the following order.
■ まず第２図（第１図の７−７′の部分の斜視図）に
示すように所望の回路に電解メッキを施すためにつなぐ
電解メッキ用導通線のうち実際に回路として使用される
時に導体回路として必要な部分以外の不要な回路部分を
除いた回路パターンを従来の方法により銅箔をエツチン
グして形成する。■ First, as shown in Figure 2 (a perspective view of the section 7-7' in Figure 1), among the conductive wires for electrolytic plating that are connected to apply electrolytic plating to a desired circuit, when actually used as a circuit, A circuit pattern is formed by etching copper foil using a conventional method, excluding unnecessary circuit parts other than those required as a conductive circuit.
■ 第３図に示すように前記銅回路パターン９及び絶縁
基板８全面に薄く無電解銅メッキ１０’ｉｉ行う。(2) As shown in FIG. 3, a thin electroless copper plating 10'ii is applied to the entire surface of the copper circuit pattern 9 and the insulating substrate 8.
■ 第４図に示すように打抜き外形線の内側の電解メッ
キ用導体回路形成のためのパターンでエツチングレジス
ト１１を形成したのちソフトエツチングを行い、外形線
の内側の電解メッキ用導体回路以外の薄い無電解銅メッ
キ層（第３図１ｏ）ｆ：除去する。■ As shown in Figure 4, after forming an etching resist 11 with a pattern for forming a conductor circuit for electrolytic plating inside the punched outline, soft etching is performed to form a thin layer of the conductor circuit for electrolytic plating inside the outline. Electroless copper plating layer (FIG. 3 1o) f: Removed.
■ 次にこのエツチングレジストを除去し、外形線の内
側の電解メッキ用導通線１２ｆ、形成し、第５図に示す
ようにこの電解メッキ用導通線１２の上にこれよシ少し
太めのメッキレジスト１３を形成する。■ Next, remove this etching resist, form a conductive line 12f for electrolytic plating inside the outline line, and place a slightly thicker plating resist on top of this conductive line 12 for electrolytic plating, as shown in FIG. form 13.
■ 第６図に示すように外形線の内側の電解メッキ用導
通線１２°以外の所望の電気回路に電解ニッケルメッキ
−電解金メッキ１４を行う。(2) As shown in FIG. 6, electrolytic nickel plating-electrolytic gold plating 14 is applied to desired electric circuits other than the 12° conductive line for electrolytic plating inside the outline.
■ その後メッキレジスト１３を除去し、ソフトエツチ
ングで外形線の内側の電解メッキ用導通線の薄い無電解
メッキ層の部分１２を除去する（第１図）。(2) Thereafter, the plating resist 13 is removed, and the thin electroless plating layer portion 12 of the conductive wire for electrolytic plating inside the outline is removed by soft etching (FIG. 1).
■ 最後に外形線の外側の電解メッキ用導通線２をプリ
ント配線板の外形打抜きと同時に切断し、所望の回路パ
ターンを有するプリント配線板を得ることができる。(2) Finally, the conductive wires 2 for electrolytic plating outside the outline are cut at the same time as the outline of the printed wiring board is punched, and a printed wiring board having a desired circuit pattern can be obtained.
以上のように本実施例によれば打抜き外形線の内側の電
解メッキ用導通線を化学的エツチング法で除去すること
によシ導体回路が複雑で電解メッキ用導通線の全てを外
形線の外側に設定することができず外形線の内側に孤立
した導体回路が残った場合でも所望のところに電解ニッ
ケルメッキ−電解金メッキをすることができる。As described above, according to this embodiment, by removing the conductive wires for electrolytic plating inside the punched outline line by chemical etching, the conductor circuit is complicated and all the conductive wires for electrolytic plating are removed outside the outline line. Even if it cannot be set and an isolated conductor circuit remains inside the outline, electrolytic nickel plating-electrolytic gold plating can be applied to the desired location.
発明の効果
以上のように本発明によれば打抜き外形線の内側にある
不用な電解メッキ用導通線を化学的エツチング法で除去
することにより、導体回路が複雑になり電解メッキ用導
通線の全てを外形線の外側に設定することが！きないよ
うなプリント配線板でも、外形線の内側にも電解メッキ
用導通線を設定することができ、高密度、薄型のプリン
ト配線板でも自由に設計でき、量産性に優れた高品質の
プリント配線板を製造することができる。Effects of the Invention As described above, according to the present invention, by removing unnecessary conductive wires for electrolytic plating inside the punched outline line by chemical etching, the conductor circuit becomes complicated and all of the conductive wires for electrolytic plating are removed. can be set outside the outline! Even on printed wiring boards that are difficult to clean, conductive wires for electrolytic plating can be set inside the outline lines, allowing for flexible design of high-density, thin printed wiring boards, and high-quality printing with excellent mass production. Wiring boards can be manufactured.
第１図はプレスによる外形線打抜き前ではあるが、本発
明の一実施例で得られた電解メッキにより導体回路が形
成されたチップ搭載用のプリント配線板の要部上面図で
ある。第２図〜第６図は本発明の一実施例の製造過程を
説明した要部拡大斜視図である。
１・・・・・・打抜き外形線、３・・・・・・導体回路
、８・・・・・・絶縁基板。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第２
図
第 ３ 区
第４図
第５図
第６図FIG. 1 is a top view of a main part of a printed wiring board for mounting a chip on which a conductive circuit is formed by electrolytic plating obtained in one embodiment of the present invention, although the printed wiring board is not yet punched out by a press. FIGS. 2 to 6 are enlarged perspective views of essential parts illustrating the manufacturing process of an embodiment of the present invention. 1...Punched outline line, 3...Conductor circuit, 8...Insulating board. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 Ward 4 Figure 5 Figure 6
Claims (2)
載用のプリント配線板の打抜き外形線の内側と外側に電
解メッキ用の導通線として使用した後は不用となる電解
メッキ用の導通線を形成し、前記打抜き外形線の内側の
電解メッキ用導通線を、化学的エッチング法で除去する
ことにより所望の回路パターンを形成するプリント配線
板の製造方法。(1) Conductive wires for electrolytic plating that will become unnecessary after being used as conductive wires for electrolytic plating are formed on the inside and outside of the punched outline of a printed wiring board for mounting a chip on which a conductive circuit is formed by electrolytic plating. and a method for manufacturing a printed wiring board, in which a desired circuit pattern is formed by removing the conductive wire for electrolytic plating inside the punched outline line by a chemical etching method.
望の回路パターンを銅回路で形成した後、前記銅回路パ
ターン及び絶縁基板全面に薄く無電解銅メッキを行い、
次に打抜き外形線の内側の電解メッキ用導体回路形成の
ためのパターンでエッチングレジストを形成し、その後
ソフトエッチングを行って外形線の内側の電解メッキ用
導体回路以外の前工程で形成した薄い無電解銅メッキ層
を除去し、次にこの様にして形成された外形線の内側の
電解メッキ用導体回路の上にこれよりも少し太めのメッ
キレジストを形成し、前記外形線の内側の電解メッキ用
導体回路以外の所望の電気回路にニッケル、または金の
少なくとも一方のメッキを行い、その後、前記メッキレ
ジストを除去し、ソフトエッチングで、前記外形線の内
側の電解メッキ用導体回路の無電解メッキ層の部分を除
去し、最後に外形線の外側の電解メッキ用導体回路をプ
リント配線板の外形打抜きと同時に切断し、所望の回路
パターンを形成する特許請求の範囲第１項記載のプリン
ト配線板の製造方法。(2) After forming a desired circuit pattern including an electrolytic plating circuit outside the punched outline line with a copper circuit, perform a thin electroless copper plating on the copper circuit pattern and the entire surface of the insulating substrate,
Next, an etching resist is formed with a pattern for forming a conductor circuit for electrolytic plating inside the punched outline, and then soft etching is performed to remove the thin resist formed in the previous process other than the conductor circuit for electrolytic plating inside the outline. The electrolytic copper plating layer is removed, and then a slightly thicker plating resist is formed on the conductor circuit for electrolytic plating inside the outer line formed in this way, and the electrolytic plating inside the outer line is applied. At least one of nickel and gold is plated on the desired electric circuit other than the conductor circuit for electrolytic plating inside the outline line, and then the plating resist is removed and soft etching is performed to perform electroless plating of the conductor circuit for electrolytic plating inside the outline line. The printed wiring board according to claim 1, wherein a portion of the layer is removed and finally the conductor circuit for electrolytic plating outside the outline line is cut at the same time as the outline punching of the printed wiring board to form a desired circuit pattern. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7463387A JPS63240093A (en) | 1987-03-27 | 1987-03-27 | Manufacture of printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7463387A JPS63240093A (en) | 1987-03-27 | 1987-03-27 | Manufacture of printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63240093A true JPS63240093A (en) | 1988-10-05 |
Family
ID=13552804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7463387A Pending JPS63240093A (en) | 1987-03-27 | 1987-03-27 | Manufacture of printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63240093A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003101195A (en) * | 2001-09-26 | 2003-04-04 | Nec Toppan Circuit Solutions Inc | Substrate for semiconductor device and production method therefor |
| JP2006287034A (en) * | 2005-04-01 | 2006-10-19 | Shinko Electric Ind Co Ltd | Manufacturing method of wiring substrate utilizing electrolytic plating |
| JP2007019062A (en) * | 2005-07-05 | 2007-01-25 | Fujitsu Ltd | Production of printed circuit board |
-
1987
- 1987-03-27 JP JP7463387A patent/JPS63240093A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003101195A (en) * | 2001-09-26 | 2003-04-04 | Nec Toppan Circuit Solutions Inc | Substrate for semiconductor device and production method therefor |
| JP2006287034A (en) * | 2005-04-01 | 2006-10-19 | Shinko Electric Ind Co Ltd | Manufacturing method of wiring substrate utilizing electrolytic plating |
| JP2007019062A (en) * | 2005-07-05 | 2007-01-25 | Fujitsu Ltd | Production of printed circuit board |
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