JP2859741B2 - Manufacturing method of printed wiring board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board on which a chip component electrically connected by soldering and a bare chip IC electrically connected by wire bonding are mounted.

[0002]

2. Description of the Related Art Conventionally, when electronic components such as a flat package IC, a chip resistor, and a chip capacitor are mounted on a printed circuit board, a predetermined pattern is printed on the printed circuit board using cream solder, and the electronic components are arranged there. After that, the electronic component is mounted on a printed circuit board by heating with an infrared heater or the like to reflow the cream solder. In this case, nickel-gold plating by electroless plating or electrolytic plating is applied to prevent rust of copper as a pattern.

Further, in order to mount a bare chip IC on a printed circuit board and perform wire bonding with a gold wire, it is necessary to apply nickel-gold plating to the pad portion by electrolytic plating or electroless plating. In this case, nickel must have a thickness of 5 to 10 μm in order to have a hardness that resists heating and pressing during wire bonding, and gold must have a high purity of 99.99% or more, and a thickness of 0.
It needs to be 3 to 0.5 μm or more.

[0004]

However, in recent years, together with a bare chip IC by wire bonding, chip components such as a resistor and a capacitor are mixedly mounted around the bare chip IC. In this case, as long as several resistors, capacitors, etc. are arranged around the bare chip IC and its periphery, all plating leads are provided to the bare chip IC and the pads of the chip components, and nickel by electrolytic plating,
Gold plating can be performed. However, for example, in a hybrid IC application, when there are a large number of tens of resistors, capacitors, and the like, and when these and a bare chip IC must be mixed, there are the following restrictions.
Since wiring is complicated and detour is difficult, it is difficult to provide plated leads to all pads of the chip component. In addition, when the size of the printed circuit board is increased, the wiring length becomes longer, noise is more likely to be picked up, and electrical characteristics such as propagation delay are increased. Further, multi-layering increases costs. 0.3 to 0.5 μm on pad for mounting chip parts
When gold plating of m is applied, solder is diffused into the gold plating layer by heating for solder printing and solder reflow to form a thick diffusion layer, thereby lowering the reliability of soldering. This decrease in reliability has a greater overall effect as the number of chip components increases. Therefore, in order to prevent the above-mentioned diffusion of solder, gold plating is required to have a thickness of 0.1 μm or less for pads for mounting chip components, not to form a thick diffusion layer, and to perform wire bonding of bare chip ICs. 0.3 to 0.5 μ
m thickness is required.

Under these conditions, when the electronic components are mounted on a printed circuit board by reflowing the cream solder, nickel-gold plating by electrolytic plating attaches plating leads for plating and makes the circuit independent after plating. For this reason, it is necessary to cut the plating leads, and there is a problem that performing such an operation over the entire printed circuit board is costly and is not preferable.

Accordingly, an object of the present invention is to eliminate the need for a large number of plated leads and to reduce the reliability of connection when a large number of chip components and bare chip ICs are mounted together.
Moreover, it is an object of the present invention to provide a method of manufacturing a printed wiring board, which enables high-density wiring, maintains electrical characteristics, and reduces manufacturing costs.

[0007]

According to the present invention, in order to achieve the above object, a chip component for making an electrical connection by soldering on a printed circuit board made of an insulating material and an electrical connection by wire bonding are provided. In a method of manufacturing a printed wiring board for mounting a bare chip IC, a step of forming a conductive pattern on the printed circuit board and then plating nickel and gold on the conductive pattern by electroless plating, and an area for mounting the bare chip IC. The gist of the present invention is a method for manufacturing a printed wiring board, comprising: a step of covering a region except for the plating resist with a plating resist; and a step of performing gold plating by electroplating on a conductor pattern other than the plating resist.

[0008]

First, after a conductor pattern is formed on a printed circuit board, nickel and gold are plated on the entire conductor pattern by electroless plating, and the area excluding the area for mounting the bare chip IC is covered with a plating resist. ,
Subsequently, gold plating is applied to regions other than the plating resist by electrolytic plating. As a result, a printed wiring board is formed on which both chip components for making electrical connections by soldering and bare chip ICs for making electrical connections by wire bonding can be mounted under favorable conditions.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. (1) A step of plating nickel and gold by electroless plating. As shown in FIG. 6, first, a through hole 2 is provided through a printed board 1 made of a copper-clad glass epoxy laminate by an NC drill, and then, as shown in FIG. 7, electroless copper plating and electrolytic copper plating are performed. Thereby, the copper plating layer 3 is formed. Instead of the glass epoxy laminate, a laminate of composite, glass polyimide, glass triazine, paper epoxy, Teflon, or the like can be used. Next, as shown in FIG. 8, after the etching resist layer 4 is formed on the portion of the conductor pattern using a dry film, etching is performed as shown in FIG. Subsequently, as shown in FIG. 10, the conductive pattern 5 is formed by removing the etching resist layer 4.

Next, as shown in FIG. 2, a nickel plating layer 6 is formed on the conductor pattern 5 by electroless plating using a commercially available nickel (Ni) -phosphorus (P) plating bath. It is formed to a thickness of 5 μm. Then, a gold plating layer 7 having a thickness of about 0.05 μm is formed on the nickel plating layer 6 by a commercially available replacement gold plating bath. In addition, as a method of forming the conductor pattern 5 on the printed circuit board 1, a semi-additive method or a full-additive method can be adopted in addition to the above-described subtractive method by etching. As the electroless nickel plating bath, a nickel-boron bath or the like can be used instead of the nickel-phosphorus plating bath, and a reduced gold plating bath can be used instead of the replacement gold plating bath. However, when using this reduced gold plating bath, it is important to shorten the processing time so that the thickness of the gold plating does not become much larger than 0.1 μm.

As described above, in this step, since gold is formed to a thickness of 0.1 μm or less on the conductor pattern 5 and the pad portion of the chip component, even if cream solder is applied thereon and heated and reflowed, Since a thick diffusion layer is not formed between solder and gold, and there is no so-called solder erosion, the reliability of soldering is excellent. Also,
Since the thickness of the gold plating can be made thinner than before, the cost can be reduced accordingly. Further, the conductor pattern 5
Since the whole is covered with gold, it is possible to prevent migration in which copper is melted from the conductor pattern 5. (2) A step of covering a region other than a region where the bare chip IC is mounted with a plating resist.

As shown in FIGS. 3 and 5, the solder resist layer 9 was printed by a screen printing method except for the pad portions 8a and 8b on the gold-plated printed circuit board 1. As shown in FIGS. 1 and 5, the chip component 13 is mounted on the one pad portion 8a, and the other pad portion 8b
The other end of the gold wire 14 whose one end is connected to the bare chip IC 10 is wire-bonded. As the solder resist layer 9, an epoxy resin applied by a screen printing method, a photocurable acrylic resin in the form of a film to be used by adhesion, a liquid photocurable acrylic resin to be applied and used, or the like can be used.
Next, a dry film plating resist layer 11 was formed in a region other than the region R where the bare chip IC 10 was mounted.

The step of applying the solder resist layer 9 may be performed before or after gold plating by electrolytic plating, as described below, as long as the entire conductor pattern 5 is plated with nickel or gold by electroless plating. (3) A step of applying gold plating by electrolytic plating. As shown in FIG. 4, a gold plating layer having a thickness of 0.5 μm is formed by electroplating using a plating lead (not shown) on a portion of the printed circuit board 1 where the dry film plating resist layer 11 is not provided and where the bare chip IC 10 is mounted. 1
2 was given. Next, as shown in FIG. 1, after the dry film plating resist layer 11 was peeled off, outer shape processing was performed. Then, the desired printed wiring board was obtained by mounting the bare chip IC 10 by wire bonding using the gold wire 14.

In the step of applying the gold plating layer 12 by the electrolytic plating, the thickness of the gold plating layer 12 can be secured to 0.3 μm or more, so that the wire bonding can be performed with high reliability. As described above, according to the method of manufacturing a printed wiring board of the present embodiment, when a large number of chip components 13 and bare chip ICs 10 are mixed and mounted, plating leads need only be attached to the pad portions 8b for bare chip ICs 10. Since there is no need to attach the component 13 to the pad portion 8a, the number of plating leads can be minimized, and the printed board 1 does not need to be enlarged or multilayered for plating leads. Therefore, it is possible to prevent deterioration of electrical characteristics such as noise and propagation speed, and to reduce manufacturing costs. Further, high-density wiring can be made possible by the amount of unnecessary plating leads.

[0015]

According to the present invention, when a large number of chip components and bare chip ICs are mixedly mounted, the number of plating leads for performing electrolytic plating can be minimized, and the reliability of connection is not reduced. In addition, there is an excellent effect that high-density wiring is possible, electrical characteristics can be maintained, and manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a view showing an embodiment of the present invention, and is a cross-sectional view showing a printed wiring board on which a bare chip IC is mounted.

FIG. 2 is a cross-sectional view showing a state in which a gold plating layer is formed on a conductor pattern portion by electroless plating.

FIG. 3 is a cross-sectional view showing a state where plating resist is applied to a portion other than a region where a bare chip IC is mounted.

FIG. 4 is a cross-sectional view showing a state where gold plating is applied by electroplating to a region where a bare chip IC is mounted.

FIG. 5 shows a chip component and a bare chip IC on a printed circuit board.
FIG. 6 is a partial plan view showing a state in which is mounted.

FIG. 6 is a cross-sectional view showing a state in which a through-hole is provided in a printed circuit board.

FIG. 7 shows the printed circuit board of FIG. 6 by electroless copper plating.
It is sectional drawing which shows the state in which the copper plating layer was formed.

FIG. 8 is a cross-sectional view showing a state where an etching resist layer is provided in a portion of a conductor pattern.

FIG. 9 is a cross-sectional view showing a state where the printed board of FIG. 8 is etched.

FIG. 10 is a cross-sectional view showing a state where an etching resist layer is peeled off from the printed circuit board of FIG. 9;

[Explanation of symbols]

Reference Signs List 1 printed board, 5 conductor pattern, 10 bare chip IC, 11 dry film plating resist layer as plating resist layer, 13 chip parts, area for mounting R bare chip IC

Continuation of the front page (56) References JP-A-2-185509 (JP, A) JP-A-4-7892 (JP, A) JP-A-60-76187 (JP, A) JP-A-1-196195 (JP) JP-A-1-200694 (JP, A) JP-A-63-128788 (JP, A) JP-A-57-64943 (JP, A) JP-A-2-54274 (JP, U) (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/60 301 H05K 3/24 H05K 1/18

Claims (1)

(57) [Claims] 1. A chip component (13) for making an electrical connection by soldering and a bare chip IC (10) for making an electrical connection by wire bonding are mounted on a printed board (1) made of an insulating material. Forming a conductor pattern (5) on the printed circuit board (1), and then forming the conductor pattern (5) on the printed circuit board (1).
A step of plating nickel and gold thereon by electroless plating, a step of covering the area excluding the area (R) where the bare chip IC (10) is mounted with a plating resist (11), and a step other than the plating resist (11) Applying gold plating by electroplating to the conductor pattern (5) in the portion (1).