JPH05144821A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05144821A JPH05144821A JP3098724A JP9872491A JPH05144821A JP H05144821 A JPH05144821 A JP H05144821A JP 3098724 A JP3098724 A JP 3098724A JP 9872491 A JP9872491 A JP 9872491A JP H05144821 A JPH05144821 A JP H05144821A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- electrode
- substrate
- solder
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】［発明の目的］[Object of the Invention]
【０００２】[0002]
【産業上の利用分野】この発明はフリップチップ法によ
り半導体回路素子を基板に実装する半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor circuit element mounted on a substrate by a flip chip method.
【０００３】[0003]
【従来の技術】近年電子機器の小型、軽量、薄型化にと
もない集積回路化した半導体素子の実装も薄型で高密度
のもが要求されて来ている。これらの半導体素子を実装
する技術としてはワイヤボンディング、フィルムキャリ
ア（ＴＡＢ）、フリップチップ等が実用化されている。
中でも半導体のチップに直接バンプを固着し、この面を
プリント基板を対向させた格好とバンプと基板とを半田
付けするフリップチップは接続用リードを介さずに住む
ため、他の手段では不可能な高密度の多端子化が可能と
なる。2. Description of the Related Art In recent years, as electronic equipment has become smaller, lighter and thinner, it has been required to mount semiconductor elements integrated into an integrated circuit to be thin and have high density. Wire bonding, film carrier (TAB), flip chip and the like have been put into practical use as a technique for mounting these semiconductor elements.
Among them, a bump is directly fixed to a semiconductor chip, and a flip chip that solders the bump and the substrate with this surface facing the printed circuit board lives without connecting leads, so it cannot be done by other means. High-density multiple terminals are possible.
【０００４】図２は従来のフリップチップ法による半導
体素子の実装を説明するものである。 図２（ａ）にお
いて、半導体素子２１上に接続用のアルミニウム電極２
２とガラスによるパッシペーション膜２３を一体形成す
る。次に図２（ｂ）に示すように、アルミニウム電極２
２上に金ワイヤ２４を用いたボールボンディング法によ
り、電極にワイヤを付着しバンプ２５ａ形成する第１ボ
ンディングを行う。続いて図２（ｃ）に示すようにバン
プ２５ａ上にさらにバンプ２５ｂからワイヤを切り離し
高さも揃えた第２ボンディングを行うことによって図２
（ｄ），（ｅ）に示すように金バンプ２５を形成する。
次に図２（ｆ）に示すようにアルミナ等の基板２６上に
銅厚膜等の配線パターン２７を形成し、半導体素子２１
との接続部に半田ペースト層２８をスクリーン印刷法等
により形成する。図２（ｇ）に示すように基板２６上に
半導体素子２１をマウントし、図２（ｈ）に示すように
リフロー半田付により両者の接続を行う。FIG. 2 illustrates mounting of a semiconductor element by a conventional flip chip method. In FIG. 2A, the aluminum electrode 2 for connection is provided on the semiconductor element 21.
2 and the passivation film 23 made of glass are integrally formed. Next, as shown in FIG. 2B, the aluminum electrode 2
The first bonding is performed by attaching the wire to the electrode and forming the bump 25a by the ball bonding method using the gold wire 24 on the second electrode. Then, as shown in FIG. 2C, a wire is further cut off from the bump 25b and second bonding is performed on the bump 25a so that the height of the bump 25a is uniform.
Gold bumps 25 are formed as shown in (d) and (e).
Next, as shown in FIG. 2F, a wiring pattern 27 such as a copper thick film is formed on a substrate 26 such as alumina, and the semiconductor element 21
A solder paste layer 28 is formed on the connection portion with and by a screen printing method or the like. The semiconductor element 21 is mounted on the substrate 26 as shown in FIG. 2 (g), and both are connected by reflow soldering as shown in FIG. 2 (h).
【０００５】しかしながら、金バンプ２５がリフロー半
田付時に半田ぐわれを起こし、接続不良が生じるという
問題があった。However, there is a problem in that the gold bumps 25 are soldered during reflow soldering, resulting in poor connection.
【０００６】[0006]
【発明が解決しようとする課題】従来のフリップチップ
法においては、金バンプの半田ぐわれに起因した接続不
良が生じる問題があった。In the conventional flip chip method, there is a problem in that a connection failure may occur due to solder bumping of gold bumps.
【０００７】この発明は上記問題点を解決するために、
半田ぐわれの少ないバンプ構造とした半導体取付け装置
を提供するものである。In order to solve the above problems, the present invention provides
Provided is a semiconductor mounting device having a bump structure with less solder leakage.
【０００８】［発明の構成］[Structure of Invention]
【０００９】[0009]
【課題を解決するための手段】この発明は半導体基板の
一主面に形成したアルミニウム電極および上記半導体基
板の上に設けるとともに上記アルミニウム電極に接続す
るバンプを備え、上記バンプを耐半田性の高い金属材料
で覆ったものである。The present invention has an aluminum electrode formed on one main surface of a semiconductor substrate and a bump provided on the semiconductor substrate and connected to the aluminum electrode, and the bump has high solder resistance. It is covered with a metallic material.
【００１０】[0010]
【作用】上記した手段により耐半田性の高い金属材料は
金バンプの半田ぐわれを押え、狭ピッチでオープンやシ
ョートのない信頼性の高い接続が可能となる。With the above-mentioned means, the metal material having high soldering resistance suppresses the solder gap of the gold bumps, and enables highly reliable connection at a narrow pitch with no open or short circuit.
【００１１】[0011]
【実施例】以下、この発明の実施例につき図面を参照し
て詳細に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.
【００１２】図１はこの発明の一実施例を示すものであ
る。図１（ａ）において、半導体素子１０のシリコン基
板上に接続用のアルミニウム電極１１をガラスのパッシ
ベーション膜１２を一体形成する。次に図１（ｂ）に示
すようにアルミニウム電極１１上に金ワイヤ１３を用い
たボールボンディング法により、電極にワイヤを付着
し、バンプ１４ａ形成する第１ボンディングを行う。続
いて図１（ｃ）に示すように第１ボンディング上にさら
にバンプ１４ｂを形成するとともにバンプ１４ｂから金
ワイヤ１３を切り離し高さも揃えた第２ボンディングを
行うことによって、図１（ｄ），（ｅ）に示すバンプ１
５を形成する。FIG. 1 shows an embodiment of the present invention. In FIG. 1A, an aluminum electrode 11 for connection and a glass passivation film 12 are integrally formed on a silicon substrate of a semiconductor element 10. Next, as shown in FIG. 1B, a wire is attached to the aluminum electrode 11 by the ball bonding method using the gold wire 13, and the first bonding is performed to form the bump 14a. Subsequently, as shown in FIG. 1C, a bump 14b is further formed on the first bonding, and the gold wire 13 is separated from the bump 14b to perform second bonding with a uniform height. bump 1 shown in e)
5 is formed.
【００１３】次に図１（ｆ）に示すように無電界メッキ
によりバンプ１５を完全に覆うようにニッケル、パラジ
ウム等のメッキ層１６を形成する。図１（ｇ）におい
て、アルミナ等の基板１７上に銅厚膜等により配線パタ
ーン１８を形成する。そして半導体素子１０との接続部
に半田ペースト層１９をスクリーン印刷法により形成す
る。図１（ｈ）において、半導体素子１０を基板１７上
にマウントし、図１（ｉ）に示すようにリフロー半田付
けにより両者の接続を行う。Next, as shown in FIG. 1 (f), a plating layer 16 of nickel, palladium or the like is formed by electroless plating so as to completely cover the bumps 15. In FIG. 1G, a wiring pattern 18 is formed of a thick copper film or the like on a substrate 17 made of alumina or the like. Then, the solder paste layer 19 is formed on the connection portion with the semiconductor element 10 by the screen printing method. In FIG. 1 (h), the semiconductor element 10 is mounted on the substrate 17, and both are connected by reflow soldering as shown in FIG. 1 (i).
【００１４】バリアとなるメッキ層１６はバンプ１５を
半田のくわれから防ぐことができ、オープン、ショート
のない信頼性の高い接続を可能とすることができる。The plating layer 16 serving as a barrier can prevent the bumps 15 from being damaged by solder, and can realize highly reliable connection without open or short circuits.
【００１５】[0015]
【発明の効果】以上記載したようにこの発明の半導体装
置によれば、フリップチップ接続におけるバンプの半田
ぐわれを防止することができ、オープン、ショートのな
い信頼性の高い接続を行なうことができる。As described above, according to the semiconductor device of the present invention, bump soldering can be prevented in flip-chip connection, and a highly reliable connection without open or short can be made. .
【図１】この発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】従来の断面図である。FIG. 2 is a conventional cross-sectional view.
１２………アルミニウム電極 １５………バンプ １６………メッキ層 12 ... Aluminum electrode 15 Bump 16 Plating layer
Claims (3)
ム電極を、上記半導体基板の上に設けるとともに上記ア
ルミニウム電極に接続したバンプと、 上記半導体基板の上に設けるとともに上記アルミニウム
電極に接続したバンプと、 上記バンプを耐半田性の高い金属材料が覆う手段とから
なることを特徴とすることを特徴とする半導体装置。1. A bump having an aluminum electrode formed on one surface of a semiconductor substrate and provided on the semiconductor substrate and connected to the aluminum electrode; and a bump provided on the semiconductor substrate and connected to the aluminum electrode. A semiconductor device, comprising: a means for covering the bump with a metal material having high solder resistance.
形成する第１の工程と、 上記半導体基板上及び上記アルミニウム電極にバンプを
接続する第２の工程と、上記バンプを耐半田性の高い金
属材料で覆う第３の工程とからなることを特徴とする半
導体装置。2. A first step of forming an aluminum electrode on one surface of a semiconductor substrate, a second step of connecting a bump to the semiconductor substrate and to the aluminum electrode, and a metal material having high solder resistance to the bump. And a third step of covering with a semiconductor device.
ニッケル、パラジウム等のメッキ層であることを特徴と
する請求項１または２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the metal material having a high solder resistance for covering the bumps is a plated layer of nickel, palladium or the like.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3098724A JPH05144821A (en) | 1991-04-30 | 1991-04-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3098724A JPH05144821A (en) | 1991-04-30 | 1991-04-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05144821A true JPH05144821A (en) | 1993-06-11 |
Family
ID=14227471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3098724A Withdrawn JPH05144821A (en) | 1991-04-30 | 1991-04-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05144821A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6103551A (en) * | 1996-03-06 | 2000-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit and method for manufacturing the same |
| US6452280B1 (en) | 1996-03-06 | 2002-09-17 | Matsushita Electric Industrial Co., Ltd. | Flip chip semiconductor apparatus with projecting electrodes and method for producing same |
| SG96200A1 (en) * | 2000-02-18 | 2003-05-23 | Hitachi Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
| US7969004B2 (en) | 2007-10-05 | 2011-06-28 | Sharp Kabushiki Kaisha | Semiconductor device, method for mounting semiconductor device, and mounting structure of semiconductor device |
| CN106298557A (en) * | 2015-05-22 | 2017-01-04 | 中国科学院苏州纳米技术与纳米仿生研究所 | A kind of low-temperature bonding method based on Au/In isothermal solidification |
-
1991
- 1991-04-30 JP JP3098724A patent/JPH05144821A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6103551A (en) * | 1996-03-06 | 2000-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit and method for manufacturing the same |
| US6452280B1 (en) | 1996-03-06 | 2002-09-17 | Matsushita Electric Industrial Co., Ltd. | Flip chip semiconductor apparatus with projecting electrodes and method for producing same |
| SG96200A1 (en) * | 2000-02-18 | 2003-05-23 | Hitachi Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
| US7969004B2 (en) | 2007-10-05 | 2011-06-28 | Sharp Kabushiki Kaisha | Semiconductor device, method for mounting semiconductor device, and mounting structure of semiconductor device |
| CN106298557A (en) * | 2015-05-22 | 2017-01-04 | 中国科学院苏州纳米技术与纳米仿生研究所 | A kind of low-temperature bonding method based on Au/In isothermal solidification |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980711 |