JP3006957B2 - Semiconductor device package - Google Patents
Semiconductor device packageInfo
- Publication number
- JP3006957B2 JP3006957B2 JP4119341A JP11934192A JP3006957B2 JP 3006957 B2 JP3006957 B2 JP 3006957B2 JP 4119341 A JP4119341 A JP 4119341A JP 11934192 A JP11934192 A JP 11934192A JP 3006957 B2 JP3006957 B2 JP 3006957B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electrode
- circuit board
- bisn
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置を回路基板
に実装した半導体装置の実装体に関するものであり、特
にフェースダウンで実装される半導体装置の実装体に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounted with a semiconductor device mounted on a circuit board, and more particularly to a semiconductor device mounted face-down.
【０００２】[0002]
【従来の技術】従来、半導体装置を回路基板上へ実装す
るには半田付けが利用されることが多かったが、近年、
半導体装置のパッケージが小型化し、かつ接続端子数が
増加したことにより、接続端子間隔が狭くなり、従来の
半田付け技術で対処することは次第に困難になってき
た。2. Description of the Related Art Conventionally, soldering has often been used to mount a semiconductor device on a circuit board.
As the package of the semiconductor device has become smaller and the number of connection terminals has increased, the interval between the connection terminals has become narrower, and it has become increasingly difficult to deal with the conventional soldering technology.
【０００３】そこで最近では、半導体装置を回路基板上
に直付けして実装面積を小型化し、回路基板の効率的使
用を図ろうとする方法が考案されている。なかでも、半
導体装置を回路基板に接続するに際し、アルミ電極パッ
ド上にあらかじめ密着金属や拡散防止金属の蒸着膜を形
成し、さらにその上にメッキにより半田層を形成してな
る電極構造を有する半導体装置を製造し、この半導体装
置を回路基板に下向き（フェースダウン）に積載して高
温に加熱することにより半田と回路基板の端子電極とを
融着させてなる実装構造が、接続後の機械的強度が強
く、一括して接続できることなどから有効な方法である
とされている（たとえば、工業調査会、１９８０年１月
１５日発行、日本マイクロエレクトロニクス協会編、
『ＩＣ化実装技術』）。Therefore, recently, a method has been devised in which a semiconductor device is directly mounted on a circuit board to reduce the mounting area, and the circuit board is used efficiently. Above all, when connecting a semiconductor device to a circuit board, a semiconductor having an electrode structure in which a vapor deposition film of an adhesion metal or a diffusion preventing metal is previously formed on an aluminum electrode pad, and a solder layer is formed thereon by plating. After the device is manufactured, the semiconductor device is mounted on the circuit board downward (face down) and heated to a high temperature so that the solder and the terminal electrodes of the circuit board are fused to form a mounting structure. It is considered to be an effective method because it is strong and can be connected collectively (for example, the Industrial Research Council, published on January 15, 1980, edited by the Japan Microelectronics Association,
"IC mounting technology").
【０００４】以下に図面を参照しながら、従来の半導体
装置用電極とその実装体の一例について説明する。図３
は従来の半田バンプ電極を有する半導体装置用電極を示
す概略説明図であり、図４は上記半導体装置の実装体を
示す概略説明図である。Hereinafter, an example of a conventional semiconductor device electrode and its mounting body will be described with reference to the drawings. FIG.
FIG. 4 is a schematic explanatory view showing a conventional semiconductor device electrode having solder bump electrodes, and FIG. 4 is a schematic explanatory view showing a mounted body of the semiconductor device.
【０００５】図３において、８は半導体装置のＩＣ基板
であり、９はアルミ電極パッドである。１０は密着金属
膜であり、１１は拡散防止金属膜である。１２は半田突
起であり、１３はパッシベーション膜である。図４にお
いて、１４は回路基板であり、１５は端子電極である。In FIG. 3, reference numeral 8 denotes an IC substrate of a semiconductor device, and reference numeral 9 denotes an aluminum electrode pad. Reference numeral 10 denotes an adhesion metal film, and reference numeral 11 denotes a diffusion prevention metal film. Reference numeral 12 denotes a solder protrusion, and reference numeral 13 denotes a passivation film. In FIG. 4, 14 is a circuit board, and 15 is a terminal electrode.
【０００６】以上のように構成された従来の半田バンプ
電極を有する半導体装置用電極とその実装体について、
以下にその製造方法の概略を説明する。まず、半導体装
置のＩＣ基板８のアルミ電極パッド９上にＣｕなどの密
着金属膜１０およびＣｒなどの拡散防止金属膜１１を蒸
気により形成する。その後、電極部以外をフォトレジス
ト１３で覆い、メッキ法により拡散防止金属膜１１上に
半田を析出させる。次に半田リフローを行うことによっ
て、半田突起１２を形成し、図３の半田バンプ電極を得
る。A conventional semiconductor device electrode having a solder bump electrode configured as described above and a package thereof are described below.
The outline of the manufacturing method will be described below. First, an adhesion metal film 10 such as Cu and a diffusion prevention metal film 11 such as Cr are formed on an aluminum electrode pad 9 of an IC substrate 8 of a semiconductor device by vapor. Thereafter, the portions other than the electrode portions are covered with a photoresist 13 and solder is deposited on the diffusion preventing metal film 11 by a plating method. Next, solder protrusions 12 are formed by performing solder reflow, and the solder bump electrodes of FIG. 3 are obtained.
【０００７】さらに、上記のようにして得た半田バンプ
電極を有する半導体装置を、回路基板１４の所定の位置
に位置合わせを行ってフェースダウンで積載した後、２
００〜３００℃の高温に加熱し半田突起１２を溶融して
端子電極１５に融着させることにより半導体装置の実装
を行う。Further, the semiconductor device having the solder bump electrodes obtained as described above is aligned face-to-face at a predetermined position on the circuit board 14 and mounted face-down.
The semiconductor device is mounted by heating to a high temperature of 00 to 300 ° C. to melt the solder protrusions 12 and fuse them to the terminal electrodes 15.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら上記のよ
うな半田バンプ電極を有する半導体装置用電極やその実
装体は、１．半導体装置のアルミ電極パッド上に密着金
属膜や拡散防止金属膜が必要であるため電極構造が複雑
となり、汎用性に欠ける、２．半田を溶融する際に高温
に加熱する必要があり、熱応力の影響を受ける、３．高
温に加熱し半田を溶融して端子電極と接続する際に、Ｉ
Ｃ基板と回路基板とのギャップを維持することが出来
ず、そのため半田が広がって隣接部とショートする危険
性がある、４．熱膨張率の異なるＩＣ基板と回路基板と
を半田で接続しているため、熱応力に対して脆い、など
といった課題を有していた。However, an electrode for a semiconductor device having a solder bump electrode as described above and a packaged body thereof are: 1. Since an adhesion metal film or a diffusion prevention metal film is required on an aluminum electrode pad of a semiconductor device, the electrode structure becomes complicated and lacks versatility. 2. The solder must be heated to a high temperature when it is melted, and is affected by thermal stress. When heated to a high temperature to melt the solder and connect it to the terminal electrode,
3. The gap between the C board and the circuit board cannot be maintained, so that there is a risk that the solder spreads and short-circuits with the adjacent part. Since an IC substrate having a different coefficient of thermal expansion and a circuit substrate are connected by solder, they have a problem that they are brittle against thermal stress.
【０００９】本発明は上記の課題に鑑みてなされたもの
であり、その目的とするところは、半導体装置と回路基
板とが信頼性高く接続された半導体装置の実装体を提供
することにある。[0009] The present invention has been made in view of the above problems, and an object is to the semiconductor device and the circuit board to provide a mount assembly for reliably connected semiconductor device.
【００１０】[0010]
【課題を解決するための手段】本発明は上記の課題を解
決するため、半導体装置用電極がフェースダウンで回路
基板に実装された半導体装置の実装体であって、半導体
装置の電極パッド部上の２段突起状バンプ電極が、有機
接着剤中の導電フィラーとして少なくともＢｉＳｎを含
む導電性接着剤からなる接合層を介して回路基板上端子
電極に電気的に接続されていることを特徴とする半導体
装置の実装体を提供する。According to the present invention, there is provided a semiconductor device comprising:
A package of a semiconductor device mounted on a substrate, the
The two-stage protruding bump electrode on the electrode pad of the device is
At least BiSn is contained as a conductive filler in the adhesive.
Terminal on the circuit board via a bonding layer made of conductive adhesive
A semiconductor which is electrically connected to an electrode
Provide an implementation of the device .
【００１１】[0011]
【００１２】２段突起状のバンプ電極は、Ａｕ等の金属
を用い、ワイヤボンディング等の方法により形成するこ
とができる。回路基板上の端子電極にはＣｕを使用する
ことができる。また、ＢｉＳｎの導電フィラーを含む導
電性接着剤は少なくともＢｉＳｎの導電フィラーを含ん
でおればよい。The bump electrode having a two-step projection can be formed by a method such as wire bonding using a metal such as Au. Cu can be used for the terminal electrode on the circuit board. In addition, the conductive adhesive containing the BiSn conductive filler only needs to contain at least the BiSn conductive filler.
【００１３】[0013]
【作用】本発明は、半導体装置の電極パッド部上に直
接、２段突起状バンプ電極よりなり頂上部にのみ少なく
ともＢｉＳｎ導電フィラーを含む導電性接着剤からなる
接合層が形成された電極を構成することにより、半導体
装置を回路基板の端子電極に接合する際に接合層が隣接
部とショートすることなく微細ピッチで接合可能とな
る。しかも回路基板のＣｕ端子電極に直接接合すること
ができるため、信頼性の高い半導体装置の実装体を得る
ことができる。According to the present invention, there is provided an electrode in which a bonding layer made of a conductive adhesive containing at least a BiSn conductive filler is formed directly on a top of an electrode pad portion of a semiconductor device and composed of a two-stage projecting bump electrode only at the top. Accordingly, when the semiconductor device is joined to the terminal electrode of the circuit board, the joining layer can be joined at a fine pitch without short-circuiting with the adjacent portion. Moreover, since the semiconductor device can be directly bonded to the Cu terminal electrode of the circuit board, a highly reliable semiconductor device package can be obtained.
【００１４】[0014]
【実施例】以下、本発明の一実施例の半導体装置の実装
体について、図面を参照しながら説明する。EXAMPLES Hereinafter, the implementation of a semiconductor device of an embodiment of the present invention will be described with reference to the drawings.
【００１５】図１は、本発明の一実施例における半導体
装置用電極を示す概略説明図であり、図２は、上記実施
例の電極を有する半導体装置の実装体を示す概略説明図
である。FIG. 1 is a schematic explanatory view showing an electrode for a semiconductor device according to one embodiment of the present invention, and FIG. 2 is a schematic explanatory view showing a mounted body of the semiconductor device having the electrode of the above embodiment.
【００１６】図１において、１は半導体装置のＩＣ基板
であり、２はアルミ電極パッドである。３は台座部３ａ
と頂上部３ｂからなる２段突起状バンプ電極であり、４
は２段突起状バンプ電極３の頂上部３ｂにのみ形成され
たＢｉＳｎの導電フィラーを含む導電性接着剤からなる
接合層である。５はパッシベーション膜である。図２に
おいて、６は回路基板であり、７はＣｕからなる端子電
極である。In FIG. 1, reference numeral 1 denotes an IC substrate of a semiconductor device, and reference numeral 2 denotes an aluminum electrode pad. 3 is a pedestal 3a
And a two-step protruding bump electrode composed of
Is a bonding layer made of a conductive adhesive containing a BiSn conductive filler formed only on the top 3b of the two-step protruding bump electrode 3. 5 is a passivation film. In FIG. 2, 6 is a circuit board, and 7 is a terminal electrode made of Cu.
【００１７】以上のように構成された半導体装置用電極
とその実装体とを製造するときには、まず、半導体装置
のＩＣ基板１のアルミ電極パッド２上に通常のワイヤボ
ンディング技術によってＡｕワイヤの先端のＡｕボール
を固着し、その後Ａｕワイヤを切断することにより、台
座部３ａと頂上部３ｂとを有する２段突起状バンプ電極
３を形成する。When manufacturing the semiconductor device electrode and its mounting body configured as described above, first, the tip of the Au wire is formed on the aluminum electrode pad 2 of the IC substrate 1 of the semiconductor device by a normal wire bonding technique. By fixing the Au ball and then cutting the Au wire, the two-step protruding bump electrode 3 having the pedestal portion 3a and the top 3b is formed.
【００１８】次に、２段突起状バンプ電極３の頂上部に
のみ、ＢｉＳｎ導電フィラーを含む導電性接着剤からな
る接合層４を転写法や印刷法によって形成する。上記に
より、汎用の半導体装置のアルミ電極パッド２上に、２
段突起状バンプ電極３よりなり、頂上部にのみＢｉＳｎ
導電フィラーを含む導電性接着剤からなる接合層４が形
成された半導体装置用電極が容易に得られる。Next, a bonding layer 4 made of a conductive adhesive containing a BiSn conductive filler is formed only on the tops of the two-step protruding bump electrodes 3 by a transfer method or a printing method. As described above, the aluminum electrode pad 2 of the general-purpose semiconductor device
It consists of a step-shaped bump electrode 3 and BiSn only on the top.
An electrode for a semiconductor device on which the bonding layer 4 made of a conductive adhesive containing a conductive filler is formed can be easily obtained.
【００１９】本発明に係る半導体装置用電極は、上記の
ように通常のワイヤボンディング装置によって２段突起
形状のバンプ電極を得ることが出来るため、通常のアル
ミ電極パッドを有する汎用の半導体装置を用いることが
可能となり、極めて汎用性が高い。In the semiconductor device electrode according to the present invention , a bump electrode having a two-step projection can be obtained by a normal wire bonding apparatus as described above. Therefore, a general-purpose semiconductor device having a normal aluminum electrode pad is used. This makes it extremely versatile.
【００２０】さらに、以上のようにして得た電極を有す
る半導体装置を、回路基板６の所定の位置に位置合わせ
を行ってフェースダウンで積載した後、１５０℃以上に
加熱しＢｉＳｎ導電フィラーを含む導電性接着剤からな
る接合層４を硬化させて２段突起状バンプ電極３をＣｕ
からなる端子電極７に接着させる。かつ、これと同時
に、ＢｉＳｎ導電フィラーを含む導電性接着剤からなる
接合層４とＣｕからなる端子電極７との接着界面におい
て導電性接着剤中のＢｉＳｎを端子電極のＣｕに拡散結
合させることによって、半導体装置の実装体を得る。Further, after the semiconductor device having the electrodes obtained as described above is positioned at a predetermined position on the circuit board 6 and mounted face down, the semiconductor device is heated to 150 ° C. or more and contains the BiSn conductive filler. The bonding layer 4 made of a conductive adhesive is cured to form the two-step bump electrode 3 with Cu.
Is adhered to the terminal electrode 7 made of. At the same time, BiSn in the conductive adhesive is diffused and bonded to Cu of the terminal electrode at the bonding interface between the bonding layer 4 made of the conductive adhesive containing the BiSn conductive filler and the terminal electrode 7 made of Cu. To obtain a semiconductor device package.
【００２１】この半導体装置用電極を回路基板６の端子
電極７に接続する際に、２段突起状バンプ電極３により
ＩＣ基板１と回路基板６とのギャップを維持することが
でき、かつ、頂上部にのみＢｉＳｎ導電フィラーを含む
導電性接着剤からなる層４が形成されている。このた
め、導電性接着剤の拡がりを規制することが可能とな
り、隣接部とショートする危険性のない、微細ピッチで
接続可能な半導体装置の実装体が得られる。When this semiconductor device electrode is connected to the terminal electrode 7 of the circuit board 6, the gap between the IC board 1 and the circuit board 6 can be maintained by the two-step projecting bump electrode 3, and A layer 4 made of a conductive adhesive containing a BiSn conductive filler is formed only in the portion. For this reason, it is possible to regulate the spread of the conductive adhesive, and it is possible to obtain a semiconductor device package that can be connected at a fine pitch without risk of short-circuiting to an adjacent portion.
【００２２】本発明の半導体装置の実装体によれば、本
発明の２段突起状バンプ電極を用いることにより従来の
半田バンプ電極による実装体では不可能であった半田の
拡がりの規制が可能となり、極めて安定で信頼性が高
く、かつ、高密度に半導体装置を実装することができ
る。According to the semiconductor device package of the present invention, by using the two-step projection bump electrode of the present invention, it is possible to regulate the spread of solder, which was impossible with a conventional package using solder bump electrodes. The semiconductor device can be mounted with extremely high reliability and high density.
【００２３】なお、本実施例では２段突起状バンプ電極
をワイヤボンディング装置を用いて形成するとしたが、
その形状が２段突起状であればメッキなど他の方法で形
成してもよい。In this embodiment, the two-stage projecting bump electrodes are formed by using a wire bonding apparatus.
If the shape is a two-step projection, it may be formed by other methods such as plating.
【００２４】また、バンプ電極をＡｕからなるものとし
たが、その材質はＡｕに限られる物でなく、例えば、Ｃ
ｕなどの金属から形成してもよい。さらに、ＢｉＳｎの
導電フィラーを含む導電性接着剤は少なくとも、ＢｉＳ
ｎの導電フィラーを含んでいればよく、例えばＡｇの導
電フィラーとの混合系でもよい。Although the bump electrode is made of Au, the material is not limited to Au.
It may be formed from a metal such as u. Further, the conductive adhesive containing the conductive filler of BiSn is at least BiSn.
It is sufficient that the conductive filler contains n conductive fillers. For example, a mixed system with Ag conductive fillers may be used.
【００２５】[0025]
【発明の効果】以上に説明したように、本発明の半導体
装置の実装体によれば、通常のワイヤボンディング装置
により半導体装置の電極パッド部上に直接バンプ電極を
形成することができるため、汎用の半導体装置を用いる
ことが可能となり、極めて汎用性が高い。As described above, according to the present invention, according to the implementation of the semiconductor device of the present invention, it is possible to form directly bump electrodes on the electrode pads of the semiconductor device by conventional wire bonding apparatus, a general-purpose Semiconductor device can be used, and the versatility is extremely high.
【００２６】さらに、２段突起形状のバンプ電極の頂上
部にのみ導電性接着剤からなる接合層が形成された電極
を有することにより、半導体装置を回路基板の端子電極
に接合する際に導電性接着剤の拡がりも規制することが
可能となり、導電性接着剤が隣接部とショートすること
のない、微細ピッチで接合可能な実装体となり、極めて
安定で信頼性が高くなる。かつ、高密度に半導体装置を
実装することができる。Further, by providing an electrode on which a bonding layer made of a conductive adhesive is formed only on the top of the bump electrode having a two-step projection, the semiconductor device can be electrically connected to a terminal electrode of a circuit board. It is also possible to regulate the spread of the adhesive, so that the conductive adhesive can be bonded at a fine pitch without short-circuiting to the adjacent portion, and is extremely stable and highly reliable. In addition, a semiconductor device can be mounted with high density.
【００２７】また、ＢｉＳｎ導電フィラーを含む導電性
接着剤を用いるため、導電性接着剤と端子電極の接着界
面において導電性接着剤中のＢｉＳｎと端子電極のＣｕ
とを拡散接合させることができ、半導体装置が回路基板
のＣｕ端子電極に直接接合された実装体を得ることがで
きる。Further, since a conductive adhesive containing a BiSn conductive filler is used, BiSn in the conductive adhesive and Cu of the terminal electrode at the bonding interface between the conductive adhesive and the terminal electrode are used.
Can be bonded by diffusion, and a mounted body in which the semiconductor device is directly bonded to the Cu terminal electrode of the circuit board can be obtained.
【図１】本発明の一実施例における半導体装置用電極を
示す概略説明図である。FIG. 1 is a schematic explanatory view showing an electrode for a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施例の電極を有する半導体装置の
実装体を示す概略説明図である。FIG. 2 is a schematic explanatory view showing a package of a semiconductor device having electrodes according to one embodiment of the present invention.
【図３】従来の半田バンプ電極を有する半導体装置用電
極を示す概略説明図である。FIG. 3 is a schematic explanatory view showing a conventional semiconductor device electrode having solder bump electrodes.
【図４】従来の半田バンプ電極を有する半導体装置の実
装体を示す概略説明図である。FIG. 4 is a schematic explanatory view showing a conventional mounting body of a semiconductor device having solder bump electrodes.
２ 電極パッド ３ バンプ電極 ４ 導電性接着剤層 ６ 回路基板 ７ 端子電極 2 electrode pad 3 bump electrode 4 conductive adhesive layer 6 circuit board 7 terminal electrode
Claims (3)
路基板に実装された半導体装置の実装体であって、半導
体装置の電極パッド部上の２段突起状バンプ電極が少な
くともＢｉＳｎ導電フィラーを含む導電性接着剤からな
る接合層を介して回路基板上端子電極に電気的に接続さ
れていることを特徴とする半導体装置の実装体。1. A semiconductor device mounting body in which a semiconductor device electrode is mounted face down on a circuit board, wherein a two-stage projecting bump electrode on an electrode pad portion of the semiconductor device includes a conductive material containing at least a BiSn conductive filler. A package of a semiconductor device, which is electrically connected to a terminal electrode on a circuit board via a bonding layer made of a conductive adhesive.
とを特徴とする請求項１記載の半導体装置の実装体。2. The semiconductor device package according to claim 1 , wherein the two-stage projecting bump electrode is made of Au.
とを特徴とする請求項１記載の半導体装置の実装体。3. The semiconductor device according to claim 1 , wherein the terminal electrode on the circuit board is made of Cu.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4119341A JP3006957B2 (en) | 1992-05-13 | 1992-05-13 | Semiconductor device package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4119341A JP3006957B2 (en) | 1992-05-13 | 1992-05-13 | Semiconductor device package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05315337A JPH05315337A (en) | 1993-11-26 |
| JP3006957B2 true JP3006957B2 (en) | 2000-02-07 |
Family
ID=14759091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4119341A Expired - Fee Related JP3006957B2 (en) | 1992-05-13 | 1992-05-13 | Semiconductor device package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3006957B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69626747T2 (en) | 1995-11-16 | 2003-09-04 | Matsushita Electric Industrial Co., Ltd. | Printed circuit board and its arrangement |
| JP3065549B2 (en) | 1997-01-09 | 2000-07-17 | 富士通株式会社 | Semiconductor chip component mounting method |
| KR101156183B1 (en) * | 2010-11-02 | 2012-06-18 | 한국생산기술연구원 | Direct Bonding Method of Bump and Semiconductor Package Using the Same |
-
1992
- 1992-05-13 JP JP4119341A patent/JP3006957B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05315337A (en) | 1993-11-26 |
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