JP7412735B2 - Manufacturing method for semiconductor packages - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor package , and in particular to a method for manufacturing a semiconductor package, in which fine wiring with a large aspect ratio (wiring height ÷ wiring width) is formed, and package warpage is reduced by combining with a metal plate . Regarding the manufacturing method.

BACKGROUND OF THE INVENTION In recent years, with the demand for higher functionality and smaller, lighter, thinner and smaller electronic devices, electronic components are becoming more densely integrated and more densely packaged. Semiconductor packages used in these electronic devices are becoming smaller and have more pins (multiple terminals), and mounting boards on which electronic components including semiconductor packages are mounted are also becoming smaller and thinner.

As semiconductor packages become smaller, conventional packages using lead frames cannot meet the requirements, so recently BGA (Ball Grid Array) and , CSP (Chip Scale Package) and other new area-mounted packaging systems have been proposed.

In addition, in these semiconductor packages, the electrical connection between the terminals of a substrate made of various materials such as plastic and ceramics called the semiconductor package substrate, which functions as the lead frame of conventional semiconductor packages, and the electrodes of the semiconductor chip is Known connection methods include a wire bonding method, a TAB (Tape Automated Bonding) method, and an FC (Flip Chip) method. Recently, many proposals have been made for BGA and CSP structures using the FC connection method, which is advantageous for downsizing semiconductor packages. Along with this, substrates (circuit boards) used in semiconductor packages are required to have higher density and higher reliability.

Further, recently, as a thin semiconductor package to be mounted on a smartphone or the like, ultra-thin packages such as those shown in Patent Document 1, for example, have been developed. This semiconductor package uses a built-up structure to form a fine circuit.

By the way, as described in Patent Document 2, for example, pattern transfer techniques in the circuit board manufacturing technique include a subtractive method, an additive method, and a semi-additive method.
In the subtractive method, a photosensitive corrosion-resistant material is generally employed to complete the pattern transfer, and the material protects areas that do not need to be removed by etching, followed by acidic or alkaline etching agents. The copper layer in unprotected areas is removed. However, if the etching method is performed with the copper layer exposed, side etching is likely to occur, which limits the application of the subtractive method to manufacturing fine circuit lines. Therefore, it is difficult to apply it to products that are lightweight, thin, and compact.

In the additive method, a non-resistant plating pattern is formed on a photosensitive resin plate by exposure, and the non-resistant plating pattern is further plated on a chemical copper layer to form a circuit line pattern. That is, an electroless plating layer is formed as a seed layer on a photosensitive resin plate, and a pattern is formed by exposure.

Then, the copper circuit line (circuit pattern) formed using the substructive method (copper film etching method) had a line and space (width of wiring and distance between wirings) of about 50 μm/50 μm. When this additive method is used, the wiring width and the interval between wirings can be made fine to 20 μm/20 μm. Moreover, since the copper film of the copper circuit line (circuit pattern) formed by the additive method is thick, the amount of allowable current flowing through the package can also be increased.

On the other hand, the substructive manufacturing method that only etches the copper film cannot form fine circuit patterns or circuit patterns with a large aspect ratio (wiring height ÷ wiring width).
However, the copper film to be etched is electrolytic copper, and the surface of this electrolytic copper exhibits a dendritic surface, and these dendritic fine irregularities are formed by penetrating into the insulating resin film. Therefore, the adhesion strength between the copper film and the insulating resin film can be increased. Currently, commonly produced circuit boards and semiconductor packages are manufactured using this subtractive manufacturing method.

In the semi-additive method, a chemical copper layer is formed on a substrate, and then a photosensitive corrosion-resistant thin film is formed on this chemical copper layer. Then, a corrosion-resistant pattern is formed on the photosensitive corrosion-resistant thin film. Furthermore, an electroplated copper layer is formed on the corrosion-resistant pattern by electroplating. Thereafter, the photosensitive corrosion-resistant thin film is removed, and the excess chemical copper layer is further removed by an etching method.

This semi-additive method has a problem in that the bonding strength between the substrate and the chemical copper layer is poor, and the substrate and the chemical copper layer may separate under high temperatures. In addition, since both the chemical copper layer and the electroplated copper layer are the same material, there is a problem that during the etching process of the chemical copper layer, the electroplated copper layer is also etched, reducing the thickness of the electroplated copper layer. Therefore, it becomes difficult to precisely control the size of the circuit lines, making it impossible to manufacture high-quality printed circuit boards.

Special Publication No. 2018-533848 Special table 2018-11013 publication

By the way, for example, in semiconductor packages used in smartphones and the like, the current flowing through the circuit is becoming larger and larger, and there is a demand for miniaturization of the circuit pattern.

When this finer circuit pattern is formed by the additive method, the copper film can be made thicker, as described above, and the amount of allowable current flowing through the package can also be increased.
However, in this additive method, an electroless plating layer is formed as a seed layer on one surface of a resin base material (electrically insulating film), and a circuit pattern of a copper film is formed on this layer. The adhesion between the formed copper film and the resin base material (electrical insulating film) was not good, and there was a risk of peeling. Additionally, there was a technical problem in that the resin base material warped.

Furthermore, in the substructive method, as described above, the copper film to be etched is electrolytic copper, and the surface of this electrolytic copper has a dendritic shape. Therefore, fine dendritic irregularities are formed by penetrating into the film of the insulating resin base material (electrical insulating film), which increases the adhesion strength between the copper film and the resin base material (electrical insulating film). can do.
However, when this miniaturized circuit pattern is formed by a substructive method, there is a technical problem that it is impossible to form a fine circuit pattern or a circuit pattern with a large aspect ratio.

Furthermore, the semi-additive method has a technical problem in that the bonding force between the substrate and the chemical copper layer is poor, and there is a risk that the substrate and the chemical copper layer may separate at high temperatures. In addition, during the etching process of the chemical copper layer formed on the substrate, the electroplated copper layer is also etched, which reduces the thickness of the electroplated copper layer, resulting in the technical problem that circuit patterns with large aspect ratios cannot be formed. there were.

Furthermore, in the case of forming a fine circuit using a built-up structure as shown in Patent Document 1, it is impossible to expect an improvement in the aspect ratio of copper wiring, and furthermore, there are technical problems such as increased manufacturing costs. There was an issue.

In order to solve the above-mentioned technical problem, the present inventors have proposed an additive method that can form fine circuit patterns and circuit patterns with a large aspect ratio (wiring height ÷ wiring width). The present invention was completed by intensive research on improving the adhesion between the copper film (circuit pattern) on which a circuit is formed and the resin base material (electrically insulating film), and suppressing the warping of the resin base material (electrically insulating film). reached.

The present invention not only enables the formation of fine circuit patterns and circuit patterns with a large aspect ratio, but also improves the adhesion between the copper film (circuit pattern) on which the circuit is formed and the resin base material (electrical insulating film), and the resin base material. An object of the present invention is to provide a method for manufacturing a semiconductor package in which warping of the material (electrical insulating film) is suppressed.

A method for manufacturing a semiconductor package according to the present invention, which has been made to achieve the above object, includes a step of forming a circuit pattern by etching a thin copper film made of an electrolytic copper film closely adhered to both sides of an electrically insulating film. , after the step, performing a copper plating treatment, using the thin copper film as a base, and growing a copper film on the thin copper film, such that the aspect ratio of the copper film is at least 1; It is characterized by growing a copper film and forming a copper circuit pattern.

In this way, first, the circuit pattern (copper circuit pattern) is electrically insulated in order to form a circuit pattern by etching the thin copper film made of electrolytic copper film adhered to both sides of the electrically insulating film (resin base material). It can be brought into close contact with a plastic film (resin base material), and peeling of a circuit pattern (copper circuit pattern) can be suppressed. Note that the circuit pattern refers to a circuit pattern formed by etching a thin copper film made of an electrolytic copper film.

After that, copper plating treatment is performed, and a copper film is grown on the thin copper film using the thin copper film (circuit pattern) as a base, and the aspect ratio of the copper film (wiring height in the copper circuit pattern) is The copper film is grown so that the ratio (film thickness)/wiring width (copper film width) is at least 1 to form a copper circuit pattern.
As a result, the amount of allowable current flowing through the semiconductor package can also be increased.

Here, it is preferable that a perforated metal sheet is bonded to one side of the electrically insulating film, and a solder ball is soldered to the copper circuit pattern through the perforated part of the metal sheet.
In this way, since the metal sheet having the openings is adhered to one side of the electrically insulating film (resin base material), warping of the electrically insulating film (resin base material) can be suppressed.
In the semiconductor package manufactured in this way, a copper circuit pattern is formed on both sides of an electrically insulating film, and the copper circuit pattern is a copper film laminated on an electrolytic copper film by copper plating, and the copper circuit pattern is The aspect ratio of the copper film constituting the electrically insulating film is at least 1, and a metal sheet having an opening is adhered to one side of the electrically insulating film, and a solder ball is soldered onto the copper circuit pattern through the opening. It is joined.
In this way, since the aspect ratio of the copper film constituting the copper circuit pattern is at least 1, the amount of allowable current flowing through the package can also be increased. Further, the adhesion between the copper film on which the circuit pattern is formed and the electrically insulating film (resin base material) is good, and peeling can be suppressed. Furthermore, since a metal sheet having apertures is adhered to one side of the electrically insulating film (resin base material), warping of the resin base material can be suppressed.
Note that the copper circuit pattern refers to a circuit pattern in which a copper film is further laminated by copper plating treatment on a circuit pattern formed by etching a thin copper film made of an electrolytic copper film. Further, the aspect ratio refers to wiring height (copper film thickness)/wiring width (copper film width) in a copper circuit pattern.

According to the present invention, it is possible to form a fine circuit pattern or a circuit pattern with a large aspect ratio, and also to improve the adhesion between the copper film (circuit pattern) on which the circuit is formed and the electrically insulating film (resin base material). It is possible to obtain a method for manufacturing a semiconductor package in which warping of an electrically insulating film (resin base material) is suppressed.

FIG. 1 is a diagram showing steps of a method for manufacturing a semiconductor package according to the present invention. FIG. 2 is a diagram showing the steps of the method for manufacturing a semiconductor package according to the present invention following FIG. 1. FIG. 3 is a diagram showing the steps of the method for manufacturing a semiconductor package according to the present invention following FIG. 2. FIG. 4 is a diagram showing the steps of the method for manufacturing a semiconductor package according to the present invention following FIG. 3. FIG. 5 is a diagram showing the steps of the method for manufacturing a semiconductor package according to the present invention following FIG. 4. FIG. 6 is a diagram showing the steps of the method for manufacturing a semiconductor package according to the present invention following FIG. 5. FIG. 7 is a diagram showing the steps of the method for manufacturing a semiconductor package according to the present invention following FIG. 6. FIG. 8 is a diagram showing the steps of the method for manufacturing a semiconductor package according to the present invention following FIG. 7. FIG. 9 is a diagram showing the steps of the method for manufacturing a semiconductor package according to the present invention following FIG. 8. FIG. 10 is a diagram showing the steps of the method for manufacturing a semiconductor package according to the present invention following FIG. 9.

An embodiment of a method for manufacturing a semiconductor package according to the present invention will be described based on FIGS. 1 to 10. Although the present invention will be described based on embodiments, the present invention is not limited to these embodiments.

In the present invention, first, an electrically insulating film (resin base material) having an electrolytic copper film several μm thick on its surface is prepared, and a circuit pattern is formed by etching the electrolytic copper film. Electrolytic copper film is a copper film that has good adhesion to electrically insulating films. Further, by using an additive method, copper is thickly deposited on top of this to increase the aspect ratio, allowing a high current to flow and forming a fine circuit. The metal sheet to be composited is a thin plate of SUS or the like with a thickness of about 0.1 to 0.3 mm, and is bonded to the electrically insulating film on which circuit formation has been completed to suppress warpage.

Further, detailed explanation will be given based on the figures.
As shown in Fig. 1, a thin copper film 2 of 1 μm to 3 μm is formed on both sides of a polyimide film (electrical insulating film) with a thickness of about 25 μm as the basic material, and furthermore, to make it easier to handle. A dummy copper film 3 of about 20 μm thick is used.
The thin copper film 2 is made of electrolytic copper, and the surface of the copper film in contact with the surface of the polyimide film 1 has a fine dendritic shape, so the adhesion between the polyimide film 1 and the thin copper film 2 is extremely high. Peeling at the interface between the film 2 and the polyimide is difficult. Thus, it is important that the thin copper film 2 made of electrolytic copper is formed on the electrically insulating film 1.
In addition to the polyimide film, a glass epoxy resin film, a Teflon (registered trademark) resin film, a polyester film, and an LCP (liquid crystal polymer) film can be used as the electrically insulating film.

Next, as shown in FIG. 2, the dummy copper layer 3 is peeled off from the base material, and a base material having a thin copper film 2 several μm thick is formed on both sides of the polyimide film. This dummy copper film 3 can be easily peeled off. Therefore, preferably, after peeling off the copper film 3, the outer peripheral portion of the polyimide film 1 is fixed to a rigid sheet such as SUS or glass epoxy.

Furthermore, as shown in FIG. 3, the base material from which the dummy copper film 3 has been removed is subjected to a hole-opening process with a diameter of about 10 μm to 20 μm using a YAG laser. The opening 4 formed by this opening process ultimately serves as a conductive via that electrically connects the front copper pattern and the back copper pattern.

Next, as shown in FIG. 4, the thin copper film 2 having a thickness of about 1 μm to 3 μm on both sides is etched to form a fine circuit pattern 5.
This etching process can be performed using a general method, and can be performed by forming a prescribed resist film on the thin copper film 2 and immersing it in an acidic solution. In particular, since the thin copper film 2 is as thin as approximately 1 μm to 3 μm, the etching process can be easily performed, and processing with a line and space (wire width and spacing between wires) of approximately 10 μm/10 μm is possible. .

Next, as shown in FIG. 5, a dry film resist 6 with a thickness of about 20 μm to 30 μm is applied to the entire upper surface of the polyimide film 1 on which the fine circuit pattern 5 shown in FIG. to form. At this time, the thickness of the dry film resist 6 is about 20 μm to 30 μm.
Next, by exposing the dry film resist 6 to light and developing it thereafter, the dry film resist 6 only at the circuit pattern 5 in FIG. It is formed.
A circuit pattern 5 of thin film copper 2 serving as a copper-plated electrode exists under the cavity 7 .

Then, as shown in FIG. 6, a 1 μm to 3 μm thin copper film 2 is used as an electrode for copper plating, and electrolytic copper plating is performed thereon. That is, copper plating is performed using the circuit pattern 5 of the thin copper film 2 as a base, and a thick copper film (copper circuit pattern 8) is formed additively on the thin copper film 2.
The plated copper film is grown several μm from the top surface (top surface) of the dry film resist 6, and the circuit pattern 5 of the thin copper film 2 is grown in the thickness direction so that the thickness is about 20 μm to 30 μm. 8.
At this time, the copper plating progresses to the inside of the hole 4 that has been drilled with the laser, and the hole 4 disappears, and the surface copper and the back surface copper are connected metallically and electrically connected. Via) structure is formed. Note that the dry film resist 6 serves as a resist during copper plating processing.

Next, as shown in FIG. 7, the copper film protruding from the surface of the dry film resist 6 is polished together with the dry film resist 6 by a polishing process using a polishing roll or the like, so that both sides are polished to a certain thickness. A copper circuit pattern 8 having a large aspect ratio (wiring height (copper film thickness)/wiring width (copper film width) in the copper circuit pattern) is formed using a thin copper film.

Furthermore, as shown in FIG. 8, the dry film resist 6, which is a resin, is dissolved and removed using an alkaline developer to form a copper circuit pattern 8 having a uniform thickness and a large copper film thickness.
The copper circuit pattern 8 preferably has a line and space of 10/10 μm, a copper film thickness of 10 μm to 20 μm, and an aspect ratio of about 1 to 2.
Incidentally, in the conventional substructive method, this aspect ratio is limited to about 0.5. Further, in the conventional additive method, when the final copper film is removed, the copper of the circuit pattern (copper circuit pattern) is also etched, so the aspect ratio is limited to less than 1 at most.

Finally, as shown in FIG. 9, a metal sheet 10 made of SUS or the like with a thickness of 0.1 to 0.5 mm is thermocompression bonded to the copper circuit pattern 8 formed on one side of the polyimide film 1 using an adhesive 9. . It becomes the final product.
By adhering this metal sheet 10 to one side of the polyimide film 1, a structure is created in which the semiconductor package itself does not warp due to heat even if heat is applied during solder mounting.

Furthermore, as shown in FIG. 10, the metal sheet 10 is partially provided with openings 10a, and the solder balls 11 are mounted in the openings 10a, and the solder connection is made by reflow to make the semiconductor with solder balls attached. Package.
That is, a metal sheet 10 having an opening 10a is adhered to one side of an electrically insulating film 1, and a solder ball is soldered to a copper circuit pattern 8 through the opening 10a, thereby forming a semiconductor package. .

As described above, the present invention provides a semiconductor package that is thin, has a fine copper circuit pattern, and has a large aspect ratio, so that it generates little heat even when a high current is continuously passed through it. be able to. Further, even if the aspect ratio is large, the adhesion of the copper circuit pattern to the electrically insulating film is good, so it is possible to obtain a semiconductor package in which there is no risk of the circuit pattern peeling off even when components are mounted.

EXAMPLES Hereinafter, the present invention will be explained in more detail based on Examples and Comparative Examples, but the present invention is not limited by these Examples and the like.

(Example)
A commercially available product is prepared by preparing an FPC material (flexible printed circuit board material) with a 3 μm electrolytic copper film on both sides of a 25 μm thick polyimide film, and a 15 μm copper foil on top as a protective laminate. was peeled off and the outer periphery was adhesively fixed to a SUS frame plate.

Then, a through hole with a diameter of 15 μm was made using a YAG laser (an opening was formed) in a portion where a conductive via was to be formed to electrically connect the circuit patterns formed on the front and back sides of this sheet.
Next, an etching resist was formed on the thin copper portion of the electrolytic copper film having a thickness of 3 μm, and the copper film was etched with an etching solution to form a fine circuit pattern with a line and space of 15/15 μm.

Then, a commercially available thin dry film resist having a thickness of 25 μm was laminated over the entire upper surface of the polyimide film on which a fine circuit pattern was formed by thermocompression bonding with a roll so that the thickness was uniform. The thickness of the dry film at this time was about 20 to 30 μm.
Next, through the exposure process and the subsequent development process, the dry film resist only in the circuit pattern area is dissolved, forming a dry film resist with a line and space of 15/15 μm, resulting in a structure in which the circuit pattern is exposed. A void was formed.
Using this polyimide film as a cathode, the entire surface was plated with copper by electroplating. Copper plating was performed over the entire surface of the dry film resist to the extent that it protruded by several μm from the surface, but there was variation in the plating thickness, and some patterns had a plating thickness of 20 μm or less.

Therefore, in order to make the thickness of the copper film uniform, the film was flattened and polished using a ceramic polishing roll, and the copper and dry film were simultaneously polished so that the thickness of the dry film resist and the thickness of the copper were 20 μm. The thickness of the dry film after polishing was 20±3 μm.
The thickness of the copper part circuit was mostly 20 μm, but there were some parts that were 17 to 20 μm, so it was possible to form a circuit film (copper circuit pattern) with a total copper thickness of 17.5 ± 1.5 μm. Ta.

Next, the dry film resist was subjected to swelling treatment in an alkaline developer and peeled off.
Next, 3000 holes with a pitch of 0.3 mm, an opening diameter of 0.2 mm, and the number of openings were formed on the outer circumference of a 0.2 mm thick SUS sheet. The SUS sheet was adhered to a polyimide film on which a circuit was formed using an adhesive.
Further, solder flux was applied to the copper pads (copper circuit patterns) in the openings of the SUS sheet, and solder balls with a diameter of 0.175 mm were placed in the 3000 hole portions and soldered together by reflow.

In the semiconductor package manufactured in this manner, a thickness reduction of 17 μm to 20 μm can be achieved, and a fine copper circuit pattern with a line and space of 15/15 μm can be formed.
Moreover, since the aspect ratio of the copper circuit pattern is approximately 1.3, which is larger than that in conventional manufacturing methods, heat generation in the package can be suppressed even when a high current is continuously passed.
Further, even if the aspect ratio is increased, the adhesion of the copper circuit pattern to the electrically insulating film is good, so that peeling of the copper circuit pattern can be suppressed even when components are mounted.

1 Polyimide film (electrical insulating film)
2 thin copper film 3 copper film 4 opening 5 circuit pattern 6 dry film resist 7 void 8 copper circuit pattern 9 adhesive layer 10 metal sheet 10a opening in metal sheet 11 solder ball

Claims (2)

forming a circuit pattern by etching a thin copper film made of electrolytic copper film adhered to both sides of an electrically insulating film;
After the step, performing a copper plating treatment and using it as a base for a thin copper film, the method includes a step of growing a copper film on the thin copper film,
A method for manufacturing a semiconductor package, characterized in that the copper film is grown to form a copper circuit pattern such that the copper film has an aspect ratio of at least 1. 2. The method according to claim 1 , wherein a perforated metal sheet is bonded to one side of the electrically insulating film, and a solder ball is soldered to the copper circuit pattern through the perforated portion of the metal sheet. A method for manufacturing semiconductor packages.

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