JP2003045917A - Tape carrier for semiconductor device and its manufacturing method - Google Patents
Tape carrier for semiconductor device and its manufacturing methodInfo
- Publication number
- JP2003045917A JP2003045917A JP2001234800A JP2001234800A JP2003045917A JP 2003045917 A JP2003045917 A JP 2003045917A JP 2001234800 A JP2001234800 A JP 2001234800A JP 2001234800 A JP2001234800 A JP 2001234800A JP 2003045917 A JP2003045917 A JP 2003045917A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- plating
- solder resist
- tape
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、液晶デバイスやＣ
ＳＰ(Chip Scale Package)などに用いられる半導体装置
用テープキャリアおよびその製造方法に関する。TECHNICAL FIELD The present invention relates to a liquid crystal device and a C
The present invention relates to a semiconductor device tape carrier used for SP (Chip Scale Package) and the like, and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来の半導体装置用テープキャリアであ
るＴＡＢ(Tape Automated Bonding)用テープの断面図を
図４に示し、その説明を行う。2. Description of the Related Art A sectional view of a conventional tape tape for TAB (Tape Automated Bonding) which is a tape carrier for semiconductor devices is shown in FIG.
【０００３】図４に示すＴＡＢ用テープ１０は、ポリイ
ミドテープ１１と、このポリイミドテープ１１の上面に
エポキシ系の接着剤１２によって接着されたインナーリ
ード１３と、このインナーリード１３の所定の部分に塗
布されたソルダレジスト１４と、インナーリード１３に
おけるソルダレジスト１４が塗布されていない部分に施
されたＳｎ（スズ）メッキ１５とを備えている。A TAB tape 10 shown in FIG. 4 is formed by applying a polyimide tape 11, an inner lead 13 adhered to the upper surface of the polyimide tape 11 with an epoxy adhesive 12, and a predetermined portion of the inner lead 13. And the Sn (tin) plating 15 applied to the portion of the inner lead 13 where the solder resist 14 is not applied.
【０００４】即ち、Ｃｕ（銅）箔上にフォトレジスト
（感光性レジスト）をコートしてプレキュアを行い露光
して現像し、ポストキュア後にＣｕ箔のエッチングを行
って配線（インナーリード１３）を形成する。この形成
後に液状のフォトソルダレジスト又はエポキシ系ソルダ
レジストをインナーリード１３に印刷コートして露光し
た後、現像又はポストベークを行いインナーリード１３
上に絶縁保護層（ソルダレジスト１４）を形成してい
た。That is, a Cu (copper) foil is coated with a photoresist (photosensitive resist), pre-cured, exposed and developed, and post-cured, the Cu foil is etched to form wiring (inner lead 13). To do. After this formation, a liquid photo solder resist or an epoxy-based solder resist is print-coated on the inner leads 13 and exposed, and then development or post-baking is performed to carry out the inner leads 13.
An insulating protective layer (solder resist 14) was formed on the top.
【０００５】[0005]
【発明が解決しようとする課題】従来の半導体装置用テ
ープキャリア（ＴＡＢ用テープ１０）においては、一般
に、インナーリード１３上に絶縁性のある液状のエポキ
シ系ソルダレジストを印刷してポストキュアすることに
よって、インナーリード１３上に厚さが２０μｍ以下の
ソルダレジスト１４を形成するようにしている。In the conventional tape carrier for semiconductor devices (TAB tape 10), generally, an insulating liquid epoxy-based solder resist is printed on the inner leads 13 and post-cured. Thus, the solder resist 14 having a thickness of 20 μm or less is formed on the inner leads 13.
【０００６】ところが、ソルダレジスト１４が形成され
た後、Ｃｕのインナーリード１３に無電解のＳｎメッキ
１５を施すと、インナーリード１３とソルダレジスト１
４との境界部分で、ＣｕとＳｎとの置換反応により、イ
ンナーリード１３において深さ３〜５μｍ、幅２０μｍ
の後述で説明する銅食われ１６が発生し、インナーリー
ド１３の強度（リード強度）を弱くするという問題があ
る。However, when the electroless Sn plating 15 is applied to the Cu inner lead 13 after the solder resist 14 is formed, the inner lead 13 and the solder resist 1 are formed.
4 at the boundary with the inner lead 13 having a depth of 3 to 5 μm and a width of 20 μm due to the substitution reaction of Cu and Sn.
There is a problem that copper erosion 16 which will be described later occurs and the strength of the inner lead 13 (lead strength) is weakened.
【０００７】このようにリード強度が弱くなると、イン
ナーリード１３の配線ピッチが５０μｍ以下のもので
は、リード強度の低下による断線が多発して品質不良と
なってしまう。When the lead strength is weak as described above, if the inner lead 13 has a wiring pitch of 50 μm or less, disconnection frequently occurs due to a decrease in the lead strength, resulting in poor quality.
【０００８】銅食われ１６は、特にソルダレジスト１４
が流れ出し、インナーリード１３との密着性が悪くなる
境界に発生する。この銅食われ１６の発生メカニズム
を、図５を参照して説明する。The copper erosion 16 is particularly caused by the solder resist 14
Flow out and occur at the boundary where the adhesion with the inner lead 13 deteriorates. The generation mechanism of the copper erosion 16 will be described with reference to FIG.
【０００９】まず図５の（ａ）に示すように、Ｓｎメッ
キ１５の厚みが０．１μｍ以下のメッキ初めでは、Ｃｕ
のインナーリード１３の表面にＳｎメッキ１５が析出
し、ソルダレジスト１４の下は殆ど食われない。（ｂ）
に示すように、Ｓｎメッキ１５が０．１〜０．３μｍに
成長すると、この成長に伴いソルダレジスト１４の境界
部分でＣｕとＳｎとの置換反応が生じ、その境界部分の
Ｃｕが１６ｂで示すように若干食われる。First, as shown in FIG. 5A, when the Sn plating 15 has a thickness of 0.1 μm or less at the beginning of plating, Cu is used.
The Sn plating 15 is deposited on the surface of the inner lead 13 and the bottom of the solder resist 14 is hardly eaten. (B)
As shown in FIG. 3, when the Sn plating 15 grows to 0.1 to 0.3 μm, a substitution reaction between Cu and Sn occurs at the boundary portion of the solder resist 14 with this growth, and Cu at the boundary portion is indicated by 16b. To be eaten a little.
【００１０】（ｃ）に示すように、Ｓｎメッキ１５が
０．３〜０．６μｍではメッキ速度が低下し、この低下
に伴い境界部分での置換反応がより生じ、その境界部分
のＣｕが１６ｃで示すようにより食われる。（ｄ）に示
すように、Ｓｎメッキ１５が０．６〜０．７５μｍでは
メッキ速度が極端に低下し、この低下に伴い置換反応が
境界部分に集中し、これによって境界部分のＣｕが１６
ｄで示すように大きく食われる。As shown in (c), when the Sn plating 15 is 0.3 to 0.6 μm, the plating rate decreases, and with this decrease, a substitution reaction occurs at the boundary portion, and Cu at the boundary portion becomes 16c. It is eaten by as shown in. As shown in (d), when the Sn plating 15 is 0.6 to 0.75 μm, the plating rate is extremely reduced, and the substitution reaction is concentrated on the boundary portion as a result of this reduction.
It is heavily eaten as indicated by d.
【００１１】本発明はかかる点に鑑みてなされたもので
あり、インナーリードにおける銅食われの発生を防止す
ることによって所定のリード強度を確保することができ
る半導体装置用テープキャリアおよびその製造方法を提
供することを目的とする。The present invention has been made in view of the above circumstances, and provides a tape carrier for a semiconductor device and a method of manufacturing the same for which a predetermined lead strength can be secured by preventing the occurrence of copper erosion in the inner leads. The purpose is to provide.
【００１２】[0012]
【課題を解決するための手段】上記課題を解決するため
に、本発明の半導体装置用テープキャリアは、絶縁テー
プ上に所定のパターンのリードを有し、前記リードの所
定の部分にソルダレジストを塗布した半導体装置用テー
プキャリアにおいて、前記リードは、前記ソルダレジス
トの塗布部および非塗布部の両部分に渡ってＳｎメッキ
が施されていることを特徴としている。In order to solve the above problems, a tape carrier for a semiconductor device of the present invention has leads of a predetermined pattern on an insulating tape, and a solder resist is provided on a predetermined portion of the leads. In the coated tape carrier for a semiconductor device, the lead is Sn-plated over both the coated portion and the non-coated portion of the solder resist.
【００１３】また、前記ソルダレジストは、ウレタン
系、ポリイミド系およびエポキシ系何れかの熱硬化型と
感光性のソルダレジストであり、塗布処理膜の厚さが５
０〜２μｍの構造であることを特徴としている。Further, the solder resist is a thermosetting type or photosensitive type solder resist of any of urethane type, polyimide type and epoxy type, and the thickness of the coating film is 5
It is characterized by having a structure of 0 to 2 μm.
【００１４】また、前記Ｓｎメッキは、無電解メッキ又
は電気メッキであることを特徴としている。The Sn plating is characterized by electroless plating or electroplating.
【００１５】また、本発明の半導体装置用テープキャリ
アの製造方法は、絶縁テープ上に所定のパターンのリー
ドを有し、前記リードの所定の部分にソルダレジストを
塗布した半導体装置用テープキャリアの製造方法におい
て、前記絶縁テープ上に、前記所定のパターンのリード
を形成するリード形成ステップと、前記所定のパターン
のリードにＳｎメッキを施すメッキステップと、前記メ
ッキステップの終了後に、前記所定のパターンのリード
の所定の部分にソルダレジストを塗布する塗布ステップ
とを有することを特徴としている。The method for manufacturing a tape carrier for a semiconductor device according to the present invention is a method for manufacturing a tape carrier for a semiconductor device in which a lead having a predetermined pattern is provided on an insulating tape and a solder resist is applied to a predetermined portion of the lead. In the method, a lead forming step of forming leads of the predetermined pattern on the insulating tape, a plating step of performing Sn plating on the leads of the predetermined pattern, and a step of forming the predetermined pattern after completion of the plating step. And a coating step of coating a solder resist on a predetermined portion of the lead.
【００１６】また、前記メッキステップは、無電解メッ
キ又は電気メッキによって行われることを特徴としてい
る。The plating step is performed by electroless plating or electroplating.
【００１７】[0017]
【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照して詳細に説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings.
【００１８】図１は、本発明の実施の形態に係るＴＡＢ
用テープの構成を示す断面図である。但し、この図１に
示す実施の形態において図４の従来の各部に対応する部
分には同一符号を付す。FIG. 1 shows a TAB according to an embodiment of the present invention.
It is sectional drawing which shows the structure of the tape for use. However, in the embodiment shown in FIG. 1, parts corresponding to the respective parts of the prior art in FIG.
【００１９】図１に示すＴＡＢ用テープ２０は、ポリイ
ミドテープ１１と、このポリイミドテープ１１の上面に
エポキシ系の接着剤１２によって接着されたインナーリ
ード１３と、このインナーリード１３に施されたＳｎメ
ッキ２１と、このＳｎメッキ２１の上面に塗布されたソ
ルダレジスト１４とを備えて形成されている。The TAB tape 20 shown in FIG. 1 is a polyimide tape 11, inner leads 13 bonded to the upper surface of the polyimide tape 11 with an epoxy adhesive 12, and Sn plating applied to the inner leads 13. 21 and the solder resist 14 applied on the upper surface of the Sn plating 21.
【００２０】このようなＴＡＢ用テープ２０の製造工程
を説明する。まず、厚さ７５μｍ、幅７０ｍｍのポリイ
ミドテープ１１をパンチングで打ち抜くことによって、
送り穴（パーフォレーション）とデバイスホールを形成
する。この後、厚さ１８μｍの銅箔テープを接着剤１２
で張り合わせ、銅箔テープにフォトレジストを塗布する
ラミネート・キュア後、フォトアプリケーション（露光
・現像）によってリード配線用のパターンを形成し、エ
ッチングで銅配線を作成する。この後、残ったフォトレ
ジストを取り除くことによってインナーリード１３が形
成される。The manufacturing process of such a TAB tape 20 will be described. First, by punching a polyimide tape 11 having a thickness of 75 μm and a width of 70 mm by punching,
Perforations and device holes are formed. Then, a copper foil tape having a thickness of 18 μm is applied to the adhesive 12
After laminating and curing by applying photoresist to copper foil tape, a pattern for lead wiring is formed by photo application (exposure and development), and copper wiring is created by etching. After that, the inner photoresist 13 is formed by removing the remaining photoresist.
【００２１】次に、インナーリード１３の露出全面に無
電解Ｓｎメッキを０．４μｍの厚さにメッキした後、２
時間以内に１２５℃±５℃で６０分のホイスカ抑制熱処
理を行う。これによってＳｎメッキ２１が形成される。
この後、Ｓｎメッキ２１の上面にポリイミド系のソルダ
レジストを塗布し、１２０℃で９０分のキュアを行いソ
ルダレジスト１４を形成する。Next, electroless Sn plating is plated on the entire exposed surface of the inner lead 13 to a thickness of 0.4 μm, and then 2
A whisker suppression heat treatment for 60 minutes is performed at 125 ° C. ± 5 ° C. within the time. As a result, the Sn plating 21 is formed.
Thereafter, a polyimide solder resist is applied on the upper surface of the Sn plating 21, and curing is performed at 120 ° C. for 90 minutes to form the solder resist 14.
【００２２】このように、本実施の形態のＴＡＢ用テー
プによれば、インナーリード１３に先にＳｎメッキ２１
を施した後、そのＳｎメッキを施されたインナーリード
１３上にソルダレジスト１４を形成するようにした。こ
の結果、無電解Ｓｎメッキを施しても、インナーリード
１３上にはまだソルダレジスト１４が形成されていない
ので、従来のようにＣｕのインナーリード１３とソルダ
レジスト１４との境界部分で、ＣｕとＳｎとの置換反応
により、インナーリード１３において銅食われが発生す
るといったことが無くなり、これによってリード強度が
低下するといったことが無くなる。As described above, according to the TAB tape of this embodiment, the Sn plating 21 is formed on the inner lead 13 first.
Then, the solder resist 14 is formed on the Sn-plated inner lead 13. As a result, even if electroless Sn plating is performed, the solder resist 14 is not yet formed on the inner leads 13, so that Cu is not formed at the boundary between the Cu inner leads 13 and the solder resist 14 as in the conventional case. The substitution reaction with Sn eliminates the occurrence of copper erosion in the inner lead 13 and thus the reduction in lead strength.
【００２３】言い換えれば、銅食われ１６によるリード
（配線）の欠損（３．５〜５．０μｍ）が無いため、折
曲げ性の向上と微細配線ピッチに対するリード強度の確
保が容易となり、またスリムな設計が可能となり、容易
に小型化を図ることが可能なＴＡＢ用テープ２０を供給
することができる。この他、ＴＡＢ用テープ２０では、
ソルダレジスト１４となる液状ソルダレジストを任意に
選定することにより歩留と生産性が向上し、安定した量
産体制を確立可能となっている。In other words, since there is no lead (wiring) loss (3.5 to 5.0 μm) due to the copper erosion 16, it is easy to improve bendability and ensure lead strength with respect to a fine wiring pitch, and it is slim. It is possible to supply the TAB tape 20 that can be designed easily and can be easily downsized. Besides, in the TAB tape 20,
By arbitrarily selecting the liquid solder resist that becomes the solder resist 14, the yield and productivity are improved, and a stable mass production system can be established.
【００２４】このような効果を比較検証するため従来の
製造方法に従い、インナーリード１３に上記実施の形態
の条件と同様、ポリイミド系のソルダレジストを塗布
し、１２０℃で９０分のキュアを行いソルダレジスト１
４を形成し、無電解Ｓｎメッキを０．４μｍの厚さにメ
ッキした後、２時間以内に１２５℃±５℃で６０分のホ
イスカ抑制熱処理を行った。この場合、Ｃｕのインナー
リード１３とソルダレジスト１４との境界部分でＣｕと
Ｓｎとの置換反応により、リードの厚さが減少する領域
（銅食われ）が長さ３０μｍに渡り発生した。In order to compare and verify such effects, according to a conventional manufacturing method, a polyimide-based solder resist is applied to the inner leads 13 in the same manner as the conditions of the above-mentioned embodiment, and curing is performed at 120 ° C. for 90 minutes to obtain solder. Resist 1
4 was formed, electroless Sn plating was performed to a thickness of 0.4 μm, and then whisker suppressing heat treatment was performed at 125 ° C. ± 5 ° C. for 60 minutes within 2 hours. In this case, due to the substitution reaction between Cu and Sn at the boundary between the Cu inner lead 13 and the solder resist 14, a region (copper erosion) where the lead thickness decreased was generated over a length of 30 μm.
【００２５】また、本実施の形態のＴＡＢ用テープ２０
の場合、耐マイグレーション特性が安定しており信頼性
に優れていることが判明した。これは、配線パターン
（インナーリード１３）の５０μｍピッチ部で８５℃×
８５％ＲＨの環境で、３０Ｖの印加を１０００時間実施
した結果、この試験中の絶縁抵抗が１０9Ω以上あって
安定しており信頼性に優れていることが判明した。Further, the TAB tape 20 of the present embodiment
In the case of, it was found that the migration resistance property was stable and the reliability was excellent. This is 85 ℃ × 50μm pitch part of the wiring pattern (inner lead 13)
As a result of applying 30 V for 1000 hours in an environment of 85% RH, it was found that the insulation resistance during this test was 10 9 Ω or more, which was stable and was excellent in reliability.
【００２６】また、チップ接合後の異方性導電膜による
プリント基板へのアウターリード接合も良好で液晶用と
して組み立てができた。Outer lead bonding to the printed circuit board by the anisotropic conductive film after chip bonding was also good, and it was possible to assemble for liquid crystal.
【００２７】また、ＴＡＢ用テープ２０は接着剤１２が
有りの場合であるが、接着剤レスの両面配線のインナリ
ードボンディングタイプおよびデバイスホール無しのタ
イプのＴＡＢ用テープにも応用可能である。Although the TAB tape 20 has the adhesive 12, it is also applicable to an adhesiveless double-sided inner lead bonding type TAB tape without a device hole.
【００２８】更にＴＡＢ用テープ２０は、図２に一例を
示す微細配線（ピッチ５０μｍ以下）のデバイスホール
無しのフリップチップ（Ｆｌｉｐ−Ｃｈｉｐ）接続用の
デバイス、および図３に一例を示す凹部にチップを収容
したビームリードタイプのＬＣＤ(Liquid Crystal Disp
lay)用にも応用可能である。Further, the TAB tape 20 is a device for flip-chip (Flip-Chip) connection without a device hole of fine wiring (pitch of 50 μm or less), an example of which is shown in FIG. Beam-lead type LCD (Liquid Crystal Disp
lay) is also applicable.
【００２９】図２に示すフリップチップ接続用のデバイ
ス３０は、ポリイミドテープ１１上に複数のリード１３
が接着剤１２で接着されて成るＢＧＡ(Ball Grid Arra
y)用ＴＡＢテープ３３を備え、このテープ３３における
複数のリード１３にＳｎメッキ２１が施され、このＳｎ
メッキ２１上の所定箇所にソルダレジスト１４が形成さ
れ、更にポリイミドテープ１１および接着剤１２に設け
られた半田ボールビア３１を介して半田ボール３２が固
着され、所定のリード１３にＳｎメッキ２１を介してＬ
ＳＩチップ３５がフリップチップ接合３４され、更にＬ
ＳＩチップ３５がトランスファーモールド３６で被覆さ
れて構成されている。The device 30 for flip-chip connection shown in FIG. 2 has a plurality of leads 13 on a polyimide tape 11.
BGA (Ball Grid Arra
y) TAB tape 33 is provided, and a plurality of leads 13 in this tape 33 are Sn-plated 21.
A solder resist 14 is formed at a predetermined position on the plating 21, and a solder ball 32 is further fixed via a solder ball via 31 provided in the polyimide tape 11 and the adhesive 12, and a predetermined lead 13 is Sn plated 21. L
The SI chip 35 is flip-chip bonded 34, and further L
The SI chip 35 is covered with a transfer mold 36.
【００３０】図３に示すＬＣＤ用のデバイス４０は、ポ
リイミドテープ１１上に複数のリード１３が形成される
と共にポリイミドテープ１１の下にビアを介して所定の
リード１３に接続された電源・グランド層４１が形成さ
れて成る接着剤レス両面銅貼り２層ＣＣＬ４２を備え、
このＣＣＬ４２における複数のリード１３にＳｎメッキ
２１が施され、このＳｎメッキ２１上の所定箇所にソル
ダレジスト１４が形成されている。The device 40 for LCD shown in FIG. 3 has a plurality of leads 13 formed on the polyimide tape 11 and a power / ground layer connected to the predetermined leads 13 via vias under the polyimide tape 11. Adhesive-less double-sided copper-clad two-layer CCL42 formed by forming 41,
Sn plating 21 is applied to the leads 13 of the CCL 42, and a solder resist 14 is formed at a predetermined position on the Sn plating 21.
【００３１】更にポリイミドテープ１１および電源・グ
ランド層４１の下に電源・グランド層４１の所定箇所が
露出するように感光性ソルダレジスト４３が形成され、
この感光性ソルダレジスト４３から露出した電源・グラ
ンド層４１にＳｎメッキ２１が施され、このＳｎメッキ
２１に半田ボール３２が固着され、また、所定のリード
１３にＳｎメッキ２１を介してＬＳＩチップ３５がフリ
ップチップ接合３４され、更にＬＳＩチップ３５および
ソルダレジスト１４の上にスティフナ用接着剤４４によ
ってチップ収容凹部４４ａを有したスティフナ４５が接
着されて構成されている。Further, a photosensitive solder resist 43 is formed under the polyimide tape 11 and the power / ground layer 41 so that a predetermined portion of the power / ground layer 41 is exposed.
The power / ground layer 41 exposed from the photosensitive solder resist 43 is Sn-plated 21, the solder balls 32 are fixed to the Sn-plated 21, and the LSI chip 35 is attached to a predetermined lead 13 via the Sn-plating 21. Are flip-chip bonded 34, and a stiffener 45 having a chip accommodating recess 44a is further bonded onto the LSI chip 35 and the solder resist 14 by a stiffener adhesive 44.
【００３２】これらデバイス３０，４０においても、ソ
ルダレジスト１４となる液状のソルダレジスト塗布前
に、Ｓｎメッキ２１をインナーリード１３に施すことに
よって、前述したようにインナーリード１３における銅
食われを無くすことができる。In these devices 30 and 40 as well, the Sn plating 21 is applied to the inner leads 13 before applying the liquid solder resist which becomes the solder resist 14, thereby eliminating the copper erosion in the inner leads 13 as described above. You can
【００３３】また、液状のソルダレジスト塗布後のキュ
ア条件がＳｎメッキ２１と銅配線（インナーリード１
３）との拡散を制御するため、温度が１３０℃以下でソ
ルダレジスト１４の硬化が十分に完了し、その後の実装
（チップとのボンデイング）時のアウトガスの発生がな
く、図２および図３に符号５１で示すアンダフィルの流
れが阻害されなくなる。The curing condition after applying the liquid solder resist is Sn plating 21 and copper wiring (inner lead 1).
In order to control the diffusion with 3), the curing of the solder resist 14 is sufficiently completed at a temperature of 130 ° C. or less, and no outgas is generated during the subsequent mounting (bonding with the chip). The underfill flow indicated by reference numeral 51 is not obstructed.
【００３４】[0034]
【発明の効果】以上説明したように、本発明によれば、
絶縁テープ上に、所定のパターンのリードを形成し、こ
のリードにＳｎメッキを施し、このメッキ終了後に、所
定のパターンのリードの所定部分にソルダレジストを塗
布して半導体装置用テープキャリアを形成するようにし
たので、Ｓｎメッキを施してもリード上にはまだソルダ
レジストが形成されておらず、このため従来のようにＣ
ｕのリードとソルダレジストとの境界部分でＣｕとＳｎ
との置換反応により、リードにおいて銅食われが発生す
るといったことが無くなり、これによってリード強度が
低下するといったことが無くなる。つまり、インナーリ
ードにおける銅食われの発生を防止することによって所
定のリード強度を確保することができる。As described above, according to the present invention,
A lead having a predetermined pattern is formed on the insulating tape, the lead is Sn-plated, and after the plating is finished, a solder resist is applied to a predetermined portion of the lead having the predetermined pattern to form a tape carrier for a semiconductor device. As a result, even if Sn plating is applied, the solder resist is not yet formed on the leads.
Cu and Sn at the boundary between the u lead and the solder resist
By the substitution reaction with, the occurrence of copper erosion in the lead is eliminated, and thus the lead strength is not reduced. That is, it is possible to ensure a predetermined lead strength by preventing the occurrence of copper erosion in the inner leads.
【図１】本発明の実施の形態に係るＴＡＢ用テープの構
成を示す断面図である。FIG. 1 is a cross-sectional view showing the structure of a TAB tape according to an embodiment of the present invention.
【図２】本発明の実施の形態に係るＴＡＢ用テープを用
いた微細配線のデバイスホール無しフリップチップ接続
用デバイスの構成を示す断面図である。FIG. 2 is a cross-sectional view showing a configuration of a device for flip-chip connection without a device hole of fine wiring using the TAB tape according to the embodiment of the present invention.
【図３】本発明の実施の形態に係るＴＡＢ用テープを用
いたデバイスホール有りビームリードタイプのＬＣＤ用
デバイスの構成を示す断面図である。FIG. 3 is a cross-sectional view showing a configuration of a beam lead type LCD device with device holes using the TAB tape according to the embodiment of the present invention.
【図４】従来のＴＡＢ用テープの構成を示す断面図であ
る。FIG. 4 is a cross-sectional view showing the structure of a conventional TAB tape.
【図５】インナーリードにおける銅食われ発生メカニズ
ムを説明するための図である。FIG. 5 is a diagram for explaining a copper erosion generation mechanism in an inner lead.
１０，２０ ＴＡＢ用テープ １１ ポリイミドテープ １２ 接着剤 １３ インナーリード １４ ソルダレジスト １６，１６ｂ，１６ｃ，１６ｄ 銅食われ ２１ Ｓｎメッキ ３１ 半田ボールビア ３２ 半田ボール ３３ ＢＧＡ用ＴＡＢテープ ３４ フリップチップ接合 ３５ ＬＳＩチップ ３６ トランスファーモールド ４１ 電源・グランド層 ４２ 接着剤レス両面銅貼り２層ＣＣＬ ４３ 感光性ソルダレジスト ４４ スティフナ用接着剤 ４５ スティフナ ５１ アンダフィル 10,20 TAB tape 11 Polyimide tape 12 Adhesive 13 Inner lead 14 Solder resist 16,16b, 16c, 16d Copper erosion 21 Sn plating 31 Solder ball via 32 solder balls 33 TAB tape for BGA 34 Flip chip bonding 35 LSI chip 36 Transfer Mold 41 Power supply / ground layer 42 Adhesiveless double-sided copper-clad 2-layer CCL 43 Photosensitive solder resist 44 Stiffener adhesive 45 Stiffener 51 Underfill
Claims (5)
を有し、前記リードの所定の部分にソルダレジストを塗
布した半導体装置用テープキャリアにおいて、 前記リードは、前記ソルダレジストの塗布部および非塗
布部の両部分に渡ってＳｎメッキが施されていることを
特徴とする半導体装置用テープキャリア。1. A tape carrier for a semiconductor device, comprising: a lead having a predetermined pattern on an insulating tape; and a solder resist applied to a predetermined portion of the lead, wherein the lead is a solder resist application part and a non-application part. A tape carrier for a semiconductor device, wherein Sn plating is applied to both parts of the part.
リイミド系およびエポキシ系何れかの熱硬化型と感光性
のソルダレジストであり、塗布処理膜の厚さが５０〜２
μｍの構造であることを特徴とする請求項１記載の半導
体装置用テープキャリア。2. The solder resist is a thermosetting type or photosensitive type solder resist of any one of urethane type, polyimide type and epoxy type, and has a coating treatment film thickness of 50 to 2
The tape carrier for a semiconductor device according to claim 1, wherein the tape carrier has a structure of μm.
気メッキであることを特徴とする請求項１又は２記載の
半導体装置用テープキャリア。3. The tape carrier for a semiconductor device according to claim 1, wherein the Sn plating is electroless plating or electroplating.
を有し、前記リードの所定の部分にソルダレジストを塗
布した半導体装置用テープキャリアの製造方法におい
て、 前記絶縁テープ上に、前記所定のパターンのリードを形
成するリード形成ステップと、 前記所定のパターンのリードにＳｎメッキを施すメッキ
ステップと、 前記メッキステップの終了後に、前記所定のパターンの
リードの所定の部分にソルダレジストを塗布する塗布ス
テップとを有することを特徴とする半導体装置用テープ
キャリアの製造方法。4. A method of manufacturing a tape carrier for a semiconductor device, comprising a lead having a predetermined pattern on an insulating tape, and a predetermined portion of the lead being coated with a solder resist, wherein the predetermined pattern is provided on the insulating tape. Forming a lead of a predetermined pattern, a plating step of performing Sn plating on the lead of the predetermined pattern, and a coating step of applying a solder resist to a predetermined portion of the lead of the predetermined pattern after the plating step is completed. A method of manufacturing a tape carrier for a semiconductor device, comprising:
は電気メッキによって行われることを特徴とする請求項
４記載の半導体装置用テープキャリアの製造方法。5. The method of manufacturing a tape carrier for a semiconductor device according to claim 4, wherein the plating step is performed by electroless plating or electroplating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001234800A JP2003045917A (en) | 2001-08-02 | 2001-08-02 | Tape carrier for semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001234800A JP2003045917A (en) | 2001-08-02 | 2001-08-02 | Tape carrier for semiconductor device and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003045917A true JP2003045917A (en) | 2003-02-14 |
Family
ID=19066346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001234800A Pending JP2003045917A (en) | 2001-08-02 | 2001-08-02 | Tape carrier for semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003045917A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006165426A (en) * | 2004-12-10 | 2006-06-22 | Ishihara Chem Co Ltd | Method for manufacturing film carrier or the like |
| JP2007123425A (en) * | 2005-10-26 | 2007-05-17 | Seiko Epson Corp | Manufacturing method of printed circuit board |
| CN100356553C (en) * | 2003-04-25 | 2007-12-19 | 三井金属矿业株式会社 | Thin flm bearing belt of mounting electronic parts, its prodn. method and printing screen for coating welding resistance agent |
| EP2076104A2 (en) * | 2007-12-27 | 2009-07-01 | LG Electronics Inc. | Flexible film and display device comprising the same |
| WO2010098485A1 (en) * | 2009-02-28 | 2010-09-02 | ソニーケミカル＆インフォメーションデバイス株式会社 | Wiring board |
| JP2011096721A (en) * | 2009-10-27 | 2011-05-12 | Nitto Denko Corp | Printed circuit board and method of manufacturing the same |
| US8808837B2 (en) | 2007-12-21 | 2014-08-19 | Lg Electronics Inc. | Flexible film and display device comprising the same |
| US20160329269A1 (en) * | 2015-05-04 | 2016-11-10 | Chipmos Technologies Inc. | Chip package structure and manufacturing method thereof |
-
2001
- 2001-08-02 JP JP2001234800A patent/JP2003045917A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100356553C (en) * | 2003-04-25 | 2007-12-19 | 三井金属矿业株式会社 | Thin flm bearing belt of mounting electronic parts, its prodn. method and printing screen for coating welding resistance agent |
| JP2006165426A (en) * | 2004-12-10 | 2006-06-22 | Ishihara Chem Co Ltd | Method for manufacturing film carrier or the like |
| JP2007123425A (en) * | 2005-10-26 | 2007-05-17 | Seiko Epson Corp | Manufacturing method of printed circuit board |
| US8808837B2 (en) | 2007-12-21 | 2014-08-19 | Lg Electronics Inc. | Flexible film and display device comprising the same |
| EP2076104A2 (en) * | 2007-12-27 | 2009-07-01 | LG Electronics Inc. | Flexible film and display device comprising the same |
| WO2010098485A1 (en) * | 2009-02-28 | 2010-09-02 | ソニーケミカル＆インフォメーションデバイス株式会社 | Wiring board |
| JP2011096721A (en) * | 2009-10-27 | 2011-05-12 | Nitto Denko Corp | Printed circuit board and method of manufacturing the same |
| US20160329269A1 (en) * | 2015-05-04 | 2016-11-10 | Chipmos Technologies Inc. | Chip package structure and manufacturing method thereof |
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