JP2015050307A - Wiring board and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which has less risk of developing peeling on a semiconductor element connection pad.SOLUTION: In a wiring board in which a solder resist layer 3 with a thickness of over that of a wiring conductor 2 is deposited on an insulation substrate 1 on a top face of which the wiring conductors 2 composed of copper, each of which has a predetermined thickness and some of which has a semiconductor element connection pad 4 is deposited, and a partial region A of the solder resist layer 3 is thinned to a thickness not greater than that of the wiring conductor 2 and a top part of the semiconductor element connection pad 4 is exposed on the thin-filmed region A and a bottom of the semiconductor element connection pad 4 is covered with the thinned solder resist layer 3, the semiconductor element connection pad 4 is thinned by selectively etching the top part of the semiconductor element connection pad 4, and a plated metal layer 5 is deposited on a surface of the top part.

Description

  The present invention relates to a wiring board used for mounting a semiconductor element and a manufacturing method thereof.

  Conventionally, as shown in FIG. 3, a copper substrate partially including a semiconductor element connection pad 11 to which an electrode terminal T of a semiconductor element S is connected as a wiring board used for mounting the semiconductor element S by flip chip connection or the like. A solder resist layer 14 having a thickness exceeding the wiring conductor 12 is deposited on an insulating substrate 13 having a wiring conductor 12 having a predetermined thickness deposited on the upper surface thereof, and a partial region A of the solder resist layer 14. Is a solder resist layer in which the top of the semiconductor element connection pad 11 is exposed in the thinned region A and the base of the semiconductor element connection pad 11 is thinned. A wiring board coated with 14 is known. A plated metal layer 15 having excellent solder wettability is applied in advance to a thickness of 1 to 2 μm on the surface of the semiconductor element connection pad 11 exposed from the solder resist layer 14.

  In this conventional wiring board, the semiconductor element S is formed by bonding the top of the semiconductor element connection pad 11 on which the plated metal layer 15 is deposited and the electrode terminal T of the semiconductor element S via the solder bump B. Mounted on the wiring board.

  However, in this conventional wiring substrate, since the metal plating layer 15 is deposited with a thickness of 1 to 2 μm on the surface of the semiconductor element connection pad 11 exposed from the solder resist layer 14, The width including the plated metal layer 15 at the top is increased by 2 to 4 μm. For this reason, in order to make the width including the plated metal layer 15 at the top of the semiconductor element connection pad 11 a predetermined width, the width of the semiconductor element connection pad 11 itself is formed to be about 2 to 4 μm smaller than the predetermined width in advance. In addition, it is necessary to have a predetermined width when the plated metal layer 15 is deposited on the top of the semiconductor element connection pad 11.

  By the way, in recent wiring boards, in order to cope with the high density and fine wiring of the semiconductor element S, the width including the metal plating layer 15 at the top of the semiconductor element connection pad 11 is required to be 20 μm or less. It has become like this. In this case, for example, when the metal plating layer 15 having a thickness of 2 μm is deposited on the top of the semiconductor element connection pad 11, the width of the semiconductor element connection pad 11 itself needs to be as narrow as 16 μm or less. If the width of the semiconductor element connection pad 11 itself is 16 μm or less, the area where the semiconductor element connection pad 11 is attached to the insulating substrate 13 is small, so that the semiconductor element connection pad 11 is attached to the insulating substrate 13. The risk of the semiconductor element connection pad 11 being peeled off from the insulating substrate 13 due to the low strength is increased.

JP 2009-33084 A

  The problem to be solved by the present invention is that even when the width including the metal plating layer at the top of the semiconductor element connection pad is 20 μm or less, the adhesion strength of the semiconductor element connection pad to the insulating substrate does not decrease. Another object of the present invention is to provide a wiring board with a low risk of peeling of the semiconductor element connection pads.

  In the wiring board of the present invention, a solder resist layer having a thickness exceeding the wiring conductor is deposited on an insulating substrate having a wiring conductor made of copper having a semiconductor element connection pad in part and deposited on the upper surface. In addition, a part of the solder resist layer is thinned below the thickness of the wiring conductor, and the top of the semiconductor element connection pad is exposed in the thinned area, and the semiconductor element In the wiring substrate in which the base portion of the connection pad is covered with the thinned solder resist layer, the top portion is selectively etched and thinned, and a plating metal layer is deposited on the surface of the top portion. It is characterized by that.

  In addition, the method for manufacturing a wiring board according to the present invention provides a solder resist having a thickness exceeding the wiring conductor on an insulating substrate having a predetermined thickness wiring conductor made of copper having a semiconductor element connection pad in part. A part of the solder resist layer is thinned to a thickness equal to or less than the thickness of the wiring conductor, and the top of the semiconductor element connection pad is exposed in the thinned area, and the semiconductor element connection pad Forming a base portion of the thin film so as to be covered with the thinned solder resist layer, a step of selectively etching and thinning the top portion, and a step of depositing a plating metal layer on the surface of the top portion And performing the above.

  According to the wiring board of the present invention, the top portion of the semiconductor element connection pad exposed from the solder resist layer is selectively etched and thinned, and the plated metal layer is deposited on the surface of the top portion. Therefore, the width including the plated metal layer at the top of the semiconductor element connection pad can be set to a predetermined width while the width of the base part of the semiconductor element connection pad attached to the insulating substrate is kept wide. Therefore, the deposition area of the semiconductor element connection pad on the insulating substrate is not reduced, and as a result, there is a risk that the semiconductor element connection pad is peeled off by securing the adhesion strength of the semiconductor element connection pad to the insulating substrate. Can be made small.

  In addition, according to the method for manufacturing a wiring board of the present invention, after the top of the semiconductor element connection pad exposed from the solder resist layer is selectively etched and thinned, the plated metal layer is deposited on the top. Thus, the width including the metal plating layer at the top of the semiconductor element connection pad can be set to a predetermined width while the width of the base part of the semiconductor element connection pad attached to the insulating substrate is kept wide. Therefore, the deposition area of the semiconductor element connection pad on the insulating substrate is not reduced, and as a result, there is a risk that the semiconductor element connection pad is peeled off by securing the adhesion strength of the semiconductor element connection pad to the insulating substrate. Can be obtained.

FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. 2A to 2C are schematic cross-sectional views for each step for explaining the method for manufacturing a wiring board of the present invention. FIG. 3 is a schematic cross-sectional view showing a conventional wiring board.

  Next, an example of an embodiment of the wiring board of the present invention will be described with reference to FIG. As shown in FIG. 1, the wiring board of the present invention has a wiring conductor 2 deposited on the upper surface of an insulating substrate 1 and a solder resist layer 3 deposited thereon.

  The insulating substrate 1 is made of, for example, a thermosetting resin containing glass cloth or a thermosetting resin containing an inorganic insulating filler. The wiring conductor 2 is made of copper and is formed using a known semi-additive method or the like. The thickness of the wiring conductor 2 is about 10 to 20 μm. The wiring conductor 2 includes, for example, a belt-like pattern having a width of 20 μm or less, and has a semiconductor element connection pad 4 in a part of the pattern.

  The solder resist layer 3 is made of a thermosetting resin containing an inorganic insulating filler. The solder resist layer 3 has a thickness exceeding the wiring conductor 2 by about 3 to 10 μm, and a part of the region A is thinned to be equal to or less than the thickness of the wiring conductor 2. In the thinned region A, the tops of the semiconductor element connection pads 4 are exposed. The height at which the top of the semiconductor element connection pad 4 is exposed is about 0 to 15 μm. The base of the semiconductor element connection pad 4 is covered with a thinned solder resist layer 3. The height at which the base of the semiconductor element connection pad 4 is covered is about 5 to 15 μm. As described above, the base of the semiconductor element connection pad 4 is covered with the solder resist layer 3, so that the adhesion strength of the semiconductor element connection pad 4 to the insulating substrate 1 can be reinforced. Further, for example, when a plurality of semiconductor element connection pads 4 are arranged adjacent to each other in one region A, the electrical insulation reliability between adjacent semiconductor element connection pads 4 is increased. be able to.

  Furthermore, in the present invention, the top portion of the semiconductor element connection pad 4 exposed from the solder resist layer 3 is selectively etched and thinned. The etched thickness t is about 1-2 μm. And the plating metal layer 5 which is excellent in solder wettability is deposited on the surface of the thinned top. As the plating metal layer 5, for example, a nickel plating layer and a gold plating layer are sequentially deposited, a nickel plating layer, a palladium plating layer and a gold plating layer are sequentially deposited, and a tin plating layer is deposited. What was made to use is used. The thickness of the plated metal layer 5 is about 1 to 2 μm, and is preferably substantially the same as the etched thickness t.

  Thus, in the wiring board of the present invention, the top of the semiconductor element connection pad 4 exposed from the solder resist layer 3 is selectively etched and thinned, and the plated metal layer 5 is formed on the surface of the top. Since the width of the base portion of the semiconductor element connection pad 4 attached to the insulating substrate 1 remains wide, the width including the plated metal layer 5 at the top of the semiconductor element connection pad 4 is set to a predetermined value. It can be a width. Therefore, the adhesion area of the semiconductor element connection pad 4 to the insulating substrate 1 is not reduced. As a result, the adhesion strength of the semiconductor element connection pad 4 to the insulating substrate 1 is secured and the semiconductor element connection pad 4 is peeled off from the semiconductor element connection pad 4. The risk of occurrence of this can be reduced.

  In the wiring board of the present invention, the semiconductor element S is formed by bonding the top of the semiconductor element connection pad 4 on which the plated metal layer 5 is deposited and the electrode terminal T of the semiconductor element S via the solder bump B. It will be mounted on a wiring board.

  Next, a method for manufacturing the above-described wiring board will be described with reference to FIG. In addition, the same code | symbol is provided to the location same as the location demonstrated in FIG. 1, and the detailed description is abbreviate | omitted. First, as shown in FIG. 2A, a thickness exceeding the wiring conductor 2 is formed on an insulating substrate 1 having a predetermined thickness of wiring conductor 2 made of copper having a semiconductor element connection pad 4 in part. The solder resist layer 3 of the solder resist layer 3 is partially thinned to a thickness less than the thickness of the wiring conductor 2, and the top of the semiconductor element connection pad 4 is exposed in the thinned region A, And it forms so that the base part of the semiconductor element connection pad 4 may be coat | covered with the soldering resist layer 3 thinned.

  As described above, the wiring conductor 2 is formed using the semi-additive method. The solder resist layer 3 is formed, for example, by depositing a thermosetting resin layer for the solder resist layer 3 on the insulating substrate 1 on which the wiring conductor 2 is formed to a thickness exceeding the wiring conductor 2, and then the region A in the resin layer. Is formed by excavating the film from above by sandblasting or laser processing to form a thin film. Alternatively, after the photosensitive resin layer for the solder resist layer 3 is deposited on the insulating substrate 1 on which the wiring conductor 2 is formed to a thickness exceeding the wiring conductor 2, the region A in this resin layer is selectively exposed to an unexposed portion. The remaining portion is exposed so as to remain, and the unexposed portion is developed so as to remain below the thickness of the wiring conductor 2, and then the resin layer is thermally cured.

  Next, as shown in FIG. 2B, the tops of the semiconductor element connection pads 4 exposed from the solder resist layer 3 are selectively etched and thinned. In this case, a method of selectively etching and thinning the top of the semiconductor element connection pad 4 by using the solder resist layer 3 as an etching mask may be employed. The etching thickness t is preferably in the range of 1 to 2 μm.

  Next, as shown in FIG. 2C, a plated metal layer 5 is deposited on top of the semiconductor element connection pads 4 which are thinned by etching. The thickness of the plated metal layer 5 is about 1 to 2 μm, and is preferably substantially the same as the etched thickness t. For example, when the plating metal layer 5 is formed by sequentially depositing a nickel plating layer and a gold plating layer, a gold plating layer having a thickness of about 0.1 to 1 μm is deposited on the nickel plating layer having a thickness of 1 to 2 μm. You can do it.

  As described above, according to the method for manufacturing a wiring board of the present invention, after the top portion of the semiconductor element connection pad 4 exposed from the solder resist layer 3 is selectively etched and thinned, the plated metal layer 5 is formed on the top portion. Therefore, the width including the metal plating layer 5 at the top of the semiconductor element connection pad 4 is set to a predetermined width while the width of the base part of the semiconductor element connection pad 4 applied to the insulating substrate 1 is kept wide. can do. Therefore, the adhesion area of the semiconductor element connection pad 4 to the insulating substrate 1 is not reduced. As a result, the adhesion strength of the semiconductor element connection pad 4 to the insulating substrate 1 is secured and the semiconductor element connection pad 4 is peeled off from the semiconductor element connection pad 4. It is possible to obtain a wiring board with a small risk of occurrence of

1 Insulating substrate 2 Wiring conductor 3 Solder resist layer 4 Semiconductor element connection pad 5 Plating metal layer A Thinned area

Claims (2)

  A solder resist layer having a thickness exceeding the wiring conductor is deposited on an insulating substrate having a predetermined thickness wiring conductor made of copper having a semiconductor element connection pad in part, and the solder resist A part of the layer is thinned to a thickness equal to or less than the thickness of the wiring conductor, the top of the semiconductor element connection pad is exposed in the thinned area, and the base of the semiconductor element connection pad is the thin film In the wiring board formed by coating with the solder resist layer, the top is selectively etched and thinned, and a plated metal layer is deposited on the surface of the top. Wiring board.   A solder resist layer having a thickness exceeding the wiring conductor is formed on an insulating substrate having a predetermined thickness wiring conductor made of copper having a semiconductor element connection pad as a part of the solder resist layer. Is thinned below the thickness of the wiring conductor, the top of the semiconductor element connection pad is exposed in the thinned region, and the base of the semiconductor element connection pad is the thinned solder resist layer. A wiring board comprising: a step of forming a coating, a step of selectively etching and thinning the top, and a step of depositing a plated metal layer on the surface of the top. Production method.

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