TW201832337A - Load circuit board and method for manufacturing the same - Google Patents

Load circuit board and method for manufacturing the same Download PDF

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Publication number
TW201832337A
TW201832337A TW106114228A TW106114228A TW201832337A TW 201832337 A TW201832337 A TW 201832337A TW 106114228 A TW106114228 A TW 106114228A TW 106114228 A TW106114228 A TW 106114228A TW 201832337 A TW201832337 A TW 201832337A
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layer
circuit
carrier board
solder
circuit layer
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TW106114228A
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TWI658557B (en
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黃昱程
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大陸商碁鼎科技秦皇島有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Abstract

A load circuit board includes an insulating layer, a first conductive layer and a second conductive layer mounted on opposite sides of the insulating layer, a first welding layer covered the first conductive layer, and a second welding layer covered the second conductive layer. A central portion of the insulating layer forms a first gap. The second welding layer corresponding to the first gap forms a second gap. The first gap and the second gap together define a cavity. A chip is in the cavity and is coupled with the first conductive layer.

Description

線路載板及其製造方法Circuit carrier board and manufacturing method thereof

本發明涉及一種線路載板，特別涉及一種薄型可彎折的線路載板及其製造方法。The invention relates to a circuit carrier board, in particular to a thin and flexible circuit carrier board and a manufacturing method thereof.

如今，為了滿足各種電子設備的功能多元化發展，線路載板以其輕薄、線路密度高等優勢得到了廣泛的應用。Nowadays, in order to meet the diversified development of various electronic devices, circuit boards have been widely used due to their advantages such as lightness, thinness, and high line density.

習知地，薄型線路載板由於其厚度較薄，因此在制程中容易造成彎折或者翹曲等現象，而且在後續的封裝制程中同樣容易產生此問題。因此，對於薄型線路載板來說，如何避免其制程中產生彎折或者翹曲等現象顯得尤為重要。Conventionally, because of its thin thickness, the thin circuit carrier board is prone to cause bending or warping in the manufacturing process, and this problem is also easy to occur in the subsequent packaging process. Therefore, for thin circuit board, how to avoid bending or warping in its manufacturing process is very important.

有鑑於此，本發明提供一種厚度較薄制程良率高的線路載板及其製造方法。In view of this, the present invention provides a circuit board having a thinner thickness and a higher yield rate, and a method for manufacturing the same.

一種線路載板，包括一絕緣層、分別位於所述絕緣層兩側表面的第一線路層、第二線路層、以及位於所述第一線路層一側表面包覆所述第一線路層的第一防焊層、位於所述第二線路層一側表面包覆所述第二線路層的第二防焊層，所述絕緣層中部間斷而形成一第一間隔部，所述第二防焊層對應所述第一間隔部形成一第二間隔部，所述第一間隔部和第二間隔部相互貫通且共同形成一容置區，一晶片設置于所述容置區中與所述第一線路層電連接。A circuit carrier board includes an insulating layer, a first circuit layer, a second circuit layer located on both surfaces of the insulating layer, and a first circuit layer covering the first circuit layer on a surface of the first circuit layer. A first solder mask layer, a second solder mask layer on the side of the second circuit layer, and a second solder mask layer covering the second circuit layer; the middle portion of the insulating layer is interrupted to form a first spacer; and the second solder mask A solder layer forms a second spacer portion corresponding to the first spacer portion, the first spacer portion and the second spacer portion penetrate each other and together form an accommodating area, and a wafer is disposed in the accommodating area and the accommodating area. The first circuit layer is electrically connected.

一種線路載板的製造 方法，包括如下步驟：A method for manufacturing a circuit carrier board includes the following steps:

提供一第一承載板，所述第一承載板包括一第一基底以及設置於所述第一基底一側表面的第一覆銅層；Provide a first carrier plate, the first carrier plate includes a first substrate and a first copper-clad layer disposed on a surface of one side of the first substrate;

在所述第一承載板的第一覆銅層上形成第一感光層，並通過曝光顯影技術使得所述第一感光層上形成若干第一缺口；Forming a first photosensitive layer on the first copper-clad layer of the first carrier plate, and forming a plurality of first gaps on the first photosensitive layer through exposure and development technology;

在所述第一缺口中鍍設一厚度均勻的第一金屬層；Plating a first metal layer with a uniform thickness in the first notch;

清除所述第一感光層，從而使得所述第一金屬層完全暴露而形成第一線路層；Removing the first photosensitive layer, so that the first metal layer is completely exposed to form a first circuit layer;

在所述第一線路層上形成一第一防焊層；Forming a first solder resist layer on the first circuit layer;

在所述第一防焊層外依次壓合形成一層熱隔離膜、第二承載板，所述第二承載板包括第二基底以及形成於所述第二基底兩側表面的第二覆銅層；A layer of thermal insulation film and a second carrier plate are sequentially laminated on the outside of the first solder resist layer, and the second carrier plate includes a second substrate and second copper-clad layers formed on both sides of the second substrate. ;

將所述第一承載板從所述第一線路層、第一防焊層上分離；Separating the first carrier board from the first circuit layer and the first solder resist layer;

進一步蝕刻所述第一線路層，從而使得所述第一線路層的外表面低於所述第一防焊層的外表面；Further etching the first wiring layer, so that an outer surface of the first wiring layer is lower than an outer surface of the first solder resist layer;

在所述第一線路層外形成一絕緣層，所述絕緣層中部隔斷形成一第一間隔部；Forming an insulating layer outside the first circuit layer, and a middle portion of the insulating layer is partitioned to form a first spacer portion;

通過鐳射在所述絕緣層上開設形成多個導電孔；Forming a plurality of conductive holes on the insulating layer by laser;

在所述絕緣層的第二表面壓合形成一第二感光層；Forming a second photosensitive layer by laminating on the second surface of the insulating layer;

通過曝光顯影技術，使得所述第二感光層上形成若干第二缺口；Forming a plurality of second gaps on the second photosensitive layer through exposure and development technology;

在所述第二缺口中鍍設形成第二金屬層；Forming a second metal layer in the second notch by plating;

清除所述第二感光層從而完全暴露出所述第二金屬層而形成第二線路層；Removing the second photosensitive layer to completely expose the second metal layer to form a second circuit layer;

在所述第二線路層外形成第二防焊層，使得所述第二防焊層對應所述第一間隔部位置開設形成第二間隔部，所述第二間隔部以及所述第一間隔部相互貫通且共同形成一容置區，所述第二防焊層上包括多個焊接孔；Forming a second solder resist layer outside the second circuit layer, so that the second solder resist layer is opened corresponding to the position of the first spacer to form a second spacer, the second spacer and the first spacer The two parts penetrate each other and form an accommodating area together; the second solder resist layer includes a plurality of welding holes;

在所述容置區中設置一晶片，使得所述晶片與所述第一線路層電連接；Setting a wafer in the accommodating area so that the wafer is electrically connected to the first circuit layer;

在所述容置區中填充封裝膠體以包覆所述晶片，以及在所述第二防焊層的焊接孔中鍍設形成焊球；Filling an encapsulating gel in the accommodating area to cover the wafer, and plating to form a solder ball in a welding hole of the second solder mask layer;

將所述第二承載板與所述第一防焊層分離。The second carrier plate is separated from the first solder resist layer.

如圖1所示，本發明所述線路載板100包括一絕緣層10、分別位於所述絕緣層10兩側表面的第一線路層20、第二線路層30、位於所述第一線路層20一側表面包覆所述第一線路層20的第一防焊層40、以及位於所述第二線路層30一側表面包覆所述第二線路層30的第二防焊層50。As shown in FIG. 1, the circuit carrier board 100 of the present invention includes an insulation layer 10, a first circuit layer 20, a second circuit layer 30, and a first circuit layer respectively located on both sides of the insulation layer 10. A first solder mask layer 40 on the side of the first circuit layer 20 is coated on the side of 20 and a second solder mask layer 50 on the side of the second circuit layer 30 is coated on the second circuit layer 30.

所述絕緣層10由可彎折的熱固型的防焊油墨組成，其厚度較薄且具有較好的柔性。在本發明實施例中，所述絕緣層10的厚度位於15-50微米之間。所述絕緣層10具有第一表面101及與所述第一表面101相對的第二表面102。所述絕緣層10上開設有貫穿第一表面101、第二表面102的的若干導電孔103。在本發明實施例中，所述導電孔103的橫截面呈梯形，其孔徑自第一表面101朝向第二表面102方向逐漸增加。所述絕緣層10中部間斷而形成一第一間隔部104。The insulating layer 10 is made of a bendable thermosetting solder resist ink, and has a thin thickness and good flexibility. In the embodiment of the present invention, the thickness of the insulating layer 10 is between 15-50 micrometers. The insulating layer 10 has a first surface 101 and a second surface 102 opposite to the first surface 101. The insulating layer 10 is provided with a plurality of conductive holes 103 penetrating the first surface 101 and the second surface 102. In the embodiment of the present invention, the cross-section of the conductive hole 103 is trapezoidal, and its aperture gradually increases from the first surface 101 toward the second surface 102. A middle portion of the insulating layer 10 is discontinuous to form a first spacer 104.

所述第一線路層20設置於所述絕緣層10的第一表面101上。所述第一線路層20具有多個焊墊21。所述焊墊21相應地位於所述第一間隔部104處且不位於所述第一間隔部104之內。The first circuit layer 20 is disposed on the first surface 101 of the insulating layer 10. The first circuit layer 20 has a plurality of bonding pads 21. The pads 21 are correspondingly located at the first spacer 104 and are not located within the first spacer 104.

所述第二線路層30設置於所述絕緣層10的第二表面102上。所述第二線路層30通過所述導電孔103與所述第一線路層20電連接。The second circuit layer 30 is disposed on the second surface 102 of the insulating layer 10. The second circuit layer 30 is electrically connected to the first circuit layer 20 through the conductive hole 103.

所述第一防焊層40由絕緣材料製成，其包覆所述第一線路層20。The first solder resist layer 40 is made of an insulating material and covers the first circuit layer 20.

所述第二防焊層50同為絕緣材料，其可與所述第一防焊層40的材料相同。所述第二防焊層50填充於所述第二線路層30中，所述第二防焊層50上開設有多個焊接孔51,用於填充焊料而形成焊球80。The second solder resist layer 50 is also an insulating material, which may be the same as the material of the first solder resist layer 40. The second solder mask layer 50 is filled in the second circuit layer 30. A plurality of solder holes 51 are formed in the second solder mask layer 50 for filling solder to form solder balls 80.

第二防焊層50對應所述絕緣層10的第一間隔部104均斷開而形成一第二間隔部501，所述第一間隔部104、以及所述第二間隔部501共同形成一容置區150。The second solder resist layer 50 is disconnected corresponding to the first spacer 104 of the insulating layer 10 to form a second spacer 501. The first spacer 104 and the second spacer 501 together form a capacitor. Home area 150.

進一步地，還包括一設置于所述容置區中的晶片60。所述晶片60的電極與所述第一線路層20的多個焊墊21對應電連接。Further, it further includes a wafer 60 disposed in the accommodating area. The electrodes of the wafer 60 are electrically connected to the plurality of bonding pads 21 of the first circuit layer 20.

進一步地，所述容置區150中進一步填充有封裝膠體70。所述封裝膠體70包覆所述晶片60。Further, the accommodating region 150 is further filled with an encapsulating gel 70. The encapsulant 70 covers the wafer 60.

在本發明所述線路載板100中，所述絕緣層10由可彎折的熱固型的防焊油墨組成，其厚度較薄且具有較好的柔性，因此不但可減小絕緣層10自身的厚度，而且增加了線路載板100的柔性，避免形成所述第一線路層20、第二線路層30時候發生翹曲、彎折等現象。進一步地，本發明所述線路載板100通過開設形成容置區，使得所述晶片60設置于所述容置區內與第一線路層20電連接，從而進一步地降低了線路載板100的厚度。In the circuit carrier board 100 of the present invention, the insulating layer 10 is composed of a bendable thermosetting solder resist ink, which is thinner and has better flexibility, so it can not only reduce the insulating layer 10 itself. The thickness of the circuit board 100 is increased, and the flexibility of the circuit carrier board 100 is increased, thereby avoiding warping, bending and the like when the first circuit layer 20 and the second circuit layer 30 are formed. Further, the circuit carrier board 100 of the present invention is formed to form an accommodating area, so that the chip 60 is disposed in the accommodating area and electrically connected to the first circuit layer 20, thereby further reducing the thickness.

如圖2-19所示，本發明所述線路載板100的製造方法，包括如下步驟：As shown in FIG. 2-19, the method for manufacturing the circuit carrier board 100 according to the present invention includes the following steps:

步驟一：如圖2所示，提供一第一承載板200。Step 1: As shown in FIG. 2, a first carrier board 200 is provided.

所述第一承載板200包括一第一基底210以及設置於所述第一基底210一側表面的第一覆銅層220。所述第一承載板200的厚度位於150-300μm之間。所述第一覆銅層220的厚度小於所述第一基底210的厚度。The first carrier board 200 includes a first substrate 210 and a first copper-clad layer 220 disposed on a side surface of the first substrate 210. The thickness of the first supporting plate 200 is between 150-300 μm. The thickness of the first copper-clad layer 220 is smaller than the thickness of the first substrate 210.

步驟二：如圖3所示，在所述第一承載板200的第一覆銅層220上形成第一感光層300，並通過曝光顯影技術使得所述第一感光層300上形成若干第一缺口310。Step 2: As shown in FIG. 3, a first photosensitive layer 300 is formed on the first copper-clad layer 220 of the first carrier plate 200, and a plurality of first photosensitive layers 300 are formed on the first photosensitive layer 300 by exposure and development technology. Notch 310.

步驟三：如圖4所示，在所述第一缺口310中鍍設一厚度均勻的第一金屬層20a。Step 3: As shown in FIG. 4, a first metal layer 20 a with a uniform thickness is plated in the first notch 310.

步驟四：如圖5所示，清除所述第一感光層300，從而使得所述第一金屬層20a完全暴露而形成第一線路層20。Step 4: As shown in FIG. 5, the first photosensitive layer 300 is removed, so that the first metal layer 20 a is completely exposed to form the first circuit layer 20.

所述第一線路層20具有多個焊墊21。The first circuit layer 20 has a plurality of bonding pads 21.

步驟五：如圖6所示，在所述第一線路層20上形成一第一防焊層40。Step 5: As shown in FIG. 6, a first solder resist layer 40 is formed on the first circuit layer 20.

所述第一防焊層40為絕緣材料，其包覆所述第一線路層20。The first solder resist layer 40 is an insulating material, which covers the first circuit layer 20.

步驟六：如圖7所示，在所述第一防焊層40外依次壓合形成一熱隔離膜400、第二承載板500。Step 6: As shown in FIG. 7, a thermal isolation film 400 and a second carrier plate 500 are sequentially laminated on the first solder resist layer 40.

所述熱隔離膜400位於所述第一防焊層40與所述第二承載板500之間。所述第二承載板500包括第二基底510以及形成於所述第二基底510兩側表面的第二覆銅層520。所述第二承載板500的材質與所述第一承載板200的材質相同。所述第二覆銅層520的厚度小於所述第二基底510的厚度。The thermal isolation film 400 is located between the first solder resist layer 40 and the second carrier plate 500. The second carrier board 500 includes a second substrate 510 and second copper-clad layers 520 formed on both surfaces of the second substrate 510. The material of the second bearing plate 500 is the same as that of the first bearing plate 200. The thickness of the second copper-clad layer 520 is smaller than the thickness of the second substrate 510.

步驟七：如圖8所示，將所述第一承載板200從所述第一線路層20、第一防焊層40分離。Step 7: As shown in FIG. 8, the first carrier board 200 is separated from the first circuit layer 20 and the first solder resist layer 40.

步驟八：如圖9所示，進一步蝕刻所述第一線路層20，從而使得所述第一線路層20的外表面低於所述第一防焊層40的外表面。Step 8: As shown in FIG. 9, the first circuit layer 20 is further etched so that the outer surface of the first circuit layer 20 is lower than the outer surface of the first solder resist layer 40.

步驟九：如圖10所示，在所述第一線路層20外形成一絕緣層10。Step 9: As shown in FIG. 10, an insulating layer 10 is formed outside the first circuit layer 20.

所述絕緣層10由可彎折的熱固型的防焊油墨組成，其厚度較薄而且具有較好的柔性。在本發明實施例中，所述絕緣層10的厚度位於15-50微米之間。所述絕緣層10具有第一表面101及與第一表面101相對的第二表面102。所述絕緣層10中部隔斷形成一第一間隔部104。The insulating layer 10 is made of a bendable thermosetting solder resist ink, and has a thin thickness and good flexibility. In the embodiment of the present invention, the thickness of the insulating layer 10 is between 15-50 micrometers. The insulating layer 10 has a first surface 101 and a second surface 102 opposite to the first surface 101. A middle portion of the insulating layer 10 is partitioned to form a first spacer 104.

步驟十：如圖11所示，通過鐳射在所述絕緣層10上開設形成多個導電孔103。Step 10: As shown in FIG. 11, a plurality of conductive holes 103 are formed in the insulating layer 10 by laser.

所述導電孔103的橫截面呈梯形，其孔徑自第一表面101朝向第二表面102方向逐漸增加。The cross-section of the conductive hole 103 is trapezoidal, and its aperture gradually increases from the first surface 101 toward the second surface 102.

在本步驟中，依據制程需要，開設形成所述導電孔103之前還進一步可以包括在所述絕緣層10的第二表面102上形成一層導電結合層。In this step, according to the requirements of the manufacturing process, before the conductive hole 103 is formed, it may further include forming a conductive bonding layer on the second surface 102 of the insulating layer 10.

步驟十一：如圖12所示，在所述絕緣層10的第二表面壓合形成一第二感光層600。Step 11: As shown in FIG. 12, a second photosensitive layer 600 is formed by laminating on the second surface of the insulating layer 10.

所述第二感光層600包覆所述絕緣層10的第二表面102以及所述間隔部104。The second photosensitive layer 600 covers the second surface 102 and the spacer 104 of the insulating layer 10.

步驟十二：如圖13所示，通過曝光顯影技術，使得所述第二感光層600上形成若干第二缺口601。Step 12: As shown in FIG. 13, a plurality of second notches 601 are formed on the second photosensitive layer 600 through exposure and development technology.

步驟十三：如圖14所示，在所述第二缺口601中鍍設形成第二金屬層30a。Step 13: As shown in FIG. 14, a second metal layer 30 a is formed in the second notch 601 by plating.

步驟十四：如圖15所示，清除所述第二感光層600從而完全暴露出所述第二金屬層30a而形成第二線路層30。Step 14: As shown in FIG. 15, the second photosensitive layer 600 is removed to completely expose the second metal layer 30 a to form a second circuit layer 30.

步驟十五：如圖16所示，在所述第二線路層30外形成第二防焊層50，以及使得所述第二防焊層50對應所述第一間隔部104位置開設形成第二間隔部501。Step 15: As shown in FIG. 16, a second solder resist layer 50 is formed outside the second circuit layer 30, and a second solder resist layer 50 is opened corresponding to the position of the first spacer 104 to form a second solder resist layer 50. Spacer 501.

所述第二防焊層50填充於所述第二線路層30上，且所述第二防焊層50上包括多個焊接孔51。所述第二間隔部501以及所述第一間隔部104相互貫通且共同形成一容置區150。The second solder mask layer 50 is filled on the second circuit layer 30, and the second solder mask layer 50 includes a plurality of solder holes 51. The second spacer portion 501 and the first spacer portion 104 penetrate each other and form an accommodating area 150 together.

步驟十六：如圖17所示，在所述容置區150中設置一晶片60，所述晶片60與所述第一線路層20的焊墊21電連接。Step 16: As shown in FIG. 17, a wafer 60 is disposed in the accommodating area 150, and the wafer 60 is electrically connected to the bonding pad 21 of the first circuit layer 20.

步驟十七：如圖18所示，在所述容置區中填充封裝膠體70以包覆所述晶片60，以及在所述第二防焊層50的焊接孔51中鍍設形成焊球80。Step seventeen: as shown in FIG. 18, filling the accommodating area 70 in the accommodating area to cover the wafer 60, and forming a solder ball 80 in the welding hole 51 of the second solder mask layer 50. .

步驟十八：如圖19所示，將所述第二承載板500與所述第一防焊層40分離，從而制得本發明所述線路載板100。Step 18: As shown in FIG. 19, the second carrier board 500 is separated from the first solder resist layer 40, so that the circuit carrier board 100 of the present invention is obtained.

在本發明所述線路載板100的製造方法中，通過在所述第一承載板200和第二承載板500而鍍設形成第一線路層20和第二線路層30，因此可以製作更為細化的第一線路層20和第二線路層30。另外，所述絕緣層10採用可彎折的熱固型的防焊油墨組成，其厚度較薄而且柔性較好，因此不但可減小絕緣層10自身的厚度，同時避免了所述第一承載板200、第二承載板500在拆除或分離時因應力集中而造成第一線路層20、第二線路層30發生翹、彎折等現象。In the manufacturing method of the circuit carrier board 100 according to the present invention, the first circuit board 20 and the second circuit board 30 are formed by plating on the first carrier board 200 and the second carrier board 500, so that more The thinned first circuit layer 20 and the second circuit layer 30. In addition, the insulating layer 10 is made of a bendable thermosetting solder resist ink, and its thickness is thin and flexible, so it can not only reduce the thickness of the insulating layer 10 itself but also avoid the first load When the board 200 and the second carrier board 500 are removed or separated due to stress concentration, the first circuit layer 20 and the second circuit layer 30 are warped or bent.

進一步地，本發明所述線路載板100通過開設形成容置區，使得所述晶片60設置于所述容置區內與第一線路層20電連接，從而進一步地降低了線路載板100的厚度。Further, the circuit carrier board 100 of the present invention is formed to form an accommodating area, so that the chip 60 is disposed in the accommodating area and electrically connected to the first circuit layer 20, thereby further reducing the thickness.

可以理解的是，對於本領域的普通技術人員來說，可以根據本發明的技術構思做出其它各種相應的改變與變形，而所有這些改變與變形都應屬於本發明的權利要求的保護範圍。It can be understood that for a person of ordinary skill in the art, other various corresponding changes and modifications can be made according to the technical concept of the present invention, and all these changes and modifications should fall within the protection scope of the claims of the present invention.

100‧‧‧線路載板 100‧‧‧line carrier board

10‧‧‧絕緣層 10‧‧‧ Insulation

20‧‧‧第一線路層 20‧‧‧First circuit layer

30‧‧‧第二線路層 30‧‧‧Second line layer

20a‧‧‧第一金屬層 20a‧‧‧First metal layer

30a‧‧‧第二金屬層 30a‧‧‧Second metal layer

40‧‧‧第一防焊層 40‧‧‧First solder resist

50‧‧‧第二防焊層 50‧‧‧Second solder mask

101‧‧‧第一表面 101‧‧‧first surface

102‧‧‧第二表面 102‧‧‧Second surface

103‧‧‧導電孔 103‧‧‧ conductive hole

104‧‧‧第一間隔部 104‧‧‧First spacer

501‧‧‧第二間隔部 501‧‧‧Second Spacer

21‧‧‧焊墊 21‧‧‧Soldering pad

51‧‧‧焊接孔 51‧‧‧welding hole

80‧‧‧焊球 80‧‧‧Solder Ball

60‧‧‧晶片 60‧‧‧Chip

70‧‧‧封裝膠體 70‧‧‧ encapsulated colloid

200‧‧‧第一承載板 200‧‧‧ the first bearing plate

210‧‧‧第一基底 210‧‧‧ the first base

220‧‧‧第一覆銅層 220‧‧‧The first copper layer

300‧‧‧第一感光層 300‧‧‧first photosensitive layer

400‧‧‧熱隔離膜 400‧‧‧thermal insulation film

500‧‧‧第二承載板 500‧‧‧Second loading plate

600‧‧‧第二感光層 600‧‧‧Second photosensitive layer

601‧‧‧第二缺口 601‧‧‧second gap

圖1所示為本發明一實施例中所述線路載板示意圖。FIG. 1 is a schematic diagram of a circuit carrier board according to an embodiment of the present invention.

圖2-19所示為本發明所述線路載板的製造方法示意圖。2-19 are schematic diagrams showing a method for manufacturing a circuit carrier board according to the present invention.

無no

無no

Claims (10)

一種線路載板，包括一絕緣層、分別位於所述絕緣層兩側表面的第一線路層、第二線路層、以及位於所述第一線路層一側表面包覆所述第一線路層的第一防焊層、位於所述第二線路層一側表面包覆所述第二線路層的第二防焊層，其改良在於：所述絕緣層中部間斷而形成一第一間隔部，所述第二防焊層對應所述第一間隔部形成一第二間隔部，所述第一間隔部和第二間隔部相互貫通且共同形成一容置區，一晶片設置于所述容置區中與所述第一線路層電連接。A circuit carrier board includes an insulating layer, a first circuit layer, a second circuit layer located on both surfaces of the insulating layer, and a first circuit layer covering the first circuit layer on a surface of the first circuit layer. The improvement of the first solder mask layer and the second solder mask layer on the side of the second circuit layer that covers the second circuit layer is that the middle portion of the insulation layer is interrupted to form a first spacer portion, so that The second solder resist layer forms a second spacer portion corresponding to the first spacer portion, the first spacer portion and the second spacer portion penetrate each other and together form an accommodation area, and a wafer is disposed in the accommodation area. Is electrically connected to the first circuit layer. 如申請專利範圍第1項所述線路載板，其中：所述第一線路層具有多個焊墊，所述晶片通過所述焊墊與所述第一線路層電連接。According to the circuit carrier board described in the first item of the patent application scope, wherein the first circuit layer has a plurality of bonding pads, and the wafer is electrically connected to the first circuit layer through the bonding pads. 如申請專利範圍第1項所述線路載板，其中：所述絕緣層由可彎折的熱固型防焊油墨組成，所述絕緣層的厚度位於15-50μm之間。According to the circuit carrier board described in the first item of the patent application scope, wherein the insulating layer is composed of a bendable thermosetting solder resist ink, and the thickness of the insulating layer is between 15-50 μm. 如申請專利範圍第1項所述線路載板，其中：所述絕緣層具有第一表面及與所述第一表面相對的第二表面，所述第一線路層設置於所述絕緣層的第一表面上，所述第二線路層設置於所述絕緣層的第二表面上，所述絕緣層上開設有貫穿第一表面、第二表面的的若干導電孔。According to the circuit carrier board according to item 1 of the scope of patent application, wherein the insulating layer has a first surface and a second surface opposite to the first surface, and the first circuit layer is disposed on the first of the insulating layer. On one surface, the second circuit layer is disposed on the second surface of the insulation layer, and the insulation layer is provided with a plurality of conductive holes penetrating the first surface and the second surface. 如申請專利範圍第4項所述線路載板，其中：所述第二線路層通過所述導電孔與所述第一線路層電連接。The circuit carrier board according to item 4 of the scope of patent application, wherein the second circuit layer is electrically connected to the first circuit layer through the conductive hole. 如申請專利範圍第1項所述線路載板，其中：所述第二防焊層填充於所述第二線路層中，所述第二防焊層上開設有多個焊接孔,用於填充焊料而形成焊球。For example, the circuit carrier board according to item 1 of the scope of patent application, wherein the second solder mask layer is filled in the second circuit layer, and a plurality of solder holes are provided on the second solder mask layer for filling. Solder to form solder balls. 如申請專利範圍第1項所述線路載板，其中：所述容置區中進一步填充有封裝膠體，所述封裝膠體包覆所述晶片。According to the circuit carrier board described in the first item of the patent application scope, wherein the accommodating area is further filled with an encapsulating gel, and the encapsulating gel covers the wafer. 一種線路載板的製造 方法，包括如下步驟： 提供一第一承載板，所述第一承載板包括一第一基底以及設置於所述第一基底一側表面的第一覆銅層； 在所述第一承載板的第一覆銅層上形成第一感光層，並通過曝光顯影技術使得所述第一感光層上形成若干第一缺口； 在所述第一缺口中鍍設一厚度均勻的第一金屬層； 清除所述第一感光層，從而使得所述第一金屬層完全暴露而形成第一線路層； 在所述第一線路層上形成一第一防焊層； 在所述第一防焊層外依次壓合形成一層熱隔離膜、第二承載板，所述第二承載板包括第二基底以及形成於所述第二基底兩側表面的第二覆銅層； 將所述第一承載板從所述第一線路層、第一防焊層上分離； 進一步蝕刻所述第一線路層，從而使得所述第一線路層的外表面低於所述第一防焊層的外表面； 在所述第一線路層外形成一絕緣層，所述絕緣層中部隔斷形成一第一間隔部； 通過鐳射在所述絕緣層上開設形成多個導電孔； 在所述絕緣層的第二表面壓合形成一第二感光層； 通過曝光顯影技術，使得所述第二感光層上形成若干第二缺口； 在所述第二缺口中鍍設形成第二金屬層； 清除所述第二感光層從而完全暴露出所述第二金屬層而形成第二線路層； 在所述第二線路層外形成第二防焊層，使得所述第二防焊層對應所述第一間隔部位置開設形成第二間隔部，所述第二間隔部以及所述第一間隔部相互貫通且共同形成一容置區，所述第二防焊層上包括多個焊接孔； 在所述容置區中設置一晶片，使得所述晶片與所述第一線路層電連接； 在所述容置區中填充封裝膠體以包覆所述晶片，以及在所述第二防焊層的焊接孔中鍍設形成焊球； 將所述第二承載板與所述第一防焊層分離。A method for manufacturing a circuit carrier board includes the following steps: providing a first carrier board, the first carrier board including a first substrate and a first copper-clad layer disposed on a side surface of the first substrate; A first photosensitive layer is formed on the first copper-clad layer of the first carrier plate, and a plurality of first gaps are formed on the first photosensitive layer by exposure and development technology; a uniform thickness is plated in the first gaps. A first metal layer; removing the first photosensitive layer so that the first metal layer is completely exposed to form a first wiring layer; forming a first solder resist layer on the first wiring layer; A solder resist layer is sequentially laminated to form a layer of a thermal insulation film and a second carrier plate. The second carrier plate includes a second substrate and second copper-clad layers formed on both surfaces of the second substrate. The first carrier board is separated from the first circuit layer and the first solder mask layer; the first circuit layer is further etched so that an outer surface of the first circuit layer is lower than that of the first solder mask layer Outer surface; the shape of the first circuit layer Forming an insulating layer, the middle of the insulating layer being partitioned to form a first spacer; forming a plurality of conductive holes on the insulating layer by laser; forming a second photosensitive layer by pressing on the second surface of the insulating layer; Through exposure and development technology, a plurality of second notches are formed on the second photosensitive layer; a second metal layer is formed by plating in the second notches; the second photosensitive layer is removed to completely expose the second metal Layer to form a second circuit layer; forming a second solder mask layer outside the second circuit layer, so that the second solder mask layer is opened corresponding to the position of the first spacer to form a second spacer, and the second The spacer portion and the first spacer portion penetrate each other and form an accommodating area together, and the second solder resist layer includes a plurality of welding holes; a wafer is disposed in the accommodating area so that the wafer and the Electrically connecting the first circuit layer; filling an encapsulant in the accommodating area to cover the wafer, and plating to form a solder ball in a welding hole of the second solder mask layer; loading the second carrier Board is separated from the first solder mask 如申請專利範圍第8項所述線路載板的製造方法，其中：所述第一承載板的厚度位於150-300μm之間，且所述第一覆銅層的厚度小於所述第一基底的厚度。According to the method for manufacturing a circuit carrier board according to item 8 of the scope of patent application, wherein the thickness of the first carrier board is between 150-300 μm, and the thickness of the first copper-clad layer is smaller than that of the first substrate. thickness. 如申請專利範圍第8項所述線路載板的製造方法，其中：所述絕緣層由可彎折的熱固型防焊油墨組成，所述絕緣層的厚度位於15-50μm之間。According to the method for manufacturing a circuit carrier board according to item 8 of the scope of the patent application, wherein the insulating layer is composed of a bendable thermosetting solder resist ink, and the thickness of the insulating layer is between 15-50 μm.
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