JP4638657B2 - Electronic component built-in multilayer board - Google Patents

Electronic component built-in multilayer board Download PDF

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JP4638657B2
JP4638657B2 JP2003075977A JP2003075977A JP4638657B2 JP 4638657 B2 JP4638657 B2 JP 4638657B2 JP 2003075977 A JP2003075977 A JP 2003075977A JP 2003075977 A JP2003075977 A JP 2003075977A JP 4638657 B2 JP4638657 B2 JP 4638657B2
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Prior art keywords
layer
electronic component
transition layer
pad
diameter
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JP2004288711A (en
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政志 宮崎
達郎 猿渡
光広 高山
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太陽誘電株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic component built-in type multilayer substrate, and more particularly to an electronic component built-in type multilayer substrate in which an electronic component in which a transition layer having an arbitrary height dimension is formed on a die pad.
[0002]
[Prior art]
An electronic component built-in type multi-layer substrate is an “embedded” electronic component such as a semiconductor integrated circuit (hereinafter abbreviated as “IC”) chip in a multilayer printed wiring board (in this specification, “built-in” for convenience). Expresses)) and is composed. Since the electronic component and the printed wiring board are directly connected by a via hole or the like, for example, a connecting member (wire, lead or bump) in a mounting method such as wire bonding, TAB (Tape Automated Bonding) or flip chip Etc.) is not required. Therefore, various problems (disconnection, contact failure, corrosion, etc.) related to those connecting members do not occur, and high reliability is obtained.
[0003]
<First Conventional Example: For example, see Patent Document 1>
FIG. 7 is a cross-sectional view (a) of the first conventional example and an enlarged cross-sectional view (b) thereof. In these figures, the electronic component built-in multilayer substrate 1 has a multilayer structure of one or more layers, for example, a three-layer structure, and an arbitrary layer (first layer in the figure) is a heat sink using aluminum or the like. A core substrate 3 having a predetermined thickness dimension Ha is laminated on the plate 2, and an electronic component 5 is placed in a recess (also simply referred to as a depression or a cavity) 4 formed in the core substrate 3. After fixing the bottom surface of the component 5 and the heat sink plate 2 with an adhesive, the gap between the recesses 4 is filled with an insulating resin 6 and sealed.
[0004]
Here, the electronic component 5 has an arbitrary number (for convenience, three in the figure) of electrodes (hereinafter referred to as “die pads”) 7 formed on the upper surface 5a and covers the upper surface 5a. A hole 8a is formed in the passivation film 8 so as to expose a part of each surface of the die pad 7 and has a predetermined height that is electrically connected to the die pad 7 through the hole 8a. A transition layer 9 having a dimension Hb is provided. More specifically, the transition layer 9 includes a small width portion 9a having a width dimension substantially equal to the opening dimension Da of the hole 8a formed in the passivation film 8, and a die pad 7 continuous with the upper portion of the small width portion 9a. It consists of a large part 9b having a width dimension Dc larger than the width dimension Db, and the total height dimension of the small width part 9a and the large part 9b is Hb. The surface of the transition layer 9 is roughened to increase the bonding strength with the insulating resin 6. In the example shown in the drawing, the processed surface subjected to the roughening treatment is indicated by sawtooth wavy lines. .
[0005]
The transition layer 9 is made of a highly conductive material such as copper, and the diameter dimension of the transition layer 9 (however, the width dimension when facing the drawing: Dc) is a hole 8a formed on the die pad 7. Larger than the opening diameter (Da) of (Dc> Da). This is because the description of the drawing (especially FIG. 6) of the cited reference 1 and the paragraph [0037] of the cited cited reference 1 (especially “a larger diameter transition layer is interposed on the pad of the IC chip”). ).
[0006]
In the illustrated electronic component built-in multilayer substrate 1, an insulating layer 10 having a predetermined thickness is stacked on the first layer having such a structure, and a required number of via holes 11 and a predetermined number of via holes 11 are formed in the insulating layer 10. A conductor circuit 12 having a required shape is formed to form a second layer, and an insulating layer 13 having a predetermined thickness is further laminated on the second layer, and a required number of via holes are formed in the insulating layer 13. 14 and a conductor circuit 15 of a required shape are formed to form a third layer, and solder bumps 16 for connecting to an external substrate such as a daughter board are formed on the uppermost conductor circuit 15, The entire surface of the uppermost layer except the solder bump 16 formation portion is coated with an insulating film 17.
[0007]
<Second Conventional Example: For example, see Patent Document 2>
As a second conventional example, one in which the diameter dimension (Dc) of the transition layer 9 is “more than” the opening diameter (Da) of the hole 8 a formed on the die pad 7 is known. Specifically, as described in “Claim 2” of Patent Document 2, it is defined that “the width of the transition layer is 1.0 to 30 times the width of the pad”. If attention is paid to “1.0”, which is the numerical value limitation as defined above, “the width of the transition layer = 1.0 times the width of the pad”, this means that the transition layer 9 in the first conventional example described above. This means that the diameter dimension (Dc) is equal to the opening diameter (Da) of the hole 8a formed on the die pad 7 (Dc = Da).
[0008]
<Third Conventional Example: For example, see Patent Document 3>
In the third conventional example, a stud bump is formed on a bonding pad formed on a semiconductor chip, the semiconductor chip is mounted in a concave portion of a printed circuit board, and then the semiconductor chip is embedded by filling the concave portion with an insulating resin. For example, a technique is disclosed in which the head of the stud bump is exposed from the resin layer by drilling with the method described above.
[0009]
[Patent Document 1]
JP 2001-339165 A ([0017]-[0019], [0037], FIG. 6)
[Patent Document 2]
JP 2001-352174 A ([Claim 2])
[Patent Document 3]
Japanese Patent No. 2842378 ([0016]-[0020], FIGS. 1 and 3)
[0010]
[Problems to be solved by the invention]
However, the above first to third conventional examples have the following problems.
(1) In the first conventional example, since the transition layer (diameter Dc)> pat (diameter Da), a crack is likely to occur at the contact point between the edge of the transition layer and the passivation layer. There is a problem that damage to the die occurs when the semiconductor substrate is passed through.
(2) In the second conventional example, the transition layer (diameter Dc) ≧ pat (diameter Da), and particularly when Dc = Da, no damage to the die occurs, but the transition layer and the pad are the same. It is very difficult to form with a width, and there is a problem that it is not practical.
(3) In the third conventional example, since the die pad portion (die pad portion having a high flatness) other than the bump mounting area is in contact with the resin layer, the treatment liquid passes through the bump wall surface during plating or desmear treatment. There is a problem that it easily penetrates into the interface of the layer and peeling occurs.
[0011]
Accordingly, the object of the present invention is to cause die damage from cracks starting from the contact points between the edge of the transition layer and the passivation layer among the above-mentioned problems, and the treatment liquid passes through the wall surface of the bump. Both of the fact that penetration and separation at the interface between the die pad and the resin layer are new findings and are not described in any prior art, so that these problems can be solved simultaneously and are highly reliable. An object of the present invention is to provide an electronic component built-in multilayer substrate having a connection structure.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides an electronic component embedded in a resin layer, a transition layer formed on a pad of the electronic component, a passivation film that covers the pad, and the transition layer. In a substrate with a built-in electronic component comprising a formed via hole and a wiring layer connected to the transition layer through the via hole, the diameter of the transition layer is smaller than the diameter of the pad, and the pad And the transition layer has a roughened portion on the contact surface with the resin layer.
In the present invention, since the diameter of the transition layer is set smaller than the diameter of the pad and larger than the opening diameter of the passivation film covering the periphery of the pad, the corner of the transition layer is not located on the pad. For this reason, even if there is a passivation film below the transition layer, cracks in the passivation film and the structural member (Si, etc.) below the passivation film, regardless of the stress from the top (force generated during resin pressing, etc.) Occurrence is avoided.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a cross-sectional view (a) and an enlarged cross-sectional view (b) of an essential part of a multilayer substrate with a built-in electronic component in an embodiment.
In these drawings, the electronic component built-in multilayer substrate 21 has a multilayer structure of one or more layers. Hereinafter, although not particularly limited, a three-layer structure is used for convenience of explanation. The first layer (corresponding to an arbitrary layer described in the gist of the invention) is obtained by laminating a core substrate 23 made of copper or the like having a predetermined height dimension Ha on a heat sink plate 22 made of aluminum or the like, and its core. Arbitrary electronic components 25 are put into the recesses (or depressions or cavities) 24 formed on the substrate 23, and the bottom surface of the electronic components 25 and the heat sink plate 22 are fixed with an adhesive, and then the gaps in the recesses 24 are insulated The resin 26 is filled and sealed.
[0014]
The electronic component 25 in the present embodiment has an arbitrary number (for convenience, three in the drawing) of die pads (or electrodes or terminals) 27 formed on the upper surface 25a and is formed so as to cover the upper surface 25a. A hole 28a is formed in the passivation film 28 so as to expose a part of the surface of each die pad 27, and a predetermined height is electrically connected to the die pad 27 through the hole 28a. It has a transition layer 29 made of a highly conductive material such as copper having a dimension Hb.
[0015]
The transition layer 29 has a shape with substantially the same width dimension over its entire height, for example, a shape similar to the letter “I” of the alphabet. Specifically, for example, the transition layer 29 The width dimension Dd is smaller than the diameter De of the die pad 27 over the entire height dimension Hb (De> Dd), and the hole 28a formed in the passivation film 28 has a height dimension Hd. They are arranged so as to be larger than the opening dimension Df (Df <Dd). In short, they have a cross-sectional shape of a cylindrical body having a relationship of De> Dd and Df <Dd. Further, the surface of the transition layer 29 in the present embodiment is roughened in order to increase the bonding strength with the insulating resin 26. In the example shown in the drawing, the processed surface subjected to the roughening treatment has a sawtooth shape. It is shown with a wavy line.
[0016]
In the illustrated electronic component built-in multilayer substrate 21, an insulating layer 30 having a predetermined thickness is laminated on the first layer having such a structure, and a required number of via holes 31 and a required shape are formed in the insulating layer 30. The conductive circuit 32 is formed as a second layer, and an insulating layer 33 having a predetermined thickness is further laminated on the second layer, and a predetermined number of via holes 34 are formed in the insulating layer 33. A conductor circuit 35 having a required shape is formed to form a third layer, and a solder bump 36 for connecting to an external substrate such as a daughter board is formed on the uppermost conductor circuit 35, and these solder bumps are formed. The entire surface of the uppermost layer except the portion where 36 is formed is coated with an insulating film 37.
[0017]
Said electronic component 25 is manufactured by the following processes. Here, an IC chip manufacturing process is taken as an example, but the present invention is not limited to this. For example, a passive component such as a resistor, a capacitor, or a coil, or a component including them may be used.
<Fig. 2 (a)>
First, the die pad 27 is formed on the silicon wafer 41 by a known method. The size of the die pad 27 is De.
<Fig. 2 (b)>
Next, a passivation film 28 having a predetermined thickness is formed so as to cover the die pad 27, and a hole 28 a is formed in the passivation film 28 to expose all the die pads 27. The opening size of the hole 28a is Df smaller than the size (De) of the die pad 27.
[0018]
<FIGS. 3A to 3C>
Next, a resist layer 42 is formed so as to cover the entire passivation film 28. Then, an exposure mask 43 having a predetermined size (Dd) opening 43 a is placed on the resist layer 42, and exposure and development are performed to form an opening 42 a in the resist layer 42.
<Fig. 3 (d)>
Next, the transition layer 29 is formed in the opening 42a of the resist layer 42 and the hole 28a of the passivation film 28 by bonder or plating. The material of the transition layer 29 can be arbitrarily selected from copper, nickel, gold, silver, zinc, iron, etc., but the material of the conductor layer (via hole 31) formed in the upper layer in the subsequent process is copper. Then, it is preferable that the material of the transition layer 29 is the same (copper) in terms of affinity.
[0019]
Here, the size (Dd) of the opening 43a of the exposure mask 43 is larger than the opening size Df of the hole 28a formed in the passivation film 28 (Df <Dd) and smaller than the diameter De of the die pad 27 (De>). Dd).
[0020]
<FIGS. 4A to 4C>
Next, the remaining resist layer 42 is removed to expose the transition layer 29, and the exposed surface 29a is roughened by, for example, spraying a roughening liquid such as Meltex CZ8100. . In addition, when the peak to peak of the roughness (unevenness) of the roughening treatment of the exposed surface 29a is Rz, Rz is about 0.1 to 4 μm (preferably, Rz = 0.5 to 2 μm). desirable.
<FIGS. 5A and 5B>
Finally, the silicon wafer 41 is cut into a desired size, and each piece is made into an electronic component 25, which is embedded in an arbitrary layer (first layer for convenience in this embodiment), and the electronic component shown in FIG. The built-in multilayer substrate 21 is manufactured.
[0021]
As described above, in the electronic component built-in multilayer substrate 21 of the present embodiment, the diameter (Dd) of the transition layer 29 is smaller than the diameter (De) of the pad 27 and the opening diameter (Df) of the passivation film 28. Even when the pressure (see the white arrow in FIG. 1B) when the upper layer is stacked is applied to the transition layer 29 because it is larger, that is, the relationship of “De>Dd> Df”. Since a uniform force is applied in the width direction of the transition layer 29, no stress concentration occurs. Therefore, it is possible to avoid a crack in the passivation film 28 and to obtain a specific effect that the reliability of the electronic component 25 can be improved.
[0022]
In the above embodiment, the transition layer 29 having the height dimension Hb substantially equal to the height dimension of the core substrate 23 is taken as an example, but the present invention is not limited to this. For example, it may be a thin film-like transition layer 29b having a height dimension Hb ′ much smaller than Hb (see FIG. 6A). In this case, for example, a via hole 45 is formed in the insulating resin layer 44 laminated on the transition layer 29b, and the via in the upper layer is formed via the via hole 45 and the thin film transition layer 29b. What is necessary is just to connect between the hole 31 (refer Fig.1 (a)) and the die pad 27 of the electronic component 25. FIG.
[0023]
In the above example, the transition layer 29 (or 29b) is formed directly on the die pad 27 of the electronic component 25, but it may be formed indirectly with a conductive film interposed therebetween. That is, a structure of die pad 27 / conductive film / transition layer 29 (or 29b) may be used. In this case, the conductive film can be selected from copper, gold, silver, tin, chromium, titanium, nickel, zinc, cobalt, and the like. The conductive film can be formed by sputtering or plating, and the thickness of the conductive film can be 0.01 to 1.0 μm.
[0024]
【The invention's effect】
According to the present invention, since the diameter of the transition layer is set smaller than the diameter of the pad and larger than the opening diameter of the passivation film covering the periphery of the pad, the corner of the transition layer is not located on the pad. For this reason, even if there is a passivation film under the transition layer, cracks in the passivation film and the structural member (Si, etc.) below the passivation film, regardless of the stress from the top (force generated during resin pressing, etc.) Occurrence can be avoided. Further, by roughening the surface of the transition layer, the bond with the insulating resin can be strengthened to avoid peeling and the like.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view (a) and an enlarged cross-sectional view (b) of a main part of a multilayer substrate with built-in electronic components according to an embodiment.
FIG. 2 is a manufacturing process diagram (No. 1) of an electronic component in the embodiment.
FIG. 3 is a manufacturing process diagram (No. 2) for the electronic component in the embodiment;
FIG. 4 is a manufacturing process diagram (No. 3) of the electronic component in the embodiment.
FIG. 5 is a manufacturing process diagram (No. 4) of the electronic component in the embodiment.
FIG. 6 is an enlarged cross-sectional view of an essential part showing a modification of the electronic component built-in multilayer substrate in the embodiment.
7A is a cross-sectional view showing an example of a conventional electronic component built-in multilayer substrate, and FIG.
[Explanation of symbols]
21 Multi-layer substrate with built-in electronic components 24 Cavity 25 Electronic component 27 Die pad (pad)
28 Passivation film 29 Transition layer 31 Via hole 32 Conductor circuit (wiring layer)

Claims (2)

  1. An electronic component embedded in the resin layer, a transition layer formed on the pad of the electronic component, a passivation film covering the pad, a via hole formed on the transition layer, and via the via hole In an electronic component built-in substrate comprising a wiring layer connected to the transition layer,
    While setting the diameter (Dd) of the transition layer to be smaller than the diameter (De) of the pad and larger than the opening diameter (Df) of the passivation film covering the pad,
    The transition layer has a roughened portion on a contact surface with the resin layer, and has a built-in electronic component type multilayer substrate.
  2. An electronic component embedded in the resin layer, a transition layer formed on the pad of the electronic component, a passivation film covering the pad, a via hole formed on the transition layer, and via the via hole In an electronic component built-in substrate comprising a wiring layer connected to the transition layer,
    An electronic component-embedded multilayer board characterized in that a diameter of the transition layer is set smaller than an opening diameter of a passivation film covering the pad, and a roughened portion is provided on a contact surface with the resin layer.
JP2003075977A 2003-03-19 2003-03-19 Electronic component built-in multilayer board Active JP4638657B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
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US9101075B2 (en) 2013-09-12 2015-08-04 Taiyo Yuden Co., Ltd Substrate with built-in component

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Publication number Priority date Publication date Assignee Title
WO2006006343A1 (en) * 2004-07-14 2006-01-19 Murata Manufacturing Co., Ltd. Piezoelectric device
JP5075424B2 (en) * 2007-02-19 2012-11-21 株式会社フジクラ Manufacturing method of wiring board with built-in electronic components
JP2008244029A (en) * 2007-03-27 2008-10-09 Ngk Spark Plug Co Ltd Wiring board with built-in component, and component used therefor
JP5179856B2 (en) * 2007-06-21 2013-04-10 日本特殊陶業株式会社 Wiring board built-in component and manufacturing method thereof, wiring board
KR101391040B1 (en) * 2007-08-09 2014-04-30 삼성전자주식회사 Printed circuit board and fabricating method thereof and electrical apparatus using the same
US8304915B2 (en) 2008-07-23 2012-11-06 Nec Corporation Semiconductor device and method for manufacturing the same
US9685414B2 (en) 2013-06-26 2017-06-20 Intel Corporation Package assembly for embedded die and associated techniques and configurations

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9101075B2 (en) 2013-09-12 2015-08-04 Taiyo Yuden Co., Ltd Substrate with built-in component

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