JP4208631B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
JP4208631B2
JP4208631B2 JP2003113210A JP2003113210A JP4208631B2 JP 4208631 B2 JP4208631 B2 JP 4208631B2 JP 2003113210 A JP2003113210 A JP 2003113210A JP 2003113210 A JP2003113210 A JP 2003113210A JP 4208631 B2 JP4208631 B2 JP 4208631B2
Authority
JP
Japan
Prior art keywords
formed
cavity
semiconductor chip
copper
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2003113210A
Other languages
Japanese (ja)
Other versions
JP2004319848A (en
Inventor
隆次 小松
Original Assignee
日本ミクロン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本ミクロン株式会社 filed Critical 日本ミクロン株式会社
Priority to JP2003113210A priority Critical patent/JP4208631B2/en
Publication of JP2004319848A publication Critical patent/JP2004319848A/en
Application granted granted Critical
Publication of JP4208631B2 publication Critical patent/JP4208631B2/en
Application status is Active legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor equipment, to form a cavity subjected to spot facing to the wiring board and more particularly, relates to a method of manufacturing a semiconductor equipment for manufacturing a semiconductor device by mounting a semiconductor chip in the cavity.
[0002]
[Prior art]
A wiring board on which a semiconductor chip is mounted is formed with a high density of semiconductor chips and a high density of wiring patterns, while the thickness of the board is reduced. Further, in addition to a product in which a single semiconductor chip is mounted on one package, a composite product in which a plurality of semiconductor chips are mounted on one package is also manufactured.
As a method of manufacturing such a wiring board, a manufacturing method such as a so-called build-up method is performed in which wiring patterns are sequentially stacked while electrically connecting wiring patterns between layers through vias.
[0003]
Recently, a method of forming a wiring board using a copper bump-attached copper foil in which a copper bump is formed integrally with a copper foil has been proposed (see, for example, Patent Document 1 and Patent Document 2). This copper foil with copper bumps can be formed by etching the copper foil to form a wiring pattern, and by forming a copper bump as a via that electrically connects the wiring pattern between the layers, the wiring pattern is laminated. It can utilize for manufacture of the wiring board to do.
Since the copper foil with copper bumps is formed as thin as 100 μm or less, it is possible to reduce the thickness of the wiring board, and since the copper bumps are formed in a small diameter, the wiring pattern is arranged with high density. It becomes possible. Further, by using copper bumps for vias, it is not necessary to form via holes or plating in the insulating layer by laser processing, and the wiring board can be easily manufactured.
[0004]
On the other hand, the present applicant, as a method of manufacturing a wiring board, forms a cavity by a method in which a required part of the inner layer is exposed by performing a counterboring process with a cutting blade from one side of the board on which the wiring pattern is formed on the inner layer. A method of manufacturing a wiring board by mounting a semiconductor chip in a cavity has been proposed (see, for example, Patent Document 3). The method of forming a cavity for mounting a semiconductor chip using the counterbore processing has an advantage that it can be provided as a highly reliable semiconductor device by preventing deformation of the wiring board.
[0005]
[Patent Document 1]
JP 2001-326459 A [Patent Document 2]
JP 2002-26479 A [Patent Document 3]
Japanese Patent Laid-Open No. 2002-26479 [0006]
[Problems to be solved by the invention]
As described above, a method for forming a semiconductor device by mounting a semiconductor chip in a cavity by forming a cavity for mounting a semiconductor chip by applying a counterbore process to a substrate having a wiring pattern formed on the inner layer is formed by thinning the substrate. If possible, the semiconductor device can be thinned. However, in the case of a method for manufacturing a wiring board formed by stacking wiring patterns by a conventional build-up method or the like, there is a problem that the wiring board cannot always be formed effectively thin. There was a problem of becoming complicated.
[0007]
In addition, in order to form a cavity for mounting a semiconductor chip on a wiring board, a method of manufacturing a wiring board by laminating a substrate with a window corresponding to a portion where the cavity is formed, the cavity is formed when the substrates are laminated. If the lower substrate is pushed into the inside of the substrate to form a curved shape, and if the flow of the prepreg is insufficient when laminating the substrate via the prepreg, there will be gaps due to unfilled resin between the laminated substrates There is a problem that the resin oozes into the cavity when it occurs or when the flowability of the prepreg is large.
[0008]
Therefore, the present invention has been made to solve these problems, and an object of the present invention is to provide a semiconductor device capable of easily forming a wiring pattern with high density and easily forming a thin wiring pattern. It is in providing the manufacturing method of a device.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention comprises the following arrangement.
That is, a via hole is formed from the lower surface side of a laminated board in which a copper foil is deposited on the outer surface and a wiring pattern is formed in a pad shape on the inner layer, and a conductor layer is formed on the inner surface of the via hole by plating to form the pad shape A wiring pattern is formed on the outer surface of the laminated board by forming vias connected to the wiring pattern formed on the substrate, and etching the copper foil into a predetermined pattern, and the wiring formed in the pad shape from the upper surface side of the laminated board While controlling the cutting position while detecting the height position of the pattern with the cutting blade, it performs counterboring, cutting the required part of the laminated plate to form a cavity for mounting semiconductor chips, and the semiconductor on the inner surface of the cavity The wiring pattern formed in the pad shape is exposed on the chip mounting surface, the semiconductor chip is mounted in the cavity, the resin is filled in the cavity, and the semiconductor chip is mounted. Characterized in that it stop.
[0010]
Also, via holes are formed from the lower surface side of the laminated board with copper foil deposited on the outer surface, a conductor layer is formed on the inner surface of the via holes by plating, and the copper foil is etched into a predetermined pattern By forming a wiring pattern on the outer surface of the laminated plate, the cutting position is controlled while detecting the height position of the via with a cutting blade from the upper surface side of the laminated plate, The required part is cut to form a cavity for mounting the semiconductor chip, and the end face of the via is exposed on the mounting surface of the semiconductor chip on the inner surface of the cavity, the semiconductor chip is mounted in the cavity, and the cavity is filled with resin. Then, the semiconductor chip is sealed.
[0011]
Further , it is effective to form the via as a filled via and expose the end face of the via by counterboring.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings. 1 and 2 are explanatory views showing a method of manufacturing a semiconductor device according to the present invention.
FIG. 1A shows a resin substrate 10 which is a core portion of a wiring substrate constituting a semiconductor device. The resin substrate 10 is formed by forming through holes in a double-sided copper-clad substrate, plating through holes in the through holes to form conductor portions 12 in the through holes, and etching the copper foil on both sides of the substrate into a predetermined pattern. This is obtained by forming the wiring pattern 14 on both sides. The conductor portion 12 may be formed so as to fill the through hole by plating, or a conductor layer may be formed on the inner wall surface of the through hole so that the wiring patterns 14 on both sides are electrically connected. .
[0013]
In an actual manufacturing process, a large-sized resin substrate for taking a large number is used as a workpiece, and the large-sized workpiece is subjected to necessary processing to manufacture a semiconductor device. In FIG. 1 (a), for the sake of explanation, one unit portion, which is an individual semiconductor device, of a multi-piece resin substrate is shown. The same applies to the following drawings.
[0014]
FIG. 1B shows a process of forming a wiring pattern by laminating an upper layer and a lower layer of the resin substrate 10. In the same figure, 16 and 18 are copper foils with copper bumps used for forming a wiring pattern. 16a and 16b are copper bumps integrally formed on the copper foil 16 with copper bumps, and 18a is a copper bump integrally formed on the copper foil 18 with copper bumps. The copper bumps 16a and 18a are formed in alignment with the planar arrangement of the wiring pattern 14 formed on the resin substrate 10, and the copper bump 16b is aligned with the planar arrangement of connection electrodes of the semiconductor chip mounted on the substrate. Is formed.
[0015]
In this embodiment, since the semiconductor chip is electrically connected to the copper bump 16b by flip chip connection, the copper bump 16b has the same planar arrangement as the connection electrode of the semiconductor chip. However, the semiconductor chip and the copper bump 16b are connected to each other. In the case of electrical connection by wire bonding, the arrangement position of the copper bump 16b is set in accordance with the bonding position with the semiconductor chip.
[0016]
In FIG. 1B, reference numeral 20 denotes a prepreg for integrally bonding the copper foils 16 and 18 with copper bumps to the resin substrate 10. When the copper bumps 16 and 18 with copper bumps are pressed and heated so that the resin substrate 10 is sandwiched from both sides together with the prepreg 20, the top portions of the copper bumps 16 a and 18 a of the copper foil 16 with copper bumps are formed on the resin substrate 10. The copper bumps 16a and 18a and the wiring pattern 14 are joined in an electrically conductive state. The copper bumps 16a and 18a are formed so that the tops thereof have a small diameter and the wiring pattern 14 is embedded so as to ensure electrical conduction.
Then, the prepreg is melted and cured, so that the copper bumps 16 and 18 with the copper bumps 16 and 18 are integrally bonded to the resin substrate 10 in a state where the copper bumps 16a and 18a are hard to be inserted into the wiring pattern 14. FIG. 1C shows a state in which the copper bumps 16 and 18 with copper bumps are bonded to the resin substrate 10 via the prepreg 20.
[0017]
In FIG. 2A, after copper foils 16 and 18 with copper bumps are bonded to the resin substrate 10, the copper foils 16 and 18 with copper bumps are etched into a predetermined pattern. A state in which the wiring patterns 17 and 19 are formed is shown.
Since the copper foils 16 and 18 with the copper bumps are integrally formed with the copper foil and the copper bumps 16a, 16b and 18a in advance, the copper bumps 16a, 16b and 18a are formed by etching the copper foil to form a wiring pattern. The wiring patterns 17 and 19 can be obtained in an electrically connected state.
[0018]
In FIG. 2B, the substrate is counterbored from one side of the substrate opposite to the side where the copper bumps 16b connected to the semiconductor chip are formed, thereby forming a cavity 22 for mounting the semiconductor chip. Shows the state. In counterbore processing, a cavity 22 is formed by cutting a required portion of the prepreg 20 and the resin substrate 10 from the one surface side of the substrate while rotating the counterbore cutting blade, and cutting the required portions of the prepreg 20 and the resin substrate 10.
In this embodiment, the end face A of the copper bump 16b formed in an upright shape on the lower surface of the substrate is subjected to counterboring so as to be exposed on the mounting surface on the inner surface of the cavity 22 on which the semiconductor chip is mounted. By controlling the cutting position by the cutting blade while detecting the height position of the end surface of the copper bump 16b by the cutting blade, the cavity 22 can be formed to open on one surface side of the substrate as shown in the figure. it can.
[0019]
After the cavities 22 are formed by counterboring, the exposed end surfaces of the copper bumps 16b are subjected to necessary plating such as nickel plating and gold plating, and the semiconductor chips 30 are mounted in the cavities 22 with a large workpiece. . Note that the semiconductor chip 30 may be mounted individually after a large workpiece is cut into pieces.
FIG. 2 (c) shows a state in which the connection electrode of the semiconductor chip 30 and the copper bump 16 b are aligned, the semiconductor chip 30 is mounted by flip chip connection, and then the semiconductor chip 30 is underfilled with the resin 24. . In the drawing, the outer surface of the semiconductor chip 30 is sealed with the resin 24. However, the resin 24 only needs to be able to underfill at least the connection portion between the connection electrode of the semiconductor chip 30 and the copper bump 30, and to the outer surface portion of the semiconductor chip 30. It does not have to be completely sealed.
[0020]
FIG. 3 shows a state in which a semiconductor device that can be mounted by bonding the external connection terminal 26 to the wiring pattern 19 of the substrate is formed. The example shown in FIG. 3 is an example formed as a face-down type semiconductor device. Of course, the semiconductor device is not limited to the face-down type.
The copper bumps 16 a and 18 a are used as vias for electrically connecting the wiring patterns between the layers, and the copper bumps 16 b are used as vias for electrically connecting the semiconductor chip 30 and the wiring patterns 17.
The semiconductor device according to the present embodiment is formed using the resin substrate 10 as a core portion and using copper bumps 16 and 18 with copper bumps, and is an extremely thin semiconductor device having a thickness of about 0.3 to 0.5 mm. As obtained.
[0021]
The semiconductor device of the above embodiment is an example in which the semiconductor chip 30 is mounted by flip chip connection, but FIG. 4 shows an example in which the semiconductor chip 30 is mounted by wire bonding connection. Reference numeral 28 denotes a bonding wire. In the case where the semiconductor chip 30 is mounted by wire bonding, a copper bump-attached copper foil in which the copper bump 16b is slightly displaced from the position where the semiconductor chip 30 is mounted in the cavity 22 may be used. You may use what formed the copper bump 16c utilized as a thermal via as the copper foil 16 with a copper bump. The copper bump 16c can also be used as a suitable thermal via by exposing the end face by counterboring.
[0022]
As described above, in the method for manufacturing a semiconductor device according to the present invention, after forming a wiring board using the resin substrate 10 and the copper bumps 16 and 18 with copper bumps, a cavity for mounting the semiconductor chip 30 by counterboring is performed. 22 is formed. In this way, in the method of forming the cavity 22 by counterbore processing, the substrate is not warped in the step of forming the wiring layer by stacking, and the substrate can be manufactured without being deformed, so that a thin semiconductor device is manufactured. It is extremely effective as a method.
Further, in the case of counterbore processing, it is possible to accurately process the depth position of the cavity when forming the cavity 22, and there is an advantage that the cavity can be processed easily and accurately even in a thin package. .
[0023]
In particular, in this embodiment, since the wiring substrate is formed by combining the resin substrate 10 and the copper bumps 16 and 18 with copper bumps, a method of creating a substrate by stacking wiring patterns by a conventional build-up method or the like, In comparison, there is an advantage that a thin substrate can be easily formed. In the case of creating a wiring board using copper foil with copper bumps, the insulating layer is laser processed as in the case of the build-up method to form via holes, or the board is plated to form a conductor layer. This is because the step of forming the film becomes unnecessary.
[0024]
Also, with copper foil with copper bumps, it is possible to form copper bumps with a very small diameter, so it is easy to form copper bumps according to the placement of electrodes in flip chip connection and the placement of bonding parts in wire bonding connection. is there. When a wiring board is formed using copper foil with copper bumps, the copper bumps are used as vias for electrically connecting the wiring patterns between the layers, and the counterbore processing is performed so that the end surfaces of the copper bumps are exposed. Only there is an advantage that the end face of the copper bump can be formed at the connection portion with the semiconductor chip. This is because the entire surface of the end face of the copper bump is a conductor like the filled via, and the entire end face exposed by the counterboring process can be used as a terminal portion for connection.
[0025]
In the semiconductor device shown in FIGS. 3 and 4, the wiring pattern 19 is formed in a region excluding the region where the cavity 22 is formed on the surface side of the wiring substrate on which the semiconductor chip 30 is mounted. Since the semiconductor chip 30 is completely sealed by the resin 24, the entire surface including the area where the cavity 22 is formed can be used as an area for forming a wiring pattern on the surface side on which the semiconductor chip 30 is mounted. It is.
[0026]
FIG. 5 shows an example of manufacturing a semiconductor device in which the entire surface of the substrate including the region where the cavity 22 is formed is used as a region where a wiring pattern is formed.
FIG. 5 (a) shows a semiconductor chip 30 mounted in a cavity formed by counterboring a substrate by flip chip connection, and a copper bump via a prepreg 32 on a substrate 40 in which the semiconductor chip 30 is sealed with a resin 24. The process of joining the attached copper foil 34 is shown. In the case of this manufacturing method, since the copper foil 34 with the copper bumps is bonded to the substrate 40, the cavity 22 is preferably filled with the resin 24. A copper bump 34 a is formed on the copper foil 34 with the copper bump so as to be aligned with the wiring pattern 19 formed on one end face of the substrate 40.
[0027]
FIG. 5B shows a state in which the prepreg 32 and the copper foil 34 with copper bumps are pressed and heated against the substrate 40 and the copper bump 34 with copper bumps 34 is bonded to the substrate 40 through the prepreg 32.
FIG. 5 (c) shows a state in which the wiring pattern 36 is formed on one surface of the substrate 40 by etching the copper foil 34 b of the copper foil 34 with copper bumps into a predetermined pattern. By etching the copper foil 34, a semiconductor device can be obtained in which the entire area of one surface of the substrate 40 is an area where the wiring pattern 36 is formed.
[0028]
Thus, by making the entire region of the substrate including the region where the cavity 22 is formed on the surface side on which the semiconductor chip 30 is mounted as a region for forming the wiring pattern, the wiring pattern can be easily routed in the substrate, It is possible to make a composite such as mounting circuit components on the outer surface of the substrate. Thus, the semiconductor chip 30 is mounted so as to be embedded in the substrate, and can be provided as a semiconductor device having a more complex function.
[0029]
In the above-described embodiment, an example in which one semiconductor chip 30 is mounted in one package has been shown. However, it is of course possible to form a plurality of semiconductor chips in one package, which makes it more complex. It can be provided as a manufactured semiconductor device. Further, by mounting circuit components such as capacitors and resistors on the semiconductor device, a semiconductor device further having a composite function can be obtained.
As a method of mounting a plurality of semiconductor chips and circuit components in one semiconductor device, a method of mounting a plurality of semiconductor chips and circuit components in one cavity is possible, and a counterboring process is performed in one semiconductor device. A method of forming a plurality of cavities by mounting one or a plurality of semiconductor chips in each cavity is also possible.
[0030]
FIG. 6 shows an example in which the wiring board is formed by using only the copper foil with copper bumps without using the resin board 10 as the core of the wiring board.
FIG. 6A shows a process of forming the core portion of the substrate by placing the prepreg 20 between the copper foil 11 with copper bumps 11a on which the copper bumps 11a are formed and the copper foil 11b, and applying pressure and heating. After integrating the copper foil 11 with copper bump 11 and the copper foil 11b through the prepreg 20, the copper foil portion 11 and the copper foil 11b of the copper foil 11 with copper bump are etched into a predetermined pattern to form wiring patterns 11c, 11d. To form a core.
[0031]
In FIG. 6B, copper foils 16 and 18 with copper bumps are added to both surfaces of the core portion formed using the copper foil 11 with copper bumps via the prepreg 20 as shown in FIG. The process of pressure-bonding by heating and heating is shown.
FIG. 6 (c) shows a substrate in which copper bumps 16, 18 with copper bumps are integrally joined via a prepreg 20.
6D shows a state in which the cavity 22 is formed in the substrate by counterboring, the end face of the copper bump 16b is exposed, the semiconductor chip 30 is mounted by flip chip connection, and the semiconductor chip 30 is sealed by the resin 24. Indicates. In this way, it is possible to form a substrate using only a copper foil with copper bumps without using a resin substrate.
[0032]
As described above, in the method for manufacturing a semiconductor device according to the present invention, efficient manufacturing is possible by manufacturing a large substrate for multi-piece manufacturing as a workpiece. Cavity where large-sized copper bumps and copper prepregs are used, and large-sized substrates are formed by pressurizing and heating the copper foils with copper bumps in alignment, and then subjected to counterboring to mount the semiconductor chip 30 At the same time as forming the connection portion, the connection portion that is electrically connected to the semiconductor chip 30 is formed, so that the semiconductor device can be manufactured very efficiently.
[0033]
In the above-described embodiment, a method of manufacturing a semiconductor device in which circuit components such as a semiconductor chip, a capacitor, and a resistor are incorporated in a substrate by applying counterboring as a preferred example of using copper foil with copper bumps has been described. Copper foil with copper bumps can be used effectively as conductors (vias) that electrically connect wiring patterns between layers, and flip chip connection by exposing the entire end face of copper bumps as a conductor when counterbored There is an advantage that it can be suitably used as a terminal. This is not limited to the copper foil with copper bumps, and the method for manufacturing a semiconductor device of the present invention can be similarly applied when a via used for electrical connection between layers is formed as a filled via. The filled via can be formed by, for example, filling the via hole by plating, or forming by a copper or silver paste.
[0034]
In addition to the case of filled vias, via holes are formed by laser processing from the lower surface side of the laminated plate on the laminated plate provided with the wiring pattern 50 in a pad shape on the inner layer, as shown in FIG. 7A. After forming a via layer by forming a conductor layer on the inner surface of the via hole by plating, a cavity 52 for housing a semiconductor chip or the like is formed by performing counterboring from the upper surface side of the laminated plate (FIG. 7 (b)). It is also possible to do. The wiring pattern 50 is exposed on the bottom surface of the cavity 52 by the counterboring process, and the wiring pattern 50 is electrically connected to the connection portion formed on the outer surface of the substrate through the via 54. After a semiconductor chip or a circuit board is mounted in the cavity 52, a prepreg is stacked to fill the cavity 52, and the recess of the via 54 is filled. After forming the via hole and plating the inner surface of the via hole without forming the wiring pattern 50 for the inner layer pad, the concave portion of the via hole is filled with the prepreg, and the inner surface of the cavity 52 is formed by counterboring. The package can also be formed so that the end face of the via is exposed.
[0035]
As described above, when a large number of mounting connection portions exist at very small intervals, such as when a semiconductor chip is mounted by flip chip connection, solder adheres to other connection patterns at the connection portion. It is necessary to avoid problems such as short circuit. Although it is possible to expose these connection parts by machining, as a method of preventing short circuit with other patterns, a form in which only the connection end face is exposed, that is, as described above, copper bumps or A method of counterboring so as to expose end faces of filled vias or the like is extremely effective. The present invention is not limited to the case where the layers are connected by copper bumps, but can also be applied to the case where a package provided with filled vias or inner layer pads is formed as described above.
[0036]
【The invention's effect】
According to the manufacturing method of the semiconductor equipment according to the present invention, it can be provided as a compact product with very thin as products equipped so as to embed the semiconductor chip on a wiring board. In addition , it is possible to provide a semiconductor device having a composite function by mounting a plurality of semiconductor chips in one package .
[Brief description of the drawings]
FIG. 1 is an explanatory view showing a method for manufacturing a semiconductor device according to the present invention.
FIG. 2 is an explanatory view showing the method for manufacturing a semiconductor device according to the present invention.
FIG. 3 is a cross-sectional view of a semiconductor device in a state where external connection terminals are joined.
FIG. 4 is a cross-sectional view showing another embodiment of a semiconductor device.
FIG. 5 is an explanatory diagram showing another method for manufacturing a semiconductor device;
FIG. 6 is an explanatory view showing still another manufacturing method of the semiconductor device.
FIG. 7 is an explanatory view showing still another manufacturing method of the semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Resin board | substrate 11 Copper foil 12 with copper bumps Conductor part 14, 17, 19, 36 Wiring pattern 16, 18, 34 Copper foil 16a, 16b, 16c, 18a with copper bump Copper bump 20, 30, 32 Prepreg 22 Cavity 24 Resin 26 External connection terminal 30 Semiconductor chip 40 Substrate 50 Wiring pattern 52 Cavity

Claims (3)

  1. A via hole is formed from the lower surface side of the laminated board in which copper foil is deposited on the outer surface and a wiring pattern is formed in the inner layer on the inner layer, and a conductor layer is formed on the inner surface of the via hole by plating to form the pad shape. Vias connected to the wiring pattern
    By etching the copper foil into a predetermined pattern, a wiring pattern is formed on the outer surface of the laminate,
    From the upper surface side of the laminated board, the cutting position is controlled while detecting the height position of the wiring pattern formed in the pad shape with a cutting blade, the required part of the laminated board is cut, and the semiconductor chip is cut. Forming the cavity, and exposing the wiring pattern formed in the pad shape on the mounting surface of the semiconductor chip on the inner surface of the cavity,
    A semiconductor chip is mounted in the cavity,
    A method of manufacturing a semiconductor device, wherein a semiconductor chip is sealed by filling a resin into a cavity.
  2. A via hole is formed from the lower surface side of the laminate with the copper foil deposited on the outer surface, a via is formed by forming a conductor layer on the inner surface of the via hole by plating,
    By etching the copper foil into a predetermined pattern, a wiring pattern is formed on the outer surface of the laminate,
    From the upper surface side of the laminated board, while controlling the cutting position while detecting the height position of the via with a cutting blade, the counterbore processing is performed, the required part of the laminated board is cut, and the cavity for mounting the semiconductor chip is formed And exposing the end face of the via to the mounting surface of the semiconductor chip on the inner surface of the cavity,
    A semiconductor chip is mounted in the cavity,
    A method of manufacturing a semiconductor device, wherein a semiconductor chip is sealed by filling a resin into a cavity.
  3. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the via is formed as a filled via.
JP2003113210A 2003-04-17 2003-04-17 Manufacturing method of semiconductor device Active JP4208631B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003113210A JP4208631B2 (en) 2003-04-17 2003-04-17 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003113210A JP4208631B2 (en) 2003-04-17 2003-04-17 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2004319848A JP2004319848A (en) 2004-11-11
JP4208631B2 true JP4208631B2 (en) 2009-01-14

Family

ID=33473209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003113210A Active JP4208631B2 (en) 2003-04-17 2003-04-17 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP4208631B2 (en)

Families Citing this family (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4367414B2 (en) 2004-02-09 2009-11-18 株式会社村田製作所 Component built-in module and manufacturing method thereof
JP2006165252A (en) 2004-12-07 2006-06-22 Shinko Electric Ind Co Ltd Method of manufacturing substrate with built-in chip
JP2007123753A (en) * 2005-10-31 2007-05-17 National Institute Of Advanced Industrial & Technology Interposer, semiconductor chip unit, and semiconductor chip laminated module, as well as manufacturing method therefor
US7519328B2 (en) 2006-01-19 2009-04-14 Murata Manufacturing Co., Ltd. Wireless IC device and component for wireless IC device
US9064198B2 (en) 2006-04-26 2015-06-23 Murata Manufacturing Co., Ltd. Electromagnetic-coupling-module-attached article
KR100797693B1 (en) * 2006-05-24 2008-01-23 삼성전기주식회사 Fabricating Method of Embedded Chip Printed Circuit Board
CN101467209B (en) 2006-06-30 2012-03-21 株式会社村田制作所 Optical disc
WO2008050535A1 (en) 2006-09-26 2008-05-02 Murata Manufacturing Co., Ltd. Electromagnetically coupled module and article with electromagnetically coupled module
WO2008096576A1 (en) 2007-02-06 2008-08-14 Murata Manufacturing Co., Ltd. Packing material provided with electromagnetically coupled module
JP5087302B2 (en) * 2007-03-29 2012-12-05 三洋電機株式会社 Circuit device and manufacturing method thereof
AT555453T (en) 2007-04-06 2012-05-15 Murata Manufacturing Co Radio ic device
JP4697332B2 (en) 2007-04-09 2011-06-08 株式会社村田製作所 Wireless IC device
WO2008136226A1 (en) 2007-04-26 2008-11-13 Murata Manufacturing Co., Ltd. Wireless ic device
JP4666101B2 (en) 2007-04-27 2011-04-06 株式会社村田製作所 Wireless IC device
EP2141636B1 (en) 2007-04-27 2012-02-01 Murata Manufacturing Co. Ltd. Wireless ic device
JP4525859B2 (en) 2007-05-10 2010-08-18 株式会社村田製作所 Wireless IC device
JP4666102B2 (en) 2007-05-11 2011-04-06 株式会社村田製作所 Wireless IC device
US8235299B2 (en) 2007-07-04 2012-08-07 Murata Manufacturing Co., Ltd. Wireless IC device and component for wireless IC device
CN101542831B (en) 2007-07-09 2014-06-25 株式会社村田制作所 Wireless ic device
WO2009011400A1 (en) 2007-07-17 2009-01-22 Murata Manufacturing Co., Ltd. Wireless ic device and electronic apparatus
US20090021352A1 (en) 2007-07-18 2009-01-22 Murata Manufacturing Co., Ltd. Radio frequency ic device and electronic apparatus
CN102915462B (en) 2007-07-18 2017-03-01 株式会社村田制作所 Wireless device ic
JP4434311B2 (en) 2007-07-18 2010-03-17 株式会社村田製作所 Wireless IC device and manufacturing method thereof
KR100895241B1 (en) 2007-09-10 2009-04-28 삼성전기주식회사 Method for manufacturing substrate for package
CN101595599B (en) 2007-12-20 2013-05-01 株式会社村田制作所 Radio IC device
EP2207240B1 (en) 2007-12-26 2013-08-21 Murata Manufacturing Co., Ltd. Antenna apparatus and wireless ic device
WO2009110381A1 (en) 2008-03-03 2009-09-11 株式会社村田製作所 Wireless ic device and wireless communication system
EP2251933A4 (en) 2008-03-03 2012-09-12 Murata Manufacturing Co Composite antenna
JP4404166B2 (en) 2008-03-26 2010-01-27 株式会社村田製作所 Wireless IC device
EP2264831A4 (en) 2008-04-14 2013-12-04 Murata Manufacturing Co Radio ic device, electronic device, and method for adjusting resonance frequency of radio ic device
EP2590260B1 (en) 2008-05-21 2014-07-16 Murata Manufacturing Co., Ltd. Wireless IC device
WO2009142068A1 (en) 2008-05-22 2009-11-26 株式会社村田製作所 Wireless ic device and method for manufacturing the same
CN104077622B (en) 2008-05-26 2016-07-06 株式会社村田制作所 Authenticity wireless systems and wireless devices ic ic device determination method
EP2282372B1 (en) 2008-05-28 2019-09-11 Murata Manufacturing Co. Ltd. Wireless ic device and component for a wireless ic device
JP4557186B2 (en) 2008-06-25 2010-10-06 株式会社村田製作所 Wireless IC device and manufacturing method thereof
EP2306586B1 (en) 2008-07-04 2014-04-02 Murata Manufacturing Co. Ltd. Wireless ic device
CN102124605A (en) 2008-08-19 2011-07-13 株式会社村田制作所 Wireless IC device and method for manufacturing same
JP5429182B2 (en) 2008-10-24 2014-02-26 株式会社村田製作所 Wireless IC device
WO2010050361A1 (en) 2008-10-29 2010-05-06 株式会社村田製作所 Wireless ic device
CN102187518B (en) 2008-11-17 2014-12-10 株式会社村田制作所 Ic antenna and wireless device
CN102273012B (en) 2009-01-09 2013-11-20 株式会社村田制作所 Wireless IC device, wireless IC module and wireless IC module manufacturing method
CN102204011B (en) 2009-01-16 2013-12-25 株式会社村田制作所 High frequency device and wireless IC device
EP2385580B1 (en) 2009-01-30 2014-04-09 Murata Manufacturing Co., Ltd. Antenna and wireless ic device
WO2010119854A1 (en) 2009-04-14 2010-10-21 株式会社村田製作所 Component for wireless ic device and wireless ic device
CN103022661B (en) 2009-04-21 2014-12-03 株式会社村田制作所 Antenna apparatus and resonant frequency setting method of same
WO2010140429A1 (en) 2009-06-03 2010-12-09 株式会社村田製作所 Wireless ic device and production method thereof
WO2010146944A1 (en) 2009-06-19 2010-12-23 株式会社村田製作所 Wireless ic device and method for coupling power supply circuit and radiating plates
WO2011001709A1 (en) 2009-07-03 2011-01-06 株式会社村田製作所 Antenna and antenna module
JP5182431B2 (en) 2009-09-28 2013-04-17 株式会社村田製作所 Wireless IC device and environmental state detection method using the same
CN102577646B (en) 2009-09-30 2015-03-04 株式会社村田制作所 Circuit substrate and method of manufacture thereof
JP5304580B2 (en) 2009-10-02 2013-10-02 株式会社村田製作所 Wireless IC device
JP5522177B2 (en) 2009-10-16 2014-06-18 株式会社村田製作所 Antenna and wireless IC device
JP5418600B2 (en) 2009-10-27 2014-02-19 株式会社村田製作所 Transceiver and RFID tag reader
CN102549838B (en) 2009-11-04 2015-02-04 株式会社村田制作所 The communication terminal and an information processing system
EP2498207B1 (en) 2009-11-04 2014-12-31 Murata Manufacturing Co., Ltd. Wireless ic tag, reader/writer, and information processing system
JP5333601B2 (en) 2009-11-04 2013-11-06 株式会社村田製作所 Communication terminal and information processing system
GB2487491B (en) 2009-11-20 2014-09-03 Murata Manufacturing Co Antenna device and mobile communication terminal
WO2011077877A1 (en) 2009-12-24 2011-06-30 株式会社村田製作所 Antenna and handheld terminal
JP5577734B2 (en) * 2010-02-17 2014-08-27 日本電気株式会社 Electronic device and method for manufacturing electronic device
CN102782937B (en) 2010-03-03 2016-02-17 株式会社村田制作所 The wireless communication device and a radio communication terminal
CN102792520B (en) 2010-03-03 2017-08-25 株式会社村田制作所 The wireless communication module and the wireless communication device
JP5477459B2 (en) 2010-03-12 2014-04-23 株式会社村田製作所 Wireless communication device and metal article
WO2011118379A1 (en) 2010-03-24 2011-09-29 株式会社村田製作所 Rfid system
WO2011122163A1 (en) 2010-03-31 2011-10-06 株式会社村田製作所 Antenna and wireless communication device
JP5170156B2 (en) 2010-05-14 2013-03-27 株式会社村田製作所 Wireless IC device
JP5299351B2 (en) 2010-05-14 2013-09-25 株式会社村田製作所 Wireless IC device
JP2010206215A (en) * 2010-05-20 2010-09-16 Casio Computer Co Ltd Semiconductor device
JP5376060B2 (en) 2010-07-08 2013-12-25 株式会社村田製作所 Antenna and RFID device
WO2012014939A1 (en) 2010-07-28 2012-02-02 株式会社村田製作所 Antenna device and communications terminal device
JP5423897B2 (en) 2010-08-10 2014-02-19 株式会社村田製作所 Printed wiring board and wireless communication system
JP5234071B2 (en) 2010-09-03 2013-07-10 株式会社村田製作所 RFIC module
CN103038939B (en) 2010-09-30 2015-11-25 株式会社村田制作所 Wireless device ic
WO2012050037A1 (en) 2010-10-12 2012-04-19 株式会社村田製作所 Antenna apparatus and communication terminal apparatus
GB2501385B (en) 2010-10-21 2015-05-27 Murata Manufacturing Co Communication terminal device
CN103119785B (en) 2011-01-05 2016-08-03 株式会社村田制作所 The wireless communication device
WO2012096365A1 (en) 2011-01-14 2012-07-19 株式会社村田製作所 Rfid chip package and rfid tag
WO2012117843A1 (en) 2011-02-28 2012-09-07 株式会社村田製作所 Wireless communication device
JP5630566B2 (en) 2011-03-08 2014-11-26 株式会社村田製作所 Antenna device and communication terminal device
EP2618424A4 (en) 2011-04-05 2014-05-07 Murata Manufacturing Co Wireless communication device
JP5482964B2 (en) 2011-04-13 2014-05-07 株式会社村田製作所 Wireless IC device and wireless communication terminal
WO2012157596A1 (en) 2011-05-16 2012-11-22 株式会社村田製作所 Wireless ic device
CN103370834B (en) 2011-07-14 2016-04-13 株式会社村田制作所 The wireless communication device
DE112012001977T5 (en) 2011-07-15 2014-02-20 Murata Manufacturing Co., Ltd. Radio communication equipment
CN203850432U (en) 2011-07-19 2014-09-24 株式会社村田制作所 Antenna apparatus and communication terminal apparatus
CN203553354U (en) 2011-09-09 2014-04-16 株式会社村田制作所 Antenna device and wireless device
WO2013080991A1 (en) 2011-12-01 2013-06-06 株式会社村田製作所 Wireless ic device and method for manufacturing same
WO2013115019A1 (en) 2012-01-30 2013-08-08 株式会社村田製作所 Wireless ic device
WO2013125610A1 (en) 2012-02-24 2013-08-29 株式会社村田製作所 Antenna device and wireless communication device
JP5304975B1 (en) 2012-04-13 2013-10-02 株式会社村田製作所 RFID tag inspection method and inspection apparatus
KR102011840B1 (en) * 2012-10-19 2019-08-19 해성디에스 주식회사 Method of manufacturing circuit board and chip package and circuit board prepared by the same
JP2016201424A (en) * 2015-04-08 2016-12-01 イビデン株式会社 Printed wiring board and method for manufacturing the same

Also Published As

Publication number Publication date
JP2004319848A (en) 2004-11-11

Similar Documents

Publication Publication Date Title
KR101134123B1 (en) Semiconductor device
US7485489B2 (en) Electronics circuit manufacture
JP4343044B2 (en) Interposer, manufacturing method thereof, and semiconductor device
US7816177B2 (en) Semiconductor device and method of manufacturing the same
KR100865426B1 (en) Semiconductor device and its manufacturing method
CN100364090C (en) Light-thin laminated packaged semiconductor device and manufacturing process thereof
DE60224611T2 (en) Printed circuit board with embedded electrical device and method for manufacturing a printed circuit board with embedded electrical device
US8546700B2 (en) Capacitor for incorporation in wiring board, wiring board, method of manufacturing wiring board, and ceramic chip for embedment
US5744758A (en) Multilayer circuit board and process of production thereof
TWI423745B (en) Wiring board with built-in component and method for manufacturing the same
US6861284B2 (en) Semiconductor device and production method thereof
JP3619395B2 (en) A semiconductor element built-in wiring board and a manufacturing method thereof
JP2790122B2 (en) Multilayer circuit board
JP4204989B2 (en) Semiconductor device and manufacturing method thereof
JP4551321B2 (en) Electronic component mounting structure and manufacturing method thereof
JP2009200389A (en) Method of manufacturing electronic component built-in board
US9226382B2 (en) Printed wiring board
US7777328B2 (en) Substrate and multilayer circuit board
US8225502B2 (en) Wiring board manufacturing method
US6985362B2 (en) Printed circuit board and electronic package using same
JPWO2007126090A1 (en) Circuit board, electronic device device, and circuit board manufacturing method
US6297553B1 (en) Semiconductor device and process for producing the same
US20040090758A1 (en) Multi-layered semiconductor device and method of manufacturing same
JP4760930B2 (en) IC mounting substrate, multilayer printed wiring board, and manufacturing method
KR101096614B1 (en) Electronic parts packaging structure and method of manufacturing the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060417

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060928

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070724

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070925

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080930

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20081021

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111031

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111031

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20141031

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250