JP5577734B2 - Electronic device and method for manufacturing electronic device - Google Patents

Description

  The present invention relates to an electronic device and a method for manufacturing the electronic device.

  Ball grid array (BGA) connection is used as one method for connecting a package component on which a semiconductor element is mounted and a mother substrate in order to reduce the size and increase the functionality of an electronic device. BGA connection is a method in which electrodes are formed in a grid pattern on the surface of an interposer substrate on the package component side, solder balls are mounted thereon, solder bumps are produced, and the package components and the mother substrate are connected via the solder bumps. It is. According to the BGA connection, electrodes can be formed using the entire surface of the interposer substrate, and the connection terminal height is also the solder bump height, so that the number of input / output terminals can be increased and the wiring can be shortened. As a result, the above-described electronic device can be reduced in size and functionality.

  On the other hand, in this BGA connection, due to the difference in thermal expansion coefficient between the package component and the mother substrate, stress is generated in the solder bump connecting the package component and the mother substrate, and the solder bump is destroyed by this stress. There is a problem of connection reliability that electrical connection cannot be secured. In order to suppress the stress of the solder bump, it is effective to match the thermal expansion coefficient of the interposer substrate of the package component with the thermal expansion coefficient of the mother substrate. However, semiconductor elements are mounted on the interposer substrate in a sealed connection. The sealing connection of the semiconductor element is important for ensuring the connection reliability of the package component itself. However, it is necessary to seal and mount the semiconductor element on the interposer substrate for connection reliability of solder bumps for BGA connection. It was a factor that decreased the sex. That is, even if the thermal expansion coefficients of the interposer substrate and the mother substrate are matched, the thermal expansion coefficient of the sealing connection portion on the interposer substrate is different from that of the mother substrate. For this reason, stress is generated in the BGA-connected solder bumps immediately below the sealed connection.

  For the purpose of ensuring the connection reliability of the BGA structure, for example, a prohibited area where solder bumps are not arranged in a portion corresponding to the outer periphery of a resin layer encapsulating a semiconductor element (a portion subject to stress) is provided. Providing is under consideration (for example, see Patent Documents 1 to 4). FIG. 8 shows a configuration of an example of the electronic device described in Patent Document 1. As illustrated, the electronic device 100 includes a semiconductor element 101, an interposer substrate 102, and a mother substrate 108. The interposer substrate 102 has solder bumps 107 arranged in an array on the back surface, and the semiconductor element 101 is sealed and mounted on the main surface of the interposer substrate 102 with a sealing resin 104. The solder bumps 107 are not provided in the placement prohibited area 105. A region having a width L centering on a position corresponding to a portion where the outer periphery of the sealing resin 104 is in contact with the main surface of the interposer substrate 102 is the arrangement prohibited area 105. By setting the width L of the prohibited area 105 and the thickness t1 of the sealing resin 104 to a predetermined ratio, stress concentration on the solder bump 107 can be further prevented.

JP-A-11-176980 JP 2007-317754 A JP 2008-60587 A JP 2008-252152 A

  In the electronic devices described in Patent Documents 1 to 4 described above, stress due to mounting of semiconductor elements still occurs on the solder bumps inside the placement prohibited area. Therefore, although connection failure caused by breakage of solder bumps at locations where stress is particularly likely can be avoided, it cannot be said that the connection reliability at other locations where stress is generated has been fundamentally solved. For example, it is considered that the connection reliability is improved by removing all the solder bumps directly under the semiconductor element. However, in this case, when the size of the semiconductor element is increased, the solder bump formation designation prohibition area is increased, and accordingly, there is a problem that restrictions on the board design are increased.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic device having a high connection reliability and a high degree of design freedom in board design, and a method for manufacturing the electronic device.

In order to achieve the above object, an electronic device of the present invention includes:
Including an electronic element, an interposer substrate, and a mother substrate,
An electrode is formed on the main surface of the electronic element,
One surface of the interposer substrate is a wiring surface on which a wiring pattern is formed, and the other surface includes an interposer substrate side pad electrode,
The mother substrate includes a mother substrate side pad electrode on one surface,
An electrode of the electronic element and the wiring pattern are electrically connected via a first bump to form a first connection portion, whereby the electronic element is formed on the interposer substrate. Mounted in a state where the surface and the wiring surface face each other,
The first connection portion is sealed with a sealing resin to form a connection region;
The interposer substrate-side pad electrode and the mother substrate-side pad electrode are electrically connected via a second bump to form a second connection portion, whereby the interposer substrate is formed on the mother substrate. Implemented,
The connection region between the electronic element and the interposer substrate is disposed between the pitches of the interposer substrate side pad electrodes.

In addition, a method for manufacturing an electronic device according to the present invention includes:
Forming a first bump electrode on the outer periphery of the main surface of the electronic element;
A wiring surface having a wiring pattern formed on one surface, and the other surface is selectively encapsulated in a position corresponding to the pitch between the pad electrodes on the wiring surface of the interposer substrate including the pad electrodes. A step of applying
The wiring surface coated with the sealing resin and the main surface are aligned to face each other, the first bump electrode and the wiring pattern are electrically connected, and the electronic element and the interposer A mounting process for mounting in a state of facing on the substrate;
A sealing step of curing the sealing resin;
Forming a second bump on the pad electrode of the interposer substrate;
The second bump formed on the interposer substrate is aligned with the surface on the side including the pad electrode of the mother substrate including the pad electrode on one surface, and the second bump is faced. A step of electrically connecting the interposer substrate and the mother substrate via a gap.

  According to the present invention, it is possible to provide an electronic device having a high connection reliability and a high degree of design freedom in board design, and a method for manufacturing the electronic device.

(A) is a top view which shows the structure of an example in Embodiment 1 of the electronic device of this invention. (B) is sectional drawing seen in the II direction of the electronic device shown to (a). It is sectional drawing explaining an example of the manufacturing method of the said electronic device. It is sectional drawing which shows the structure of an example in Embodiment 2 of the electronic device of this invention. It is sectional drawing which shows the structure of an example in Embodiment 3 of the electronic device of this invention. FIG. 5 is a cross-sectional view illustrating an example of a method for manufacturing the electronic device illustrated in FIG. 4. It is sectional drawing which shows the structure of an example in Embodiment 4 of the electronic device of this invention. FIG. 7 is a cross-sectional view illustrating an example of a method for manufacturing the electronic device illustrated in FIG. 6. FIG. 11 is a cross-sectional view illustrating an example of a configuration of an electronic device described in Patent Document 1.

  According to the present invention, it is possible to improve the connection reliability by suppressing the stress generated in the second bump of BGA connection, and to provide an electronic device and a method for manufacturing the electronic device with a high degree of design freedom in substrate design. Can be provided. That is, in the electronic device of the present invention, since the sealing connection region between the electronic element and the interposer substrate is arranged between the pitches of the pad electrodes on the interposer substrate side, the interposer substrate and the mother substrate are electrically connected. It is possible to suppress the generation of stress at the second bump in the BGA connection to be connected. Therefore, according to the present invention, an electronic device having excellent connection reliability in which an electronic element and an interposer substrate are sealed and connected in a flip chip manner, and the interposer substrate and the mother substrate are connected by a BGA. Can be provided.

  Further, in the method for manufacturing an electronic device according to the present invention, since the sealing connection region between the electronic element and the interposer substrate is limited to the second bump pitch for BGA connection, the bump arrangement for BGA connection is prohibited. There is no need to provide an area to remove the bump. Therefore, it is possible to provide a method for manufacturing an electronic device with high manufacturing efficiency and improved design freedom in substrate design.

  Hereinafter, the electronic device and the method of manufacturing the electronic device of the present invention will be described in detail. However, the present invention is not limited to the following embodiments.

(Embodiment 1)
FIG. 1 shows a configuration of an example of an electronic apparatus according to this embodiment. FIG. 1A is a plan view of the electronic device according to the present embodiment, and FIG. 1B is a cross-sectional view taken along the line II in FIG. 1A. In both the drawings, the same parts are denoted by the same reference numerals. As shown in both the drawings, the electronic device 10 includes a semiconductor element 11, an interposer substrate 12, and a mother substrate 18. A first bump 13 (electrode) is formed on the main surface of the semiconductor element 11 (the lower surface in FIG. 1B). The first bumps 13 are limited to the outer periphery of the semiconductor element 11. As for the interposer substrate 12, one surface (the upper surface in FIG. 1B) is the wiring surface on which the wiring pattern 12a is formed, and the other surface (the lower surface in FIG. 1B) is the interposer. A substrate-side pad electrode 16 is included. The mother substrate 18 includes a mother substrate side pad electrode 19 on one surface. The semiconductor element 11 and the wiring pattern 12a are electrically connected via a first bump 13 formed on the semiconductor element 11 to form a first connection portion, whereby the semiconductor element 11 Is mounted on the interposer substrate 12 with the main surface and the wiring surface facing each other. The first connection portion is sealed with a sealing resin 14 to form a connection region A. The interposer substrate side pad electrode 16 and the mother substrate side pad electrode 19 are electrically connected via a second bump 17 to form a second connection portion, whereby the interposer substrate 12 is It is mounted on the mother board 18. A connection region A (sealing region) between the semiconductor element 11 and the interposer substrate 12 is disposed between the pitches of the interposer substrate side pad electrodes 16. In the present invention, the “main surface” of a semiconductor element, a substrate or the like refers to the widest surface, for example, a so-called upper surface or lower surface, or front surface or back surface.

  In the electronic device of this embodiment, as described above, the interposer substrate 12 and the mother substrate 18 are electrically connected by the second bumps 17 by the BGA method. A sealing area for sealingly connecting the semiconductor element 11 and the interposer substrate 12 is disposed between the pitches of the second bumps 17 connecting the interposer substrate 12 and the mother substrate 18. By adopting such a structure, it is possible to prevent the stress caused by the difference in thermal expansion coefficient between the semiconductor element 11 and the mother substrate 18 from being directly transmitted to the second bump 17 and to improve the connection reliability of the second bump 17. Can be improved.

  As such a configuration, for example, the diameter of the first bump 13 that connects the semiconductor element 11 and the interposer substrate 12 is 100 μm, and the diameter of the second bump 17 that connects the interposer substrate 12 and the mother substrate 18 is as follows. Is 400 μm and the pitch is 800 μm. In this case, the distance between the pitches of the second bumps 17 is 400 μm, and sealing is limited to between the pitches of the second bumps 17 (between the pitches of the pad electrodes 16) by adjusting the chip size and BGA bump arrangement. It is sufficiently possible to arrange stop areas (connection areas). However, these numerical values are examples and do not limit the present invention. In the present invention, the “pitch” of the pad electrode, the second bump, etc. means the interval when a plurality of pad electrodes, the second bump, etc. are arranged at substantially equal intervals. The “substantially equidistant” may have an error of ± 20% or less, for example, even if the arrangement intervals of the plurality of pad electrodes, second bumps, and the like are not strictly equal. The error is preferably ± 10% or less, more preferably ± 5% or less, and ideally 0. In addition, the “between pitches” in this case refers to a region from the end of a specific pad electrode, second bump, etc. to the end of an adjacent pad electrode, second bump, etc. The area | region corresponding to the said area | region in the surface on the opposite side to the surface where 2 bumps etc. are arrange | positioned is also included. “Distance between pitches” refers to the distance from the end of a specific pad electrode, second bump, etc. to the end of an adjacent pad electrode, second bump, etc. in the above case. As described above, the electronic device of the present invention is characterized in that the connection region between the electronic element and the interposer substrate is disposed between the pitches of the interposer substrate side pad electrodes. In this case, “between pitches” is the pitch between the pad electrodes on the surface opposite to the surface on which the pad electrodes are arranged in the interposer substrate. The distance between the pitches of the interposer substrate-side pad electrodes is preferably not too small for ease of arrangement of the connection region, and is not too large from the viewpoint of connection reliability between the interposer substrate and the mother substrate. It is preferable. The distance between the pitches of the interposer substrate-side pad electrodes is not particularly limited, but is, for example, 200 to 1000 μm, preferably 400 to 600 μm.

  In the electronic device of this embodiment, the connection portion (the “first connection portion”) between the semiconductor element 11 and the interposer substrate 12 is sealed in the outer peripheral region A of the semiconductor element 11. The inner region inside the outer peripheral region A is a hollow portion 15 in which the sealing resin 14 does not substantially exist. In the present embodiment, the sealing resin 14 is not present in the hollow portion 15, but the present invention is not limited to this example. For example, the sealing resin 14 may be substantially absent from the hollow portion 15. The term “substantially does not exist” means that, for example, the sealing resin 14 is present in the hollow portion 15 to such an extent that the connection reliability of the second bump 17 that performs BGA connection is not affected. Means good.

  In the electronic device of this embodiment, a semiconductor element is used as the electronic element. The form at the time of mounting of the semiconductor element is not particularly limited. For example, the semiconductor element may be packaged or not packaged. Examples of the mounting mode include a CSP (Chip Size Package) and a bare chip. In addition, the electronic element used for the electronic device of this embodiment is not limited to the above-mentioned semiconductor element, A conventionally well-known electronic element can be used.

  The material of the pad electrode is not particularly limited. Both the pad electrode 16 (interposer substrate side) and the pad electrode 19 (mother substrate side) may be made of the same material as the wiring pattern material described later. For example, after forming a Ni layer on the surface about several μm, Au You may form about 0.03-0.05 micrometer.

  The interposer substrate is not particularly limited, and a conventionally known substrate can be used, but it is preferable to match a thermal expansion coefficient with a mother substrate described later. Examples of the substrate include an organic substrate and an inorganic substrate. Examples of the organic substrate include a glass epoxy substrate in which a glass fiber is impregnated with an epoxy resin, a liquid crystal polymer substrate, a Teflon (registered trademark) substrate, and the like. Examples of the inorganic substrate include a glass ceramic substrate. These substrates may be used alone or, for example, as a metal base substrate integrated with a metal plate such as Al or Cu.

  As described above, wiring patterns are formed on the interposer substrate at locations corresponding to the semiconductor element circuit surface. The material of the wiring pattern is not particularly limited, and a conventionally known material can be used. Examples of the material for the wiring pattern include Cu or a material in which a layer of Ni, Au, solder, or the like is formed on the surface of Cu.

  The first bump is not particularly limited, and a conventionally known bump can be used. Examples of the first bump include Au, Cu, and solder. The solder is not particularly limited, and examples thereof include Sn / Pb, Sn / Ag, Sn / Cu, Sn / Zn, Sn / Bi, Sn / Sb, or a material obtained by further adding a specific additive element to these materials. Can be given.

  The method for forming the first bump is not particularly limited, and a conventionally known method can be used. Examples of the forming method include a plating method, a method using a bump bonder, a printing method, a ball method, a sputtering method, a vapor deposition method, and a punching method. Two or more of these methods may be used in combination. In order to form the Au bump, it is preferable to use a method using a bump bonder or a plating method. In order to form the Cu bump, it is preferable to use a plating method. In order to form the solder bump, it is preferable to use a plating method, a printing method, or a ball method. In order to form solder bumps using the printing method, for example, solder is printed on the electrodes using a metal mask or the like, and after reflowing, the flux is removed and washed. In order to form solder bumps using the ball method, for example, the solder balls are transferred to the flux applied on the electrodes, and after reflowing, the flux is removed and washed. Also, a bump in which solder is formed on the tip of Cu using a plating method can be used in the electronic device of this embodiment.

  The periphery of the first bump connecting the semiconductor element and the interposer substrate is protected by a sealing resin. The material of the sealing resin is not particularly limited, and a conventionally known material can be used. Examples of the material include epoxy resin, acrylic resin, melamine resin, polyolefin resin, polyurethane resin, polycarbonate resin, polystyrene resin, polyether resin, polyamide resin, polyimide resin, fluorine resin, polyester resin, phenol resin, fluorene resin, Examples thereof include benzocyclobutene resin and silicone resin. These materials may be used alone or in combination of two or more. Among these, those which are liquid at room temperature (about 25 ° C.) are preferable. The material may be a thermosetting resin or a thermoplastic resin as illustrated above, but is preferably a thermosetting resin, and more preferably an epoxy resin.

  When solder is used as the first bump, it is preferable to add a flux action to the sealing resin. Heating during curing causes a flux effect to remove the solder oxide film, thereby improving the connectivity between the first bump and the interposer substrate. In order to give a flux action to the sealing resin, unsaturated acids such as acrylic acid, methacrylic acid and maleic acid, organic diacids such as oxalic acid and malonic acid, organic acids such as citric acid, and hydrocarbon side chains Further, it is possible to add at least one halogen group, hydroxyl group, nitrile group, benzyl group, carboxyl group or the like. Also, unsaturated alcohols such as allyl alcohol and methallyl alcohol, trimellitic acid, tetramellitic acid, and generally known chelating agents can be used. Such agents having the flux action can be used in combination of two or more. In addition, a well-known gelatinizer can also be included in a flux.

  From the viewpoint of suppressing the penetration of the insulating resin into the internal space, it is preferable that the viscosity of the sealing resin is high. On the other hand, it is preferable that the sealing resin has a low viscosity from the viewpoint of filling the sealing resin around the first connection portion and securely sealing the first connection portion. From both viewpoints, the viscosity of the sealing resin is, for example, about 5 Pa · s or more. However, the viscosity of the sealing resin is not limited to the above example, and may be appropriately determined according to the main surface of the semiconductor element, the wiring surface of the interposer substrate, the wettability of the sealing resin, and the like. In order to allow the sealing resin to exist only around the first bump, for example, a range of sealing with the sealing resin by selecting a mounting step and controlling a resin supply amount in a manufacturing method described later. Can be controlled.

  The sealing resin may be filled with a filler such as a silica filler. With the filler, for example, the thermal expansion coefficient can be reduced by increasing the viscosity of the sealing resin at the time of sealing and by increasing the elastic modulus of the sealing resin after curing. Due to the increase in the viscosity of the sealing resin at the time of sealing, it is possible to more reliably prevent the sealing resin from entering the internal space. Moreover, the connection reliability of the first connection portion (connection region) after resin sealing is improved by increasing the elastic modulus of the sealing resin after curing and reducing the thermal expansion coefficient. In the electronic device of this embodiment, since only the vicinity of the first connection portion is resin-sealed, the improvement in connection reliability by filling the sealing resin with the filler is remarkable. When the epoxy resin is filled with, for example, a silica filler at a ratio of about 50% by weight, the resin viscosity is, for example, about 5 Pa · S or more under a temperature condition of about 40 ° C. when the resin is injected. Then, by curing under a curing condition of about 150 ° C., for example, a sealing resin having an elastic modulus of about 8 GPa and a thermal expansion coefficient of about 35 ppm / ° C. can be obtained. The filling ratio of the silica filler is not particularly limited, but is, for example, about 50% by weight or more, preferably about 65% by weight or more.

  The second bump is not particularly limited, and a conventionally known bump can be used. An example of the second bump is solder. The solder is not particularly limited, and examples thereof include Sn / Pb, Sn / Ag, Sn / Cu, Sn / Zn, Sn / Bi, Sn / Sb, or a material obtained by further adding a specific additive element to these materials. Can be given. The method for forming the second bump is not particularly limited, and a conventionally known method can be used. For example, the second bump can be formed by the same method as the first bump. Also, for example, a resin core solder ball in which a ball of high heat resistance resin is prepared and copper and a solder layer are coated around it can be used as the second bump.

  The mother substrate is not particularly limited, and a conventionally known substrate can be used. For example, a printed wiring board in which a circuit pattern is formed by Cu wiring on the surface of a glass epoxy board in which a glass fiber is impregnated with an epoxy resin is used. be able to. As described above, the thermal expansion coefficients of the mother substrate and the interposer substrate 12 are combined to make it difficult to apply stress after mounting to the second bump, thereby improving the connection reliability of the second bump. It is preferable in terms of improvement.

  Next, a method for manufacturing the electronic device of this embodiment will be described with reference to FIG. In this figure, the same parts as those in FIG. In the manufacturing method of the electronic device of this embodiment, the case where a thermosetting resin is used as the sealing resin will be described as an example. The manufacturing method of the electronic device according to the present embodiment includes a first bump electrode forming step, a sealing resin applying step, a mounting step, a sealing step, a second bump forming step, and a connecting step. 2A shows a first bump electrode forming process and a sealing resin coating process, FIG. 2B shows a mounting process and a sealing process, and FIG. 2C shows a second bump. A formation process is shown and FIG.2 (d) shows a connection process.

[First bump electrode forming step and sealing resin coating step]
First, the first bump electrode forming step and the sealing resin applying step will be described. As shown in FIG. 2A, a semiconductor element 11 and an interposer substrate 12 are prepared. First, the first bump 13 (bump electrode) is formed on the outer peripheral portion of the main surface of the semiconductor element 11. The first bump 13 is not particularly limited, and a known method can be used. For example, when Au is used for the first bump and is connected to the interposer substrate 12 by thermocompression bonding by heating and pressing, plasma cleaning or the like is performed on the surface of the interposer substrate 12 to remove impurities on the surface of the interposer substrate 12. This improves bump connectivity. Subsequently, a partially uncured sealing resin 14 is applied in advance to a location (on the wiring pattern 12a) where the first bumps 13 on the interposer substrate 12 are connected. At this time, if the supply amount of the sealing resin 14 is too large, the sealing resin 14 does not stay around the first bump 13 but enters the central portion of the semiconductor element 11. If the supply amount is too small, the first bump is generated. It is preferable to adjust the supply amount because the periphery of 13 cannot be sufficiently protected and the connection reliability of the first bump 13 may be lowered. The supply amount of the sealing resin 14 can be determined by calculating the volume to be supplied from the target sealing area, and the viscosity and wetting spread of the sealing resin 14 to be used based on the calculated amount. It is possible to limit the sealing resin 14 only to the periphery of the first bump 13 by finely adjusting the supply amount according to the property, curability, and the like. Here, when using solder for the first bump 13, it is necessary to remove and connect the solder oxide film present on the solder surface. As an example, a flux action is added to the sealing resin 14, the flux action added to the sealing resin 14 when the first bump 13 is connected, and the oxide film of the first bump 13 is removed. A good connection can be obtained. The method of adding the oxide film removing action to the sealing resin 14 is as described above.

[Mounting process and sealing process]
Next, a mounting process and a sealing process will be described first. The semiconductor element 11 on which the first bumps 13 are formed is aligned with the interposer substrate 12, the first bumps 13 are connected to the wiring pattern 12 a on the interposer substrate 12 by heating and pressing, and the sealing resin 14 is cured. To proceed. Thereby, the electrical connection between the semiconductor element 11 and the interposer substrate 12 is completed. This state is shown in FIG. In the sealing resin application step, by finely adjusting the supply amount of the sealing resin 14, the sealing resin 14 is limited only to the periphery of the first bump 13, and the hollow portion 15 is formed in the central portion of the semiconductor element 11. It becomes possible. At this time, the sealed connection area is disposed so as to be between the pitches of the second bumps 17 (between the pitches of the pad electrodes 16) in the BGA connection in the next process.

  In this step, when the semiconductor element 11 and the interposer substrate 12 are connected via the first bump 13, it is preferable to control the position of the semiconductor element 11 during melting of the first bump 13. By doing so, the distance between the gaps between the semiconductor element 11 and the interposer substrate 12 can be adjusted more strictly. The method for controlling the position of the semiconductor element 11 is not particularly limited, and a conventionally known method can be used. In order to control the position of the semiconductor element 11, for example, a flip chip mounter is used.

[Second bump forming step]
Next, the second bump forming process will be described. As shown in FIG. 2C, the second bumps 17 are formed on the interposer substrate 12. The method for forming the second bump 17 is, for example, as follows when the second bump 17 is a solder bump. A flux is applied to the pad electrode 16 (interposer substrate side). Then, a solder ball is disposed on the pad electrode 16 using a metal mask opened in accordance with the position of the pad electrode 16. In this state, the solder balls are melted in the reflow furnace set to the melting profile of the material of the second bumps 17 to be used, and the solder balls are melted and connected to the pad electrodes 16 to form the second bumps. Is completed.

[Connection process]
Next, the connection process will be described. This connection step is a step of electrically connecting the interposer substrate 12 and the mother substrate 18. A solder paste layer made of the same material as the second bumps 17 is formed on the pad electrode 19 (mother substrate side) of the mother substrate 18 by printing using a metal mask. The interposer substrate 12 on which the second bumps 17 are formed by sealingly connecting the semiconductor elements 11 is mounted on the mother substrate 18 in a reflow furnace set to the melting profile of the material of the second bumps 17. The second bump 17 and the solder paste layer formed on the pad electrode 19 (mother substrate side) are melt-connected.

  In this way, as shown in FIG. 2D, the electronic device 10 of this embodiment can be manufactured. However, the method for manufacturing the electronic device of the present embodiment is not limited to this example. For example, in the present embodiment, the first bump electrode formation step and the sealing resin application step are performed in parallel, but the sealing resin application step may be performed after the first bump electrode formation step. .

(Embodiment 2)
FIG. 3 shows an exemplary configuration of the electronic apparatus according to the present embodiment. In this figure, the same parts as those in FIG. The difference between the electronic device 30 of the second embodiment and the first embodiment is that the wall portion 31 formed on the interposer substrate 12 divides the outer peripheral region and the inner region of the semiconductor element 11 into the sealing region A and That is, the hollow portion 15 is partitioned. The method of forming the sealing resin 14 in this case may be a method of injecting the sealing resin 14 into the gap between the semiconductor element 11 and the interposer substrate 12 by capillary action after the semiconductor element 11 is mounted on the interposer substrate 12. The method similar to that of Embodiment 1 may be used, and in any case, the sealing resin 14 does not enter the hollow portion 15 by the wall portion 31, and there is an effect that the control of the sealing resin 14 becomes unnecessary.

  The material which forms the said wall part 31 is not restrict | limited in particular, A conventionally well-known material can be used. The material may be, for example, an insulating material or a conductive material. Among these, the material is preferably a conductive material, and more preferably a metal. If the wall portion 31 is a metal, for example, since the strength is high, the wall portion 31 can be designed to be thin, and fine processing is facilitated. Examples of the metal include Cu, Al, and Ag. Examples of the insulating material include acrylic resin, melamine resin, epoxy resin, polyolefin resin, polyurethane resin, polycarbonate resin, polystyrene resin, polyether resin, polyamide resin, polyimide resin, fluorine resin, polyester resin, and phenol resin. Fluorene resin, silicone resin and the like. These materials may be used alone or in combination of two or more. These materials may be filled with an inorganic filler such as a silica filler.

  The method for forming the wall portion 31 is not particularly limited, and a conventionally known method can be used. Examples of the forming method include a method of attaching a material plate, a method of curing the paste, a method of attaching a film-like resin, and a method of forming a photosensitive solder resist. The paste is cured by, for example, supplying a paste having a predetermined thickness to a predetermined location by a printing method using a metal mask, a screen mask or the like, and curing the paste to form the wall portion 31. When the material forming the wall portion 31 is a conductive material, it is preferable to use a method of attaching the material plate. The material plate is not particularly limited, and examples thereof include a plate formed from a resin paste filled with conductive particles, a Cu plate, and an Al plate. The conductive particles are not particularly limited, and examples thereof include particles such as Ag and Cu. The plate formed in advance may be adjusted to a predetermined size by etching or the like after being attached to the interposer substrate 12. When the plate is attached to the interposer substrate 12, for example, an adhesive may be used.

  In order to lengthen the penetration path of the sealing resin 14, it is preferable to increase the width of the wall portion 31 as long as it does not contradict the demand for downsizing of the semiconductor element 11. For example, the lower limit of the width is about 20 μm and the upper limit is about 50 μm.

  By preparing the interposer substrate 12 on which the wall portion 31 is formed as described above, the electronic device 30 of this embodiment can be obtained by the same method as that described in the first embodiment.

(Embodiment 3)
FIG. 4 shows an exemplary configuration of the electronic apparatus according to the present embodiment. In this figure, the same parts as those in FIGS. 1 and 3 are denoted by the same reference numerals. The difference between the electronic device 40 of the third embodiment and the second embodiment is that the base portion 42 is formed on the interposer substrate 12 and the wall portion 31 is formed thereon. The wall portion 31 is fixed to the interposer substrate 12 via the base portion 42. According to such a configuration, since the bonding area between the wall portion 31 and the interposer substrate 12 is larger than when the base portion 42 does not exist, there is an effect that the bonding strength is improved and the stability is excellent.

  In the electronic device according to the present embodiment, for example, even when the height of the first bump 13 is different, the thickness of the base portion 42 is adjusted according to the height of the first bump 13, so that a fine wall The height position of the wall portion 31 can be optimized without changing the shape, dimensions, or the like of the portion 31. By doing in this way, the height position of the wall part 31 can be optimized easily and accurately rather than the case where the base part 42 does not exist and the shape, dimension, etc. of the wall part 31 are changed. As a result, the electronic device of this embodiment can be efficiently manufactured, and is excellent in shape stability after manufacturing. Further, when the base portion 42 is formed, for example, even when the interposer substrate 12 is warped, the influence of the warp of the interposer substrate 12 can be offset by changing the thickness of the base 42 according to the warp. Etc. are obtained. Thereby, there also exists an effect that the influence of the curvature of the interposer substrate 12 with respect to the wall part 31 can be suppressed.

  The material for forming the base portion 42 is not particularly limited, and conventionally known materials can be used. The material may be, for example, an insulating material or a conductive material. Among these, the material is preferably an insulating material, and more preferably a resin. Examples of the resin include acrylic resin, melamine resin, epoxy resin, polyolefin resin, polyurethane resin, polycarbonate resin, polystyrene resin, polyether resin, polyamide resin, polyimide resin, fluorine resin, polyester resin, phenol resin, fluorene resin, Examples thereof include silicone resins. Examples of the conductive material include Cu, Al, and Ag. These materials may be used alone or in combination of two or more. These materials may be filled with an inorganic filler such as a silica filler.

  The method for forming the base portion 42 is not particularly limited, and a conventionally known method can be used. Examples of the forming method include a method of curing a paste, a method of attaching a film-like resin, a method of forming a photosensitive solder resist, a method of attaching a material plate, and the like. As a method for curing the paste, for example, a paste having a predetermined thickness is supplied to a predetermined location by a printing method using a metal mask, a screen mask, and the like, and the base portion 42 is formed by curing the paste. When the material forming the base portion 42 is a conductive material, it is preferable to use a method of attaching the material plate. The material plate is not particularly limited, and examples thereof include a plate formed from a resin paste filled with conductive particles, a Cu plate, and an Al plate. The conductive particles are not particularly limited, and examples thereof include particles such as Ag and Cu. The plate formed in advance may be adjusted to a predetermined size by etching or the like after being attached to the wiring surface of the interposer substrate 12. When the plate is attached to the wiring surface of the interposer substrate 12, for example, an adhesive may be used. The method for adjusting the size of the base portion 42 is not particularly limited. For example, after the base portion 42 is formed by the above-described forming method, the size may be adjusted by cutting or the like.

  After the base portion 42 is formed, the wall portion 31 is formed. The material and the forming method of the wall portion 31 can be the same as those shown in the second embodiment. If a flexible material such as a resin is used for the base portion 42, stress due to warping of the interposer substrate 12 can be relieved, and if a hard material such as a metal is used for the wall portion 31, You can keep the strength.

  Next, a method for manufacturing the electronic device 40 of this embodiment will be described with reference to FIG. In this figure, the same parts as those in FIGS. 1 and 4 are denoted by the same reference numerals. The manufacturing method of the electronic device 40 of this embodiment includes a first bump electrode forming step, a wall portion forming step, a sealing resin applying step, a mounting step, a sealing step, and a second bump forming step. And a connecting step. 5A shows a first bump electrode forming step and a wall portion forming step, FIG. 5B shows a mounting step, and FIG. 5C shows a sealing resin coating step and a sealing step. FIG. 5D shows the second bump formation step, and FIG. 5E shows the connection step.

  FIG. 5A shows a state in which the semiconductor element 11 is aligned on the interposer substrate 12, and a state in which the electrical connection between the interposer substrate 12 and the semiconductor element 11 is completed via the first bump 13 by heating and pressing. It is FIG.5 (b). Subsequently, uncured sealing resin 14 is injected from the side surface of the mounted semiconductor element 11 using, for example, a capillary phenomenon. At this time, the injection of the sealing resin 14 may be promoted by heating the interposer substrate 12 to about 50 to 100 ° C. using a hot plate or the like according to the viscosity characteristics of the resin to be used. FIG. 5C shows a state where the sealing resin 14 is cured using an oven or the like after the injection of the sealing resin 14 is completed. The curing temperature when an epoxy resin is used for the sealing resin 14 is about 80 to 150 ° C. 5 shows a method of encapsulating the sealing resin 14 by capillary action after mounting the semiconductor element 11 on the interposer substrate 12, but before mounting the semiconductor element 1 as shown in FIG. A method of applying the sealing resin 14 in advance on the interposer substrate 12 may be used. In any case, there is an effect that the sealing resin 14 does not enter the hollow portion 15 by the wall portion 31 and control of the sealing resin 14 becomes unnecessary. Subsequently, the second bump formation step shown in FIG. 5D and the connection step to the mother substrate 18 shown in FIG. 5E can be performed in the same manner as the method shown in FIG. By preparing the interposer substrate 12 on which the base portion 42 and the wall portion 31 are formed as described above, the electronic device 40 of the present embodiment can be obtained by the same method as that described in the first embodiment.

(Embodiment 4)
FIG. 6 illustrates an exemplary configuration of the electronic apparatus according to the present embodiment. In this figure, the same parts as those in FIG. The difference between the electronic device 60 of the fourth embodiment and the first embodiment is that a recess 63 is formed on at least a part of the surface of the interposer substrate 12 corresponding to the hollow portion 15. When the sealing resin 14 is injected between the semiconductor element 11 and the interposer substrate 12 by capillarity, the sealing resin 14 may enter the hollow portion 15 because the recess 63 prevents the sealing resin 14 from entering. There is no need to control the sealing resin 14. The depth of the recess 63 is generally about several tens μm to several hundred μm, but the deeper the depth, the greater the effect of preventing the sealing resin 14 from entering. The formation method of the recessed part 63 is equivalent to the recessed part 63 with respect to the insulating layer of the depth which wants to form the recessed part 63, for example, when bonding the base material insulating layer whose thickness per layer is several tens of micrometers. After an opening is formed by punching the position or the like, an insulating layer can be attached to form the opening.

  Next, a method for manufacturing the electronic device 60 of this embodiment will be described with reference to FIG. In this figure, the same parts as those in FIGS. 1 and 6 are denoted by the same reference numerals. The manufacturing method of the electronic device 60 of the present embodiment includes a first bump electrode forming step, a recess forming step, a sealing resin applying step, a mounting step, a sealing step, a second bump forming step, A connecting step. FIG. 7A shows a first bump electrode forming step and a recess forming step, FIG. 7B shows a mounting step, and FIG. 7C shows a sealing resin coating step and a sealing step. FIG. 7D shows the second bump formation step, and FIG. 7E shows the connection step. When the manufacturing method shown in FIG. 7 is compared with the manufacturing method shown in FIG. 5, the state of the interposer substrate 12 is different, but it is possible to manufacture each electronic device by exactly the same process.

  FIG. 7A shows a state in which the semiconductor element 11 is aligned on the interposer substrate 12, and a state in which the electrical connection between the interposer substrate 12 and the semiconductor element 11 is completed via the first bump 13 by heating and pressing. It is FIG.7 (b). Subsequently, uncured sealing resin 14 is injected from the side surface of the mounted semiconductor element 11 using, for example, a capillary phenomenon. At this time, the injection of the sealing resin 14 may be promoted by heating the interposer substrate 12 to about 50 to 100 ° C. using a hot plate or the like according to the viscosity characteristics of the resin to be used. FIG. 7C shows a state where the sealing resin 14 is cured using an oven or the like after the injection of the sealing resin 14 is completed. The curing temperature when an epoxy resin is used for the sealing resin 14 is about 80 to 150 ° C. 7 shows a method of encapsulating the sealing resin 14 by capillary action after mounting the semiconductor element 11 on the interposer substrate 12, but before mounting the semiconductor element 1 as shown in FIG. A method of applying the sealing resin 14 in advance on the interposer substrate 12 may be used. In any case, there is an effect that the sealing resin 14 does not enter the hollow portion 15 by the concave portion 63, and the control of the sealing resin 14 becomes unnecessary. Subsequently, the second bump formation step shown in FIG. 7D and the connection step to the mother substrate 18 shown in FIG. 7E can be performed in the same manner as the method shown in FIG. By preparing the interposer substrate 12 having the recess 63 formed as described above, the electronic device 60 of the present embodiment can be obtained by the same method as that described in the first embodiment.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Supplementary note 1) includes an electronic element, an interposer substrate, and a mother substrate,
An electrode is formed on the main surface of the electronic element,
One surface of the interposer substrate is a wiring surface on which a wiring pattern is formed, and the other surface includes an interposer substrate side pad electrode,
The mother substrate includes a mother substrate side pad electrode on one surface,
An electrode of the electronic element and the wiring pattern are electrically connected via a first bump to form a first connection portion, whereby the electronic element is formed on the interposer substrate. Mounted in a state where the surface and the wiring surface face each other,
The first connection portion is sealed with a sealing resin to form a connection region;
The interposer substrate-side pad electrode and the mother substrate-side pad electrode are electrically connected via a second bump to form a second connection portion, whereby the interposer substrate is formed on the mother substrate. Implemented,
The electronic device, wherein the connection region between the electronic element and the interposer substrate is disposed between the pad electrodes on the interposer substrate side.

(Supplementary Note 2) The connection portion between the electronic element and the interposer substrate is sealed in the outer peripheral region of the electronic element in the space between the main surface and the wiring surface. The electronic device according to appendix 1, wherein the inner region on the inside is a hollow portion substantially free of the sealing resin.

(Additional remark 3) The said interposer board | substrate has a wall part on the surface of the wiring surface which is an opposing surface of the said electronic element, The space between the said main surface and the said wiring surface is the said wall part, The said surface The electronic device according to attachment 2, wherein the electronic device is partitioned into an outer peripheral region and the inner region.

(Additional remark 4) The said wall part is arrange | positioned on the said interposer substrate surface through the base part, The electronic device of Additional remark 3 characterized by the above-mentioned.

(Additional remark 5) The said wall part and the said base part are formed with a different material, The electronic device of Additional remark 4 characterized by the above-mentioned.

(Additional remark 6) The said wall part is formed from the metal, and the said base part is formed from resin, The electronic device of Additional remark 4 or 5 characterized by the above-mentioned.

(Supplementary note 7) The electronic device according to any one of supplementary notes 1 to 6, wherein the interposer substrate has a recess in at least a part of a surface of a wiring surface which is an opposing surface of the electronic element. .

(Appendix 8)
8. The electronic device according to any one of appendices 1 to 7, wherein the sealing resin is filled with 50% by weight or more of silica filler.

(Supplementary note 9) The electronic device according to any one of supplementary notes 1 to 8, wherein the electronic element is a semiconductor element.

(Additional remark 10) The process of forming a 1st bump electrode in the outer peripheral part of the main surface of an electronic element,
A wiring pattern is formed on one side and a pad electrode is included on the other side, and the wiring surface on which the wiring pattern is formed is selectively sealed at a position corresponding to the pitch between the pad electrodes. Applying a stop resin;
The wiring surface coated with the sealing resin and the main surface are aligned to face each other, the first bump electrode and the wiring pattern are electrically connected, and the electronic element and the interposer A mounting process for mounting in a state of facing on the substrate;
A sealing step of curing the sealing resin;
Forming a second bump on the pad electrode of the interposer substrate;
The second bump formed on the interposer substrate is aligned with the surface on the side including the pad electrode of the mother substrate including the pad electrode on one surface, and the second bump is faced. And a step of electrically connecting the interposer substrate and the mother substrate via a substrate.

(Supplementary note 11) The electronic device according to supplementary note 10, further comprising a wall portion forming step of forming a wall portion on a surface of the wiring surface that is the facing surface of the electronic element prior to the mounting step. Production method.

(Additional remark 12) In the said wall part formation process, a base part is formed in the said wiring surface, and then the said wall part is fixed to the said wiring surface via the said base part, and the said wall part is formed. The manufacturing method of the electronic device of Claim 11.

(Appendix 13)
13. The method of manufacturing an electronic device according to appendix 12, wherein the base portion is formed from a resin and the wall portion is formed from a metal.

(Appendix 14)
Furthermore, prior to the mounting step, the method further includes a recess forming step of forming a recess in at least a part of the surface of the wiring surface that is the facing surface of the electronic element. Method for manufacturing the electronic device.

10, 30, 40, 60 Electronic device 11 Semiconductor element (electronic element)
12 Interposer substrate 12a Wiring pattern 13 First bump (bump electrode)
14 Sealing resin 15 Hollow part 16 Pad electrode (interposer substrate side)
17 Second bump 18 Mother substrate 19 Pad electrode (mother substrate side)
31 Wall part 42 Base part 63 Concave part 100 Electronic device 101 Semiconductor element 102 Interposer substrate 104 Sealing resin 105 Arrangement prohibited area 107 Solder bump 108 Mother substrate

Claims (10)

Including an electronic element, an interposer substrate, and a mother substrate,
An electrode is formed on the main surface of the electronic element,
One surface of the interposer substrate is a wiring surface on which a wiring pattern is formed, and the other surface includes an interposer substrate side pad electrode,
The mother substrate includes a mother substrate side pad electrode on one surface,
An electrode of the electronic element and the wiring pattern are electrically connected via a first bump to form a first connection portion, whereby the electronic element is formed on the interposer substrate. Mounted in a state where the surface and the wiring surface face each other,
The first connection portion is sealed with a sealing resin to form a connection region;
The interposer substrate-side pad electrode and the mother substrate-side pad electrode are electrically connected via a second bump to form a second connection portion, whereby the interposer substrate is formed on the mother substrate. Implemented,
The electronic device, wherein the connection region between the electronic element and the interposer substrate and the sealing resin are arranged between the pad electrodes on the interposer substrate side. Sealing of a connection portion between the electronic element and the interposer substrate is performed in an outer peripheral area of the electronic element in a space between the main surface and the wiring surface, and an inner area inside the outer peripheral area. but wherein the sealing resin is nonexistent hollow portion, an electronic device according to claim 1. The interposer substrate has a wall portion on the surface of the wiring surface that is the facing surface of the electronic element, and the space between the main surface and the wiring surface is separated from the outer peripheral portion region by the wall portion. The electronic device according to claim 2, wherein the electronic device is partitioned into the internal region. The electronic device according to claim 3, wherein the wall portion is disposed on the surface of the interposer substrate via a base portion. The electronic device according to claim 4, wherein the wall portion and the base portion are formed of different materials. 6. The electronic device according to claim 4, wherein the wall portion is made of metal and the base portion is made of resin. The electronic device according to any one of claims 1 to 6, wherein the interposer substrate has a recess in at least a part of a surface of a wiring surface which is a surface facing the electronic element. The electronic device according to claim 1, wherein the sealing resin is filled with 50% by weight or more of silica filler. The electronic device according to claim 1, wherein the electronic element is a semiconductor element. Forming a first bump electrode on the outer periphery of the main surface of the electronic element;
A wiring pattern is formed on one surface and a pad electrode is included on the other surface, and the wiring surface on which the wiring pattern is formed is selectively placed at a position corresponding to the pitch between the pad electrodes. Applying a sealing resin;
The wiring surface coated with the sealing resin and the main surface are aligned to face each other, the first bump electrode and the wiring pattern are electrically connected, and the electronic element and the interposer A mounting process for mounting in a state of facing on the substrate;
A sealing step of curing the sealing resin;
Forming a second bump on the pad electrode of the interposer substrate;
The second bump formed on the interposer substrate is aligned with the surface on the side including the pad electrode of the mother substrate including the pad electrode on one surface, and the second bump is faced. And a step of electrically connecting the interposer substrate and the mother substrate via a substrate.

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