JPH11284104A - Integrated circuit package and manufacture thereof - Google Patents
Integrated circuit package and manufacture thereofInfo
- Publication number
- JPH11284104A JPH11284104A JP10012198A JP10012198A JPH11284104A JP H11284104 A JPH11284104 A JP H11284104A JP 10012198 A JP10012198 A JP 10012198A JP 10012198 A JP10012198 A JP 10012198A JP H11284104 A JPH11284104 A JP H11284104A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit board
- organic resin
- circuit chip
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、バンプを介して
互いの電極間を接続して回路板上に集積回路チップを実
装する集積回路実装体、およびその製造方法に関する。[0001] 1. Field of the Invention [0002] The present invention relates to an integrated circuit package for mounting an integrated circuit chip on a circuit board by connecting electrodes via bumps, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、集積回路実装体の中には、最短距
離の接続が可能となり、しかも超高密度実装が可能なこ
とから、たとえば図４に示すように、バンプ４を介して
互いの電極５・６間を接続して回路板１上に集積回路チ
ップ２を取り付けるフリップチップ方式を用いて製造す
るものがある。2. Description of the Related Art Conventionally, since the shortest distance connection and the ultra-high-density mounting are possible in an integrated circuit package, they are mutually connected via bumps 4 as shown in FIG. Some are manufactured using a flip-chip method in which the integrated circuit chip 2 is mounted on the circuit board 1 by connecting the electrodes 5 and 6.
【０００３】このフリップチップ方式では、回路板１と
集積回路チップ２間の熱膨張係数の差などから反り等が
生じて接続不良を発生するおそれがあることに鑑み、そ
れら回路板１と集積回路チップ２間に有機樹脂３を充填
してそれらを一体化し、その反り等に起因する接続不良
の発生を防止していた。In this flip-chip system, in consideration of the possibility that warpage or the like may occur due to a difference in thermal expansion coefficient between the circuit board 1 and the integrated circuit chip 2 and a connection failure may occur, the circuit board 1 and the integrated circuit chip 2 may be connected. The organic resin 3 is filled between the chips 2 to integrate them, thereby preventing the occurrence of connection failure due to warpage or the like.
【０００４】有機樹脂３を充填するには、２通りの方法
があった。まず第１は、バンプ４を介して互いの電極５
・６間を接続して後に、集積回路チップ２の周囲から回
路板１との間の数十ミクロン程度の隙間に有機樹脂３を
注入し、熱硬化させる方法である。There are two methods for filling the organic resin 3. First, the electrodes 5 are connected to each other via the bumps 4.
After the connection between the six, the organic resin 3 is injected into a gap of about several tens of microns from the periphery of the integrated circuit chip 2 to the circuit board 1 and thermally cured.
【０００５】第２は、バンプ４を介して互いの電極５・
６間を接続する前に、回路板１または集積回路チップ２
のいずれか一方に有機樹脂３を付着し、それに他方を重
ね合わせて加圧し、加熱する方法である。[0005] Second, the electrodes 5.
6 before connecting the circuit board 1 or the integrated circuit chip 2
This is a method in which the organic resin 3 is adhered to any one of the above, and the other is overlapped with the organic resin 3 and pressurized and heated.
【０００６】[0006]
【発明が解決しようとする課題】ところが、第１の方法
では、回路板１と集積回路チップ２間の隙間が数十ミク
ロン程度と小さいことから、特にフィラー入りの樹脂を
用いる場合には、その隙間への樹脂３の注入に時間がか
かり、またその隙間に均一に樹脂３を充填することが困
難で、信頼性を欠く課題があった。However, in the first method, the gap between the circuit board 1 and the integrated circuit chip 2 is as small as about several tens of microns. It takes time to inject the resin 3 into the gap, it is difficult to uniformly fill the gap with the resin 3, and there is a problem of lack of reliability.
【０００７】第２の方法でも、フィラー入りの樹脂を用
いると、互いの電極５・６間にフィラーが挟まって、接
続不良を生ずるおそれがある課題があった。Also in the second method, when a resin containing a filler is used, there is a problem that the filler may be sandwiched between the electrodes 5 and 6 to cause a connection failure.
【０００８】そこで、この発明の目的は、集積回路実装
体およびその製造方法において、接着力のあるフィラー
入りの樹脂を用いる場合にも、回路板と集積回路チップ
間に、時間がかからず、均一に、しかも接続不良を生ず
るおそれなく、樹脂を注入することができるようにする
ことにある。Accordingly, an object of the present invention is to provide an integrated circuit package and a method of manufacturing the same, in which even if a resin containing an adhesive filler is used, no time is required between the circuit board and the integrated circuit chip. An object of the present invention is to make it possible to inject a resin uniformly and without causing a connection failure.
【０００９】[0009]
【課題を解決するための手段】そのため、請求項１に記
載の発明は、たとえば以下の図１を用いて説明する実施
の形態のとおり、バンプ１８を介して互いの電極１２・
１６間を接続して回路板１０上に集積回路チップ１４を
実装する集積回路実装体において、前記集積回路チップ
１４の周囲と前記回路板１０間の、前記バンプ１８と、
前記両電極１２・１６の該バンプ１８と接続する部分を
有機樹脂２０で被うとともに、その有機樹脂２０で囲ん
で前記集積回路チップ１４と前記回路板１０間に空間ｓ
を形成し、その空間ｓを外部と連通する貫通孔１１ａを
前記回路板１０に形成してなる、ことを特徴とする。For this reason, the invention as defined in claim 1 is based on the embodiment described with reference to FIG. 1 below.
An integrated circuit chip mounting the integrated circuit chip 14 on the circuit board 10 by connecting the bumps 18 between the periphery of the integrated circuit chip 14 and the circuit board 10;
The portions of the electrodes 12 and 16 connected to the bumps 18 are covered with an organic resin 20 and surrounded by the organic resin 20 so that a space s is formed between the integrated circuit chip 14 and the circuit board 10.
And a through-hole 11a communicating the space s with the outside is formed in the circuit board 10.
【００１０】請求項２に記載の発明は、たとえば以下の
図２を用いて説明する実施の形態のとおり、バンプ１８
を介して互いの電極１２・１６間を接続して回路板１０
上に集積回路チップ１４を実装する集積回路実装体にお
いて、前記集積回路チップ１４の周囲と前記回路板１０
間の、前記バンプ１８と、前記両電極１２・１６の該バ
ンプ１８と接続する部分を有機樹脂２０で被うととも
に、その有機樹脂２０で囲んで前記集積回路チップ１４
と前記回路板１０間に空間ｓを形成し、その空間ｓを外
部と連通する開口２０ａを該有機樹脂２０に形成してな
る、ことを特徴とする。According to a second aspect of the present invention, for example, as shown in FIG.
Between the electrodes 12 and 16 through the circuit board 10
In an integrated circuit package on which the integrated circuit chip 14 is mounted, the periphery of the integrated circuit chip 14 and the circuit board 10
The bumps 18 and the portions of the electrodes 12 and 16 connected to the bumps 18 are covered with an organic resin 20 and surrounded by the organic resin 20.
A space s is formed between the organic resin 20 and the circuit board 10, and an opening 20 a communicating the space s with the outside is formed in the organic resin 20.
【００１１】請求項３に記載の発明は、集積回路実装体
の製造方法において、たとえば以下の図３を用いて説明
する実施の形態のとおり、バンプ１８を介して互いの電
極１２・１６間を接続して回路板１０上に集積回路チッ
プ１４を取り付けて後、それら集積回路チップ１４の周
囲から前記回路板１０との間に有機樹脂２０を注入し、
その回路板１０に設ける貫通孔１１ａを通して吸引して
前記有機樹脂２０を前記回路板１０との間の前記集積回
路チップ１４の奥まで引き込んでなる、ことを特徴とす
る。According to a third aspect of the present invention, there is provided a method of manufacturing an integrated circuit package, comprising the steps of connecting between electrodes 12 and 16 via bumps 18 as in an embodiment described with reference to FIG. After connecting and mounting the integrated circuit chip 14 on the circuit board 10, an organic resin 20 is injected between the integrated circuit chip 14 and the circuit board 10 from around the integrated circuit chip 14,
The organic resin 20 is drawn into the integrated circuit chip 14 with the circuit board 10 by suction through a through hole 11a provided in the circuit board 10.
【００１２】[0012]
【発明の実施の形態】以下、図面を参照しつつ、この発
明の実施の形態につき説明する。図１には、請求項１に
記載の発明による集積回路実装体の縦断面を示す。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a vertical cross section of an integrated circuit package according to the first aspect of the present invention.
【００１３】図中符号１０は、回路板である。この回路
板１０は、基板１１の表面に電極１２を有し、その電極
１２位置を避けて基板１１に貫通孔１１ａをあけてな
る。貫通孔１１ａは、径を数ミクロンから数ミリメータ
とする。In the figure, reference numeral 10 denotes a circuit board. The circuit board 10 has an electrode 12 on the surface of a substrate 11, and a through hole 11 a is formed in the substrate 11 avoiding the position of the electrode 12. The through hole 11a has a diameter of several microns to several millimeters.
【００１４】一方、図中符号１４は、集積回路チップで
ある。この集積回路チップ１４は、基板１５の表面に電
極１６を有する。そして、従来と同様に、フェイスダウ
ンで前記回路板１０上に乗せ、Auや半田製のバンプ１８
を介して電極１６を電極１２に接続してなる。On the other hand, reference numeral 14 in the figure denotes an integrated circuit chip. This integrated circuit chip 14 has electrodes 16 on the surface of a substrate 15. Then, as in the conventional case, the bump 18 made of Au or solder is placed face-down on the circuit board 10.
And the electrode 16 is connected to the electrode 12.
【００１５】その後、集積回路チップ１４の周囲から回
路板１０間に、ディスペンサ等で有機樹脂２０を注入
し、バンプ１８と、電極１２・１６の該バンプ１８と接
続する部分を被うとともに、その有機樹脂２０で回路板
１０に集積回路チップ１４を機械的に固定してなる。Thereafter, an organic resin 20 is injected between the periphery of the integrated circuit chip 14 and the circuit board 10 with a dispenser or the like to cover the bumps 18 and the portions of the electrodes 12 and 16 connected to the bumps 18. The integrated circuit chip 14 is mechanically fixed to the circuit board 10 with the organic resin 20.
【００１６】このとき、有機樹脂２０で囲まれた回路板
１０と集積回路チップ１４間の空間ｓが、回路板１０に
設けた前記貫通孔１１ａを介して外部と連通するように
してなる。At this time, a space s between the circuit board 10 and the integrated circuit chip 14 surrounded by the organic resin 20 communicates with the outside through the through hole 11a provided in the circuit board 10.
【００１７】これにより、有機樹脂２０で回路板１０と
集積回路チップ１４とを一体化し、それらの間の熱膨張
係数の差などから反り等が生じて接続不良が発生するよ
うな事態が起こらないようにする。As a result, the circuit board 10 and the integrated circuit chip 14 are integrated with the organic resin 20, and there is no possibility that warpage or the like occurs due to a difference in thermal expansion coefficient between them and a connection failure occurs. To do.
【００１８】ところで、この請求項１に記載の発明で
は、集積回路チップ１４の周囲から回路板１０との間に
有機樹脂２０を注入し、従来のように回路板１０と集積
回路チップ１４間のすべてに充填するのではなく、集積
回路チップ１４の周囲と回路板１０間の、バンプ１８
と、電極１２・１６の該バンプ１８と接続する部分を被
うように充填する。よって、時間がかからず、均一に充
填することができる。また、フィラー入りの樹脂を用い
ても、互いの電極１２・１６間にフィラーが挟まって、
接続不良を生ずる心配もない。According to the first aspect of the present invention, the organic resin 20 is injected between the periphery of the integrated circuit chip 14 and the circuit board 10 so that the organic resin 20 is formed between the circuit board 10 and the integrated circuit chip 14 as in the prior art. Rather than filling all, bumps 18 between the periphery of the integrated circuit chip 14 and the circuit board 10
Is filled so as to cover the portions of the electrodes 12 and 16 connected to the bumps 18. Therefore, it can be uniformly filled without taking much time. Even if a resin containing a filler is used, the filler is sandwiched between the electrodes 12 and 16 of each other,
There is no need to worry about poor connection.
【００１９】さらに、温度上昇により空間ｓ内の空気が
膨張したとしても、貫通孔１１ａから逃げ、空間ｓ内の
空気やガスの膨張により応力が発生して接続不良を生ず
るおそれもない。Further, even if the air in the space s expands due to the temperature rise, there is no possibility that the air escapes from the through hole 11a and the expansion of the air or gas in the space s generates a stress to cause a connection failure.
【００２０】図２には、（Ａ）に請求項２に記載の発明
による集積回路実装体の平面を示し、（Ｂ）にそのａ−
ａ線に沿う縦断面を示す。この図２では、図１で対応部
分に用いた符号をそのまま使用し、重複する説明を省略
する。FIG. 2A is a plan view of an integrated circuit package according to the second aspect of the present invention, and FIG.
3 shows a vertical section along line a. In FIG. 2, the reference numerals used for the corresponding parts in FIG. 1 are used as they are, and redundant description is omitted.
【００２１】図から判るとおり、この図２に示す集積回
路実装体では、図１で回路板１０に設けた貫通孔１１ａ
に代え、集積回路チップ１４の周囲に設ける有機樹脂２
０の一部を切り欠いて開口２０ａを形成する。そして、
その開口２０ａにより、有機樹脂２０で囲まれた集積回
路チップ１４と回路板１０間の空間ｓを外部と連通す
る。なお、開口２０ａは、バンプ１８位置を避けてバン
プ１８が露出しない位置に形成する。As can be seen from the drawing, in the integrated circuit package shown in FIG. 2, the through holes 11a formed in the circuit board 10 in FIG.
The organic resin 2 provided around the integrated circuit chip 14
The opening 20a is formed by cutting out a part of 0. And
The opening 20a allows a space s between the integrated circuit chip 14 and the circuit board 10 surrounded by the organic resin 20 to communicate with the outside. The opening 20a is formed at a position where the bump 18 is not exposed except for the position of the bump 18.
【００２２】これにより、請求項１に記載の発明と同様
に、有機樹脂２０で回路板１０と集積回路チップ１４と
を一体化し、それらの間の熱膨張係数の差などから反り
等が生じて接続不良が発生するような事態が起こらない
ようにする。As a result, the circuit board 10 and the integrated circuit chip 14 are integrated with the organic resin 20 in the same manner as in the first aspect of the present invention. Avoid situations where connection failures occur.
【００２３】また、集積回路チップ１４の周囲と回路板
１０間の、バンプ１８と、電極１２・１６の該バンプ１
８と接続する部分を被うように充填するだけであるか
ら、時間がかからず、均一に充填することができ、フィ
ラー入りの樹脂を用いても、互いの電極１２・１６間に
フィラーが挟まって、接続不良を生ずる心配もない。The bumps 18 between the periphery of the integrated circuit chip 14 and the circuit board 10 and the bumps 1 of the electrodes 12 and 16 are provided.
Since it is only filled so as to cover the portion connected to the electrode 8, it can be uniformly filled in a short time, and even if a resin containing a filler is used, the filler is filled between the electrodes 12 and 16. There is no fear of being pinched and causing poor connection.
【００２４】そして、この請求項２に記載の発明では、
温度上昇により空間ｓ内の空気やガスが膨張したとして
も、開口２０ａから逃げ、空間ｓ内の空気の膨張により
応力が発生して接続不良を生ずる心配もない。According to the second aspect of the present invention,
Even if the air or gas in the space s expands due to the temperature rise, there is no fear that the air or gas escapes from the opening 20a and the expansion of the air in the space s generates stress to cause a connection failure.
【００２５】図３には、請求項３に記載の発明による集
積回路実装体の製造方法を示す。この図３でも、図１で
対応部分に用いた符号をそのまま使用する。FIG. 3 shows a method of manufacturing an integrated circuit package according to the third aspect of the present invention. Also in FIG. 3, the reference numerals used for the corresponding parts in FIG. 1 are used as they are.
【００２６】この製造方法では、図１に示す集積回路実
装体と同様に、まず図３（Ａ）に示すように、Auや半田
製のバンプ１８を介して互いの電極１２・１６間を接続
して回路板１０上に集積回路チップ１４をフェイスダウ
ンで乗せる。たとえば回路板１０の電極１２およびバン
プ１８がともにAuであるときは、集積回路チップ１４の
裏面側から、200〜350℃で加熱したボンディングツール
で加圧してAu−Au接合を得る。バンプ１８が半田である
ときは、Au−半田接合となる。In this manufacturing method, similarly to the integrated circuit package shown in FIG. 1, first, as shown in FIG. 3A, the electrodes 12 and 16 are connected to each other via bumps 18 made of Au or solder. Then, the integrated circuit chip 14 is mounted face down on the circuit board 10. For example, when both the electrodes 12 and the bumps 18 of the circuit board 10 are made of Au, pressure is applied from the back surface side of the integrated circuit chip 14 with a bonding tool heated at 200 to 350 ° C. to obtain Au-Au bonding. When the bumps 18 are solder, Au-solder bonding is performed.
【００２７】その後、図３（Ｂ）に示すように、集積回
路チップ１４の周囲から回路板１０間に、たとえばディ
スペンサ２２で有機樹脂２０を注入する。この注入によ
り、有機樹脂２０は、その粘性に応じて回路板１０と集
積回路チップ１４間に入り込む。たとえば粘度が１００
ＣＰであれば、集積回路チップ１４のかなり奥まで入り
込む。なお、有機樹脂２０としては、エポキシ系樹脂、
アクリル系樹脂、シリコーン系樹脂、ポリイミド系樹脂
などの流動性のある樹脂を用いる。Thereafter, as shown in FIG. 3B, an organic resin 20 is injected between the circuit board 10 and the periphery of the integrated circuit chip 14 using, for example, a dispenser 22. By this injection, the organic resin 20 enters between the circuit board 10 and the integrated circuit chip 14 according to its viscosity. For example, if the viscosity is 100
In the case of a CP, it penetrates far into the integrated circuit chip 14. In addition, as the organic resin 20, an epoxy resin,
A fluid resin such as an acrylic resin, a silicone resin, or a polyimide resin is used.
【００２８】そして、回路板１０に設ける貫通孔１１ａ
を通して図３（Ｃ）中矢印ｂ方向に真空吸引し、空間ｓ
内を減圧して有機樹脂２０を回路板１０と集積回路チッ
プ１４間の奥まで引き込み、たとえば図３（Ｃ）に示す
ように貫通孔１１ａ内にまで充填する。吸引の程度を調
整することにより、回路板１０と集積回路チップ１４間
の所望のところまで有機樹脂２０を充填することができ
る。そして、少なくともバンプ１８と、電極１２・１６
の該バンプ１８と接続する部分を被うとともに、その有
機樹脂２０で回路板１０に集積回路チップ１４を機械的
に固定する。Then, a through hole 11a provided in the circuit board 10 is provided.
Through the vacuum in the direction of arrow b in FIG.
The interior is decompressed and the organic resin 20 is drawn deep into the space between the circuit board 10 and the integrated circuit chip 14, and is filled into the through hole 11a as shown in FIG. 3C, for example. By adjusting the degree of suction, the organic resin 20 can be filled to a desired position between the circuit board 10 and the integrated circuit chip 14. Then, at least the bumps 18 and the electrodes 12 and 16
Of the integrated circuit chip 14 is mechanically fixed to the circuit board 10 with the organic resin 20.
【００２９】これにより、この製造方法で製造した集積
回路実装体は、請求項１および２に記載の発明と同様
に、有機樹脂２０で回路板１０と集積回路チップ１４と
を一体化し、それらの間の熱膨張係数の差などから反り
等が生じて接続不良が発生するような事態が起こらない
ようにする。Thus, in the integrated circuit package manufactured by this manufacturing method, the circuit board 10 and the integrated circuit chip 14 are integrated with the organic resin 20 in the same manner as in the first and second aspects of the invention. The occurrence of a connection failure due to warpage or the like due to a difference in thermal expansion coefficient between them is prevented.
【００３０】また、真空吸引することで回路板１０と集
積回路チップ１４間に有機樹脂２０を充填するから、時
間がかからず、均一に充填することができ、フィラー入
りの樹脂を用いても、互いの電極１２・１６間にフィラ
ーが挟まって、接続不良を生ずる心配もない。Further, since the organic resin 20 is filled between the circuit board 10 and the integrated circuit chip 14 by vacuum suction, the organic resin 20 can be uniformly filled in a short time without using a resin. In addition, there is no fear that a filler is sandwiched between the electrodes 12 and 16 to cause a connection failure.
【００３１】さらに、この請求項３に記載の発明では、
温度上昇により空間ｓ内の空気やガスが膨張したとして
も、請求項１に記載の発明と同様に貫通孔１１ａから逃
げ、空間ｓ内の空気の膨張により応力が発生して接続不
良を生ずるおそれがなく、また有機樹脂２０内や、有機
樹脂２０と回路板１０間や、有機樹脂２０と集積回路チ
ップ１４間に存在する気泡や水分等を吸引除去すること
もできる。Further, in the invention according to claim 3,
Even if the air or gas in the space s expands due to the temperature rise, it escapes from the through-hole 11a as in the first aspect of the present invention, and the expansion of the air in the space s may cause stress to cause connection failure. In addition, air bubbles, moisture, and the like existing in the organic resin 20, between the organic resin 20 and the circuit board 10, or between the organic resin 20 and the integrated circuit chip 14 can be removed by suction.
【００３２】[0032]
【発明の効果】したがって、請求項１および２に記載の
発明によれば、有機樹脂を充填して回路板と集積回路チ
ップを一体化し、それらの間の熱膨張係数の差などから
反り等が生じて接続不良が発生することを防止すること
ができる。Therefore, according to the first and second aspects of the present invention, the circuit board and the integrated circuit chip are integrated by filling with an organic resin, and warpage or the like is caused by a difference in thermal expansion coefficient between the circuit board and the integrated circuit chip. This can prevent the occurrence of connection failure.
【００３３】また、集積回路チップの周囲と回路板間
の、バンプと、両電極の該バンプと接続する部分を被う
ように充填するだけであるから、時間がかからず、均一
に充填することができ、フィラー入りの樹脂を用いて
も、互いの電極間にフィラーが挟まって、接続不良を生
ずるおそれもない。In addition, since only the bumps between the periphery of the integrated circuit chip and the circuit board are covered so as to cover the portions connected to the bumps of the two electrodes, the filling is uniform without any time. Thus, even if a resin containing a filler is used, there is no possibility that the filler will be sandwiched between the electrodes to cause poor connection.
【００３４】請求項１に記載の発明によれば、さらに、
温度上昇により、有機樹脂で囲まれた空間内の空気が膨
張したとしても、貫通孔から逃げ、該空間内の空気やガ
スの膨張により応力が発生して接続不良を生ずる心配も
ない。According to the first aspect of the present invention,
Even if the air in the space surrounded by the organic resin expands due to the temperature rise, there is no fear that the air escapes from the through-hole and the stress is generated due to the expansion of the air or gas in the space to cause a connection failure.
【００３５】請求項２に記載の発明によれば、温度上昇
により、有機樹脂で囲まれた空間内の空気が膨張したと
しても、開口から逃げ、該空間内の空気の膨張により応
力が発生して接続不良を生ずる心配もない。According to the second aspect of the present invention, even if the air in the space surrounded by the organic resin expands due to the temperature rise, the air escapes from the opening and the stress is generated by the expansion of the air in the space. There is no concern about poor connection.
【００３６】請求項３に記載の発明による製造方法で製
造した集積回路実装体は、請求項１および２に記載の発
明と同様に、有機樹脂で回路板と集積回路チップとを一
体化し、それらの間の熱膨張係数の差などから反り等が
生じて接続不良が発生することを防止することができ
る。In the integrated circuit package manufactured by the manufacturing method according to the third aspect of the present invention, the circuit board and the integrated circuit chip are integrated with an organic resin in the same manner as in the first and second aspects of the invention. Can be prevented from generating a warp or the like due to a difference in thermal expansion coefficient between them, and the like, resulting in poor connection.
【００３７】また、真空吸引することで回路板と集積回
路チップ間に有機樹脂を充填するから、時間がかから
ず、均一に充填することができ、フィラー入りの樹脂を
用いても、互いの電極間にフィラーが挟まって、接続不
良を生ずる心配もない。Further, since the organic resin is filled between the circuit board and the integrated circuit chip by vacuum suction, it is possible to uniformly fill the organic resin in a short time. There is no fear that the connection failure occurs due to the filler being interposed between the electrodes.
【００３８】さらに、この請求項３に記載の発明では、
温度上昇により、有機樹脂で囲まれた空間内の空気が膨
張したとしても、貫通孔から逃げ、該空間内の空気やガ
スの膨張により応力が発生して接続不良を生ずるおそれ
がなく、また有機樹脂内や、有機樹脂と回路板間や、有
機樹脂と集積回路チップ間に存在する気泡や水分等を吸
引除去することができる効果もある。量産に最適で、高
い生産性と信頼性を実現できる。Further, in the invention according to claim 3,
Even if the air in the space surrounded by the organic resin expands due to the temperature rise, the air escapes from the through-holes, and there is no possibility that a stress may be generated due to the expansion of the air or gas in the space to cause a connection failure. There is also an effect that air bubbles, moisture, and the like existing in the resin, between the organic resin and the circuit board, or between the organic resin and the integrated circuit chip can be removed by suction. Ideal for mass production, high productivity and reliability can be achieved.
【図１】請求項１に記載の発明による集積回路実装体の
縦断面図である。FIG. 1 is a longitudinal sectional view of an integrated circuit package according to the first embodiment of the present invention.
【図２】請求項２に記載の発明による集積回路実装体
で、（Ａ）はその平面図、（Ｂ）はそのａ−ａ線に沿う
縦断面図である。FIG. 2 is a plan view of the integrated circuit package according to the second aspect of the present invention, and FIG. 2B is a longitudinal sectional view taken along line aa of FIG.
【図３】請求項３に記載の発明による集積回路実装体の
製造方法を示すもので、（Ａ）は回路板上への集積回路
チップの取り付け工程、（Ｂ）は有機樹脂の充填工程、
（Ｃ）は有機樹脂で囲まれた空間からの空気の吸引工程
を示す集積回路実装体の縦断面図である。FIG. 3 shows a method of manufacturing an integrated circuit package according to the invention of claim 3, wherein (A) is a step of mounting an integrated circuit chip on a circuit board, (B) is a step of filling an organic resin,
(C) is a longitudinal cross-sectional view of the integrated circuit mounted body, showing a process of sucking air from a space surrounded by an organic resin.
【図４】従来の集積回路実装体の縦断面図である。FIG. 4 is a longitudinal sectional view of a conventional integrated circuit package.
１０ 回路板 １１ 基板 １１ａ 貫通孔 １２ 電極 １４ 集積回路チップ １５ 基板 １６ 電極 １８ バンプ ２０ 有機樹脂 ２０ａ 開口 ２２ ディスペンサ ｓ 空間 Reference Signs List 10 circuit board 11 substrate 11a through hole 12 electrode 14 integrated circuit chip 15 substrate 16 electrode 18 bump 20 organic resin 20a opening 22 dispenser s space
Claims (3)
回路板上に集積回路チップを実装する集積回路実装体に
おいて、前記集積回路チップの周囲と前記回路板間の、
前記バンプと、前記両電極の該バンプと接続する部分を
有機樹脂で被うとともに、その有機樹脂で囲んで前記集
積回路チップと前記回路板間に空間を形成し、その空間
を外部と連通する貫通孔を前記回路板に形成してなる、
集積回路実装体。1. An integrated circuit mounting body for mounting an integrated circuit chip on a circuit board by connecting electrodes to each other via bumps, wherein an area between the periphery of the integrated circuit chip and the circuit board is
The bump and a portion of the two electrodes connected to the bump are covered with an organic resin, and a space is formed between the integrated circuit chip and the circuit board by surrounding the organic resin, and the space communicates with the outside. Forming a through hole in the circuit board;
Integrated circuit package.
回路板上に集積回路チップを実装する集積回路実装体に
おいて、前記集積回路チップの周囲と前記回路板間の、
前記バンプと、前記両電極の該バンプと接続する部分を
有機樹脂で被うとともに、その有機樹脂で囲んで前記集
積回路チップと前記回路板間に空間を形成し、その空間
を外部と連通する開口を該有機樹脂に形成してなる、集
積回路実装体。2. An integrated circuit mounting body for mounting an integrated circuit chip on a circuit board by connecting electrodes to each other via bumps, wherein an area between the periphery of the integrated circuit chip and the circuit board is provided.
The bump and a portion of the two electrodes connected to the bump are covered with an organic resin, and a space is formed between the integrated circuit chip and the circuit board by surrounding the organic resin, and the space communicates with the outside. An integrated circuit package having an opening formed in the organic resin.
回路板上に集積回路チップを取り付けて後、 それら集積回路チップの周囲から前記回路板との間に有
機樹脂を注入し、 その回路板に設ける貫通孔を通して吸引して前記有機樹
脂を前記回路板との間の前記集積回路チップの奥まで引
き込んでなる、集積回路実装体の製造方法。3. An integrated circuit chip is mounted on a circuit board by connecting the electrodes via bumps, and an organic resin is injected between the integrated circuit chip and the circuit board from around the integrated circuit chip. A method of manufacturing an integrated circuit package, wherein the organic resin is drawn into a depth of the integrated circuit chip between the circuit board and the organic resin by suction through a through hole provided in the circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10012198A JPH11284104A (en) | 1998-03-27 | 1998-03-27 | Integrated circuit package and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10012198A JPH11284104A (en) | 1998-03-27 | 1998-03-27 | Integrated circuit package and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11284104A true JPH11284104A (en) | 1999-10-15 |
Family
ID=14265518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10012198A Pending JPH11284104A (en) | 1998-03-27 | 1998-03-27 | Integrated circuit package and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11284104A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1303678C (en) * | 2002-06-28 | 2007-03-07 | 矽品精密工业股份有限公司 | Chip carrier holed semiconductor package element and mfg. method thereof |
| CN100367481C (en) * | 2005-06-03 | 2008-02-06 | 天水华天科技股份有限公司 | Method for producing plastic packaged thin type integrated circuit in long leads, low radian, and large area |
| JP2011171458A (en) * | 2010-02-17 | 2011-09-01 | Nec Corp | Electronic device and method for manufacturing electronic device |
| US8179686B2 (en) | 2007-11-09 | 2012-05-15 | Panasonic Corporation | Mounted structural body and method of manufacturing the same |
-
1998
- 1998-03-27 JP JP10012198A patent/JPH11284104A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1303678C (en) * | 2002-06-28 | 2007-03-07 | 矽品精密工业股份有限公司 | Chip carrier holed semiconductor package element and mfg. method thereof |
| CN100367481C (en) * | 2005-06-03 | 2008-02-06 | 天水华天科技股份有限公司 | Method for producing plastic packaged thin type integrated circuit in long leads, low radian, and large area |
| US8179686B2 (en) | 2007-11-09 | 2012-05-15 | Panasonic Corporation | Mounted structural body and method of manufacturing the same |
| JP2011171458A (en) * | 2010-02-17 | 2011-09-01 | Nec Corp | Electronic device and method for manufacturing electronic device |
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