JP2007096087A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

Info

Publication number
JP2007096087A
JP2007096087A JP2005285003A JP2005285003A JP2007096087A JP 2007096087 A JP2007096087 A JP 2007096087A JP 2005285003 A JP2005285003 A JP 2005285003A JP 2005285003 A JP2005285003 A JP 2005285003A JP 2007096087 A JP2007096087 A JP 2007096087A
Authority
JP
Japan
Prior art keywords
semiconductor chip
resin
wiring board
semiconductor device
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2005285003A
Other languages
Japanese (ja)
Inventor
Daisuke Ejima
大介 江島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Priority to JP2005285003A priority Critical patent/JP2007096087A/en
Publication of JP2007096087A publication Critical patent/JP2007096087A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a wiring board curves when underfill resin is heated to be cured during flip-chip bonding between a semiconductor chip and the wiring board. <P>SOLUTION: The method of manufacturing a semiconductor device includes a connection step of connecting a conductor bump 7 formed on a semiconductor chip 8 to a conductive pad 9 formed on a wiring board 5 which corresponds thereto, a fixing step of fixing the wiring board 5 on a vacuum suction tool 1 through vacuum suction, a resin injection step of injecting the underfill resin 7 between the semiconductor chip 8 and the wiring board 5 below it, and a resin curing step of heating the underfill resin 7 to cure it. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体装置の製造方法に関し、特に、半導体チップを半導体基板にフリップチップ接合する製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor chip by flip-chip bonding to a semiconductor substrate.

半導体装置は、トランジスタ、抵抗、コンデンサ等の多数の回路素子を形成した半導体チップを配線基板等に実装し、要求される回路動作や機能を果たすように、各回路素子間を結線して構成される。半導体チップ-配線基板間の結線方法としては金線によるワイヤーボンディング法、直接回路面を配線基板面に向けて接合するフリップチップ接合法等がある。   A semiconductor device is configured by mounting a semiconductor chip on which a large number of circuit elements such as transistors, resistors, capacitors, etc. are mounted on a wiring board, etc., and connecting each circuit element so as to perform the required circuit operation and function. The As a connection method between the semiconductor chip and the wiring substrate, there are a wire bonding method using a gold wire, a flip chip bonding method in which the circuit surface is directly directed to the wiring substrate surface, and the like.

従来、フリップチップ接合を行う際に、半導体チップと配線基板間を接合した後に、アンダーフィル（以下、ＵＦと称する）樹脂を注入し、ＵＦ樹脂を加熱することによって硬化させて、固定していた。   Conventionally, when performing flip chip bonding, after bonding between a semiconductor chip and a wiring board, an underfill (hereinafter referred to as UF) resin is injected, and the UF resin is heated and cured to be fixed. .

以下に、図９乃至図１２を参照して、半導体チップと配線基板間を接合し、ＵＦ樹脂を注入し、固定する製造方法について述べる。   Hereinafter, a manufacturing method in which a semiconductor chip and a wiring board are joined, UF resin is injected, and fixed will be described with reference to FIGS.

まず、図９に示すように、バンプ電極２７が形成された半導体チップ２８を、パッド電極２９を有する配線基板２５の上方にもってくる。次に、図１０に示すように、半導体チップ２８に形成されたバンプ電極２７と、配線基板２５に形成されたパッド電極２９を、既知の方法を用いて接合する。次に、図１１に示すように半導体チップ２８と配線基板２５との間に、ＵＦ樹脂２６を注入し、半導体チップ２８と配線基板２５との間の空間をＵＦ樹脂２６で充填する。その後、図１２に示すように、加熱ヒータ３０によって、ＵＦ樹脂２６を加熱し、硬化させて、固定させる。このようにして、フリップチップ接合を行っていた。   First, as shown in FIG. 9, the semiconductor chip 28 on which the bump electrode 27 is formed is brought above the wiring substrate 25 having the pad electrode 29. Next, as shown in FIG. 10, the bump electrode 27 formed on the semiconductor chip 28 and the pad electrode 29 formed on the wiring substrate 25 are bonded using a known method. Next, as shown in FIG. 11, UF resin 26 is injected between the semiconductor chip 28 and the wiring substrate 25, and the space between the semiconductor chip 28 and the wiring substrate 25 is filled with the UF resin 26. Then, as shown in FIG. 12, the UF resin 26 is heated by the heater 30 and is cured and fixed. In this way, flip chip bonding is performed.

このようなフリップチップ接合の方法が、例えば、特許文献１（特開２０００−２８６２７６号公報）の段落番号０００２から０００４に記載されている。   Such a flip-chip bonding method is described in paragraph numbers 0002 to 0004 of Patent Document 1 (Japanese Patent Laid-Open No. 2000-286276), for example.

特開２０００−２８６２７６号公報JP 2000-286276 A

以下に、図１３および図１４を参照して、上述したフリップチップ接合を行うときの問題点について、以下に説明する。   Below, with reference to FIG. 13 and FIG. 14, the problem at the time of performing the flip-chip joining mentioned above is demonstrated below.

ＵＦ樹脂２６を加熱する時に、半導体チップ２８を上面に積載している配線基板２５が、図１３に示すように、凸に反る場合があり、このときには、半導体チップ中央部における半導体チップ−配線間距離が狭くなる。逆に、半導体チップ２８を上面に積載している配線基板２５が、図１４に示すように、凹に反る場合もあり、このときには、半導体チップ中央部における半導体チップ−配線間距離が広くなる。どちらの場合にも、ＵＦ樹脂２６が硬化後もこの状態が維持される。   When the UF resin 26 is heated, the wiring board 25 on which the semiconductor chip 28 is stacked may warp convexly as shown in FIG. 13, and in this case, the semiconductor chip-wiring in the central part of the semiconductor chip may occur. The distance between them becomes narrower. Conversely, the wiring board 25 on which the semiconductor chip 28 is stacked may warp in a concave shape as shown in FIG. 14, and in this case, the distance between the semiconductor chip and the wiring at the center of the semiconductor chip becomes large. . In either case, this state is maintained even after the UF resin 26 is cured.

このような配線基板の反りが生ずる原因として、以下のことが考えられる。
半導体チップの熱膨張率が、３ｐｐｍ／℃であるのに対して、配線基板の熱膨張率は、１６ｐｐｍ／℃程度である。半導体チップと配線基板間を接合した後に、ＵＦ樹脂を注入し、これを硬化させるために加熱すると、半導体チップと配線基板の熱膨張差により反りが発生する。 The following can be considered as causes of the warping of the wiring board.
The thermal expansion coefficient of the semiconductor chip is 3 ppm / ° C., whereas the thermal expansion coefficient of the wiring board is about 16 ppm / ° C. When the UF resin is injected after the semiconductor chip and the wiring substrate are joined and heated to cure the UF resin, warpage occurs due to the difference in thermal expansion between the semiconductor chip and the wiring substrate.

配線基板の作製方法、構造、材料によっては、上述した加熱時の配線基板の反りが大きくなり、その後の組立プロセス、信頼性に大きな影響を与えるという問題があった。   Depending on the manufacturing method, structure, and material of the wiring board, there has been a problem that the warping of the wiring board during the heating described above becomes large, greatly affecting the subsequent assembly process and reliability.

上述した課題を鑑みて、本発明によれば、半導体チップに形成された導電パンプと、それに対応する配線基板に形成された導電パッドとを接続する接続工程と、配線基板を矯正治具上に固定する固定工程と、前記第１の半導体チップと、その下方の前記配線基板との間にアンダーフィル樹脂を注入する樹脂注入工程と、アンダーフィル樹脂を加熱することにより硬化させる樹脂硬化工程と、を含む半導体装置の製造方法が提供される。   In view of the above-described problems, according to the present invention, a connection step for connecting a conductive bump formed on a semiconductor chip and a corresponding conductive pad formed on a wiring board, and the wiring board on a correction jig. A fixing step of fixing, a resin injecting step of injecting an underfill resin between the first semiconductor chip and the wiring board below the first semiconductor chip, a resin curing step of curing by heating the underfill resin, A method for manufacturing a semiconductor device is provided.

本発明によれば、配線基板を矯正治具上に固定してから、半導体チップとその下方の配線基板との間にアンダーフィル樹脂を注入し、アンダーフィル樹脂を加熱することにより硬化させることによって、加熱に起因する配線基板の反りを抑えることができ、それによって、以下に示す項目に起因して、後続の組立プロセス、信頼性に大きな影響を与えるようなことがなくなる。   According to the present invention, after fixing the wiring board on the correction jig, the underfill resin is injected between the semiconductor chip and the wiring board below the semiconductor chip, and the underfill resin is cured by heating. Further, it is possible to suppress the warping of the wiring board due to heating, thereby preventing the subsequent assembly process and reliability from being greatly affected due to the following items.

１) 中央部の密着力弱化、剥離
半導体チップ中央部の半導体チップ−配線基板間が狭くなる場合に、半導体チップ中央部での密着力が弱くなり、剥離しやすくなってしまう。すなわち、半導体チップ-配線基板間が狭いということはそれだけＵＦが薄くなるということであり、例えば５ｕｍ以下の厚みとなると、後工程で行われる吸湿リフローに耐えるだけの十分な密着強度を確保できない。 1) Adhesive strength at the center is weakened, and when the distance between the semiconductor chip and the wiring substrate at the central portion of the peeled semiconductor chip is narrowed, the adhesive strength at the central portion of the semiconductor chip is weakened, and peeling becomes easy. That is, the narrowness between the semiconductor chip and the wiring board means that the UF is thinned accordingly. For example, when the thickness is 5 μm or less, it is not possible to secure sufficient adhesion strength enough to withstand moisture reflow performed in a subsequent process.

２）気泡残留、フィラー偏析の発生
半導体チップ中央部の半導体チップ−配線基板間が狭くなる場合、中央部へのＵＦ樹脂注入性が低下し、ＵＦ樹脂の巻き込みが発生しやすく、また、ＵＦ樹脂に混入されたフィラー径よりも狭くなると、そこにフィラーが入らず、フィラーの偏析が発生する。 2) Occurrence of bubbles and segregation of filler When the space between the semiconductor chip and the wiring board in the central part of the semiconductor chip becomes narrow, the UF resin injection property to the central part is lowered, and the UF resin is likely to be caught. When the filler diameter becomes smaller than the filler diameter, the filler does not enter there and segregation of the filler occurs.

３) 正常なフィレット形成が困難
ＵＦ樹脂注入時からＵＦ樹脂キュア時への更なる加熱による基板反りによって、ギャップが狭くなる場合はＵＦ樹脂が溢れ、広くなる場合はＵＦ樹脂引きが発生する。 3) It is difficult to form a normal fillet. When the gap becomes narrow due to the substrate warp due to further heating from the time of UF resin injection to the time of UF resin curing, the UF resin overflows, and when it becomes wider, UF resin pulling occurs.

４）上層チップを積載する時のダイマウントが困難
半導体チップ−基板間のＵＦ樹脂が均一な厚みを確保できず、平面性が悪くなる。また、半導体チップ中央部の半導体チップ−配線基板間が狭くなる場合には気泡を巻き込みやすく、逆に広くなる場合は半導体チップの外周部が浮きやすく、その後のワイヤーボンディング性に影響がある。さらに、半導体チップの外周部が浮いた場合には、モールド封止時に封止樹脂が隙間に入り込むこともある。 4) Difficult to die mount when an upper layer chip is loaded. The UF resin between the semiconductor chip and the substrate cannot secure a uniform thickness, resulting in poor flatness. In addition, when the space between the semiconductor chip and the wiring substrate at the center of the semiconductor chip is narrow, bubbles are likely to be caught, and when the space is widened, the outer periphery of the semiconductor chip is likely to float, which affects the subsequent wire bonding properties. Further, when the outer peripheral portion of the semiconductor chip floats, the sealing resin may enter the gap during mold sealing.

５）モールド封止時のチップ上樹脂厚が不均一（チップ曲げ応力集中）
半導体チップ−基板間のＵＦ樹脂が均一な厚みを確保できず、半導体チップ中央部の半導体チップ−配線基板間が狭くなる場合はチップ中央部モールド封止樹脂厚が厚くなり、逆に広くなる場合はチップ中央部モールド封止樹脂厚が薄くなり、応力が偏る。 5) Non-uniform resin thickness on chip during mold sealing (concentration of chip bending stress)
When the UF resin between the semiconductor chip and the substrate cannot secure a uniform thickness and the space between the semiconductor chip and the wiring substrate at the center of the semiconductor chip becomes narrower, the thickness of the mold sealing resin at the center of the chip becomes thicker and vice versa. The thickness of the mold sealing resin at the center of the chip is reduced, and the stress is biased.

６）局所的な反りの発生
半導体チップ-基板間のＵＦ樹脂が均一な厚みを確保できず、局所的な反りが発生する。 6) Generation of local warpage The UF resin between the semiconductor chip and the substrate cannot secure a uniform thickness, and local warpage occurs.

本発明によれば、加熱に起因する配線基板の反りを抑えることができ、それによって、後続の組立プロセス、信頼性に大きな影響を与えるようなことがなくなる。   According to the present invention, it is possible to suppress the warpage of the wiring board due to heating, thereby eliminating the great influence on the subsequent assembly process and reliability.

以下、本発明の実施の形態について図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第１の実施形態First embodiment

図１乃至図５は、本発明の第１の実施形態のフリップチップ接合方法を説明するための工程断面図である。   1 to 5 are process cross-sectional views for explaining a flip chip bonding method according to the first embodiment of the present invention.

以下に、図１乃至図５を参照して、本発明の第１の実施形態のフリップチップ接合方法について説明する。   Hereinafter, a flip chip bonding method according to the first embodiment of the present invention will be described with reference to FIGS.

まず、図１に示すように、バンプ電極７が形成された半導体チップ８を、パッド電極９を有する配線基板５の上方にもってくる。なお、配線基板２５は実装基板との仲介の機能を有するインターポーザであってもよい。   First, as shown in FIG. 1, the semiconductor chip 8 on which the bump electrodes 7 are formed is brought above the wiring substrate 5 having the pad electrodes 9. The wiring board 25 may be an interposer having a function of mediation with the mounting board.

次に、図２に示すように、半導体チップ８に形成されたバンプ電極７と、配線基板５に形成されたパッド電極９とを、既知の方法を用いて接合する。（接続工程）   Next, as shown in FIG. 2, the bump electrodes 7 formed on the semiconductor chip 8 and the pad electrodes 9 formed on the wiring substrate 5 are bonded using a known method. (Connection process)

さらに、図３に示すように、半導体チップ８を積載している配線基板５を、真空吸着治具１の上に載せ、配線基板５を面吸着して、真空吸着治具１上に固定する。この真空吸着治具１は、配線基板５と接する上面にポーラスな物質からなる層２（真空吸着部）が設けられた低膨張矯正治具４からなり、さらに、ポーラスな物質からなる層２の下には、真空ポンプに接続される真空引き用開口部３が形成されている。このような構成により、真空吸着治具１は、ポーラスな物質からなる層２に接している配線基板５を真空吸着することができる。（固定工程）   Further, as shown in FIG. 3, the wiring board 5 on which the semiconductor chip 8 is loaded is placed on the vacuum suction jig 1, and the wiring board 5 is surface-sucked and fixed on the vacuum suction jig 1. . The vacuum suction jig 1 includes a low expansion correction jig 4 provided with a layer 2 (vacuum suction portion) made of a porous material on the upper surface in contact with the wiring board 5, and further includes a layer 2 made of a porous material. A vacuuming opening 3 connected to a vacuum pump is formed below. With such a configuration, the vacuum suction jig 1 can vacuum-suck the wiring substrate 5 in contact with the layer 2 made of a porous material. (Fixing process)

なお、配線基板５を面吸着して、真空吸着治具１上に固定する工程は、バンプ電極７と、パッド電極９とを接合する工程の前に行ってもよい。すなわち、図１に示す状態で、配線基板５を真空吸着治具１上に固定してもよい。また、層２は、所定の間隔で複数の貫通孔が形成されている層であってもよい。また、低膨張矯正治具４は、熱膨張係数が小さい物質からなることが好ましい。   Note that the step of surface-adsorbing the wiring substrate 5 and fixing it on the vacuum suction jig 1 may be performed before the step of bonding the bump electrode 7 and the pad electrode 9. That is, the wiring board 5 may be fixed on the vacuum suction jig 1 in the state shown in FIG. The layer 2 may be a layer in which a plurality of through holes are formed at a predetermined interval. The low expansion correction jig 4 is preferably made of a material having a small thermal expansion coefficient.

その後、図４に示すように、配線基板５が真空吸着治具１の上に固定されている状態（すなわち、半導体チップ−配線基板間のギャップを均一に保った状態）で、半導体チップ８と配線基板５との間に、ＵＦ樹脂６を注入する。（樹脂注入工程）   Thereafter, as shown in FIG. 4, in a state where the wiring substrate 5 is fixed on the vacuum suction jig 1 (that is, a state in which the gap between the semiconductor chip and the wiring substrate is kept uniform) A UF resin 6 is injected between the wiring substrate 5. (Resin injection process)

次に、図５に示すように、配線基板５が真空吸着治具１の上に固定されている状態（すなわち、半導体チップ−配線基板間のギャップを均一に保った状態）で、加熱ヒータ１０の上に載せ、加熱ヒータ１０によってＵＦ樹脂６を加熱し、硬化させて、固定させる。（樹脂硬化工程）   Next, as shown in FIG. 5, the heater 10 in a state where the wiring substrate 5 is fixed on the vacuum suction jig 1 (that is, a gap between the semiconductor chip and the wiring substrate is kept uniform). The UF resin 6 is heated by the heater 10 and cured and fixed. (Resin curing process)

その後は、さらに、上層の半導体チップまたはＳｉスペーサを積載することができる。積載された上層の半導体チップは、ワイヤーボンディング法等により前記配線基板と接続
し、最後にトランスファーモールド法等により前記半導体チップ等を封止し、半田ボール
等の外部端子を形成することにより、半導体装置をパッケージングすることができる。 Thereafter, an upper semiconductor chip or Si spacer can be further loaded. The stacked upper layer semiconductor chip is connected to the wiring substrate by a wire bonding method or the like, and finally the semiconductor chip or the like is sealed by a transfer mold method or the like, thereby forming an external terminal such as a solder ball. The device can be packaged.

上述したように、本実施形態では、ＵＦ樹脂６を加熱して硬化させるときに、配線基板５は、低膨張矯正治具４からなる真空吸着治具１の上に固定されているので、半導体チップ−配線基板間のギャップを均一に保つことができ、配線基板５の反りを効果的に抑えることができる。   As described above, in the present embodiment, when the UF resin 6 is heated and cured, the wiring board 5 is fixed on the vacuum suction jig 1 including the low expansion correction jig 4. The gap between the chip and the wiring board can be kept uniform, and the warping of the wiring board 5 can be effectively suppressed.

なお、ＵＦ樹脂６を加熱する手段は、加熱ヒータに限定されるものではなく、ＵＦ樹脂６を加熱するできるものであればよい。   The means for heating the UF resin 6 is not limited to the heater, and any means that can heat the UF resin 6 may be used.

次に、本実施形態の効果について説明する。   Next, the effect of this embodiment will be described.

本実施形態のフリップチップ接合方法によれば、ＵＦ樹脂６を加熱して硬化させる際に生じる配線基板５の反りを効果的に抑えることにより、以下の項目に示すような効果が得られる。   According to the flip chip bonding method of the present embodiment, the effects shown in the following items can be obtained by effectively suppressing the warpage of the wiring board 5 that occurs when the UF resin 6 is heated and cured.

１）半導体チップ−配線基板間のＵＦ樹脂が均一な厚みを確保できるため、十分な密着
力を発揮できる 1) Since the UF resin between the semiconductor chip and the wiring board can ensure a uniform thickness, sufficient adhesion can be exhibited.

２）半導体チップ−配線基板間のギャップを均一にできるため、品種によってさまざまなＵＦ樹脂注入方法や、さまざまな基板設計（ＳＲ開口、配線パターン等）を選定することできる。   2) Since the gap between the semiconductor chip and the wiring substrate can be made uniform, various UF resin injection methods and various substrate designs (SR openings, wiring patterns, etc.) can be selected depending on the product type.

３）半導体チップ―配線基板間のギャップを均一にできるため、通常ならばＵＦ樹脂注入時からＵＦ樹脂硬化時への更なる加熱による基板反りによって、ギャップが狭くなる場合はＵＦ樹脂が溢れ、広くなる場合はＵＦ樹脂引きが発生するのを防ぐことができる。   3) Since the gap between the semiconductor chip and the wiring board can be made uniform, the UF resin overflows when the gap becomes narrow due to substrate warping caused by further heating from UF resin injection to UF resin curing. In this case, UF resin pulling can be prevented from occurring.

４）半導体チップ-配線基板間のＵＦ樹脂が均一な厚みを確保できるため、平面性を向上させることができる。   4) Since the UF resin between the semiconductor chip and the wiring substrate can ensure a uniform thickness, the planarity can be improved.

５）半導体チップ-配線基板間のＵＦ樹脂が均一な厚みを確保できるため、配線基板に対し、平行にフリップチップ接合、チップ積層が可能になる。   5) Since the UF resin between the semiconductor chip and the wiring board can ensure a uniform thickness, flip chip bonding and chip stacking can be performed in parallel to the wiring board.

６）半導体チップ-配線基板間のＵＦ樹脂が均一な厚みを確保できるため、局所的な反り等を防止することができる。   6) Since the UF resin between the semiconductor chip and the wiring board can ensure a uniform thickness, local warping or the like can be prevented.

第２の実施形態Second embodiment

次に、図１乃至図２、および図６乃至図８を参照して、本発明の第２の実施形態のフリップチップ接合方法について説明する。本実施形態のフリップチップ接合方法は、第１の実施形態と比較して、配線基板の矯正治具への固定方法が異なっている。     Next, a flip chip bonding method according to the second embodiment of the present invention will be described with reference to FIGS. The flip chip bonding method of this embodiment is different from the first embodiment in the method of fixing the wiring board to the correction jig.

図６乃至図８は、本実施形態のフリップチップ接合方法を説明するための工程断面図である。   6 to 8 are process cross-sectional views for explaining the flip chip bonding method of the present embodiment.

まず、第１の実施形態と同様にして、図１および図２に示すように、半導体チップ８に形成されたバンプ電極７と、配線基板５に形成されたパッド電極９とを接合する。（接続工程）   First, similarly to the first embodiment, as shown in FIGS. 1 and 2, the bump electrode 7 formed on the semiconductor chip 8 and the pad electrode 9 formed on the wiring substrate 5 are bonded. (Connection process)

次に、図６に示すように、半導体チップ８を積載している配線基板５を、粘着性のある樹脂１１を塗布した低膨張矯正治具４’に貼り付けることによって、配線基板５を低膨張矯正治具４’に固定する。（固定工程）   Next, as shown in FIG. 6, the wiring board 5 on which the semiconductor chip 8 is loaded is attached to a low expansion correction jig 4 ′ coated with an adhesive resin 11, thereby lowering the wiring board 5. Fix to the expansion correction jig 4 '. (Fixing process)

なお、配線基板５を粘着性のある樹脂１１を介して低膨張矯正治具４’上に固定する工程は、バンプ電極７と、パッド電極９とを接合する工程の前に行ってもよい。すなわち、図１に示す状態で、配線基板５を低膨張矯正治具４’上に固定してもよい。また、低膨張矯正治具４’は、熱膨張係数が小さい物質からなることが好ましい。また、粘着性のある樹脂１１は、高温においても粘着性を失わない物質からなることが好ましい。   The step of fixing the wiring board 5 on the low expansion correction jig 4 ′ via the adhesive resin 11 may be performed before the step of bonding the bump electrode 7 and the pad electrode 9. That is, in the state shown in FIG. 1, the wiring board 5 may be fixed on the low expansion correction jig 4 '. The low expansion correction jig 4 ′ is preferably made of a material having a small thermal expansion coefficient. The adhesive resin 11 is preferably made of a material that does not lose its adhesiveness even at high temperatures.

その後、図７に示すように、配線基板５が低膨張矯正治具４’の上に固定されている状態（すなわち、半導体チップ−配線基板間のギャップを均一に保った状態）で、半導体チップ８と配線基板５との間に、ＵＦ樹脂６を注入する。（樹脂注入工程）   Thereafter, as shown in FIG. 7, in a state where the wiring substrate 5 is fixed on the low expansion correction jig 4 ′ (that is, a state where the gap between the semiconductor chip and the wiring substrate is kept uniform), the semiconductor chip A UF resin 6 is injected between 8 and the wiring board 5. (Resin injection process)

次に、図８に示すように、配線基板５が低膨張矯正治具４’の上に固定されている状態（すなわち、半導体チップ−配線基板間のギャップを均一に保った状態）で、加熱ヒータ１０の上に載せ、加熱ヒータ１０によってＵＦ樹脂６を加熱し、硬化させて、固定させる。（樹脂硬化工程）   Next, as shown in FIG. 8, heating is performed in a state where the wiring board 5 is fixed on the low expansion correction jig 4 ′ (that is, a gap between the semiconductor chip and the wiring board is kept uniform). The UF resin 6 is placed on the heater 10 and heated by the heater 10 to be cured and fixed. (Resin curing process)

その後は、さらに、上層の半導体チップまたはＳｉスペーサを積載することができる。積載された上層の半導体チップは、ワイヤーボンディング法等により前記配線基板と接続
し、最後にトランスファーモールド法等により前記半導体チップ等を封止し、半田ボール
等の外部端子を形成することにより、半導体装置をパッケージングすることができる。 Thereafter, an upper semiconductor chip or Si spacer can be further loaded. The stacked upper layer semiconductor chip is connected to the wiring substrate by a wire bonding method or the like, and finally the semiconductor chip or the like is sealed by a transfer mold method or the like, thereby forming an external terminal such as a solder ball. The device can be packaged.

上述したように、本実施形態においても、ＵＦ樹脂６を加熱して硬化させるときに、配線基板５は、低膨張矯正治具４’の上に固定されているので、半導体チップ−配線基板間のギャップを均一に保つことができ、配線基板５の反りを効果的に抑えることができる。さらに、本実施形態では、粘着性のある樹脂１１を介して、矯正治具に固定しているので、矯正治具として真空吸着機能を有する真空吸着治を使っている実施形態１と比較して、矯正治具の構造を簡素化することができる。   As described above, also in the present embodiment, when the UF resin 6 is heated and cured, the wiring substrate 5 is fixed on the low expansion correction jig 4 ′. Therefore, the warp of the wiring board 5 can be effectively suppressed. Furthermore, in this embodiment, since it is fixed to the correction jig through the adhesive resin 11, it is compared with the first embodiment using a vacuum adsorption treatment having a vacuum suction function as the correction jig. The structure of the correction jig can be simplified.

本発明の第１の実施形態の工程断面を示す図である。It is a figure which shows the process cross section of the 1st Embodiment of this invention. 本発明の第１の実施形態の工程断面を示す図である。It is a figure which shows the process cross section of the 1st Embodiment of this invention. 本発明の第１の実施形態の工程断面を示す図である。It is a figure which shows the process cross section of the 1st Embodiment of this invention. 本発明の第１の実施形態の工程断面を示す図である。It is a figure which shows the process cross section of the 1st Embodiment of this invention. 本発明の第１の実施形態の工程断面を示す図である。It is a figure which shows the process cross section of the 1st Embodiment of this invention. 本発明の第２の実施形態の工程断面を示す図である。It is a figure which shows the process cross section of the 2nd Embodiment of this invention. 本発明の第２の実施形態の工程断面を示す図である。It is a figure which shows the process cross section of the 2nd Embodiment of this invention. 本発明の第２の実施形態の工程断面を示す図である。It is a figure which shows the process cross section of the 2nd Embodiment of this invention. 従来のフリップチップ接合方法の工程断面を示す図である。It is a figure which shows the process cross section of the conventional flip chip joining method. 従来のフリップチップ接合方法の工程断面を示す図である。It is a figure which shows the process cross section of the conventional flip chip joining method. 従来のフリップチップ接合方法の工程断面を示す図である。It is a figure which shows the process cross section of the conventional flip chip joining method. 従来のフリップチップ接合方法の工程断面を示す図である。It is a figure which shows the process cross section of the conventional flip chip joining method. 従来のフリップチップ接合方法の問題点を示す図である。It is a figure which shows the problem of the conventional flip chip joining method. 従来のフリップチップ接合方法の問題点を示す図である。It is a figure which shows the problem of the conventional flip chip joining method.

符号の説明Explanation of symbols

１ 真空吸着治具
２ ポーラスな物質からなる層
３ 真空引き用開口部
４ 低膨張矯正治具
５ 配線基板
６ ＵＦ樹脂
７ バンプ電極
８ 半導体チップ
９ パッド電極
１０ 加熱ヒータ
１１ 粘着性のある樹脂
２５ 配線基板
２６ ＵＦ樹脂
２７ バンプ電極
２８ 半導体チップ
２９ パッド電極
３０ 加熱ヒータ
DESCRIPTION OF SYMBOLS 1 Vacuum adsorption jig 2 Porous material layer 3 Vacuum opening 4 Low expansion correction jig 5 Wiring board 6 UF resin 7 Bump electrode 8 Semiconductor chip 9 Pad electrode 10 Heater 11 Adhesive resin 25 Wiring Substrate 26 UF resin 27 Bump electrode 28 Semiconductor chip 29 Pad electrode 30 Heater

Claims (9)

第１の半導体チップに形成された導電パンプと、それに対応する配線基板に形成された導電パッドとを接続する接続工程と、
前記配線基板を矯正治具上に固定する固定工程と、
前記第１の半導体チップと、その下方の前記配線基板との間にアンダーフィル樹脂を注入する樹脂注入工程と、
前記アンダーフィル樹脂を加熱することにより硬化させる樹脂硬化工程と、
を含むことを特徴とする半導体装置の製造方法。 A connection step of connecting a conductive bump formed on the first semiconductor chip and a corresponding conductive pad formed on the wiring board;
A fixing step of fixing the wiring board on a correction jig;
A resin injection step of injecting an underfill resin between the first semiconductor chip and the wiring substrate below the first semiconductor chip;
A resin curing step for curing the underfill resin by heating;
A method for manufacturing a semiconductor device, comprising: 前記固定工程が、前記接続工程の前にあることを特徴とする請求項１に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein the fixing step is performed before the connecting step. 前記固定工程が、前記接続工程の後にあることを特徴とする請求項１に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein the fixing step is after the connecting step. 前記固定工程が、真空吸着によって、真空吸着部を有する矯正治具上に前記配線基板を固定する工程であることを特徴とする請求項１乃至３のいずれかに記載の半導体装置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 1, wherein the fixing step is a step of fixing the wiring board on a correction jig having a vacuum suction portion by vacuum suction. 前記固定工程が、
前記矯正治具の上面に、粘着性のある樹脂を塗布する工程と、
前記粘着性のある樹脂上に、前記配線基板を固定する工程と、
を含むことを特徴とする請求項１乃至３のいずれかに記載の半導体装置の製造方法。 The fixing step includes
Applying an adhesive resin to the upper surface of the correction jig;
Fixing the wiring board on the adhesive resin;
The method for manufacturing a semiconductor device according to claim 1, comprising: 前記真空吸着部が、ポーラスな物質からなることを特徴とする請求項４に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 4, wherein the vacuum suction portion is made of a porous material. 前記真空吸着部が、複数の貫通孔を有する層からなることを特徴とする請求項４に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 4, wherein the vacuum suction portion is formed of a layer having a plurality of through holes. 前記樹脂硬化工程の後に、第２の半導体チップまたはSiスペーサを積層する積層工程を有することを特徴とする、請求項１乃至７のいずれかに記載の半導体装置の製造方法。 8. The method of manufacturing a semiconductor device according to claim 1, further comprising a stacking step of stacking a second semiconductor chip or an Si spacer after the resin curing step. 前記積層工程の後に、前記第２の半導体チップに形成された導電パッドと、前記配線基板に形成された導電パッドとを、ボンディングワイヤーで接続するボンディングワイヤー接続工程を有することを特徴とする、請求項８に記載の半導体装置の製造方法。
A bonding wire connecting step of connecting the conductive pad formed on the second semiconductor chip and the conductive pad formed on the wiring substrate with a bonding wire after the stacking step is provided. Item 9. A method for manufacturing a semiconductor device according to Item 8.
JP2005285003A 2005-09-29 2005-09-29 Method of manufacturing semiconductor device Withdrawn JP2007096087A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005285003A JP2007096087A (en) 2005-09-29 2005-09-29 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005285003A JP2007096087A (en) 2005-09-29 2005-09-29 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2007096087A true JP2007096087A (en) 2007-04-12

Family

ID=37981409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005285003A Withdrawn JP2007096087A (en) 2005-09-29 2005-09-29 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2007096087A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013123849A (en) * 2011-12-14 2013-06-24 Apic Yamada Corp Resin sealing device and resin sealing method
CN110326100A (en) * 2017-01-30 2019-10-11 普利莫1D公司 Method and apparatus for implementing the method for being inserted into wiring in the groove of semiconductor chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013123849A (en) * 2011-12-14 2013-06-24 Apic Yamada Corp Resin sealing device and resin sealing method
CN110326100A (en) * 2017-01-30 2019-10-11 普利莫1D公司 Method and apparatus for implementing the method for being inserted into wiring in the groove of semiconductor chip
CN110326100B (en) * 2017-01-30 2023-08-15 普利莫1D公司 Method for inserting wiring into trench of semiconductor chip and apparatus for implementing the method

Similar Documents

Publication Publication Date Title
US8305766B2 (en) Electronic component-embedded printed circuit board and method of manufacturing the same
JP2010034403A (en) Wiring substrate and electronic component device
JP2009260255A (en) Semiconductor device, multilayer wiring board, and manufacturing method for them
JP2010251347A (en) Method of manufacturing semiconductor device
KR20030013737A (en) Semiconductor package and method for manufacturing the same
JP4110189B2 (en) Semiconductor package
KR101997548B1 (en) Semiconductor device and method of manufacturing the same
JP2010010301A (en) Semiconductor device and method of manufacturing the same
JP5186741B2 (en) Circuit board and semiconductor device
JP2001015650A (en) Ball grid array package and its manufacture
US7663254B2 (en) Semiconductor apparatus and method of manufacturing the same
JP2003338518A (en) Bump of semiconductor chip and method of manufacturing the same
JP2012009655A (en) Semiconductor package and method of manufacturing the semiconductor package
US9281269B2 (en) Integrated circuit package and method of manufacture
JP6467775B2 (en) Manufacturing method of component-embedded substrate
US7714417B2 (en) Substrate for mounting semiconductor element and method of manufacturing the same
JP3116926B2 (en) Package structure and semiconductor device, package manufacturing method, and semiconductor device manufacturing method
JP2007096087A (en) Method of manufacturing semiconductor device
US20020079578A1 (en) Semiconductor device having exposed adhesive sheet and method for manufacturing the same
TWI492344B (en) Semiconductor package and method of manufacture
KR20090122514A (en) Flip chip package and method of manufacturing the same
JP4593444B2 (en) Manufacturing method of electronic component mounting structure
KR101440340B1 (en) Supporting device and method for manufacturing semiconductor package using the same
JP2967080B1 (en) Method of manufacturing semiconductor device package
JP2007227608A (en) Semiconductor device and method of manufacturing semiconductor device

Legal Events

Date Code Title Description
RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20070705

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080512

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20100304