JP6467775B2 - Manufacturing method of component-embedded substrate - Google Patents

Manufacturing method of component-embedded substrate Download PDF

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JP6467775B2
JP6467775B2 JP2014046745A JP2014046745A JP6467775B2 JP 6467775 B2 JP6467775 B2 JP 6467775B2 JP 2014046745 A JP2014046745 A JP 2014046745A JP 2014046745 A JP2014046745 A JP 2014046745A JP 6467775 B2 JP6467775 B2 JP 6467775B2
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adhesive layer
component
resin material
substrate
electronic component
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JP2015170814A (en
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石月　義克
義克 石月
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Description

本発明は、部品内蔵基板の製造方法に関する。   The present invention relates to a method for manufacturing a component-embedded substrate.

ウェハレベルパッケージ（ＷＬＰ：wafer level package）の一つに、ベアチップ等の半導体チップの端子をチップエリアの外側にも配置したファンアウト（fan-out）ＷＬＰがある。ファンアウトＷＬＰの製造方法の一つに、支持体上の粘着層上に半導体チップを貼り付け、半導体チップを封止し、粘着層を除去して基板を剥離し、半導体チップに接続される配線層を形成するというものがある。また、チップコンデンサ等の受動部品を内蔵する部品内蔵基板の製造に上記の方法を適用することについて検討されている。   One of wafer level packages (WLP) is a fan-out WLP in which terminals of a semiconductor chip such as a bare chip are also arranged outside the chip area. One method of manufacturing fan-out WLP is to attach a semiconductor chip on an adhesive layer on a support, seal the semiconductor chip, remove the adhesive layer, peel off the substrate, and connect to the semiconductor chip. There is one that forms a layer. Further, the application of the above method to the manufacture of a component-embedded substrate that incorporates a passive component such as a chip capacitor has been studied.

しかしながら、これまでのところ、上記の方法を適用して部品内蔵基板を製造したときに所望の特性を安定して確保することが容易ではない。つまり、高い信頼性を得ることが容易ではない。   However, so far, it is not easy to stably secure desired characteristics when a component-embedded substrate is manufactured by applying the above method. That is, it is not easy to obtain high reliability.

特開平７−７１３４号公報Japanese Patent Laid-Open No. 7-7134 特開２００２−２０４０４５号公報JP 2002-204045 A

本発明の目的は、高い信頼性を得ることができる部品内蔵基板及びその製造方法を提供することにある。   An object of the present invention is to provide a component-embedded substrate that can obtain high reliability and a method for manufacturing the same.

部品内蔵基板の製造方法の一態様では、基板上に粘着層を形成し、前記粘着層の一部上に樹脂材を設け、複数の電極を有する電子部品を前記粘着層に前記樹脂材が前記基板の表面に平行な方向において前記複数の電極の間に位置するように貼り付け、前記電子部品を封止樹脂で封止する。前記電子部品を前記封止樹脂内に残しながら前記粘着層の粘着力を低下させ、前記基板を前記封止樹脂から剥離し、前記複数の電極に接続される配線層を形成する。 In the method for manufacturing the component-embedded substrate, an adhesive layer formed on the substrate, a resin material is provided on a portion of the adhesive layer, the resin material is the electronic component on the adhesive layer having a plurality of electrodes Affixing so as to be positioned between the plurality of electrodes in a direction parallel to the surface of the substrate, the electronic component is sealed with a sealing resin. The adhesive force of the adhesive layer is reduced while leaving the electronic component in the sealing resin, the substrate is peeled from the sealing resin, and a wiring layer connected to the plurality of electrodes is formed.

上記の部品内蔵基板の製造方法等によれば、適切な樹脂材を設けているため、高い信頼性を得ることができる。   According to the above-described method for manufacturing a component-embedded substrate, since an appropriate resin material is provided, high reliability can be obtained.

参考例を示す図である。It is a figure which shows a reference example. 第１の実施形態に係る部品内蔵基板の製造方法を工程順に示す断面図である。It is sectional drawing which shows the manufacturing method of the component built-in board | substrate concerning 1st Embodiment in order of a process. 第１の実施形態に係る部品内蔵基板の製造方法を工程順に示す平面図である。It is a top view which shows the manufacturing method of the component built-in board | substrate concerning 1st Embodiment in order of a process. 第２の実施形態に係る部品内蔵基板の製造方法を工程順に示す断面図である。It is sectional drawing which shows the manufacturing method of the component built-in board | substrate concerning 2nd Embodiment in order of a process. 図４Ａに引き続き、部品内蔵基板の製造方法を工程順に示す断面図である。FIG. 4B is a cross-sectional view illustrating the method of manufacturing the component-embedded substrate in the order of steps, following FIG. 第２の実施形態に係る部品内蔵基板の使用例を示す断面図である。It is sectional drawing which shows the usage example of the component built-in board | substrate which concerns on 2nd Embodiment. 第２の実施形態に係る部品内蔵基板の製造方法を工程順に示す平面図である。It is a top view which shows the manufacturing method of the component built-in board | substrate concerning 2nd Embodiment in order of a process. 第３の実施形態に係る部品内蔵基板の製造方法を工程順に示す断面図である。It is sectional drawing which shows the manufacturing method of the component built-in board | substrate concerning 3rd Embodiment in order of a process. 第３の実施形態に係る部品内蔵基板の製造方法を工程順に示す平面図である。It is a top view which shows the manufacturing method of the component built-in board | substrate concerning 3rd Embodiment in order of a process.

本願発明者は、従来のファンアウトＷＬＰの技術を適用して部品内蔵基板を製造したときに所望の特性を安定して確保することが容易でない原因について検討を行った。この結果、図１（ａ）に示すように、受動部品５０６の電極５０５が活性部５０４よりも突出していることが特性に影響を及ぼしていることが判明した。例えば、受動部品５０６が十分に基板５０１上の粘着層５０２に貼り付けられておらず、図１（ｂ）に示すように、封止の際に封止樹脂５０７から受ける応力により受動部品５０６が粘着層５０２から外れてしまうことがある。また、図１（ｃ）に示すように、電極５０５と活性部５０４との間の段差に伴う凹凸が配線層５１４内の絶縁膜５１２及び導電膜５１３に反映され、導電膜５１３の屈曲した部分で断線が生じることがある。   The inventor of the present application has examined the cause that it is not easy to stably secure desired characteristics when a component-embedded substrate is manufactured by applying the conventional fan-out WLP technique. As a result, as shown in FIG. 1A, it has been found that the characteristics of the electrode 505 of the passive component 506 projecting from the active portion 504 are affected. For example, the passive component 506 is not sufficiently attached to the adhesive layer 502 on the substrate 501, and as shown in FIG. 1B, the passive component 506 is caused by stress received from the sealing resin 507 during sealing. The adhesive layer 502 may come off. Further, as shown in FIG. 1C, the unevenness due to the step between the electrode 505 and the active portion 504 is reflected in the insulating film 512 and the conductive film 513 in the wiring layer 514, and the bent portion of the conductive film 513 May cause disconnection.

本願発明者は、これらの知見に基づいて以下に示す諸態様に相当した。以下、実施形態について添付の図面を参照しながら具体的に説明する。   The inventors of the present application corresponded to various aspects shown below based on these findings. Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

（第１の実施形態）
先ず、第１の実施形態について説明する。第１の実施形態は、部品内蔵基板の製造方法に関する。図２は、第１の実施形態に係る部品内蔵基板の製造方法を工程順に示す断面図であり、図３は、第１の実施形態に係る部品内蔵基板の製造方法を工程順に示す平面図である。 (First embodiment)
First, the first embodiment will be described. The first embodiment relates to a method for manufacturing a component-embedded substrate. FIG. 2 is a cross-sectional view illustrating the manufacturing method of the component built-in substrate according to the first embodiment in the order of steps, and FIG. 3 is a plan view illustrating the manufacturing method of the component built-in substrate according to the first embodiment in the order of steps. is there.

第１の実施形態では、先ず、図２（ａ）及び図３（ａ）に示すように、基板１０１上に粘着層１０２を形成する。次いで、図２（ｂ）及び図３（ｂ）に示すように、粘着層１０２の一部上に樹脂材１０３を設ける。その後、図２（ｃ）及び図３（ｃ）に示すように、複数の電極１０５を有する電子部品１０６を粘着層１０２に、樹脂材１０３が複数の電極１０５の間に位置するように貼り付ける。電子部品１０６には活性部１０４も含まれる。続いて、図２（ｄ）及び図３（ｄ）に示すように、電子部品１０６を封止樹脂１０７で封止する。次いで、図２（ｅ）に示すように、電子部品１０６を封止樹脂１０７内に残しながら粘着層１０２の粘着力を低下させ、基板１０１を封止樹脂１０７から剥離する。その後、図２（ｆ）に示すように、複数の電極１０５に接続される配線層を形成する。このようにして、部品内蔵基板１００が得られる。   In the first embodiment, first, as shown in FIGS. 2A and 3A, the adhesive layer 102 is formed on the substrate 101. Next, as shown in FIGS. 2B and 3B, a resin material 103 is provided on a part of the adhesive layer 102. Thereafter, as shown in FIGS. 2C and 3C, the electronic component 106 having the plurality of electrodes 105 is attached to the adhesive layer 102 so that the resin material 103 is positioned between the plurality of electrodes 105. . The electronic component 106 also includes an active portion 104. Subsequently, as shown in FIGS. 2D and 3D, the electronic component 106 is sealed with a sealing resin 107. Next, as shown in FIG. 2E, the adhesive force of the adhesive layer 102 is reduced while leaving the electronic component 106 in the sealing resin 107, and the substrate 101 is peeled from the sealing resin 107. Thereafter, as shown in FIG. 2F, a wiring layer connected to the plurality of electrodes 105 is formed. In this way, the component built-in substrate 100 is obtained.

そして、第１の実施形態により製造された部品内蔵基板１００には、図２（ｆ）に示すように、配線層１０８と、配線層１０８上の複数の電極１０５を有する電子部品１０６と、配線層１０８上で電子部品１０６を封止する封止樹脂１０７と、が含まれる。更に、電子部品１０６と配線層１０８との間、かつ複数の電極１０５間の樹脂材１０３も部品内蔵基板１００に含まれる。この部品内蔵基板１００では、電極１０５の配線層１０８と接する面と、樹脂材１０３の配線層１０８と接する面とが実質的に同一の平面内にある。   The component-embedded substrate 100 manufactured according to the first embodiment includes a wiring layer 108, an electronic component 106 having a plurality of electrodes 105 on the wiring layer 108, and a wiring, as shown in FIG. And a sealing resin 107 that seals the electronic component 106 on the layer 108. Furthermore, the resin material 103 between the electronic component 106 and the wiring layer 108 and between the plurality of electrodes 105 is also included in the component-embedded substrate 100. In the component-embedded substrate 100, the surface of the electrode 105 in contact with the wiring layer 108 and the surface of the resin material 103 in contact with the wiring layer 108 are substantially in the same plane.

このような第１の実施形態によれば、電子部品１０６の電極１０５と粘着層１０２との間に樹脂材１０３が存在するため、樹脂材１０３が設けられない場合と比較して、電子部品１０６と粘着層１０２との間の付着性を向上することができる。このため、封止の際に電子部品１０６を粘着層１０２上に安定して保持することができる。更に、粘着層１０２の除去後に、電極１０５の間に樹脂材１０３が残存しているため、配線層１０８は実質的に平坦な面上に形成される。従って、電子部品１０６の電極１０５が活性部１０４より突出していても、配線層１０８内の導電膜は電極１０５と活性部１０４との間の段差の影響を受けにくく、この段差に伴う断線を抑制することができる。   According to the first embodiment, since the resin material 103 exists between the electrode 105 and the adhesive layer 102 of the electronic component 106, the electronic component 106 is compared with the case where the resin material 103 is not provided. And adhesion between the adhesive layer 102 can be improved. For this reason, the electronic component 106 can be stably held on the adhesive layer 102 during sealing. Further, since the resin material 103 remains between the electrodes 105 after the adhesion layer 102 is removed, the wiring layer 108 is formed on a substantially flat surface. Therefore, even if the electrode 105 of the electronic component 106 protrudes from the active portion 104, the conductive film in the wiring layer 108 is hardly affected by the step between the electrode 105 and the active portion 104, and the disconnection due to this step is suppressed. can do.

（第２の実施形態）
次に、第２の実施形態について説明する。第２の実施形態は、部品内蔵基板の製造方法に関する。図４Ａ乃至図４Ｂは、第２の実施形態に係る部品内蔵基板の製造方法を工程順に示す断面図である。 (Second Embodiment)
Next, a second embodiment will be described. The second embodiment relates to a method for manufacturing a component-embedded substrate. 4A to 4B are cross-sectional views illustrating a method of manufacturing a component-embedded substrate according to the second embodiment in the order of steps.

第２の実施形態では、先ず、図４Ａ（ａ）に示すように、基板２０１上に粘着層２０２を形成する。基板２０１としては、例えばステンレス基板を用いる。粘着層２０２としては、例えば熱発泡フィルムを用いる。   In the second embodiment, first, an adhesive layer 202 is formed on a substrate 201 as shown in FIG. 4A (a). As the substrate 201, for example, a stainless steel substrate is used. As the adhesive layer 202, for example, a thermally foamed film is used.

次いで、図４Ａ（ｂ）に示すように、粘着層２０２の一部上に樹脂材２０３を設ける。例えば、エポキシ系樹脂、ポリイミド系樹脂又はアクリル系樹脂を樹脂材２０３として粘着層２０２上に滴下する。   Next, as shown in FIG. 4A (b), a resin material 203 is provided on a part of the adhesive layer 202. For example, an epoxy resin, a polyimide resin, or an acrylic resin is dropped on the adhesive layer 202 as the resin material 203.

その後、図４Ａ（ｃ）に示すように、半導体チップ２１１を粘着層２０２に貼り付け、活性部２０４及び複数の電極２０５を有する電子部品２０６を粘着層２０２に、樹脂材２０３が複数の電極２０５の間に位置するように貼り付ける。半導体チップ２１１は能動部品の一例である。電子部品２０６は受動部品の一例であり、電子部品２０６としては、例えばチップコンデンサ等が用いられる。樹脂材２０３は、例えば、活性部２０４と電極２０５との間の段差の大きさよりも高くなるように滴下しておく。樹脂材２０３をこのように滴下しておくことにより、電子部品２０６を粘着層１０２に貼り付ける際に、樹脂材２０３が電子部品２０６と粘着層２０２との間、かつ複数の電極２０５間に広がる。樹脂材２０３の滴下量は、例えば電極２０５と粘着層２０２との間にまで樹脂材２０３が入り込まないように調整しておくことが好ましい。樹脂材２０３としてシリカフィラーを含有するエポキシ樹脂又はポリイミド樹脂を用いてもよい。この場合、樹脂材２０３中のシリカフィラーの粒径（直径）は、活性部２０４と電極２０５との間の段差の大きさよりも小さいものとする。   4A (c), the semiconductor chip 211 is attached to the adhesive layer 202, the electronic component 206 having the active portion 204 and the plurality of electrodes 205 is attached to the adhesive layer 202, and the resin material 203 is the plurality of electrodes 205. Paste so that it is located between. The semiconductor chip 211 is an example of an active component. The electronic component 206 is an example of a passive component. As the electronic component 206, for example, a chip capacitor or the like is used. For example, the resin material 203 is dropped so as to be higher than the level difference between the active portion 204 and the electrode 205. By dropping the resin material 203 in this manner, the resin material 203 spreads between the electronic component 206 and the adhesive layer 202 and between the plurality of electrodes 205 when the electronic component 206 is attached to the adhesive layer 102. . The dropping amount of the resin material 203 is preferably adjusted so that the resin material 203 does not enter between the electrode 205 and the adhesive layer 202, for example. An epoxy resin or a polyimide resin containing a silica filler may be used as the resin material 203. In this case, the particle size (diameter) of the silica filler in the resin material 203 is smaller than the size of the step between the active portion 204 and the electrode 205.

続いて、図４Ａ（ｄ）に示すように、半導体チップ２１１及び電子部品２０６を封止樹脂１０７で封止する。封止の際には、例えば１２０℃で８分間の熱処理を行って封止樹脂１０７を熱硬化（キュア）させる。この熱処理の際に樹脂材２０３も熱硬化する。封止樹脂２０７としては、例えばシリカフィラーを含有するエポキシ樹脂又はポリイミド樹脂を用いる。封止樹脂２０７中のシリカフィラーの粒径は、活性部２０４と電極２０５との間の段差の大きさより大きくてもよい。電子部品２０６と粘着層２０２との間に納まる必要がないからである。一般的に、シリカフィラーの粒径が大きい樹脂ほど低コストで入手できる。   Subsequently, as shown in FIG. 4A (d), the semiconductor chip 211 and the electronic component 206 are sealed with a sealing resin 107. At the time of sealing, for example, heat treatment is performed at 120 ° C. for 8 minutes to thermally cure (cure) the sealing resin 107. The resin material 203 is also thermally cured during this heat treatment. As the sealing resin 207, for example, an epoxy resin or a polyimide resin containing a silica filler is used. The particle size of the silica filler in the sealing resin 207 may be larger than the size of the step between the active part 204 and the electrode 205. This is because it is not necessary to fit between the electronic component 206 and the adhesive layer 202. Generally, a resin having a larger silica filler particle size can be obtained at a lower cost.

次いで、図４Ａ（ｅ）に示すように、基板２０１が上側になるように反転させ、図４Ｂ（ｆ）に示すように、半導体チップ２１１及び電子部品２０６を封止樹脂２０７内に残しながら粘着層２０２の粘着力を低下させ、基板２０１を封止樹脂２０７から剥離する。例えばホットプレートを用いて１８０℃で２分間の熱処理を行うことにより、粘着層２０２の粘着力を低下させることができる。熱処理により粘着層２０２が発泡するため、粘着層２０２の粘着力が低下するのである。   Next, as shown in FIG. 4A (e), the substrate 201 is turned over so as to be on the upper side, and the semiconductor chip 211 and the electronic component 206 are left in the sealing resin 207 as shown in FIG. 4B (f). The adhesive force of the layer 202 is reduced, and the substrate 201 is peeled from the sealing resin 207. For example, the adhesive strength of the adhesive layer 202 can be reduced by performing a heat treatment at 180 ° C. for 2 minutes using a hot plate. Since the adhesive layer 202 is foamed by the heat treatment, the adhesive force of the adhesive layer 202 is reduced.

その後、図４Ｂ（ｇ）に示すように、複数の電極２０５に接続される配線層２１４を形成する。配線層２１４の形成では、例えばセミアディティブ法により、絶縁膜２１２及び導電膜２１３を形成する。導電膜２１３の一部を電極２０５に接続する。   Thereafter, as shown in FIG. 4B (g), a wiring layer 214 connected to the plurality of electrodes 205 is formed. In forming the wiring layer 214, the insulating film 212 and the conductive film 213 are formed by a semi-additive method, for example. Part of the conductive film 213 is connected to the electrode 205.

続いて、図４Ｂ（ｈ）に示すように、配線層２１４上に配線層２１７を形成する。配線層２１７の形成では、例えばセミアディティブ法により、絶縁膜２１５及び導電膜２１６を形成する。導電膜２１６の一部を導電膜２１３に接続する。   Subsequently, as shown in FIG. 4B (h), a wiring layer 217 is formed on the wiring layer 214. In forming the wiring layer 217, the insulating film 215 and the conductive film 216 are formed by, for example, a semi-additive method. Part of the conductive film 216 is connected to the conductive film 213.

次いで、図４Ｂ（ｉ）に示すように、導電膜２１６のパッドとなる部分上に半田ボール２１８を形成する。その後、ダイシングを行う。このようにして、個片化された部品内蔵基板２００が得られる。   Next, as shown in FIG. 4B (i), a solder ball 218 is formed on a portion to be a pad of the conductive film 216. Thereafter, dicing is performed. In this way, the component-embedded substrate 200 that is separated into pieces is obtained.

そして、部品内蔵基板２００は、例えば、図５に示すように、プリント基板２２０上に実装して用いられる。   The component-embedded substrate 200 is used by being mounted on a printed circuit board 220, for example, as shown in FIG.

このような第２の実施形態によれば、電子部品２０６の電極２０５と粘着層２０２との間に樹脂材２０３が存在するため、樹脂材２０３が設けられない場合と比較して、電子部品２０６と粘着層２０２との間の付着性を向上することができる。このため、封止の際に電子部品２０６を粘着層２０２上に安定して保持することができる。更に、粘着層２０２の除去後に、電極２０５の間に樹脂材２０３が残存しているため、配線層２１４は実質的に平坦な面上に形成される。従って、電子部品２０６の電極２０５が活性部２０４より突出していても、配線層２１４内の導電膜２１６は電極２０５と活性部２０４との間の段差の影響を受けにくく、この段差に伴う断線を抑制することができる。   According to the second embodiment, since the resin material 203 exists between the electrode 205 and the adhesive layer 202 of the electronic component 206, the electronic component 206 is compared with the case where the resin material 203 is not provided. And adhesion between the adhesive layer 202 can be improved. For this reason, the electronic component 206 can be stably held on the adhesive layer 202 during sealing. Furthermore, since the resin material 203 remains between the electrodes 205 after the adhesion layer 202 is removed, the wiring layer 214 is formed on a substantially flat surface. Therefore, even if the electrode 205 of the electronic component 206 protrudes from the active portion 204, the conductive film 216 in the wiring layer 214 is not easily affected by the step between the electrode 205 and the active portion 204, and disconnection due to this step is prevented. Can be suppressed.

（第３の実施形態）
次に、第３の実施形態について説明する。第３の実施形態は、部品内蔵基板の製造方法に関する。図７は、第３の実施形態に係る部品内蔵基板の製造方法を工程順に示す断面図である。図８は、第３の実施形態に係る部品内蔵基板の製造方法を工程順に示す平面図である。 (Third embodiment)
Next, a third embodiment will be described. The third embodiment relates to a method for manufacturing a component-embedded substrate. FIG. 7 is a cross-sectional view showing the method of manufacturing the component-embedded substrate according to the third embodiment in the order of steps. FIG. 8 is a plan view illustrating the method for manufacturing the component-embedded substrate according to the third embodiment in the order of steps.

上記のように、第２の実施形態では、図４Ａ（ｂ）及び図６（ａ）に示すように、樹脂材２０３を粘着層２０２上に滴下した後に、図４Ａ（ｃ）及び図６（ｂ）に示すように、樹脂材２０３を潰すようにして電子部品２０６を粘着層２０２に貼り付ける。第３の実施形態では、図７（ａ）及び図８（ａ）に示すように、複数の開口部３０４が形成されたシート状の樹脂材３０３を粘着層２０２上に設ける。次いで、図７（ｂ）及び図８（ｂ）に示すように、電子部品２０６の電極２０５を開口部３０４を通じて粘着層２０２に接触させる。そして、第３の実施形態と同様に、半導体チップ２１１及び電子部品２０６を封止樹脂１０７で封止する。封止の際には、例えば１２０℃で８分間の熱処理を行って封止樹脂１０７を熱硬化（キュア）させる。この熱処理の際に、樹脂材２０３が一旦流動化し、その後に熱硬化する。他の処理は第２の実施形態と同様である。   As described above, in the second embodiment, as shown in FIG. 4A (b) and FIG. 6 (a), after the resin material 203 is dropped on the adhesive layer 202, FIG. 4A (c) and FIG. As shown in b), the electronic component 206 is attached to the adhesive layer 202 so as to crush the resin material 203. In the third embodiment, as shown in FIGS. 7A and 8A, a sheet-like resin material 303 in which a plurality of openings 304 are formed is provided on the adhesive layer 202. Next, as shown in FIGS. 7B and 8B, the electrode 205 of the electronic component 206 is brought into contact with the adhesive layer 202 through the opening 304. Then, as in the third embodiment, the semiconductor chip 211 and the electronic component 206 are sealed with a sealing resin 107. At the time of sealing, for example, heat treatment is performed at 120 ° C. for 8 minutes to thermally cure (cure) the sealing resin 107. During this heat treatment, the resin material 203 is once fluidized and then thermally cured. Other processes are the same as those in the second embodiment.

このような第３の実施形態によっても第２の実施形態と同様の効果を得ることができる。   The effect similar to 2nd Embodiment can be acquired also by such 3rd Embodiment.

樹脂材３０３の材料としては、例えばエポキシ系樹脂、ポリイミド系樹脂又はアクリル系樹脂が挙げられる。   Examples of the material of the resin material 303 include an epoxy resin, a polyimide resin, and an acrylic resin.

第２の実施形態及び第３の実施形態において、粘着層２０２は熱発泡フィルムに限定されない。例えば、加熱により粘着力が低下する材料、及び紫外線の照射により粘着力が低下する材料等を粘着層２０２に用いることができる。   In the second embodiment and the third embodiment, the adhesive layer 202 is not limited to a thermally foamed film. For example, a material whose adhesive strength is reduced by heating, a material whose adhesive strength is reduced by irradiation with ultraviolet rays, or the like can be used for the adhesive layer 202.

上記のように、樹脂材２０３中のシリカフィラーの粒径は、活性部２０４と電極２０５との間の段差の大きさよりも小さいものとすることが好ましく、封止樹脂２０７中のシリカフィラーの粒径は、活性部２０４と電極２０５との間の段差の大きさより大きくてもよい。また、シリカフィラーの粒径が大きい樹脂ほど低コストで入手できる。従って、封止樹脂２０７中のシリカフィラーの粒径は樹脂材２０３中のシリカフィラーの粒径より大きいことが好ましい。樹脂材３０３についても同様である。   As described above, the particle size of the silica filler in the resin material 203 is preferably smaller than the size of the step between the active portion 204 and the electrode 205, and the silica filler particles in the sealing resin 207 The diameter may be larger than the size of the step between the active part 204 and the electrode 205. Further, a resin having a larger silica filler particle size can be obtained at a lower cost. Therefore, the particle size of the silica filler in the sealing resin 207 is preferably larger than the particle size of the silica filler in the resin material 203. The same applies to the resin material 303.

第２の実施形態及び第３の実施形態では、樹脂材２０３又は３０３の熱硬化（キュア）を封止樹脂２０７の熱硬化と共に行っているが、封止樹脂２０７の熱硬化の前に樹脂材２０３又は３０３を熱硬化させてもよい。   In the second and third embodiments, the thermosetting (curing) of the resin material 203 or 303 is performed together with the thermosetting of the sealing resin 207. However, the resin material before the thermosetting of the sealing resin 207 is performed. 203 or 303 may be thermally cured.

また、部品内蔵基板に含まれる配線層の数は限定されない。第１の実施形態のように１層でもよく、第２の実施形態及び第３の実施形態のように２層でもよく、より多くの配線層が設けられていてもよい。   Further, the number of wiring layers included in the component built-in substrate is not limited. One layer may be used as in the first embodiment, two layers may be used as in the second and third embodiments, and more wiring layers may be provided.

以下、本発明の諸態様を付記としてまとめて記載する。   Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

（付記１）
基板上に粘着層を形成する工程と、
前記粘着層の一部上に樹脂材を設ける工程と、
複数の電極を有する電子部品を前記粘着層に前記樹脂材が前記複数の電極の間に位置するように貼り付ける工程と、
前記電子部品を封止樹脂で封止する工程と、
前記電子部品を前記封止樹脂内に残しながら前記粘着層の粘着力を低下させる工程と、
前記基板を前記封止樹脂から剥離する工程と、
前記複数の電極に接続される配線層を形成する工程と、
を有することを特徴とする部品内蔵基板の製造方法。 (Appendix 1)
Forming an adhesive layer on the substrate;
Providing a resin material on a part of the adhesive layer;
A step of attaching an electronic component having a plurality of electrodes to the adhesive layer so that the resin material is positioned between the plurality of electrodes;
Sealing the electronic component with a sealing resin;
Reducing the adhesive force of the adhesive layer while leaving the electronic component in the sealing resin;
Peeling the substrate from the sealing resin;
Forming a wiring layer connected to the plurality of electrodes;
A method of manufacturing a component-embedded substrate, comprising

（付記２）
前記粘着層として熱発泡フィルムを形成し、
前記粘着層の粘着力を低下させる工程は、前記熱発泡フィルムを加熱する工程を有することを特徴とする付記１に記載の部品内蔵基板の製造方法。 (Appendix 2)
Forming a thermally foamed film as the adhesive layer,
The method for manufacturing a component built-in substrate according to claim 1, wherein the step of reducing the adhesive strength of the adhesive layer includes a step of heating the thermally foamed film.

（付記３）
前記電子部品は受動部品であることを特徴とする付記１又は２に記載の部品内蔵基板の製造方法。 (Appendix 3)
The method for manufacturing a component-embedded substrate according to appendix 1 or 2, wherein the electronic component is a passive component.

（付記４）
前記樹脂材を設ける工程は、前記樹脂材を前記粘着層の一部上に滴下する工程を有することを特徴とする付記１乃至３のいずれか１項に記載の部品内蔵基板の製造方法。 (Appendix 4)
4. The method for manufacturing a component-embedded substrate according to any one of appendices 1 to 3, wherein the step of providing the resin material includes a step of dripping the resin material onto a part of the adhesive layer.

（付記５）
前記樹脂材を設ける工程は、複数の開口部が形成されたシート状の樹脂材を前記粘着層上に設ける工程を有し、
前記電子部品を前記粘着層に貼り付ける工程は、前記複数の電極を前記複数の開口部を通じて前記粘着層に接触させる工程を有することを特徴とする付記１乃至３のいずれか１項に記載の部品内蔵基板の製造方法。 (Appendix 5)
The step of providing the resin material includes a step of providing a sheet-like resin material having a plurality of openings formed on the adhesive layer,
4. The method according to claim 1, wherein the step of attaching the electronic component to the adhesive layer includes a step of bringing the plurality of electrodes into contact with the adhesive layer through the plurality of openings. A method for manufacturing a component-embedded substrate.

（付記６）
前記樹脂材は、第１の平均粒径のシリカフィラーを含有し、
前記封止樹脂は、前記第１の平均粒径よりも大きい第２の平均粒径のシリカフィラーを含有することを特徴とする付記１乃至５のいずれか１項に記載の部品内蔵基板の製造方法。 (Appendix 6)
The resin material contains a silica filler having a first average particle diameter,
6. The component built-in substrate according to any one of appendices 1 to 5, wherein the sealing resin contains a silica filler having a second average particle size larger than the first average particle size. Method.

（付記７）
配線層と、
前記配線層上の複数の電極を有する電子部品と、
前記配線層上で前記電子部品を封止する封止樹脂と、
前記電子部品と前記配線層との間、かつ前記複数の電極間の樹脂材と、
を有することを特徴とする部品内蔵基板。 (Appendix 7)
A wiring layer;
An electronic component having a plurality of electrodes on the wiring layer;
A sealing resin for sealing the electronic component on the wiring layer;
A resin material between the electronic component and the wiring layer, and between the plurality of electrodes,
A component-embedded substrate comprising:

（付記８）
前記複数の電極の前記配線層と接する面と、前記樹脂材の前記配線層と接する面とは実質的に同一の平面内にあることを特徴とする付記７に記載の部品内蔵基板。 (Appendix 8)
The component built-in substrate according to appendix 7, wherein a surface of the plurality of electrodes that contacts the wiring layer and a surface of the resin material that contacts the wiring layer are in substantially the same plane.

（付記９）
前記電子部品は受動部品であることを特徴とする付記７又は８に記載の部品内蔵基板。 (Appendix 9)
9. The component built-in substrate according to appendix 7 or 8, wherein the electronic component is a passive component.

（付記１０）
前記樹脂材は、第１の平均粒径のシリカフィラーを含有し、
前記封止樹脂は、前記第１の平均粒径よりも大きい第２の平均粒径のシリカフィラーを含有することを特徴とする付記７乃至９のいずれか１項に記載の部品内蔵基板。 (Appendix 10)
The resin material contains a silica filler having a first average particle diameter,
10. The component built-in substrate according to any one of appendices 7 to 9, wherein the sealing resin contains a silica filler having a second average particle size larger than the first average particle size.

１００、２００：部品内蔵基板
１０１、２０１：基板
１０２、２０２：粘着層
１０３、２０３、３０３：樹脂材
１０４、２０４：活性部
１０５、２０５：電極
１０６、２０６：電子部品
１０７、２０７：封止樹脂
１０８、２１４、２１７：配線層
２１１：半導体チップ
２１３、２１６：導電膜
２１８：半田ボール
３０４：開口部 100, 200: Component built-in substrate 101, 201: Substrate 102, 202: Adhesive layer 103, 203, 303: Resin material 104, 204: Active part 105, 205: Electrode 106, 206: Electronic component 107, 207: Sealing resin 108, 214, 217: wiring layer 211: semiconductor chip 213, 216: conductive film 218: solder ball 304: opening

Claims (5)

基板上に粘着層を形成する工程と、
前記粘着層の一部上に樹脂材を設ける工程と、
複数の電極を有する電子部品を前記粘着層に前記樹脂材が前記基板の表面に平行な方向において前記複数の電極の間に位置するように貼り付ける工程と、
前記電子部品を封止樹脂で封止する工程と、
前記電子部品を前記封止樹脂内に残しながら前記粘着層の粘着力を低下させる工程と、
前記基板を前記封止樹脂から剥離する工程と、
前記複数の電極に接続される配線層を形成する工程と、
を有することを特徴とする部品内蔵基板の製造方法。 Forming an adhesive layer on the substrate;
Providing a resin material on a part of the adhesive layer;
A step of attaching an electronic component having a plurality of electrodes to the adhesive layer so that the resin material is positioned between the plurality of electrodes in a direction parallel to the surface of the substrate;
Sealing the electronic component with a sealing resin;
Reducing the adhesive force of the adhesive layer while leaving the electronic component in the sealing resin;
Peeling the substrate from the sealing resin;
Forming a wiring layer connected to the plurality of electrodes;
A method of manufacturing a component-embedded substrate, comprising 前記粘着層として熱発泡フィルムを形成し、
前記粘着層の粘着力を低下させる工程は、前記熱発泡フィルムを加熱する工程を有することを特徴とする請求項１に記載の部品内蔵基板の製造方法。 Forming a thermally foamed film as the adhesive layer,
The method of manufacturing a component built-in substrate according to claim 1, wherein the step of reducing the adhesive strength of the adhesive layer includes a step of heating the thermally foamed film. 前記電子部品は受動部品であることを特徴とする請求項１又は２に記載の部品内蔵基板の製造方法。   The method for manufacturing a component-embedded substrate according to claim 1, wherein the electronic component is a passive component. 前記樹脂材を設ける工程は、前記樹脂材を前記粘着層の一部上に滴下する工程を有することを特徴とする請求項１乃至３のいずれか１項に記載の部品内蔵基板の製造方法。   The method for producing a component-embedded board according to claim 1, wherein the step of providing the resin material includes a step of dropping the resin material onto a part of the adhesive layer. 前記樹脂材を設ける工程は、複数の開口部が形成されたシート状の樹脂材を前記粘着層上に設ける工程を有し、
前記電子部品を前記粘着層に貼り付ける工程は、前記複数の電極を前記複数の開口部を通じて前記粘着層に接触させる工程を有することを特徴とする請求項１乃至３のいずれか１項に記載の部品内蔵基板の製造方法。 The step of providing the resin material includes a step of providing a sheet-like resin material having a plurality of openings formed on the adhesive layer,
4. The method according to claim 1, wherein the step of attaching the electronic component to the adhesive layer includes a step of bringing the plurality of electrodes into contact with the adhesive layer through the plurality of openings. Manufacturing method of component built-in board.
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