JP2001332584A - Semiconductor device and method of manufacturing the same, and substrate and semiconductor chip - Google Patents
Semiconductor device and method of manufacturing the same, and substrate and semiconductor chipInfo
- Publication number
- JP2001332584A JP2001332584A JP2000150298A JP2000150298A JP2001332584A JP 2001332584 A JP2001332584 A JP 2001332584A JP 2000150298 A JP2000150298 A JP 2000150298A JP 2000150298 A JP2000150298 A JP 2000150298A JP 2001332584 A JP2001332584 A JP 2001332584A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electrode
- bump
- semiconductor chip
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
- H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体チップを基
板に実装した半導体装置、その製造方法、基板及び半導
体チップに関し、特に、接続部の信頼性が向上する半導
体装置、その製造方法、基板及び半導体チップに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor chip mounted on a substrate, a method of manufacturing the same, a substrate, and a semiconductor chip. It relates to a semiconductor chip.
【０００２】[0002]
【従来の技術】半導体チップを基板に実装するための工
法の一つに、半導体チップの電極パッド上に金バンプを
形成するとともに、この金バンプの先端に導電性樹脂を
塗布し、この金バンプ及び導電性樹脂を介してチップの
電極パッドと基板の電極パッドとを結合させる工法が知
られている。この工法で製造された半導体装置を図７に
示す。2. Description of the Related Art One of the methods for mounting a semiconductor chip on a substrate is to form a gold bump on an electrode pad of the semiconductor chip and apply a conductive resin to the tip of the gold bump. In addition, a method of connecting an electrode pad of a chip to an electrode pad of a substrate via a conductive resin is known. FIG. 7 shows a semiconductor device manufactured by this method.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、この工
法で製造された半導体装置は、実装時の残留熱応力、或
いは、温度サイクル等の熱ストレス等によって基板の電
極パッド１２２と導電性樹脂１３０との間で剥離が生じ
ることがあった。However, in the semiconductor device manufactured by this method, the electrode pad 122 of the substrate and the conductive resin 130 may not be connected to each other due to residual thermal stress during mounting or thermal stress such as a temperature cycle. Peeling sometimes occurred between them.
【０００４】また、前記工法における導電性樹脂の代わ
りに半田を用いる工法が知られているが、半田の場合で
は、基板の電極パッドと金バンプとの間の接続が強すぎ
るため、残留熱応力及び熱ストレスが半導体チップ上に
形成された金バンプと基板の電極パッドとの接続部分に
集中し、半導体チップの電極パッドを破壊するという問
題があった。Also, a method using solder instead of a conductive resin in the above-mentioned method is known. However, in the case of solder, since the connection between the electrode pad and the gold bump on the substrate is too strong, the residual thermal stress is reduced. Further, there is a problem that heat stress is concentrated on a connection portion between the gold bump formed on the semiconductor chip and the electrode pad of the substrate, and the electrode pad of the semiconductor chip is broken.
【０００５】本発明の第１の目的は、接続部の信頼性の
高い半導体装置を提供することである。A first object of the present invention is to provide a semiconductor device having a highly reliable connection portion.
【０００６】本発明の第２の目的は、製造時間の短縮が
可能な半導体装置を提供することである。A second object of the present invention is to provide a semiconductor device capable of shortening a manufacturing time.
【０００７】[0007]
【課題を解決するための手段】本発明の第１の視点にお
いては、半導体チップを基板に実装した半導体装置にお
いて、前記半導体チップの電極上に形成された凸部を有
するバンプと、前記バンプと対応する前記基板の電極に
設けられた当該バンプの凸部を差込むための穴と、を有
し、前記基板の電極とこれと対応する前記バンプとは導
電性樹脂を介して電気的に接続する、ことを特徴とす
る。According to a first aspect of the present invention, in a semiconductor device having a semiconductor chip mounted on a substrate, a bump having a convex portion formed on an electrode of the semiconductor chip; A hole provided in the corresponding electrode of the substrate for inserting a projection of the bump, and the electrode of the substrate and the corresponding bump are electrically connected via a conductive resin. To be characterized.
【０００８】また、前記半導体装置において、前記基板
の電極の穴は、当該電極を貫通するとともに、前記基板
の電極の穴に面する基板の基材部分にも穴を有してもよ
い。In the above-mentioned semiconductor device, the hole of the electrode of the substrate may have a hole in the base material portion of the substrate that passes through the electrode and faces the hole of the electrode of the substrate.
【０００９】また、前記半導体装置において、前記基板
の電極の穴は、有底孔であってもよい。In the semiconductor device, the hole of the electrode on the substrate may be a hole with a bottom.
【００１０】また、前記半導体装置において、前記バン
プの凸部は、先端が尖っていっていてもよい。[0010] In the semiconductor device, the protrusion of the bump may have a pointed tip.
【００１１】また、前記半導体装置において、前記基板
と前記半導体チップとの間に充填される封止樹脂を有す
ることが好ましい。Further, the semiconductor device preferably has a sealing resin filled between the substrate and the semiconductor chip.
【００１２】また、前記半導体装置において、前記基板
の電極は、前記バンプの凸部を差込むための穴とは別に
前記導電性樹脂を充填するための少なくとも１以上の穴
を有することが好ましい。In the semiconductor device, it is preferable that the electrode of the substrate has at least one hole for filling the conductive resin, in addition to a hole for inserting a projection of the bump.
【００１３】また、前記半導体装置において、前記半導
体チップは、前記基板側の面にのみ電極を有することが
好ましい。In the semiconductor device, the semiconductor chip preferably has an electrode only on a surface on the substrate side.
【００１４】本発明の第２の視点においては、半導体チ
ップを基板に実装した半導体装置の製造方法において、
電極上に凸部を有するバンプが形成された半導体チップ
の当該バンプの凸部周辺に導電性樹脂を塗布する工程
と、電極に前記バンプの凸部を差込むための穴があけら
れた基板の当該穴に対応する前記バンプの凸部を差込ん
で実装する工程と、実装後、前記基板と前記半導体チッ
プと間の間隙に封止樹脂を流し込んで前記導電性樹脂と
ともに硬化させる工程と、を含むことを特徴とする。According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a semiconductor chip mounted on a substrate.
A step of applying a conductive resin around the bumps of the bumps of the semiconductor chip on which the bumps having the bumps on the electrodes are formed; and a step of forming a hole in the electrode for inserting the bumps of the bumps into the substrate. A step of inserting and mounting the bumps of the bumps corresponding to the holes, and after the mounting, a step of pouring a sealing resin into a gap between the substrate and the semiconductor chip and curing the same together with the conductive resin, It is characterized by including.
【００１５】本発明の第３の視点においては、電極上に
凸部を有するバンプが形成された半導体チップを実装す
るための基板において、前記バンプと対応する前記基板
の電極に前記バンプの凸部を差込むための穴を有するこ
とを特徴とする。According to a third aspect of the present invention, in a substrate for mounting a semiconductor chip on which a bump having a protrusion on an electrode is formed, the bump of the bump is provided on an electrode of the substrate corresponding to the bump. Characterized by having a hole for inserting
【００１６】本発明の第４の視点においては、電極上に
凸部を有するバンプが形成された半導体チップにおい
て、前記バンプの凸部は、先端が尖っていることを特徴
とする。According to a fourth aspect of the present invention, in a semiconductor chip having a bump having a convex portion formed on an electrode, the convex portion of the bump has a sharp tip.
【００１７】[0017]
【発明の実施の形態】半導体チップを基板に実装した半
導体装置において、前記半導体チップの電極上に形成さ
れた凸部を有するバンプと、前記バンプと対応する前記
基板の電極に設けられた当該バンプの凸部を差込むため
の穴と、を有し、前記基板の電極とこれと対応する前記
バンプとは導電性樹脂を介して電気的に接続することに
より、基板の電極と導電性樹脂の接続面積が増大するの
で、基板の電極と導電性樹脂との界面で剥離が起こりに
くくなるとともに、製造の際、半導体チップを基板上に
位置決めするのにも役立つ。DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor device having a semiconductor chip mounted on a substrate, a bump having a convex portion formed on an electrode of the semiconductor chip, and the bump provided on an electrode of the substrate corresponding to the bump A hole for inserting a convex portion of the substrate, the electrodes of the substrate and the corresponding bumps are electrically connected to each other via a conductive resin, so that the electrodes of the substrate and the conductive resin are electrically connected to each other. Since the connection area is increased, peeling is less likely to occur at the interface between the electrode of the substrate and the conductive resin, and also helps to position the semiconductor chip on the substrate during manufacturing.
【００１８】[0018]
【実施例】本発明の実施例を図面を用いて説明する。図
１は、本発明の実施例１に係る半導体装置の部分側断面
を示した模式図であり、（Ａ）は半導体チップの実装
前、（Ｂ）はその実装後である。この半導体装置は、基
板１０と、半導体チップ２０と、を備える。この基板１
０の電極パッド１２は、半導体チップ２０に形成された
金バンプの凸部２４を差し込むための穴１４が空いてい
る点で、従来の基板と異なる（図７参照）。半導体チッ
プ２０は、そのＡｌパッド２２上に凸部２４を有する金
バンプ２３が形成されており、この金バンプ２３と対応
する基板の電極パッド１２とは導電性樹脂３０（導電性
接着剤）などを介して接続する。Embodiments of the present invention will be described with reference to the drawings. FIGS. 1A and 1B are schematic views showing a partial cross section of a semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A shows a state before the semiconductor chip is mounted, and FIG. This semiconductor device includes a substrate 10 and a semiconductor chip 20. This substrate 1
The zero electrode pad 12 is different from the conventional substrate in that a hole 14 for inserting the convex portion 24 of the gold bump formed on the semiconductor chip 20 is open (see FIG. 7). In the semiconductor chip 20, a gold bump 23 having a convex portion 24 is formed on the Al pad 22. The gold bump 23 and the corresponding electrode pad 12 on the substrate are made of a conductive resin 30 (conductive adhesive) or the like. Connect through.
【００１９】このように金バンプ２３を用いた半導体装
置では、半導体チップ２０のＡｌパッド２２上に形成さ
れた金バンプの凸部２４周辺に導電性接着剤３０等を塗
布して（図１（Ａ）参照）、金バンプの凸部２４を対応
する電極パッドの穴１４にあわせて実装される（図１
（Ｂ）参照）。導電性接着剤３０は、実装中あるいは実
装後に硬化する。実装後、基板１０と半導体チップ２０
と間の間隙に封止樹脂（熱硬化樹脂、アンダーフィル樹
脂）を毛細管現象を利用して流し込み、硬化させる。封
止樹脂を硬化させた後の実施例１を図２に示す。図２
は、本発明の実施例１に係る半導体装置を示した模式図
であり、（Ａ）は斜視図、（Ｂ）はＸ−Ｘ’間の側断面
図である。In the semiconductor device using the gold bumps 23 as described above, a conductive adhesive 30 or the like is applied around the convex portions 24 of the gold bumps formed on the Al pads 22 of the semiconductor chip 20 (FIG. 1 ( A)), and the bumps 24 of the gold bumps are mounted in correspondence with the holes 14 of the corresponding electrode pads (FIG. 1).
(B)). The conductive adhesive 30 cures during or after mounting. After mounting, the substrate 10 and the semiconductor chip 20
A sealing resin (thermosetting resin, underfill resin) is poured into the gap between the two by utilizing the capillary phenomenon and is cured. FIG. 2 shows Example 1 after the sealing resin was cured. FIG.
1A is a schematic view showing a semiconductor device according to a first embodiment of the present invention, FIG. 1A is a perspective view, and FIG. 1B is a side cross-sectional view taken along line XX ′.
【００２０】導電性樹脂３０及び封止樹脂４０として
は、例えば、エポキシ系、アクリル系、シリコーン系、
ポリイミド系の樹脂があり、その硬化温度は一般的に１
００〜２００℃の間である。導電性樹脂３０の基材と封
止樹脂４０の基材は同じものが好ましいが、別のもので
も信頼性上問題が無ければ使用可能である。As the conductive resin 30 and the sealing resin 40, for example, epoxy-based, acrylic-based, silicone-based,
There is a polyimide resin whose curing temperature is generally 1
It is between 00 and 200 ° C. The base material of the conductive resin 30 and the base material of the sealing resin 40 are preferably the same, but different base materials can be used if there is no problem in reliability.
【００２１】この実施例によれば、従来のフリップチッ
プ実装が可能なばかりではなく、工程所要時間（タク
ト）の短い実装も可能である。つまり、フリップチップ
実装する際、従来のように熱を与えて導電性樹脂を硬化
させるのではなく、常温のまま導電性樹脂がついた金バ
ンプを対応する基板の電極パッドに差し込み、封止樹脂
を封入した後に封止樹脂の硬化と同時に導電性樹脂を硬
化させる。これによって、基板と半導体チップとの接点
ズレを防げるとともに、導電性樹脂の硬化を待つ必要が
なくなりタクトの短縮化が図れる。According to this embodiment, not only conventional flip-chip mounting is possible, but also mounting with a short process time (tact) is possible. In other words, instead of applying heat to harden the conductive resin as in the past when flip-chip mounting, insert the gold bump with the conductive resin at room temperature into the electrode pad of the corresponding substrate, and seal the resin. After sealing the conductive resin, the conductive resin is cured simultaneously with the curing of the sealing resin. This prevents contact deviation between the substrate and the semiconductor chip, and eliminates the need to wait for the conductive resin to cure, thereby reducing tact time.
【００２２】次に、本発明の他の実施例に係る半導体装
置における基板について説明する。図３は、本発明の実
施例２に係る基板の部分側断面を示した模式図である。
図４は、本発明の実施例３に係る基板の部分側断面を示
した模式図である。図５は、本発明の実施例４に係る基
板の部分側断面を示した模式図である。Next, a substrate in a semiconductor device according to another embodiment of the present invention will be described. FIG. 3 is a schematic diagram illustrating a partial side cross section of a substrate according to the second embodiment of the present invention.
FIG. 4 is a schematic diagram showing a partial side cross section of a substrate according to a third embodiment of the present invention. FIG. 5 is a schematic view showing a partial side cross section of a substrate according to a fourth embodiment of the present invention.
【００２３】図１における基板１０では、電極パッドの
穴１４を貫通孔としてしているが、図３のように有底孔
としてもよい。これにより金バンプの先端が基材に突き
刺さることなく実装できる。In the substrate 10 shown in FIG. 1, the holes 14 of the electrode pads are formed as through holes, but may be formed as bottomed holes as shown in FIG. This allows the mounting without the tip of the gold bump piercing the base material.
【００２４】また、図４のように電極パッドの穴１４を
貫通孔とするとともに、基材１１にも穴１５を空け、金
バンプを深く差し込めるようにしてもよい。この基板で
は導電性樹脂を使用しなくても金バンプの凸部先端を基
材の穴にはめ込むことにより機械的に接続することも可
能である。Further, as shown in FIG. 4, the holes 14 of the electrode pads may be formed as through holes, and the holes 15 may be formed in the base material 11 so that the gold bumps can be inserted deeply. This substrate can be mechanically connected without using a conductive resin by fitting the tip of the convex portion of the gold bump into the hole of the base material.
【００２５】さらに、図５の基板のように、金バンプを
差し込むための穴１４だけではなく、樹脂と電極パッド
の接合面積を増大させるための穴１６を設けてもよい。
このように樹脂が流れ込む穴１６を設けることで、基板
の電極パッドと導電性樹脂の接続面積が増大し、接続信
頼性が向上する。Further, as shown in the substrate of FIG. 5, not only the hole 14 for inserting the gold bump but also a hole 16 for increasing the bonding area between the resin and the electrode pad may be provided.
By providing the hole 16 into which the resin flows, the connection area between the electrode pad of the substrate and the conductive resin increases, and the connection reliability improves.
【００２６】次に、本発明の他の実施例に係る半導体装
置における半導体チップを図面を用いて説明する。図６
は、本発明の実施例５に係る半導体チップの部分側断面
を示した模式図である。この半導体チップ２０は、Ｓｉ
チップ２１と、Ｓｉチップ上に配設されたＡｌパッド２
２と、Ａｌパッド上に形成された先の尖った凸部を有す
る金バンプ２３と、を備える。この半導体チップでは導
電性樹脂を使用しなくても金バンプの先端を基板（プリ
ント配線板など）の基材に突き刺すことにより機械的に
接続することも可能である。Next, a semiconductor chip in a semiconductor device according to another embodiment of the present invention will be described with reference to the drawings. FIG.
FIG. 9 is a schematic diagram showing a partial side cross section of a semiconductor chip according to Example 5 of the present invention. This semiconductor chip 20 is made of Si
Chip 21 and Al pad 2 provided on Si chip
2 and a gold bump 23 having a sharp projection formed on an Al pad. In this semiconductor chip, it is possible to mechanically connect the tip of the gold bump by piercing the base of a substrate (such as a printed wiring board) without using a conductive resin.
【００２７】[0027]
【発明の効果】本発明によれば、基板の電極パッドと導
電性樹脂の接続面積が増大するので、基板の電極パッド
と導電性樹脂との界面で剥離が起こりにくくなり、接続
部の信頼性の向上する。According to the present invention, since the connection area between the electrode pad of the substrate and the conductive resin increases, the peeling does not easily occur at the interface between the electrode pad of the substrate and the conductive resin, and the reliability of the connection portion is reduced. To improve.
【００２８】また、実装温度が半田を用いた従来工法に
比べて低いため、基板と半導体チップの熱膨張差による
金バンプと半導体チップの電極パッドとの間への応力を
低減させることができるとともに、チップの電極パッド
に亀裂がはいるという不具合を低減させることが可能で
ある。Also, since the mounting temperature is lower than that of the conventional method using solder, the stress between the gold bump and the electrode pad of the semiconductor chip due to the difference in thermal expansion between the substrate and the semiconductor chip can be reduced. In addition, it is possible to reduce the defect that the electrode pad of the chip is cracked.
【００２９】さらに、製造時間の短縮によるコストダウ
ンである。つまり、金バンプの先端が基板の電極パッド
に機械的に接続することにより、基板とチップとの接点
のズレの心配がなくなるため、従来工法のように導電性
樹脂を硬化させることなくチップと基板との間を封止樹
脂で充填できる。それゆえ、導電性樹脂の硬化時間分だ
けタクトを短縮できるので、コストダウンにつながる。Further, the cost is reduced by shortening the manufacturing time. In other words, since the tip of the gold bump is mechanically connected to the electrode pad of the substrate, there is no need to worry about the displacement of the contact between the substrate and the chip. Can be filled with a sealing resin. Therefore, the tact can be shortened by the curing time of the conductive resin, which leads to cost reduction.
【図１】本発明の実施例１に係る半導体装置の部分側断
面を示した模式図であり、（Ａ）は半導体チップの実装
前、（Ｂ）はその実装後である。FIG. 1 is a schematic view showing a partial side cross section of a semiconductor device according to a first embodiment of the present invention, wherein (A) is before mounting a semiconductor chip and (B) is after mounting.
【図２】本発明の実施例１に係る半導体装置を示した模
式図であり、（Ａ）は斜視図、（Ｂ）はＸ−Ｘ’間の側
断面図である。FIGS. 2A and 2B are schematic views showing a semiconductor device according to a first embodiment of the present invention, wherein FIG. 2A is a perspective view and FIG. 2B is a side sectional view taken along line XX ′.
【図３】本発明の実施例２に係る基板の部分側断面を示
した模式図である。FIG. 3 is a schematic diagram showing a partial cross section of a substrate according to a second embodiment of the present invention.
【図４】本発明の実施例３に係る基板の部分側断面を示
した模式図である。FIG. 4 is a schematic view showing a partial side cross section of a substrate according to a third embodiment of the present invention.
【図５】本発明の実施例４に係る基板の部分側断面を示
した模式図である。FIG. 5 is a schematic diagram showing a partial side cross section of a substrate according to a fourth embodiment of the present invention.
【図６】本発明の実施例５に係る半導体チップの部分側
断面を示した模式図である。FIG. 6 is a schematic diagram showing a partial side cross section of a semiconductor chip according to a fifth embodiment of the present invention.
【図７】従来の一例に係る半導体装置の部分側断面を示
した模式図であり、（ａ）は半導体チップの実装前、
（ｂ）はその実装後である。FIG. 7 is a schematic view showing a partial side cross section of a semiconductor device according to an example of the related art.
(B) is after the implementation.
１０、１１０ 基板 １１、１１１ 基材 １２、１１２ 電極パッド １３、１１３ 絶縁層 １４ 電極パッドの穴（バンプ差込用） １５ 基材の穴 １６ 電極パッドの穴（接合面積増大用） ２０、１２０ 半導体チップ ２１、１２１ Ｓｉチップ ２２、１２２ Ａｌパッド（電極） ２３、１２３ 金バンプ ２４、１２４ 台付凸部（金バンプ） ２５ 先尖凸部（金バンプ） ３０、１３０ 導電性樹脂（導電性接着剤） ４０ 封止樹脂 10, 110 Substrate 11, 111 Base material 12, 112 Electrode pad 13, 113 Insulating layer 14 Electrode pad hole (for bump insertion) 15 Base material hole 16 Electrode pad hole (for increasing bonding area) 20, 120 Semiconductor Chip 21, 121 Si chip 22, 122 Al pad (electrode) 23, 123 Gold bump 24, 124 Convex projection (gold bump) 25 Pointed projection (gold bump) 30, 130 Conductive resin (conductive adhesive) ) 40 sealing resin
Claims (13)
において、 前記半導体チップの電極上に形成された凸部を有するバ
ンプと、 前記バンプと対応する前記基板の電極に設けられた当該
バンプの凸部を差込むための穴と、を有し、 前記基板の電極とこれと対応する前記バンプとは導電性
樹脂を介して電気的に接続する、ことを特徴とする半導
体装置。1. A semiconductor device having a semiconductor chip mounted on a substrate, comprising: a bump having a convex portion formed on an electrode of the semiconductor chip; and a bump of the bump provided on an electrode of the substrate corresponding to the bump. And a hole for inserting a portion, wherein the electrode of the substrate and the corresponding bump are electrically connected via a conductive resin.
るとともに、 前記基板の電極の穴に面する基板の基材部分にも穴を有
する、ことを特徴とする請求項１記載の半導体装置。2. The electrode according to claim 1, wherein the hole of the electrode of the substrate penetrates the electrode and has a hole in a base material portion of the substrate facing the hole of the electrode of the substrate. Semiconductor device.
を特徴とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the holes of the electrodes on the substrate are bottomed holes.
とを特徴とする請求項１又は２記載の半導体装置。4. The semiconductor device according to claim 1, wherein said bump has a pointed tip.
される封止樹脂を有することを特徴とする請求項１乃至
４のいずれか一に記載の半導体装置。5. The semiconductor device according to claim 1, further comprising a sealing resin filled between said substrate and said semiconductor chip.
込むための穴とは別に前記導電性樹脂を充填するための
少なくとも１以上の穴を有することを特徴とする請求項
５記載の半導体装置。6. The electrode according to claim 5, wherein the electrode of the substrate has at least one hole for filling the conductive resin, in addition to the hole for inserting the projection of the bump. Semiconductor device.
み電極を有することを特徴とする請求項１乃至６のいず
れか一に記載の半導体装置。7. The semiconductor device according to claim 1, wherein the semiconductor chip has an electrode only on a surface on the substrate side.
の製造方法において、 電極上に凸部を有するバンプが形成された半導体チップ
の当該バンプの凸部周辺に導電性樹脂を塗布する工程
と、 電極に前記バンプの凸部を差込むための穴があけられた
基板の当該穴に対応する前記バンプの凸部を差込んで実
装する工程と、 実装後、前記基板と前記半導体チップと間の間隙に封止
樹脂を流し込んで前記導電性樹脂とともに硬化させる工
程と、を含むことを特徴とする半導体装置の製造方法。8. A method of manufacturing a semiconductor device in which a semiconductor chip is mounted on a substrate, wherein a step of applying a conductive resin to the periphery of the bumps of the bumps of the semiconductor chip having the bumps formed on the electrodes; A step of inserting and mounting the bumps of the bumps corresponding to the holes of the substrate on which a hole for inserting the bumps of the bumps into the electrodes has been mounted; and Pouring a sealing resin into the gap and curing the sealing resin together with the conductive resin.
半導体チップを実装するための基板において、 前記バンプと対応する前記基板の電極に設けられた当該
バンプの凸部を差込むための穴を有することを特徴とす
る基板。9. A substrate for mounting a semiconductor chip on which a bump having a convex portion formed on an electrode is mounted, wherein the convex portion of the bump provided on the electrode of the substrate corresponding to the bump is inserted. A substrate having holes.
するとともに、 前記基板の電極の穴に面する基板の基材部分にも穴を有
する、ことを特徴とする請求項８記載の基板。10. The electrode according to claim 8, wherein the hole of the electrode of the substrate penetrates the electrode and has a hole in a base material portion of the substrate facing the hole of the electrode of the substrate. substrate.
る請求項８記載の基板。11. The substrate according to claim 8, wherein said holes are bottomed holes.
差込むための穴とは別に、少なくとも１以上の穴を有す
ることを特徴とする請求項８乃至１０のいずれか一に記
載の基板。12. The electrode according to claim 8, wherein the electrode of the substrate has at least one or more holes in addition to holes for inserting protrusions of the bumps. substrate.
た半導体チップにおいて、 前記バンプの凸部は、先端が尖っていることを特徴とす
る半導体チップ。13. A semiconductor chip in which a bump having a projection on an electrode is formed, wherein the projection of the bump has a sharp tip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000150298A JP2001332584A (en) | 2000-05-22 | 2000-05-22 | Semiconductor device and method of manufacturing the same, and substrate and semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000150298A JP2001332584A (en) | 2000-05-22 | 2000-05-22 | Semiconductor device and method of manufacturing the same, and substrate and semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001332584A true JP2001332584A (en) | 2001-11-30 |
Family
ID=18656031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000150298A Withdrawn JP2001332584A (en) | 2000-05-22 | 2000-05-22 | Semiconductor device and method of manufacturing the same, and substrate and semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001332584A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006278352A (en) * | 2005-03-24 | 2006-10-12 | Seiko Instruments Inc | Thermoelectric element and its fabrication process |
| US7847417B2 (en) | 2005-12-22 | 2010-12-07 | Shinko Electric Industries Co., Ltd. | Flip-chip mounting substrate and flip-chip mounting method |
| WO2014033977A1 (en) * | 2012-08-29 | 2014-03-06 | パナソニック株式会社 | Semiconductor device |
-
2000
- 2000-05-22 JP JP2000150298A patent/JP2001332584A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006278352A (en) * | 2005-03-24 | 2006-10-12 | Seiko Instruments Inc | Thermoelectric element and its fabrication process |
| JP4667922B2 (en) * | 2005-03-24 | 2011-04-13 | セイコーインスツル株式会社 | Method for manufacturing thermoelectric element |
| US7847417B2 (en) | 2005-12-22 | 2010-12-07 | Shinko Electric Industries Co., Ltd. | Flip-chip mounting substrate and flip-chip mounting method |
| US8669665B2 (en) | 2005-12-22 | 2014-03-11 | Shinko Electric Industries Co., Ltd. | Flip-chip mounting substrate and flip-chip mounting method |
| WO2014033977A1 (en) * | 2012-08-29 | 2014-03-06 | パナソニック株式会社 | Semiconductor device |
| US9520381B2 (en) | 2012-08-29 | 2016-12-13 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device for use in flip-chip bonding, which reduces lateral displacement |
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