JPH09153514A - Semiconductor unit and semiconductor element packaging method - Google Patents

Semiconductor unit and semiconductor element packaging method

Info

Publication number
JPH09153514A
JPH09153514A JP7314198A JP31419895A JPH09153514A JP H09153514 A JPH09153514 A JP H09153514A JP 7314198 A JP7314198 A JP 7314198A JP 31419895 A JP31419895 A JP 31419895A JP H09153514 A JPH09153514 A JP H09153514A
Authority
JP
Japan
Prior art keywords
semiconductor element
sealing resin
circuit board
conductive adhesive
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7314198A
Other languages
Japanese (ja)
Other versions
JP2965496B2 (en
Inventor
Yoshihiro Bessho
芳宏 別所
Tsukasa Shiraishi
司 白石
Yoshihiro Tomura
善広 戸村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7314198A priority Critical patent/JP2965496B2/en
Publication of JPH09153514A publication Critical patent/JPH09153514A/en
Application granted granted Critical
Publication of JP2965496B2 publication Critical patent/JP2965496B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Abstract

PROBLEM TO BE SOLVED: To reduce the internal strain in a bonded part by impregnating in porous spaces of a conductive adhesive agent a liq. sealing resin to fill the gap between a semiconductor element and circuit board and hardening this resin to unify a sealing resin layer with a bonding layer of the adhesive agent. SOLUTION: In a bonding layer 10 of terminal electrodes 2 of a semiconductor element 1 and connecting electrodes 5 of a circuit board 4, porous spaces 13 are filled with a sealing resin, the gap between the element 1 and board 4 is filled with a sealing resin layer 9, and bonded part of the element 1 and board 4 is unified with the filled gap between the element 1 and board 4 whereby the internal strain caused in the bonded part can be reduced by dispersing it in the filled part of the resin, thus ensuring the bond of the element 1 to the board 4, improving the strength and adhesion of the bonded part with the adhesive agent between the element 1 and board 4 as well as the stability of the bond.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子をフェ
ースダウン状態で回路基板上に実装してなる半導体ユニ
ット及びそれに適する半導体素子の実装方法に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor unit in which a semiconductor element is mounted face down on a circuit board and a semiconductor element mounting method suitable for the semiconductor unit.

【0002】[0002]

【従来の技術】従来、半導体素子を回路基板上へ実装す
る際、半田付けが広く利用されていた。しかし、近年、
半導体素子のパッケージの小型化及び接続端子数の増加
により接続端子間隔が狭くなり、従来の半田付け技術で
対処することが次第に困難になってきた。
2. Description of the Related Art Conventionally, soldering has been widely used when mounting a semiconductor element on a circuit board. However, in recent years,
Due to the miniaturization of the package of the semiconductor device and the increase in the number of connection terminals, the connection terminal spacing becomes narrower, and it has become increasingly difficult to cope with it by the conventional soldering technique.

【0003】そこで、裸の半導体素子を回路基板上に直
付けし、実装面積の小型化と効率的使用を図ろうとする
方法が考えだされた。例えば、半導体素子を回路基板に
接続する際、あらかじめ半導体素子の端子電極上に密着
金属や拡散防止金属の蒸着膜を形成し、さらにその上に
メッキにより形成した半田層を形成して電極を構成す
る。次に、半導体素子をフェースダウンにし、高温に加
熱して半田を回路基板の接続電極に融着させる。この実
装方法は、接続後の機械的強度が強く、接続が一括にで
きることなどから有効な方法であるとされている(例え
ば、工業調査会、1980年1月15日発行、日本マイ
クロエレクトロニクス協会編、『IC化実装技術』)。
Therefore, a method of directly mounting a bare semiconductor element on a circuit board to reduce the mounting area and use it efficiently has been devised. For example, when connecting a semiconductor element to a circuit board, a vapor deposition film of adhesion metal or diffusion prevention metal is formed on the terminal electrode of the semiconductor element in advance, and a solder layer formed by plating is further formed thereon to form the electrode. To do. Next, the semiconductor element is faced down and heated to a high temperature to fuse the solder to the connection electrode of the circuit board. This mounting method is said to be an effective method because the mechanical strength after connection is strong and the connection can be made all at once (for example, Industrial Research Society, published on January 15, 1980, edited by Japan Microelectronics Association). , "IC implementation technology").

【0004】さらに、米国特許5121190号や特開
平6−61303号公報等に示されるように、半田によ
る接合部の安定性を確保するために、封入剤を用いた実
装方法及び半導体ユニットが提案されている。以下、図
5を参照しながら、この従来の半導体素子の実装方法及
びそれにより実装された半導体ユニットについて説明す
る。図5は、フェースダウンで実装された従来の半導体
ユニットの要部断面図である。
Further, as disclosed in US Pat. No. 5,121,190 and Japanese Patent Application Laid-Open No. 6-61303, a mounting method and a semiconductor unit using an encapsulant have been proposed in order to secure the stability of a joint portion by soldering. ing. Hereinafter, with reference to FIG. 5, the conventional method of mounting a semiconductor element and a semiconductor unit mounted by the method will be described. FIG. 5 is a sectional view of an essential part of a conventional semiconductor unit mounted face down.

【0005】図5に示すフェースダウンで実装された従
来の半導体ユニットは、半導体素子1と、半導体素子1
の端子電極2と、回路基板4と、回路基板4の表面に形
成された接続電極5と、接続電極5と端子電極2を接合
した半田接合部15と、半導体素子1を封止した封止樹
脂16等で構成されている。
A conventional semiconductor unit mounted face down as shown in FIG. 5 includes a semiconductor element 1 and a semiconductor element 1.
Of the terminal electrode 2, the circuit board 4, the connection electrode 5 formed on the surface of the circuit board 4, the solder joint portion 15 in which the connection electrode 5 and the terminal electrode 2 are joined, and the sealing in which the semiconductor element 1 is sealed. It is composed of resin 16 and the like.

【0006】次に、上記従来の半導体ユニットを形成す
るための半導体素子の実装方法を説明する。まず、半田
バンプを有する半導体素子1をフェースダウン状態で回
路基板4に搭載し、半田バンプを接続端子5の所定の位
置に位置合わせを行う。次に、200〜300℃の高温
に加熱して半田を溶融し、半田バンプと接続端子5を接
合し、半導体素子1を半田接合部15により回路基板4
に固定する。その後、半導体素子1と回路基板4との間
隙に液状の封止樹脂16を充填し、120℃程度で加熱
硬化することにより、封止樹脂16を固化させる。この
ようにして、半導体1の回路基板4への実装が完了す
る。
Next, a method of mounting a semiconductor element for forming the conventional semiconductor unit will be described. First, the semiconductor element 1 having solder bumps is mounted face down on the circuit board 4, and the solder bumps are aligned with predetermined positions of the connection terminals 5. Next, the solder is melted by heating to a high temperature of 200 to 300 ° C., the solder bumps and the connection terminals 5 are joined, and the semiconductor element 1 is connected to the circuit board 4 by the solder joints 15.
Fixed to After that, the liquid sealing resin 16 is filled in the gap between the semiconductor element 1 and the circuit board 4 and is heated and cured at about 120 ° C. to solidify the sealing resin 16. In this way, the mounting of the semiconductor 1 on the circuit board 4 is completed.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上記従
来の半導体ユニット及び半導体素子の実装方法において
は、次のような問題があった。第1に、半田接合部15
は剛性が大でフレキシビリティに欠ける。そのため、半
導体素子1と回路基板4との間隙に充填した液状の封止
樹脂16を熱硬化する際に、半導体素子1と回路基板4
の熱膨張係数の差により生じる熱応力が半田接合部15
に加わり、大きな内部歪が生ずる。第2に、半導体ユニ
ットを使用する際に、半導体素子1と回路基板4の熱膨
張係数の差により生ずる熱応力が半田接合部15に加わ
り、特に高温領域で使用する際には、半導体素子1と回
路基板4との間隙の封止樹脂16の熱膨張により生じる
新たな熱応力が半田接合部15に加わる。これらの結
果、半導体素子1と回路基板4との接続の信頼性が低
く、あまり実用的とはいえなかった。
However, the conventional semiconductor unit and semiconductor element mounting method described above has the following problems. First, the solder joint 15
Has high rigidity and lacks flexibility. Therefore, when the liquid sealing resin 16 filled in the gap between the semiconductor element 1 and the circuit board 4 is thermally cured, the semiconductor element 1 and the circuit board 4 are cured.
The thermal stress caused by the difference in the coefficient of thermal expansion of the solder joint 15
And a large internal distortion occurs. Secondly, when the semiconductor unit is used, thermal stress caused by the difference in thermal expansion coefficient between the semiconductor element 1 and the circuit board 4 is applied to the solder joint portion 15, and particularly when the semiconductor element 1 is used in a high temperature region. New thermal stress caused by the thermal expansion of the sealing resin 16 in the gap between the circuit board 4 and the circuit board 4 is applied to the solder joint portion 15. As a result, the reliability of the connection between the semiconductor element 1 and the circuit board 4 was low, and it was not so practical.

【0008】本発明は上記従来例の問題点を解決するた
めになされたものであり、半導体素子と回路基板との接
続の信頼性を向上させた半導体ユニット及び半導体素子
の実装方法を提供することを目的としている。
The present invention has been made to solve the above-mentioned problems of the conventional example, and provides a semiconductor unit and a mounting method of the semiconductor element in which the reliability of the connection between the semiconductor element and the circuit board is improved. It is an object.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するた
め、本発明の半導体ユニットは、半導体素子をフェース
ダウン状態で回路基板に実装したものであって、前記半
導体素子の端子電極と前記回路基板の接続電極とを電気
的及び機械的に接続する接続層と、前記半導体素子と前
記回路基板との間隙に充填された封止樹脂層を備え、前
記接合層がポーラスな導電性接着剤と前記導電性接着剤
のポーラスな空間に封止樹脂を含浸させ、硬化させるこ
とにより一体化されている。
In order to achieve the above object, a semiconductor unit of the present invention comprises a semiconductor element mounted face down on a circuit board, wherein the terminal electrodes of the semiconductor element and the circuit board are mounted. A connection layer for electrically and mechanically connecting the connection electrode of, and a sealing resin layer filled in a gap between the semiconductor element and the circuit board, wherein the bonding layer is a porous conductive adhesive and The porous space of the electrically conductive adhesive is impregnated with the sealing resin and cured to be integrated.

【0010】上記構成において、前記半導体素子の端子
電極上に突起電極を設けたことが好ましい。また、上記
各構成において、前記接合層と前記封止樹脂層が同じ熱
膨張係数を有することが好ましい。
In the above structure, it is preferable that a protruding electrode is provided on the terminal electrode of the semiconductor element. Further, in each of the above configurations, it is preferable that the bonding layer and the sealing resin layer have the same coefficient of thermal expansion.

【0011】また、上記各構成において、前記封止樹脂
層が、前記ポーラスな導電性接着剤のポーラスな空間よ
りも大きな無機フィラーを含むことが好ましい。
Further, in each of the above constitutions, it is preferable that the sealing resin layer contains an inorganic filler larger than the porous space of the porous conductive adhesive.

【0012】一方、本発明の半導体素子の実装方法は、
半導体素子をフェースダウン状態で回路基板に実装する
ものであって、前記半導体素子の端子電極をポーラスな
導電性接着剤により前記回路基板の接続電極にフェース
ダウン状態で接続する工程と、前記半導体素子と前記回
路基板との間隙に液状の封止樹脂を充填する工程と、前
記液状の封止樹脂を前記ポーラスな導電性接着剤の空間
に含浸させる工程と、前記液状の封止樹脂を硬化させる
工程を含む。
On the other hand, the semiconductor element mounting method of the present invention is
A step of mounting a semiconductor element on a circuit board in a face-down state, the step of connecting the terminal electrode of the semiconductor element to a connection electrode of the circuit board in a face-down state by a porous conductive adhesive; A step of filling a liquid sealing resin in a gap between the liquid sealing resin and the circuit board; a step of impregnating the liquid sealing resin into a space of the porous conductive adhesive; and a step of curing the liquid sealing resin. Including steps.

【0013】上記構成において、前記半導体素子の端子
電極上に突起電極を設ける工程を含むことが好ましい。
また、上記各構成において、前記ポーラスな導電性接着
剤が、少なくとも溶剤と、有機樹脂と、導電フィラーを
含む溶剤型の導電性接着剤を硬化して得られるものであ
ることが好ましい。
In the above structure, it is preferable to include a step of providing a protruding electrode on the terminal electrode of the semiconductor element.
In each of the above configurations, it is preferable that the porous conductive adhesive be obtained by curing a solvent-type conductive adhesive containing at least a solvent, an organic resin, and a conductive filler.

【0014】また、上記各構成において、前記液状の封
止樹脂が、硬化後の導電性接着剤に対して溶解性を有し
ないことが好ましい。
Further, in each of the above constitutions, it is preferable that the liquid sealing resin has no solubility in the conductive adhesive after curing.

【0015】[0015]

【発明の実施の形態】本発明の半導体ユニット及びそれ
に適する半導体素子の実装方法は、半導体素子をポーラ
スな導電性接着剤を用いて回路基板にフェースダウン状
態で搭載し、半導体素子と回路基板との間隙に充填する
液状の封止樹脂を導電性接着剤のポーラスな空間に含浸
させ、この液状の封止樹脂を硬化させる。それにより、
半導体素子と回路基板との接合部と半導体素子と回路基
板との間隙の充填部とが一体化される。その結果、接合
部に生ずる内部歪を封止樹脂の充填部へ分散させること
により内部歪を減少させることができ、半導体素子と回
路基板の接合を確実なものとすることができる。また、
接合部の導電性接着剤は、封止樹脂によりポーラスであ
った空間が充填されるため、半導体素子と回路基板の導
電性接着剤による接合部の強度や密着力が増し、接合の
安定性を向上させることができる。
BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor unit and a semiconductor element mounting method suitable for the same according to the present invention include a semiconductor element and a circuit board, which are mounted face down on a circuit board using a porous conductive adhesive. The porous space of the conductive adhesive is impregnated with the liquid sealing resin that fills the gaps, and the liquid sealing resin is cured. Thereby,
The joint portion between the semiconductor element and the circuit board and the filling portion in the gap between the semiconductor element and the circuit board are integrated. As a result, it is possible to reduce the internal strain by dispersing the internal strain generated in the bonding portion to the filling portion of the sealing resin, and to ensure the bonding between the semiconductor element and the circuit board. Also,
Since the conductive adhesive at the joint portion fills the porous space with the sealing resin, the strength and adhesion of the joint portion due to the conductive adhesive between the semiconductor element and the circuit board are increased to improve the stability of the joint. Can be improved.

【0016】(第1の実施形態)以下、本発明の半導体
ユニット及び半導体素子の実装方法の第1の実施形態に
ついて、図1から図3を参照しつつ説明する。図1にお
いて、(a)から(d)は第1の実施形態における半導
体素子の実装方法を説明する工程図であり、同時に
(d)は第1の実施形態における半導体ユニットの構成
を示す断面図である。また、図2はポーラスな導電性接
着剤の接合層を説明する要部断面図であり、図3は封止
樹脂と一体化した導電性接着剤の接合層を説明する要部
断面図である。
(First Embodiment) A first embodiment of a semiconductor unit and semiconductor element mounting method according to the present invention will be described below with reference to FIGS. 1 to 3. In FIG. 1, (a) to (d) are process drawings for explaining a mounting method of a semiconductor element in the first embodiment, and (d) is a sectional view showing a configuration of a semiconductor unit in the first embodiment. Is. Further, FIG. 2 is a cross-sectional view of a main part for explaining a bonding layer of a porous conductive adhesive, and FIG. 3 is a cross-sectional view of a main part for explaining a bonding layer of a conductive adhesive integrated with a sealing resin. .

【0017】図1(d)に示すように、第1の実施形態
に係る半導体ユニットは、半導体素子1と、半導体1に
形成された端子電極2と、回路基板4と、回路基板4の
表面に形成された接続電極5と、端子電極2と接続電極
5とを電気的及び機械的に接続する接合層10と、半導
体素子1と回路基板4との隙間に充填された封止樹脂層
9等で構成されている。なお、図1(a)〜(c)中、
3は半導体素子1を実装するのに用いる溶剤型の導電性
接着剤、6はポーラスな導電性接着剤の接合層、7は液
状の封止樹脂、8は液状の封止樹脂7が含浸した導電性
接着剤の接合層である。
As shown in FIG. 1D, the semiconductor unit according to the first embodiment has a semiconductor element 1, a terminal electrode 2 formed on the semiconductor 1, a circuit board 4, and a surface of the circuit board 4. The connection electrode 5 formed on the substrate, the bonding layer 10 for electrically and mechanically connecting the terminal electrode 2 and the connection electrode 5, and the sealing resin layer 9 filled in the gap between the semiconductor element 1 and the circuit board 4. Etc. In addition, in FIG. 1 (a)-(c),
3 is a solvent-type conductive adhesive used for mounting the semiconductor element 1, 6 is a bonding layer of a porous conductive adhesive, 7 is a liquid sealing resin, and 8 is a liquid sealing resin 7 impregnated. It is a bonding layer of a conductive adhesive.

【0018】次に、第1の実施形態に係る半導体素子の
実装方法について説明する。あらかじめ半導体素子1の
端子電極2に溶剤型の導電性接着剤3を塗布しておく。
溶剤型の導電性接着剤3は、少なくとも溶剤(例えばB
CA)と有機樹脂(例えばフェノキシ樹脂)と導電フィ
ラー(例えばAg粉)とを含む組成物である。そして、
図1(a)に示すように、この半導体素子1をフェース
ダウン(下向き)にして回路基板4の接続電極5に位置
合わせを行い、回路基板4上に半導体素子1を搭載す
る。その後、図1(b)に示すように、溶剤型の導電性
接着剤3を硬化させ、半導体素子1の端子電極2と回路
基板4の接続電極5をポーラスな導電性接着剤の接合層
6により電気的に接続される。このとき溶剤型の導電性
接着剤3を硬化させることにより含有する溶剤が蒸発
し、図2に示すように、導電フィラー11と有機樹脂1
2が残り、ポーラスな空間13を有するポーラスな導電
性接着剤の接合層6が形成される。
Next, a method of mounting the semiconductor element according to the first embodiment will be described. The solvent-type conductive adhesive 3 is applied to the terminal electrodes 2 of the semiconductor element 1 in advance.
The solvent-type conductive adhesive 3 has at least a solvent (for example, B
CA), an organic resin (for example, a phenoxy resin), and a conductive filler (for example, Ag powder). And
As shown in FIG. 1A, the semiconductor element 1 is placed face down (downward) on the connection electrodes 5 of the circuit board 4, and the semiconductor element 1 is mounted on the circuit board 4. Thereafter, as shown in FIG. 1B, the solvent-type conductive adhesive 3 is cured, and the terminal electrode 2 of the semiconductor element 1 and the connection electrode 5 of the circuit board 4 are bonded to each other by a porous conductive adhesive bonding layer 6 Electrically connected by. At this time, by curing the solvent-type conductive adhesive 3, the contained solvent evaporates, and as shown in FIG. 2, the conductive filler 11 and the organic resin 1
2 remains to form a porous conductive adhesive bonding layer 6 having a porous space 13.

【0019】次に、図1(c)に示すように、半導体素
子1と回路基板4との間隙に液状の封止樹脂7(例えば
ビスフェノールF型液状樹脂とフェノール化合物の硬化
剤とシリカフィラーとを含む組成物)を充填する。この
とき、液状の封止樹脂7はポーラスな導電性接着剤の接
合層6のポーラスな空間13に含浸され、液状の封止樹
脂が含浸した導電性接着剤の接合層8が得られる。この
とき、導電性接着剤による電気的接続を保つために、液
状の封止樹脂7には導電性接着剤に対して溶解性を持た
ないものを用いる。
Next, as shown in FIG. 1C, a liquid sealing resin 7 (for example, a bisphenol F type liquid resin, a curing agent of a phenol compound, and a silica filler) is filled in the gap between the semiconductor element 1 and the circuit board 4. The composition containing) is filled. At this time, the liquid sealing resin 7 is impregnated into the porous space 13 of the porous conductive adhesive bonding layer 6, and the conductive adhesive bonding layer 8 impregnated with the liquid sealing resin is obtained. At this time, in order to maintain the electrical connection by the conductive adhesive, a liquid sealing resin 7 that is not soluble in the conductive adhesive is used.

【0020】その後、液状の封止樹脂7の硬化を行うこ
とにより、図1(d)に示すように、半導体素子1と回
路基板4との間隙に硬化後の封止樹脂の充填層9が得ら
れると同時に、封止樹脂と一体化した導電性接着剤の接
合層10が得られる。このとき封止樹脂と一体化した導
電性接着剤の接合層10においては、図3に示すよう
に、ポーラスな導電性接着剤のポーラスな空間13に封
止樹脂が含浸された状態となる。そのため、封止樹脂の
充填層9と一体化した半導体ユニットが得られる。
Then, the liquid encapsulating resin 7 is cured to form a cured encapsulating resin filling layer 9 in the gap between the semiconductor element 1 and the circuit board 4 as shown in FIG. 1D. At the same time, the bonding layer 10 of the conductive adhesive integrated with the sealing resin is obtained. At this time, in the conductive adhesive bonding layer 10 integrated with the sealing resin, as shown in FIG. 3, the porous space 13 of the porous conductive adhesive is impregnated with the sealing resin. Therefore, a semiconductor unit integrated with the filling layer 9 of the sealing resin can be obtained.

【0021】液状の封止樹脂7の硬化工程においては、
ポーラスな導電性接着剤の接合層6のポーラスな空間1
3に含浸した液状の封止樹脂と半導体素子1と回路基板
4との間隙の液状の封止樹脂7は同時に硬化反応が進
む。このとき、半導体素子1と回路基板4との熱膨張係
数の差により硬化工程中に生じる接合部への内部歪を分
散させることにより、内部歪を減少させることができ、
半導体素子1と回路基板4の接合を確実なものとするこ
とができる。
In the process of hardening the liquid sealing resin 7,
Porous space 1 of the bonding layer 6 of porous conductive adhesive
The liquid sealing resin impregnated in 3 and the liquid sealing resin 7 in the gap between the semiconductor element 1 and the circuit board 4 simultaneously undergo a curing reaction. At this time, the internal strain can be reduced by dispersing the internal strain generated in the bonding step during the curing process due to the difference in the thermal expansion coefficient between the semiconductor element 1 and the circuit board 4.
The bonding between the semiconductor element 1 and the circuit board 4 can be ensured.

【0022】以上のようにして形成された半導体ユニッ
トにおいて、半導体素子1端子電極2と回路基板4の接
続電極5との接合層10において、ポーラスであった空
間が封止樹脂により充填され、かつ、半導体素子1と回
路基板4との間隙には封止樹脂層9が充填されている。
そのため、半導体素子1と回路基板4の導電性接着剤に
よる接合部の強度や密着力が増加し、半導体素子1と回
路基板4の接続の信頼性の高い半導体ユニットが得られ
る。このとき、封止樹脂と一体化した導電性接着剤の接
合層10と半導体素子1と回路基板4との間隙の封止樹
脂層9の熱膨張係数が同じとなるように封止樹脂中のシ
リカフィラーの配合量を調整することが望ましい。
In the semiconductor unit formed as described above, in the bonding layer 10 between the semiconductor element 1 terminal electrode 2 and the connection electrode 5 of the circuit board 4, the porous space is filled with the sealing resin, and A sealing resin layer 9 is filled in the gap between the semiconductor element 1 and the circuit board 4.
Therefore, the strength and adhesion of the joint between the semiconductor element 1 and the circuit board 4 by the conductive adhesive are increased, and a semiconductor unit with a highly reliable connection between the semiconductor element 1 and the circuit board 4 can be obtained. At this time, in the sealing resin, the bonding layer 10 of the conductive adhesive integrated with the sealing resin, the sealing resin layer 9 in the gap between the semiconductor element 1 and the circuit board 4 have the same thermal expansion coefficient. It is desirable to adjust the compounding amount of the silica filler.

【0023】(第2の実施形態)次に、本発明の半導体
ユニット及び半導体素子の実装方法の第1の実施形態に
ついて、図4を参照しつつ説明する。図4は第2の実施
形態に係る半導体ユニットの構成を示す要部断面図であ
る。上記第1の実施形態の場合と比較して、半導体素子
1の端子電極2に突起電極14を形成した点が異なる。
その他の構成は、第1の実施形態の場合と実質的に同じ
であるため、説明を省略する。
(Second Embodiment) Next, a first embodiment of a method of mounting a semiconductor unit and a semiconductor element according to the present invention will be described with reference to FIG. FIG. 4 is a main-portion cross-sectional view showing the structure of the semiconductor unit according to the second embodiment. Compared to the case of the first embodiment, the difference is that the protruding electrode 14 is formed on the terminal electrode 2 of the semiconductor element 1.
The other configuration is substantially the same as that of the first embodiment, and thus the description is omitted.

【0024】突起電極14の材料として、Au等を用い
る。端子電極2に突起電極14を形成することにより、
上記第1の実施形態の効果に加えて、半導体素子1を回
路基板4に実装する際の導電性接着剤3の広がりを規制
することができ、微細ピッチでの接合が可能になる。ま
た、突起電極14の高さ分だけ半導体素子1と回路基板
4との隙間を広くすることができ、熱応力をより緩和さ
せることができる。
Au or the like is used as the material of the bump electrodes 14. By forming the protruding electrode 14 on the terminal electrode 2,
In addition to the effects of the first embodiment, the spread of the conductive adhesive 3 when the semiconductor element 1 is mounted on the circuit board 4 can be restricted, and the bonding can be performed at a fine pitch. Further, the gap between the semiconductor element 1 and the circuit board 4 can be widened by the height of the bump electrode 14, and the thermal stress can be further alleviated.

【0025】なお、上記各実施形態において、導電性接
着剤3を半導体素子1側に塗布するように構成したが、
回路基板4の接続電極5側に導電性接着剤3を塗布して
も同様の効果が得られる。また、導電性接着剤3は溶剤
型の導電性接着剤に限られず、その硬化後にポーラスな
空間を有し、かつ電気的導通を有するものであればいか
なるものであってもよい。さらに、熱膨張係数を調整す
るために封止樹脂層9に配合するシリカ等の無機フィラ
ーの大きさとして、ポーラスな導電性接着剤のポーラス
な空間13よりも大きなものを用いるとさらにその効果
を発揮することができる。
In each of the above embodiments, the conductive adhesive 3 is applied to the semiconductor element 1 side.
The same effect can be obtained by applying the conductive adhesive 3 to the connection electrode 5 side of the circuit board 4. Further, the conductive adhesive 3 is not limited to the solvent-type conductive adhesive, and may be any one as long as it has a porous space and has electrical continuity after curing. Furthermore, if the size of the inorganic filler such as silica to be mixed in the sealing resin layer 9 to adjust the thermal expansion coefficient is larger than the porous space 13 of the porous conductive adhesive, the effect is further enhanced. Can be demonstrated.

【0026】[0026]

【発明の効果】以上に説明したように、本発明の半導体
ユニットは、半導体素子をフェースダウン状態で回路基
板に実装したものであって、半導体素子の端子電極と回
路基板の接続電極とを電気的及び機械的に接続する接続
層と、半導体素子と回路基板との間隙に充填された封止
樹脂層を備え、接合層がポーラスな導電性接着剤と導電
性接着剤のポーラスな空間に封止樹脂を含浸させ、硬化
させることにより一体化されているので、半導体素子と
回路基板との接合部と半導体素子と回路基板との間隙の
充填部とが一体化される。その結果、接合部に生ずる内
部歪を封止樹脂の充填部へ分散させることにより内部歪
を減少させることができ、半導体素子と回路基板の接合
を確実なものとすることができる。また、接合部の導電
性接着剤は、封止樹脂によりポーラスであった空間が充
填されるため、半導体素子と回路基板の導電性接着剤に
よる接合部の強度や密着力が増し、接合の安定性を向上
させることができる。
As described above, the semiconductor unit of the present invention is one in which a semiconductor element is mounted face down on a circuit board, and the terminal electrodes of the semiconductor element and the connection electrodes of the circuit board are electrically connected. It has a connection layer for mechanical and mechanical connection and a sealing resin layer filled in the gap between the semiconductor element and the circuit board, and the bonding layer is sealed in a porous space between the conductive adhesive and the conductive adhesive. Since they are integrated by being impregnated with the stop resin and then cured, the joint portion between the semiconductor element and the circuit board and the filling portion in the gap between the semiconductor element and the circuit board are integrated. As a result, it is possible to reduce the internal strain by dispersing the internal strain generated in the bonding portion to the filling portion of the sealing resin, and to ensure the bonding between the semiconductor element and the circuit board. In addition, since the conductive adhesive at the joint is filled with the porous space by the sealing resin, the strength and adhesion of the joint due to the conductive adhesive between the semiconductor element and the circuit board are increased to stabilize the joint. It is possible to improve the sex.

【0027】また、半導体素子の端子電極上に突起電極
を設けることにより、半導体素子を回路基板に実装する
際の導電性接着剤の広がりを規制することができ、微細
ピッチでの接合が可能になる。また、突起電極の高さ分
だけ半導体素子と回路基板との隙間を広くすることがで
き、熱応力をより緩和させることができる。また、接合
層と封止樹脂層の熱膨張係数を同じにすることにより、
接合層と封止樹脂層の界面における剥離やひび割れ等の
発生を防止することができる。また、封止樹脂層に、ポ
ーラスな導電性接着剤のポーラスな空間よりも大きな無
機フィラーを含めることにより、接合層と封止樹脂層の
熱膨張係数の調整が容易になる。
Further, by providing the protruding electrodes on the terminal electrodes of the semiconductor element, it is possible to restrict the spread of the conductive adhesive when the semiconductor element is mounted on the circuit board, and it is possible to join at a fine pitch. Become. Further, the gap between the semiconductor element and the circuit board can be widened by the height of the protruding electrode, and the thermal stress can be further alleviated. Further, by making the thermal expansion coefficient of the bonding layer and the sealing resin layer the same,
It is possible to prevent peeling or cracking at the interface between the bonding layer and the sealing resin layer. Further, by including an inorganic filler larger than the porous space of the porous conductive adhesive in the sealing resin layer, it becomes easy to adjust the thermal expansion coefficient of the bonding layer and the sealing resin layer.

【0028】一方、本発明の半導体素子の実装方法は、
半導体素子をフェースダウン状態で回路基板に実装する
ものであって、半導体素子の端子電極をポーラスな導電
性接着剤により回路基板の接続電極にフェースダウン状
態で接続する工程と、半導体素子と回路基板との間隙に
液状の封止樹脂を充填する工程と、液状の封止樹脂をポ
ーラスな導電性接着剤の空間に含浸させる工程と、液状
の封止樹脂を硬化させる工程を含むので、上記構成を有
する半導体ユニットを容易に製造することができる。
On the other hand, the semiconductor element mounting method of the present invention is
A semiconductor element is mounted face down on a circuit board, the step of connecting the terminal electrodes of the semiconductor element to the connection electrodes of the circuit board in a face down state with a porous conductive adhesive, and the semiconductor element and the circuit board. Since it includes a step of filling a liquid sealing resin in a gap between the liquid sealing resin, a step of impregnating the liquid sealing resin into the space of the porous conductive adhesive, and a step of curing the liquid sealing resin, It is possible to easily manufacture a semiconductor unit having.

【0029】また、ポーラスな導電性接着剤として、少
なくとも溶剤と、有機樹脂と、導電フィラーを含む溶剤
型の導電性接着剤を硬化させることにより、溶剤の揮発
により容易にポーラスな空間を形成することができる。
また、液状の封止樹脂として、硬化後の導電性接着剤に
対して溶解性を有しないものを用いることにより、封止
樹脂の注入によっていったん形成された結合層の破損を
防止することができる。
As a porous conductive adhesive, a solvent-type conductive adhesive containing at least a solvent, an organic resin, and a conductive filler is cured to easily form a porous space by volatilizing the solvent. be able to.
Further, by using a liquid encapsulating resin that is not soluble in the conductive adhesive after curing, it is possible to prevent damage to the bonding layer once formed by the injection of the encapsulating resin. .

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(d)は本発明の半導体素子の実装方
法の第1の実施形態を示す工程図であり、さらに(d)
は本発明の半導体ユニットの第1の実施形態の構成を示
す要部断面図を兼ねる。
1A to 1D are process diagrams showing a first embodiment of a semiconductor element mounting method of the present invention, and further, FIG.
Also serves as a main-portion cross-sectional view showing the configuration of the first embodiment of the semiconductor unit of the present invention.

【図2】第1の実施形態におけるポーラスな導電性接着
剤の接合層を説明する要部断面図である。
FIG. 2 is a cross-sectional view of an essential part for explaining a bonding layer of a porous conductive adhesive according to the first embodiment.

【図3】第1の実施形態における封止樹脂と一体化した
導電性接着剤の接合層を説明する要部断面図である。
FIG. 3 is a cross-sectional view of essential parts for explaining a bonding layer of a conductive adhesive integrated with a sealing resin according to the first embodiment.

【図4】本発明の半導体ユニットの第2の実施形態の構
成を示す要部断面図である。
FIG. 4 is a main-portion cross-sectional view showing the configuration of the second embodiment of the semiconductor unit of the present invention.

【図5】フェースダウンで実装された従来の半導体ユニ
ットの構成を示す要部断面図である。
FIG. 5 is a cross-sectional view of essential parts showing the configuration of a conventional semiconductor unit mounted face down.

【符号の説明】[Explanation of symbols]

1 :半導体素子 2 :端子電極 3 :溶剤型の導電性接着剤 4 :回路基板 5 :接続電極 6 :ポーラスな導電性接着剤の接合層 7 :液状の封止樹脂 8 :液状の封止樹脂が含浸した導電性接着剤の接合層 9 :硬化後の封止樹脂層 10 :封止樹脂と一体化した導電性接着剤の接合層 11 :導電フィラー 12 :有機樹脂 13 :ポーラスな空間 14 :突起電極 15 :半田接合部 16 :封止樹脂 1: Semiconductor element 2: Terminal electrode 3: Solvent-type conductive adhesive 4: Circuit board 5: Connection electrode 6: Porous conductive adhesive bonding layer 7: Liquid sealing resin 8: Liquid sealing resin Bonding layer of conductive adhesive impregnated with 9: Sealing resin layer after curing 10: Bonding layer of conductive adhesive integrated with sealing resin 11: Conductive filler 12: Organic resin 13: Porous space 14: Projection electrode 15: Solder joint 16: Sealing resin

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子をフェースダウン状態で回路
基板に実装した半導体ユニットであって、前記半導体素
子の端子電極と前記回路基板の接続電極とを電気的及び
機械的に接続する接続層と、前記半導体素子と前記回路
基板との間隙に充填された封止樹脂層を備え、前記接合
層がポーラスな導電性接着剤と前記導電性接着剤のポー
ラスな空間に封止樹脂を含浸させ、硬化させることによ
り一体化された半導体ユニット。
1. A semiconductor unit in which a semiconductor element is mounted on a circuit board in a face-down state, the connection layer electrically and mechanically connecting a terminal electrode of the semiconductor element and a connection electrode of the circuit board, A sealing resin layer filled in a gap between the semiconductor element and the circuit board, the bonding layer impregnating the sealing resin into a porous conductive adhesive and a porous space of the conductive adhesive, and curing A semiconductor unit that is integrated as a result.
【請求項2】 前記半導体素子の端子電極上に突起電極
を設けた請求項1記載の半導体ユニット。
2. The semiconductor unit according to claim 1, wherein a protruding electrode is provided on the terminal electrode of the semiconductor element.
【請求項3】 前記接合層と前記封止樹脂層が同じ熱膨
張係数を有する請求項1又は2に記載の半導体ユニッ
ト。
3. The semiconductor unit according to claim 1, wherein the bonding layer and the sealing resin layer have the same thermal expansion coefficient.
【請求項4】 前記封止樹脂層が、前記ポーラスな導電
性接着剤のポーラスな空間よりも大きな無機フィラーを
含む請求項1から3のいずれかに記載の半導体ユニッ
ト。
4. The semiconductor unit according to claim 1, wherein the sealing resin layer contains an inorganic filler larger than a porous space of the porous conductive adhesive.
【請求項5】 半導体素子をフェースダウン状態で回路
基板に実装する半導体素子の実装方法であって、前記半
導体素子の端子電極をポーラスな導電性接着剤により前
記回路基板の接続電極にフェースダウン状態で接続する
工程と、前記半導体素子と前記回路基板との間隙に液状
の封止樹脂を充填する工程と、前記液状の封止樹脂を前
記ポーラスな導電性接着剤の空間に含浸させる工程と、
前記液状の封止樹脂を硬化させる工程を含む半導体素子
の実装方法。
5. A semiconductor element mounting method for mounting a semiconductor element on a circuit board in a face-down state, wherein a terminal electrode of the semiconductor element is face-down to a connection electrode of the circuit board with a porous conductive adhesive. A step of connecting with, a step of filling a liquid sealing resin in the gap between the semiconductor element and the circuit board, a step of impregnating the liquid sealing resin into the space of the porous conductive adhesive,
A method for mounting a semiconductor element, comprising the step of curing the liquid sealing resin.
【請求項6】 前記半導体素子の端子電極上に突起電極
を設ける工程を含む請求項5記載の半導体素子の実装方
法。
6. The method of mounting a semiconductor element according to claim 5, including a step of providing a projection electrode on a terminal electrode of the semiconductor element.
【請求項7】 前記ポーラスな導電性接着剤が、少なく
とも溶剤と、有機樹脂と、導電フィラーを含む溶剤型の
導電性接着剤を硬化して得られるものである請求項5又
は6記載の半導体素子の実装方法。
7. The semiconductor according to claim 5, wherein the porous conductive adhesive is obtained by curing a solvent-type conductive adhesive containing at least a solvent, an organic resin and a conductive filler. Device mounting method.
【請求項8】 前記液状の封止樹脂が、硬化後の導電性
接着剤に対して溶解性を有しない請求項5から7のいず
れかに記載の半導体素子の実装方法。
8. The method for mounting a semiconductor element according to claim 5, wherein the liquid encapsulating resin has no solubility in a cured conductive adhesive.
JP7314198A 1995-12-01 1995-12-01 Semiconductor unit and semiconductor element mounting method Expired - Lifetime JP2965496B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7314198A JP2965496B2 (en) 1995-12-01 1995-12-01 Semiconductor unit and semiconductor element mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7314198A JP2965496B2 (en) 1995-12-01 1995-12-01 Semiconductor unit and semiconductor element mounting method

Publications (2)

Publication Number Publication Date
JPH09153514A true JPH09153514A (en) 1997-06-10
JP2965496B2 JP2965496B2 (en) 1999-10-18

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ID=18050456

Family Applications (1)

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Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000013190A1 (en) * 1998-08-28 2000-03-09 Matsushita Electric Industrial Co., Ltd. Conductive paste, conductive structure using the same, electronic part, module, circuit board, method for electrical connection, method for manufacturing circuit board, and method for manufacturing ceramic electronic part
WO2016189952A1 (en) * 2015-05-22 2016-12-01 株式会社村田製作所 Electronic component
US11752551B2 (en) 2020-04-15 2023-09-12 Nichia Corporation Resin impregnation method, method of manufacturing wavelength-conversion module, and wavelength-conversion module

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0442550A (en) * 1990-06-08 1992-02-13 Matsushita Electric Ind Co Ltd Method of mounting electronic component
JPH04137630A (en) * 1990-09-28 1992-05-12 Seiko Epson Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0442550A (en) * 1990-06-08 1992-02-13 Matsushita Electric Ind Co Ltd Method of mounting electronic component
JPH04137630A (en) * 1990-09-28 1992-05-12 Seiko Epson Corp Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000013190A1 (en) * 1998-08-28 2000-03-09 Matsushita Electric Industrial Co., Ltd. Conductive paste, conductive structure using the same, electronic part, module, circuit board, method for electrical connection, method for manufacturing circuit board, and method for manufacturing ceramic electronic part
US6479763B1 (en) 1998-08-28 2002-11-12 Matsushita Electric Industrial Co., Ltd. Conductive paste, conductive structure using the same, electronic part, module, circuit board, method for electrical connection, method for manufacturing circuit board, and method for manufacturing ceramic electronic part
WO2016189952A1 (en) * 2015-05-22 2016-12-01 株式会社村田製作所 Electronic component
US10917069B2 (en) 2015-05-22 2021-02-09 Murata Manufacturing Co., Ltd. Electronic component
US11752551B2 (en) 2020-04-15 2023-09-12 Nichia Corporation Resin impregnation method, method of manufacturing wavelength-conversion module, and wavelength-conversion module

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