JP2914569B1 - Semiconductor device mounting method and its mounting body - Google Patents
Semiconductor device mounting method and its mounting bodyInfo
- Publication number
- JP2914569B1 JP2914569B1 JP15136298A JP15136298A JP2914569B1 JP 2914569 B1 JP2914569 B1 JP 2914569B1 JP 15136298 A JP15136298 A JP 15136298A JP 15136298 A JP15136298 A JP 15136298A JP 2914569 B1 JP2914569 B1 JP 2914569B1
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor element
- inorganic filler
- semiconductor device
- fine irregularities
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
【要約】
【課題】 信頼性の高い半導体素子の実装体、及びその
ような実装体を作業性よく得ることができる半導体素子
の実装方法を提供する。
【解決手段】 表面に微細な凹凸６を有する回路基板４
に半導体素子１をフェースダウンで実装し、半導体素子
１と回路基板４の間隙に樹脂８と微細な凹凸６よりも小
さな形状を有する無機フィラー９とを含有する液状の樹
脂組成物７を充填し、硬化する。An object of the present invention is to provide a highly reliable semiconductor device package and a method for mounting such a semiconductor device with good workability. A circuit board (4) having fine irregularities (6) on its surface.
The semiconductor element 1 is mounted face down, and a gap between the semiconductor element 1 and the circuit board 4 is filled with a liquid resin composition 7 containing a resin 8 and an inorganic filler 9 having a shape smaller than the fine irregularities 6. To cure.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子の実装
方法とその実装体に関し、特にフェースダウンで実装し
てなる半導体素子の実装方法とその実装体に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor device and a mounting body thereof, and more particularly, to a method for mounting a semiconductor device and mounting the semiconductor device face down.
【０００２】[0002]
【従来の技術】従来、半導体素子の回路基板上への実装
方法としては、半田付けが一般的であった。しかし近
年、半導体素子のパッケージの小型化と接続端子数の増
加により、接続端子間の間隔が狭くなり、従来の半田付
け技術によって対処することが次第に困難になってき
た。2. Description of the Related Art Conventionally, soldering is generally used as a method for mounting a semiconductor element on a circuit board. However, in recent years, with the miniaturization of the package of the semiconductor element and the increase in the number of connection terminals, the interval between the connection terminals has been narrowed, and it has become increasingly difficult to cope with the conventional soldering technology.
【０００３】そこで最近では、裸の半導体素子を回路基
板上に直付けすることによって、実装面積の小型化と効
率的使用を図ろうとする方法が考え出されてきた。その
一例としては次のようなものがある。すなわち、半導体
素子を回路基板に接続する際に、端子電極上にあらかじ
め密着金属や拡散防止金属の蒸着膜と、メッキによって
形成された半田層とを積層した電極構造を有する半導体
素子をフェースダウンにし、高温に加熱して半田を回路
基板の接続電極に融着するようにしたものである。この
実装構造は、接続後の機械的強度が強く、接続を一括し
て行うことができることなどから、有効な方法であると
されている。また、米国特許第５１２１１９０号明細書
には、半田による接合部の安定性を確保するために樹脂
封止された半導体素子の実装体が開示されている。Therefore, recently, a method has been devised in which a bare semiconductor element is directly mounted on a circuit board to reduce the mounting area and efficiently use the semiconductor element. One example is as follows. That is, when connecting a semiconductor element to a circuit board, a semiconductor element having an electrode structure in which a deposited film of an adhesion metal or a diffusion preventing metal is previously laminated on a terminal electrode and a solder layer formed by plating is face-down. Then, the solder is heated to a high temperature to fuse the solder to the connection electrodes of the circuit board. This mounting structure is considered to be an effective method because the mechanical strength after connection is high and the connection can be performed collectively. U.S. Pat. No. 5,121,190 discloses a package of a semiconductor element which is sealed with a resin in order to secure the stability of a joint portion formed by soldering.
【０００４】以下、従来の半導体素子の実装方法とその
実装体の一例について説明する。Hereinafter, a conventional method for mounting a semiconductor device and an example of a mounting body thereof will be described.
【０００５】図３は従来技術による半導体素子の実装方
法とその実装体の要部断面図である。図３において、１
は半導体素子、２は半導体素子１の端子電極、４は回路
基板、５は接続電極、１１は半田による接合部、１２は
封止樹脂である。FIG. 3 is a sectional view of a main part of a conventional semiconductor device mounting method and its mounting body. In FIG. 3, 1
Is a semiconductor element, 2 is a terminal electrode of the semiconductor element 1, 4 is a circuit board, 5 is a connection electrode, 11 is a joint portion by solder, and 12 is a sealing resin.
【０００６】以下、このような構成を有する半導体素子
の実装体の実装方法について概説する。Hereinafter, a method of mounting a semiconductor device having the above configuration will be described.
【０００７】まず、半田バンプが端子電極２の上に形成
された半導体素子１を、回路基板４の接続端子５の所定
の位置に位置合わせを行ってフェースダウンで搭載す
る。ついで、２００℃〜３００℃の高温に加熱すること
により、半田バンプを溶融して接続端子５に融着し、半
導体素子１を半田による接合部１１によって接続する。
ついで、半導体素子１と回路基板４との間隙に液状の封
止樹脂を充填し、１５０℃程度の温度で加熱硬化する。
これにより、半導体素子１を封止樹脂１２で封止した実
装体を得ることができる。First, the semiconductor element 1 having the solder bumps formed on the terminal electrodes 2 is mounted face-down by positioning the semiconductor elements 1 at predetermined positions of the connection terminals 5 of the circuit board 4. Then, by heating to a high temperature of 200 ° C. to 300 ° C., the solder bump is melted and fused to the connection terminal 5, and the semiconductor element 1 is connected by the joint 11 made of solder.
Next, a gap between the semiconductor element 1 and the circuit board 4 is filled with a liquid sealing resin, and is heated and cured at a temperature of about 150 ° C.
Thus, a package in which the semiconductor element 1 is sealed with the sealing resin 12 can be obtained.
【０００８】[0008]
【発明が解決しようとする課題】しかし、上記のような
従来の半導体素子の実装体には、次のような問題点があ
る。すなわち、半導体素子を使用する際に、半導体素子
１と回路基板４の熱膨張係数の差によって生ずる熱応力
が半田による接合部１１に加わる。更に、高温領域で使
用する場合には、半導体素子１と回路基板４との間隙の
封止樹脂１２の熱膨張によって生ずる新たな熱応力も半
田による接合部１１に加わる。このため、半導体素子１
と回路基板４との接続の信頼性に乏しいといった問題点
がある。However, the above-mentioned conventional semiconductor device package has the following problems. That is, when a semiconductor element is used, a thermal stress caused by a difference in thermal expansion coefficient between the semiconductor element 1 and the circuit board 4 is applied to the joint portion 11 made of solder. Further, when used in a high-temperature region, new thermal stress generated by thermal expansion of the sealing resin 12 in the gap between the semiconductor element 1 and the circuit board 4 is also applied to the joint portion 11 by solder. Therefore, the semiconductor device 1
There is a problem that the reliability of connection between the semiconductor device and the circuit board 4 is poor.
【０００９】これを避けるには、封止樹脂１２として熱
膨張係数の小さなものを用いることにより、半田による
接合部１１の安定性を確保する必要がある。そして、こ
れを実現するためには、封止樹脂１２に無機フィラーを
約４０〜７５重量％（さらに好ましくは約５０〜６０重
量％）含有させなければならない。In order to avoid this, it is necessary to ensure the stability of the joint 11 by soldering by using a resin having a small thermal expansion coefficient as the sealing resin 12. To achieve this, the sealing resin 12 must contain about 40 to 75% by weight (more preferably, about 50 to 60% by weight) of an inorganic filler.
【００１０】しかし、このように封止樹脂１２に無機フ
ィラーを約４０〜７５重量％も含有させると、封止樹脂
１２は硬化前の液状の状態でも粘度が高くなり、半導体
素子１と回路基板４との狭い間隙に充填する際の作業性
が悪いといった問題点がある。However, when the sealing resin 12 contains about 40 to 75% by weight of the inorganic filler, the sealing resin 12 has a high viscosity even in a liquid state before being cured, and the semiconductor element 1 and the circuit board are hardened. There is a problem that workability at the time of filling into a narrow gap with No. 4 is poor.
【００１１】本発明は、従来技術における前記課題を解
決し、信頼性の高い半導体素子の実装体と、そのような
実装体を作業性よく得ることができる半導体素子の実装
方法を提供することを目的とする。An object of the present invention is to solve the above-mentioned problems in the prior art and to provide a highly reliable semiconductor device package and a semiconductor device mounting method capable of obtaining such a package with good workability. Aim.
【００１２】[0012]
【課題を解決するための手段】前記目的を達成するた
め、本発明は以下の構成とする。To achieve the above object, the present invention has the following constitution.
【００１３】即ち、本発明に係る半導体素子の実装方法
は、半導体素子をフェースダウンで回路基板に実装する
半導体素子の実装方法であって、表面に微細な凹凸を有
する回路基板に半導体素子を実装し、前記半導体素子と
前記回路基板の間隙に少なくとも樹脂と回路基板の前記
微細な凹凸よりも小さな形状を有する無機フィラーとを
含有する液状の樹脂組成物を充填し、前記液状の樹脂組
成物を硬化することを特徴とする。That is, a method for mounting a semiconductor element according to the present invention is a method for mounting a semiconductor element on a circuit board face down, wherein the semiconductor element is mounted on a circuit board having fine irregularities on the surface. Then, a gap between the semiconductor element and the circuit board is filled with a liquid resin composition containing at least a resin and an inorganic filler having a shape smaller than the fine unevenness of the circuit board, and the liquid resin composition is It is characterized by curing.
【００１４】上記の構成によれば、半導体素子と表面に
微細な凹凸が形成された回路基板の間隙に樹脂と無機フ
ィラーとを含有する液状の樹脂組成物を充填する際に、
無機フィラーが回路基板の表面の微細な凹凸よりも小さ
な形状を有するので、液状の樹脂組成物中の樹脂だけで
なく無機フィラーをも、回路基板に形成された微細な凹
凸に充填することができる。その結果、半導体素子と回
路基板の間隙の無機フィラー濃度が各箇所で一定に保た
れ、無機フィラーが微細な凹凸に入り込めず、無機フィ
ラー濃度が高くなるということに起因する半導体素子と
回路基板との間隙中での無機フィラーを含有する液状の
樹脂組成物の詰まりを抑制することができる。したがっ
て、封止樹脂の充填工程の作業性が向上する。また、無
機フィラーを高濃度に含有でき、しかもこれを均一に分
散できるので、封止樹脂の熱膨張むらが少なく、接合部
の信頼性が高い実装体を得ることができる。よって、本
発明において無機フィラーが「回路基板の微細な凹凸よ
りも小さな形状を有する」とは、上記趣旨より、回路基
板表面に形成された微細な凹凸の凹部に無機フィラーが
入り込むことが可能であるほどに無機フィラーが凹凸よ
り小さいことを意味し、より詳しくは、無機フィラーが
前記凹部に入った場合に当該凹部の両側の凸部の頂点を
結ぶ直線より無機フィラーが上にはみ出さないほどに無
機フィラーが凹凸より小さいことを意味する。According to the above configuration, when the liquid resin composition containing the resin and the inorganic filler is filled in the gap between the semiconductor element and the circuit board having fine irregularities formed on the surface,
Since the inorganic filler has a shape smaller than the fine unevenness on the surface of the circuit board, not only the resin in the liquid resin composition but also the inorganic filler can be filled in the fine unevenness formed on the circuit board. . As a result, the concentration of the inorganic filler in the gap between the semiconductor element and the circuit board is kept constant at each location, the inorganic filler cannot enter the fine irregularities, and the concentration of the inorganic filler increases, resulting in a high inorganic filler concentration. Clogging of the liquid resin composition containing the inorganic filler in the gap between the resin composition. Therefore, the workability of the sealing resin filling step is improved. In addition, since the inorganic filler can be contained at a high concentration and can be dispersed uniformly, a package having less unevenness in thermal expansion of the sealing resin and high reliability of the joint can be obtained. Therefore, in the present invention, the inorganic filler "has a shape smaller than the fine irregularities of the circuit board" means that the inorganic filler can enter the concaves of the fine irregularities formed on the surface of the circuit board from the above purpose. It means that the inorganic filler is smaller than the irregularities to a certain extent, more specifically, when the inorganic filler enters the concave portion, the inorganic filler does not protrude above a straight line connecting the vertices of the convex portions on both sides of the concave portion. Mean that the inorganic filler is smaller than the unevenness.
【００１５】上記の構成において、前記半導体素子を半
田バンプを用いて前記回路基板に実装するのが好まし
い。かかる好ましい構成によれば、接続を一括して行う
ことができるので、実装の作業性が向上する。また、半
導体素子を回路基板に接続した後の機械的強度が強く、
信頼性も向上する。In the above configuration, it is preferable that the semiconductor element is mounted on the circuit board using solder bumps. According to such a preferable configuration, the connection can be performed collectively, so that the mounting workability is improved. Also, the mechanical strength after connecting the semiconductor element to the circuit board is strong,
Reliability is also improved.
【００１６】また、上記の構成において、前記半導体素
子を導電性接着剤を用いて前記回路基板に実装するのが
好ましい。かかる好ましい構成によれば、半導体素子を
回路基板に搭載するだけで簡単に実装することができる
ので、実装の作業性が向上する。なお、この際、半導体
素子に突起電極を形成し、突起電極に導電性接着剤を付
着させて回路基板に搭載してもよい。かかる構成によれ
ば、導電性接着剤の突起電極への付着を、突起電極を導
電性接着剤浴へ浸すことにより容易に一括して転写でき
るので、作業性が向上する。In the above structure, it is preferable that the semiconductor element is mounted on the circuit board using a conductive adhesive. According to such a preferred configuration, the semiconductor element can be easily mounted simply by mounting it on the circuit board, so that the mounting workability is improved. At this time, a bump electrode may be formed on the semiconductor element, and a conductive adhesive may be attached to the bump electrode to mount the bump on the circuit board. According to such a configuration, the adhesion of the conductive adhesive to the protruding electrodes can be easily and collectively transferred by immersing the protruding electrodes in the conductive adhesive bath, so that the workability is improved.
【００１７】また、上記の構成において、前記微細な凹
凸が、回路基板にドリル又はレーザー等で形成されるの
が好ましい。かかる好ましい構成によれば、任意の形状
及び大きさの凹凸を形成することが容易にできるので、
無機フィラーの選択の幅が広がる。また、無機フィラー
の径に応じて凹凸の大きさ変えれば、無機フィラーを確
実に凹凸に充填させることができる。In the above structure, it is preferable that the fine unevenness is formed on the circuit board by a drill or a laser. According to such a preferred configuration, it is possible to easily form irregularities of any shape and size,
The range of choice of inorganic filler is expanded. Further, if the size of the unevenness is changed according to the diameter of the inorganic filler, the inorganic filler can be reliably filled in the unevenness.
【００１８】また、上記の構成において、前記微細な凹
凸が、回路基板表面を化学的処理を施すことにより形成
されるのが好ましい。かかる好ましい構成によれば、一
括して凹凸を形成することができるので作業性が向上す
る。また、化学的処理の時間を選択することにより、任
意の大きさの凹凸を形成することが容易にできるので、
無機フィラーの選択の幅が広がる。また、無機フィラー
の径に応じて凹凸の大きさ変えれば、無機フィラーを確
実に凹凸に充填させることができる。In the above structure, it is preferable that the fine unevenness is formed by performing a chemical treatment on the surface of the circuit board. According to such a preferred configuration, the unevenness can be formed collectively, so that the workability is improved. Also, by selecting the time of the chemical treatment, it is possible to easily form irregularities of any size,
The range of choice of inorganic filler is expanded. Further, if the size of the unevenness is changed according to the diameter of the inorganic filler, the inorganic filler can be reliably filled in the unevenness.
【００１９】また、上記の構成において、前記表面に微
細な凹凸を有する回路基板が、多孔質の回路基板である
のが好ましい。かかる好ましい構成によれば、多孔質の
凹凸の大きさに応じて無機フィラーの径を変えれば、無
機フィラーを確実に凹凸に充填させることができる。In the above structure, it is preferable that the circuit board having fine irregularities on the surface is a porous circuit board. According to such a preferred configuration, if the diameter of the inorganic filler is changed according to the size of the porous unevenness, the inorganic filler can be reliably filled in the unevenness.
【００２０】また、本発明にかかる半導体素子の実装体
は、表面に微細な凹凸を有する回路基板と、前記回路基
板にフェースダウンで実装された半導体素子と、前記半
導体素子と前記回路基板の間隙に充填された、少なくと
も樹脂と回路基板の前記微細な凹凸よりも小さな形状を
有する無機フィラーを含有した樹脂組成物とを備えたこ
とを特徴とする。Further, a semiconductor device mounted body according to the present invention includes a circuit board having fine irregularities on its surface, a semiconductor element mounted face down on the circuit board, and a gap between the semiconductor element and the circuit board. And a resin composition containing at least a resin and an inorganic filler having a shape smaller than the fine irregularities of the circuit board.
【００２１】上記の構成によれば、半導体素子と回路基
板との間の封止樹脂に含有された無機フィラーが回路基
板の表面の微細な凹凸よりも小さな形状を有するので、
無機フィラーは微細な凹凸部にも均一に入り込むことが
できる。したがって、封止樹脂中に無機フィラーを高濃
度かつ均一に分散した実装体とすることができ、封止樹
脂の熱膨張むらが少なく、接合部の信頼性が高い実装体
を得ることができる。According to the above structure, the inorganic filler contained in the sealing resin between the semiconductor element and the circuit board has a shape smaller than the fine irregularities on the surface of the circuit board.
The inorganic filler can even penetrate into fine irregularities. Therefore, it is possible to obtain a package in which the inorganic filler is uniformly dispersed at a high concentration in the sealing resin, and it is possible to obtain a package in which the thermal expansion of the sealing resin is small and the bonding portion has high reliability.
【００２２】上記の構成において、前記微細な凹凸が、
半導体素子が実装された表面にのみ形成されているのが
好ましい。かかる好ましい構成によれば、裏面に別の要
領で実装する場合、その実装の妨げにならない。In the above arrangement, the fine irregularities are
Preferably, it is formed only on the surface on which the semiconductor element is mounted. According to such a preferable configuration, when mounting on the back surface in another manner, the mounting is not hindered.
【００２３】[0023]
【発明の実施の形態】以下、実施例を用いて本発明をさ
らに具体的に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described more specifically with reference to examples.
【００２４】図１は本発明に関わる半導体素子の実装方
法の一実施例を示す工程図、図２は本発明に関わる半導
体素子の実装体の一実施例を示す要部断面図である。FIG. 1 is a process diagram showing one embodiment of a method for mounting a semiconductor device according to the present invention, and FIG. 2 is a sectional view of a main part showing one embodiment of a semiconductor device mounting body according to the present invention.
【００２５】図１、図２において、１は半導体素子、２
は端子電極、３は導電性接着剤、４は回路基板、５は接
続電極、６は回路基板４に施された微細な凹凸、７は液
状の樹脂組成物、８は樹脂、９は無機フィラー、１０は
硬化後の樹脂組成物である。1 and 2, reference numeral 1 denotes a semiconductor element;
Is a terminal electrode, 3 is a conductive adhesive, 4 is a circuit board, 5 is a connection electrode, 6 is fine irregularities formed on the circuit board 4, 7 is a liquid resin composition, 8 is a resin, and 9 is an inorganic filler. Reference numeral 10 denotes a cured resin composition.
【００２６】以下、このような構成を有する半導体素子
の実装方法について、図１を参照しながら説明する。Hereinafter, a method for mounting a semiconductor device having such a configuration will be described with reference to FIG.
【００２７】まず、図１（ａ）に示すように、半導体素
子１の端子電極２にあらかじめ導電性接着剤３を形成し
ておく。この場合、導電性接着剤３は端子電極２の上に
直接形成してもよいし、端子電極２にあらかじめ形成し
た突起電極（バンプ）上に形成してもよい。一方、回路
基板４の表面には、ドリルやレーザーなどであらかじめ
微細な凹凸６を施しておく。この場合、化学的処理によ
って回路基板４の表面に微細な凹凸を施してもよい。ま
た、多孔質の基板材料を回路基板４として用いてもよ
い。First, as shown in FIG. 1A, a conductive adhesive 3 is formed on the terminal electrodes 2 of the semiconductor element 1 in advance. In this case, the conductive adhesive 3 may be formed directly on the terminal electrode 2 or may be formed on a bump electrode (bump) formed on the terminal electrode 2 in advance. On the other hand, fine irregularities 6 are previously formed on the surface of the circuit board 4 with a drill, a laser, or the like. In this case, fine irregularities may be formed on the surface of the circuit board 4 by a chemical treatment. Further, a porous substrate material may be used as the circuit board 4.
【００２８】次いで、この半導体素子１をフェースダウ
ン（下向き）にして回路基板４の接続電極５の所定の位
置に位置合わせを行い、回路基板４の上に半導体素子１
を搭載する。これにより、半導体素子１の端子電極２と
回路基板４の接続電極５とが導電性接着剤３によって電
気的に接続される（図１（ｂ））。Next, the semiconductor element 1 is face down (downward), and is positioned at a predetermined position of the connection electrode 5 on the circuit board 4.
With. Thus, the terminal electrodes 2 of the semiconductor element 1 and the connection electrodes 5 of the circuit board 4 are electrically connected by the conductive adhesive 3 (FIG. 1B).
【００２９】次いで、図１（ｃ）に示すように、半導体
素子１と回路基板４との間隙に液状の樹脂組成物７を充
填する。そして、１５０℃程度の温度で加熱することに
より、液状の樹脂組成物７を硬化する。Next, as shown in FIG. 1C, the gap between the semiconductor element 1 and the circuit board 4 is filled with a liquid resin composition 7. Then, by heating at a temperature of about 150 ° C., the liquid resin composition 7 is cured.
【００３０】これにより、図２に示すような半導体素子
１の実装体を得ることができる。Thus, a package of the semiconductor device 1 as shown in FIG. 2 can be obtained.
【００３１】このとき用いる液状の樹脂組成物７には、
少なくとも樹脂８（例えばエポキシ樹脂）と無機フィラ
ー９（例えばシリカ）とが含有されており、かつ、無機
フィラー９としては回路基板４に形成された微細な凹凸
６よりも小さな形状のものが用いられている。これによ
り、無機フィラー９が回路基板４に形成されている微細
な凹凸６に入り込めず、無機フィラー９の濃度が高くな
ることに起因する半導体素子１と回路基板４との間隙中
での無機フィラー９を含有する液状の樹脂組成物７の詰
まりを抑制することができる。したがって、封止樹脂の
充填工程の作業性が向上する。また、半導体素子１と回
路基板４との間隙に存する硬化後の樹脂組成物１０にお
いて、無機フィラー９の濃度を高濃度としても、無機フ
ィラー９の濃度が各箇所において一定となり、封止樹脂
の熱膨張むらが少なくなり、接合部の信頼性が向上す
る。以上の結果、半導体素子１の実装体は信頼性高いも
のを得ることができる。The liquid resin composition 7 used at this time includes:
At least a resin 8 (for example, an epoxy resin) and an inorganic filler 9 (for example, silica) are contained, and the inorganic filler 9 has a shape smaller than the fine unevenness 6 formed on the circuit board 4. ing. As a result, the inorganic filler 9 cannot enter the fine irregularities 6 formed on the circuit board 4, and the inorganic filler 9 in the gap between the semiconductor element 1 and the circuit board 4 due to the increased concentration of the inorganic filler 9 Clogging of the liquid resin composition 7 containing the filler 9 can be suppressed. Therefore, the workability of the sealing resin filling step is improved. Further, in the cured resin composition 10 existing in the gap between the semiconductor element 1 and the circuit board 4, even if the concentration of the inorganic filler 9 is set to be high, the concentration of the inorganic filler 9 becomes constant at each location, and the sealing resin Thermal expansion unevenness is reduced, and the reliability of the joint is improved. As a result, a highly reliable mounting body of the semiconductor element 1 can be obtained.
【００３２】尚、半導体素子１は導電性接着剤３を用い
て回路基板４に実装されているが、必ずしも導電性接着
剤３に限定されるものではなく、例えば半田バンプを用
いて実装するなど、他の方法で半導体素子１を実装して
もよい。Although the semiconductor element 1 is mounted on the circuit board 4 using the conductive adhesive 3, it is not necessarily limited to the conductive adhesive 3, and may be mounted using, for example, solder bumps. Alternatively, the semiconductor element 1 may be mounted by another method.
【００３３】また、回路基板４の表面にドリルやレーザ
ーなどであらかじめ微細な凹凸６を施す場合、用いるド
リルやレーザーによって微細な凹凸の大きさを制御する
ことができる。そこで、使用する無機フィラーに応じて
形成する凹凸の大きさを制御すれば、微細な凹凸よりも
小さな径を有する無機フィラーを含有する液状の樹脂組
成物を確実に選択できるので、微細な凹凸に樹脂だけで
なく無機フィラーをも確実に充填することができる。In the case where the fine unevenness 6 is previously formed on the surface of the circuit board 4 with a drill or laser, the size of the fine unevenness can be controlled by the drill or laser used. Therefore, by controlling the size of the unevenness formed according to the inorganic filler to be used, it is possible to reliably select a liquid resin composition containing an inorganic filler having a smaller diameter than the fine unevenness. Inorganic fillers as well as resins can be reliably filled.
【００３４】更に、回路基板４の表面に化学的処理によ
ってあらかじめ微細な凹凸６を施す場合、化学的処理を
施す時間によって微細な凹凸の大きさを制御することが
できる。そこで、使用する無機フィラーに応じて形成す
る凹凸の大きさを制御すれば、微細な凹凸よりも小さな
径を有する無機フィラーを含有する液状の樹脂組成物を
確実に選択できるので、微細な凹凸に樹脂だけでなく無
機フィラーをも確実に充填することができる。また、一
括して凹凸を施すことができるので作業性がよい。Further, when the fine irregularities 6 are previously formed on the surface of the circuit board 4 by a chemical treatment, the size of the fine irregularities can be controlled by the time for performing the chemical treatment. Therefore, by controlling the size of the unevenness formed according to the inorganic filler to be used, it is possible to reliably select a liquid resin composition containing an inorganic filler having a smaller diameter than the fine unevenness. Inorganic fillers as well as resins can be reliably filled. In addition, the workability is good because the unevenness can be formed collectively.
【００３５】[0035]
【発明の効果】以上説明したように、本発明に関わる半
導体素子の実装方法によれば、液状の樹脂組成物中の樹
脂のみだけでなく無機フィラーをも、回路基板に施され
た微細な凹凸に充填することができる。このため、半導
体素子と回路基板の間隙に液状の樹脂組成物を注入する
際、無機フィラーが回路基板上の微細な凹凸に入り込め
ず、無機フィラーの濃度が高くなるということに起因す
る半導体素子と回路基板との間隙中での液状の樹脂組成
物の詰まりを抑制することができる。したがって、封止
樹脂の充填工程の作業性が向上する。また、無機フィラ
ーを高濃度に含有でき、しかもこれを均一に分散できる
ので、封止樹脂の熱膨張むらが少なく、接合部の信頼性
が高い実装体を得ることができる。以上の結果、半導体
素子を回路基板に信頼性高く実装することができる。As described above, according to the method of mounting a semiconductor device according to the present invention, not only the resin in the liquid resin composition but also the inorganic filler is applied to the fine irregularities formed on the circuit board. Can be filled. Therefore, when a liquid resin composition is injected into the gap between the semiconductor element and the circuit board, the inorganic filler cannot enter into the fine irregularities on the circuit board, and the concentration of the inorganic filler is increased. Clogging of the liquid resin composition in the gap between the substrate and the circuit board can be suppressed. Therefore, the workability of the sealing resin filling step is improved. In addition, since the inorganic filler can be contained at a high concentration and can be dispersed uniformly, a package having less unevenness in thermal expansion of the sealing resin and high reliability of the joint can be obtained. As a result, the semiconductor element can be mounted on the circuit board with high reliability.
【００３６】また、本発明の半導体素子の実装体によれ
ば、半導体素子と回路基板との間の封止樹脂に含有され
た無機フィラーが回路基板の表面の微細な凹凸よりも小
さな形状を有するので、無機フィラーは微細な凹凸部に
も均一に入り込むことができる。したがって、封止樹脂
中に無機フィラーを高濃度かつ均一に分散した実装体と
することができ、封止樹脂の熱膨張むらが少なく、接合
部の信頼性が高い実装体を得ることができる。According to the semiconductor device package of the present invention, the inorganic filler contained in the sealing resin between the semiconductor device and the circuit board has a shape smaller than fine irregularities on the surface of the circuit board. Therefore, the inorganic filler can uniformly penetrate into fine irregularities. Therefore, it is possible to obtain a package in which the inorganic filler is uniformly dispersed at a high concentration in the sealing resin, and it is possible to obtain a package in which the thermal expansion of the sealing resin is small and the bonding portion has high reliability.
【図１】 本発明に関わる半導体素子の実装方法の一実
施例を示す工程図である。FIG. 1 is a process chart showing one embodiment of a method for mounting a semiconductor device according to the present invention.
【図２】 本発明に関わる半導体素子の実装体の一実施
例を示す要部断面図である。FIG. 2 is a cross-sectional view of a principal part showing one embodiment of a semiconductor element package according to the present invention.
【図３】 従来の半導体素子の実装体を示す要部断面図
である。FIG. 3 is a cross-sectional view illustrating a main part of a conventional semiconductor device package.
１ 半導体素子 ２ 端子電極 ３ 導電性接着剤 ４ 回路基板 ５ 接続電極 ６ 微細な凹凸 ７ 液状の樹脂組成物 ８ 樹脂 ９ 無機フィラー １０ 硬化後の樹脂組成物 １１ はんだバンプ １２ 封止樹脂 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Terminal electrode 3 Conductive adhesive 4 Circuit board 5 Connection electrode 6 Fine unevenness 7 Liquid resin composition 8 Resin 9 Inorganic filler 10 Cured resin composition 11 Solder bump 12 Sealing resin
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平４−364743（ＪＰ，Ａ) 特開 平７−201917（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/29 H01L 21/56 H01L 21/60 311 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-364743 (JP, A) JP-A-7-201917 (JP, A) (58) Fields investigated (Int.Cl. 6 , DB name) H01L 23/29 H01L 21/56 H01L 21/60 311
Claims (13)
に実装する半導体素子の実装方法であって、表面に微細
な凹凸を有する回路基板に半導体素子を実装し、前記半
導体素子と前記回路基板の間隙に少なくとも樹脂と回路
基板の前記微細な凹凸よりも小さな形状を有する無機フ
ィラーとを含有する液状の樹脂組成物を充填し、前記液
状の樹脂組成物を硬化することを特徴とする半導体素子
の実装方法。1. A method of mounting a semiconductor element on a circuit board face down, wherein the semiconductor element is mounted on a circuit board having fine irregularities on a surface, and a gap between the semiconductor element and the circuit board is provided. Filling a liquid resin composition containing at least a resin and an inorganic filler having a shape smaller than the fine irregularities of the circuit board, and curing the liquid resin composition. Method.
記回路基板に実装する請求項１に記載の半導体素子の実
装方法。2. The method according to claim 1, wherein the semiconductor element is mounted on the circuit board using solder bumps.
前記回路基板に実装する請求項１に記載の半導体素子の
実装方法。3. The method according to claim 1, wherein the semiconductor element is mounted on the circuit board using a conductive adhesive.
はレーザーで形成された請求項１に記載の半導体素子の
実装方法。4. The method according to claim 1, wherein the fine unevenness is formed on the circuit board by a drill or a laser.
的処理を施すことにより形成された請求項１に記載の半
導体素子の実装方法。5. The method according to claim 1, wherein the fine unevenness is formed by performing a chemical treatment on a surface of the circuit board.
が、多孔質の回路基板である請求項１に記載の半導体素
子の実装方法。6. The method according to claim 1, wherein the circuit board having fine irregularities on the surface is a porous circuit board.
前記回路基板にフェースダウンで実装された半導体素子
と、前記半導体素子と前記回路基板の間隙に充填され
た、少なくとも樹脂と回路基板の前記微細な凹凸よりも
小さな形状を有する無機フィラーを含有した樹脂組成物
とを備えたことを特徴とする半導体素子の実装体。7. A circuit board having fine irregularities on the surface,
A semiconductor element mounted face-down on the circuit board, and a resin filled with at least a resin and an inorganic filler having a shape smaller than the fine unevenness of the circuit board, which is filled in a gap between the semiconductor element and the circuit board. And a composition comprising the composition.
記回路基板に実装されている請求項７に記載の半導体素
子の実装体。8. The package according to claim 7, wherein the semiconductor element is mounted on the circuit board using solder bumps.
前記回路基板に実装されている請求項７に記載の半導体
素子の実装体。9. The semiconductor device package according to claim 7, wherein the semiconductor device is mounted on the circuit board using a conductive adhesive.
又はレーザーで形成されたものである請求項７に記載の
半導体素子の実装体。10. The semiconductor device package according to claim 7, wherein the fine unevenness is formed on the circuit board by a drill or a laser.
学的処理を施すことにより形成されたものである請求項
７に記載の半導体素子の実装体。11. The semiconductor device package according to claim 7, wherein the fine irregularities are formed by performing a chemical treatment on a surface of the circuit board.
板が、多孔質の回路基板である請求項７に記載の半導体
素子の実装体。12. The semiconductor device package according to claim 7, wherein the circuit board having fine irregularities on the surface is a porous circuit board.
された表面にのみ形成されている請求項７に記載の半導
体素子の実装体。13. The semiconductor device package according to claim 7, wherein the fine unevenness is formed only on a surface on which the semiconductor device is mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15136298A JP2914569B1 (en) | 1998-06-01 | 1998-06-01 | Semiconductor device mounting method and its mounting body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15136298A JP2914569B1 (en) | 1998-06-01 | 1998-06-01 | Semiconductor device mounting method and its mounting body |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2914569B1 true JP2914569B1 (en) | 1999-07-05 |
| JPH11345918A JPH11345918A (en) | 1999-12-14 |
Family
ID=15516892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15136298A Expired - Fee Related JP2914569B1 (en) | 1998-06-01 | 1998-06-01 | Semiconductor device mounting method and its mounting body |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2914569B1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002026198A (en) | 2000-07-04 | 2002-01-25 | Nec Corp | Semiconductor device and manufacturing method therefor |
| JP5160813B2 (en) * | 2007-05-25 | 2013-03-13 | パナソニック株式会社 | Conductive paste and substrate |
| JP5353153B2 (en) | 2007-11-09 | 2013-11-27 | パナソニック株式会社 | Mounting structure |
-
1998
- 1998-06-01 JP JP15136298A patent/JP2914569B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11345918A (en) | 1999-12-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2571024B2 (en) | Multi-chip module | |
| US6387794B2 (en) | Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device | |
| JPH08236654A (en) | Chip carrier and manufacture thereof | |
| JPH0855938A (en) | Semiconductor device and manufacture thereof | |
| JP2930186B2 (en) | Semiconductor device mounting method and semiconductor device mounted body | |
| EP0969503A2 (en) | Electronic circuit device | |
| JP3116926B2 (en) | Package structure and semiconductor device, package manufacturing method, and semiconductor device manufacturing method | |
| JP2914569B1 (en) | Semiconductor device mounting method and its mounting body | |
| JPS601849A (en) | Connecting method of electronic part | |
| JP3260249B2 (en) | Semiconductor device mounting method and its mounting body | |
| JP2892348B1 (en) | Semiconductor unit and semiconductor element mounting method | |
| JP2965496B2 (en) | Semiconductor unit and semiconductor element mounting method | |
| JPH0831871A (en) | Interface sealing film used for surface mount electronic device and surface mount structure | |
| JP2721790B2 (en) | Semiconductor device sealing method | |
| JPH05315397A (en) | Sealing method and sealing structure of semiconductor device | |
| JP3006957B2 (en) | Semiconductor device package | |
| JP3375477B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3951903B2 (en) | Semiconductor device and method for manufacturing semiconductor device package | |
| JP3405136B2 (en) | Electronic component, method of manufacturing electronic component, and mounting structure of electronic component | |
| JP2637684B2 (en) | Semiconductor device sealing method | |
| JPH1126641A (en) | Semiconductor device and manufacture thereof | |
| JP3697902B2 (en) | Electronic component mounting method | |
| JPH0992654A (en) | Electrode structure of semiconductor device, its forming method, mounting body of semiconductor device, and semiconductor device | |
| JPH1079403A (en) | Semiconductor device and manufacturing thereof | |
| JPH10335386A (en) | Semiconductor mounting method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 9 Free format text: PAYMENT UNTIL: 20080416 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090416 Year of fee payment: 10 |
|
| LAPS | Cancellation because of no payment of annual fees |