JPH1079403A - Semiconductor device and manufacturing thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the process for manufacturing a semiconductor device by a method, wherein first connection pads are provided on the surface of a semiconductor chip, a first insulating layer is formed on the region of the chip excluding the connection pads and a second insulating layer, barrier metal layers, conductive bonding meterial layers, second connection pads, and a wiring board are sequentially formed on the first insulating layer. SOLUTION: First connection pads 2 are provided on the surface of a semiconductor chip 1 and a first insulating layer 3 is formed on the region of the chip 1, excluding the pads 2. A second insulating layer 4 having openings on the pads 2 is formed on the layer 3 and, at the same time, recessed part-shaped barrier metal layers 5 are formed on the pads 2 and the inner walls of the openings. Conductive bonding material layers 8 are made to be bonded to the interiors of recessed parts formed in the layers 5, and a wiring board 6 is provided on the layers 8 via second connection pads 7. Thereby the process for manufacturing a semiconductor device is made simple, and the cost of the device can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device, in which a semiconductor chip is face-down on a required wiring board surface via a conductive bonding material layer such as metal, solder, or a conductive adhesive. The present invention relates to a mounted semiconductor device.

[0002]

2. Description of the Related Art Recently, as a technique relating to high speed and high density of electronic equipment, many methods using a bare chip have been developed. Specific examples of these methods include a wire bonding method, a TAB method, and a flip chip method.

[0003] The wire bonding method is a method in which a semiconductor chip is placed face-up, and a pad of the chip and a pad on a substrate are connected by a wire such as gold.
In the wire bonding method, it is difficult at present to connect a very small pitch such as a 50 μm pitch, and there is a limit in increasing the density.

[0004] The TAB method is a method in which a wiring is made of a copper foil on a polyimide film, and an electrode pad of a semiconductor chip and a lead of the copper foil are connected via a bump-shaped connection electrode. This method has the drawbacks that the polyimide film itself is expensive and that dimensional accuracy cannot be sufficiently obtained due to heat shrinkage of the film with respect to fine equipment.

[0005] On the other hand, there is a flip chip method as a technique for making connection at a fine pitch. A semiconductor manufacturing process using the flip chip method is shown in FIG.
This will be described with reference to FIG.

As shown in FIG. 15, in the flip chip method, first, a semiconductor chip 20 having an insulating layer 23 formed in a connection pad 21 and other areas is prepared. First, a barrier metal layer 23 is formed on the entire surface of the connection pad 21 and the insulating layer 22. Next, as shown in FIG. 16, a conductive bonding material layer 24 is formed on the connection pad 21 by an evaporation method, a dipping method, a plating method, or the like. Next, as shown in FIG. 17, an unnecessary barrier metal layer is removed by etching.
The heat treatment at 30 ° C. allows the metal bump electrode 24
To form Thereafter, as shown in FIG. 18, the metal bump electrodes 24 are aligned with the metal pads 26 on the surface of the wiring board 25, and are connected by performing thermal reflow at 230 ° C. After the connection, for example, as shown in FIG. 19, the gap between the semiconductor chip 20 and the wiring board 25 is filled with a sealing resin.

The flip chip method is different from the wire bonding method, the TAB method and the like in that connection can be made using the entire surface of the semiconductor chip, and a very fine pitch resin is connected to the core for connection by bump electrodes. However, there is a problem in that the bump electrode has a large connection resistance and poor reliability.

On the other hand, although proposals have been made to connect a semiconductor chip by forming bump electrodes on a circuit board, there has been a problem that a short-circuit occurs between adjacent bumps if the bump electrode pitch is reduced. Moreover, in this proposal, it was difficult to increase the height of the bump electrode necessary for increasing the reliability.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and the flip-chip mounting process is simple, low in cost, easy to assemble for fine pitch, and reliable. It is an object to provide a semiconductor device with high reliability.

[0010]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor chip, a first connection pad provided on a surface of the semiconductor chip, a first insulating layer formed in a region excluding the first connection pad, a first insulating layer formed on the first insulating layer,
A second insulating layer having an opening on the first connection pad, a concave-shaped barrier metal layer formed on the opened first connection pad and at least on the inner wall surface of the opening, and joined to the concave portion of the barrier metal layer A conductive bonding material layer, a second connection pad bonded on the conductive bonding material layer, and the second bonding pad.
And a wiring board provided on the connection pad.

Further, a method of manufacturing a semiconductor device according to the present invention
4A and 4B show a method for forming the above-mentioned semiconductor device, wherein the first method comprises a first connection pad and a first connection pad.
Preparing a semiconductor chip having on its surface a first insulating layer formed in a region excluding the connection pad of (a), and having a second opening on the semiconductor chip for exposing at least a part of the first connection pad. Forming a semiconductor chip portion by forming a barrier metal layer in at least the opening and obtaining a barrier metal layer having a concave shape, and forming a wiring board having a second connection pad on the surface. Preparing and forming a conductive bonding material layer on the second connection pad; and positioning the recess of the barrier metal layer on the conductive bonding material layer and performing bonding, thereby forming the wiring. A step of mounting the semiconductor chip on a substrate.

In a second method, a semiconductor chip having on its surface a first connection pad and a first insulating layer formed in a region excluding the first connection pad is prepared, and the semiconductor chip is provided on the semiconductor chip. Forming a second insulating layer having an opening exposing at least a part of the first connection pad, forming a barrier metal layer in at least the opening to obtain a concave-shaped barrier metal layer; A step of applying a conductive bonding material layer in the concave portion; preparing a wiring board having a second connection pad on the surface; and forming the second connection pad and the barrier metal layer to which the conductive bonding material layer is applied. A step of mounting the semiconductor chip on the wiring board by aligning and joining the concave portions of the first and second connection pads with each other. On the inner wall When the inclination angle between the formed barrier metal layer and the semiconductor chip surface is θ, the height of the concave portion is h, and the height of the conductive bonding material layer before bonding is H, h / a is 0.25 or more. It is preferable that θ is not less than 30 ° and less than 90 °, and that H is not more than four times h.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing an example of the semiconductor device of the present invention. Semiconductor device 50 of the present invention
Has a configuration including a wiring board section 40 having connection pads and a semiconductor chip section 30 having a barrier metal layer mounted thereon.

As shown in FIG. 1, in a semiconductor chip section 30, a semiconductor chip 1 has a first insulating film 3 and a second insulating film 4 thicker than the first insulating layer formed on the surface thereof. The second insulating film 4 is opened so that a portion of the connection pad 2 on the semiconductor chip 1 is exposed.
A concave-shaped barrier metal layer 5 formed on the upper side and at least on the inner wall 11 of the opening is provided as a connecting member. On the other hand, on the wiring board side on which the semiconductor chip portion 30 is mounted, the wiring board 6 is mounted.
A conductive bonding material layer 8 is formed as a connection member on the connection pad 7 provided thereon.

In the present invention, the concave portion of the barrier metal layer 5 is aligned with the conductive bonding material layer 8, and the conductive bonding material layer 8 is bonded in the concave portion of the barrier metal layer 5 by performing, for example, thermal reflow. Then, the semiconductor chip 1 is mounted on the wiring board 6.

The main feature of the present invention resides in the use of such a connecting member, particularly a barrier metal layer formed in a concave shape. FIG. 2 shows an enlarged view of the barrier metal layer 5 of FIG. As shown in FIG. 2, the barrier metal layer 5 having a concave shape has a bottom surface 10 directly bonded to a connection pad 2 having a diameter a provided on the semiconductor chip 1 and a side wall 1.
1 and the upper end is open. The concave shape is widened so that its cross section becomes larger toward the upper end than the bottom surface, the side wall 11 has an inclination angle of θ with respect to the semiconductor chip surface, and the concave portion has a height (depth) h. With.

FIG. 3 is a diagram showing a state of the conductive bonding material layer 8 before bonding the semiconductor chips. The conductive bonding material layer 8 before bonding has a height H, and is provided on the connection pad 7 provided on the wiring board 6.

The ratio (h / a) of the size a of the connection pad of the semiconductor chip to the height h of the concave portion of the barrier metal layer is as follows:
It is preferably 0.25 or more. If it is less than 0.25, when the semiconductor chip and the wiring board are connected, the conductive bonding material may protrude from the concave portion and short-circuit with the adjacent connecting member. Further, at the time of connection, the conductive bonding material is pressed against the connection pads of the semiconductor chip, and the wiring and the insulating film near the connection pads of the semiconductor chip tend to be broken. Furthermore, when the distance between the wiring board and the semiconductor chip is reduced, the connection reliability tends to deteriorate.

The angle θ between the side wall of the barrier metal layer and the surface of the semiconductor chip is preferably 30 ° or more and less than 90 °. If the angle θ between the side wall of the barrier metal layer and the surface of the semiconductor chip is less than 30 °, the opening of the barrier metal layer becomes large, and it tends to be difficult to connect at a fine pitch. In addition, the volume of the concave portion increases, and connection failure with the conductive bonding material tends to occur. Further, at the time of connection, the conductive bonding material is pressed against the connection pads of the semiconductor chip, and the wiring near the connection pads of the semiconductor chip,
The breakdown of the insulating film tends to occur.

When the inclination angle θ between the side wall of the barrier metal layer and the surface of the semiconductor chip exceeds 90 °, it becomes difficult for the conductive bonding material layer to enter the concave portion, and the connection is insufficient due to insufficient bonding. Tend. The barrier metal layer is usually formed by, for example, a sputtering method, an evaporation method, a plating method, or the like. However, if the inclination angle θ between the side wall of the barrier metal layer and the semiconductor chip surface exceeds 90 °, it is difficult to form the barrier metal layer. Tend to be.

The height H of the conductive bonding material layer is preferably within four times the height h of the concave portion of the barrier metal layer,
If it exceeds four times, the amount of the conductive bonding material is too large, and when the semiconductor chip and the wiring board are connected, the conductive bonding material may protrude from the concave portion and short-circuit with the adjacent connecting member.

The recess of the barrier metal layer 5 and the conductive bonding material layer 8 in FIG. 2 are aligned and bonded. FIG. 4 is a view showing one mode of a bonding state in the semiconductor device of the present invention. As shown in FIG. 4, the conductive bonding material layer 8
Are bonded in the recesses 11 of the barrier metal layer 5, so that undesired spreading does not occur after the bonding. In the case of performing the assembly, since the conductive bonding material layer 8 formed on the wiring substrate 6 can be connected by wetting the concave portion 11 of the barrier metal 5 formed on the semiconductor chip 1, the connection can be achieved. Is not formed, even if the pitch becomes fine, short-circuit with the adjacent pad does not occur. Also,
For example, even if there is a variation in the amount of solder, connection can be made as long as the solder and the barrier metal portion are wet, so that miniaturization can be realized. Further, by using a solder having good wettability with a barrier metal as a conductive bonding material, bonding with better adhesion can be expected. FIG. 5 shows another embodiment of the bonding state in the semiconductor device of the present invention. FIG. As shown in FIG. 5, a conductive bonding material 9 can be applied in advance to the concave portions of the barrier metal layer 5. According to the present invention, it is possible to align the concave portion of the barrier metal layer 5 and the connection pad of the wiring board and join them. The use of the concave-shaped barrier metal has an advantage that the connection can be easily performed since the conductive bonding material can be effectively applied to the opening.

When a barrier metal having a concave shape is used, the height of the connection between the wiring substrate and the semiconductor chip can be freely set. FIG. 6 is a diagram showing still another form of the bonding in the semiconductor device of the present invention. For example, by increasing the depth of the opening formed in the semiconductor device as shown in FIG. 6, a bump having a high aspect ratio can be formed. Also, the reliability can be improved in the case of a fine bump.

Further, when the connection is made with a solder material, it is possible to effectively apply a flux for removing the solder oxide film and improving the solder wettability to the uneven portion. This has the advantage that connection is facilitated.

In the semiconductor device of the present invention, since the barrier metal is formed on the bonding pad of the semiconductor chip, the connection area can be increased as compared with the connection portion in the conventional bump formation. This makes it possible to keep the connection resistance low.

When the semiconductor chip and the wiring board have different coefficients of thermal expansion, it has conventionally been necessary to inject a sealing resin between the semiconductor chip and the board. In the present invention, however, a resin is used as an insulating film. Thereby, connection reliability is improved without using a sealing resin. Needless to say, a sealing resin may be applied to the insulating peripheral portion for further improving the reliability.

Further, in the case of the present invention, since a conductive bonding material layer such as a metal and a conductive adhesive is formed on a substrate without forming a metal bump on a semiconductor chip, the material formed on the substrate is changed. Thus, there is an advantage that various materials can be connected. Of course, lead-free solder can also be used.

In the method of manufacturing a semiconductor device according to the present invention, the steps of forming the insulating film, forming the opening of the insulating film, and forming the barrier metal are all simpler than the conventional bump manufacturing process. Therefore, the yield is good and the cost is low.

In the present invention, as the insulating film, for example, SiO 2
_2. An inorganic film such as SiN or an organic film such as an acrylic resin, an epoxy resin, or a polyimide resin can be used.

Further, as the barrier metal, a simple substance such as titanium, chromium, copper, nickel, gold, palladium or the like and a composite film thereof can be used. Further, as the conductive bonding material, for example, a simple substance such as tin, lead, indium, bismuth, antimony, gallium, cadmium, gold, silver, copper, and zinc, or an alloy, or a solder material such as a composite, gold, or silver , Copper, and a conductive adhesive containing a metal such as nickel can be preferably used.

As the substrate for the wiring substrate, silicon-based substrates,
Aluminum nitride, alumina, resin substrate, and the like can be used. Example 1 Hereinafter, an example of the present invention will be described, and the present invention will be specifically described.

7 to 14 are views for explaining a method of manufacturing a semiconductor device according to one embodiment of the present invention. First, as shown in FIG. 7, a 6-inch square semiconductor wafer 101 having a thickness of 50 μm, in which, for example, a semiconductor element of 10 mm square and an aluminum electrode pad 2 of 100 μm square exist at a pad pitch of 200 μm around the semiconductor element, was prepared. On the semiconductor wafer 101, a first insulating film 3 having a thickness of 1 μm is formed in a region other than the electrode pads 2.

Next, as shown in FIG. 8, a material selected from inorganic materials such as SiO ₂ and SiN, and organic materials such as acrylic resin, epoxy resin and polyimide resin is used on the entire surface of the wafer 101. , The second insulating film 4
It is formed with a thickness of 5 to 100 μm. When an inorganic material such as SiO ₂ or SiN is used for forming the second insulating film, a spin method or a sol-gel method is used. When an organic material such as an acrylic resin, an epoxy resin, or a polyimide resin is used, a spin is used. A coating method or the like can be used.

Thereafter, as shown in FIG. 9, the second insulating film 4 on the aluminum electrode pad 2 is removed to form an opening 12, and the aluminum electrode pad 2 is exposed. For example, a photosensitive resin is applied as the second insulating film 4, and an opening is formed on the aluminum electrode pad 2 by exposure and development. When an inorganic material or a non-photosensitive resin is used, the opening can be formed by using an RIE apparatus, laser etching, or the like.

Next, as shown in FIG. 10, a barrier metal layer 5 is formed on the surface of the second insulating film 4 including the aluminum electrode pad 2 and the inner wall of the opening 12 by sputtering, vapor deposition, plating, or the like. Form. As the barrier metal, for example, a composite in which titanium / copper, titanium / nickel, or chromium / copper is arranged in order from the aluminum electrode pad 2 can be preferably used. Further, gold, palladium, or the like can be thinly applied to the surface of copper or nickel to improve the wettability with the conductive bonding material.

Further, as shown in FIG. 11, a resist is applied, exposure and etching are performed, and the barrier metal layer is removed leaving at least the barrier metal layer 5 formed in the opening 12. The peripheral wall 11 of the obtained barrier metal layer 5 has a tilt angle of 60 ° with respect to the semiconductor chip surface. The depth of the opening 12 is 50 μm, and can be adjusted by changing the thickness of the second insulating film 4.

Next, as shown in FIG. 12, a conductive bonding material such as a metal or a conductive adhesive, for example, a conductive adhesive layer made of silver is provided on the connection pads 7 made of, for example, copper on the wiring board 6. 8 can be formed to a thickness of 30 μm by, for example, a screen printing method, a plating method, a vapor deposition method, or the like.

Thereafter, as shown in FIG. 13, the semiconductor chip 1 in which the formed opening 12 is formed and the wiring board 6 in which the solder layer 8 is formed are connected. The copper pad 7 on which the solder layer 8 is formed on the wiring board 6 is brought into contact with the concave portion formed on the semiconductor chip 1 by using, for example, a positioning device using a half mirror. Next, the semiconductor chip portion 30 and the wiring substrate portion 40 having connection pads are temporarily fixed to 230.
The barrier metal 5 formed on the semiconductor chip 1 and the solder layer 8 formed on the wiring substrate 6 are connected by melting the metal on the substrate by passing through a nitrogen reflow furnace set at a temperature of ° C. When a conductive adhesive is used instead of the solder layer, connection can be achieved by assembling the semiconductor chip 1 and the wiring substrate 6 and then heating the assembly with an oven heated to 100 ° C.

FIG. 14 is a schematic diagram showing one application example of the semiconductor device of the present invention. As shown in FIG. 14, a resin 60 can be injected between the semiconductor chip 1 and the wiring board 6.

A 10 mm square semiconductor chip having 200 bumps, for example, manufactured as described above was mounted on a resin substrate such as a printed circuit board. This sample
65 ° C (30 minutes) to 25 ° C (5 minutes) to 100 ° C (30 minutes)
Min) to 25 ° C. (5 min) for 5000 cycles, no breaks were found at the connection points. Further, in the case of a semiconductor device configured by filling and curing a silicone resin 10 or the like between the semiconductor chip 1 and the wiring board 6,
No break occurred after 0000 cycles.

Example 2 In FIG. 11, in the obtained opening of the barrier metal layer,
A semiconductor device is obtained in the same manner as in Example 1, except that the conductive material layer is formed and in FIG. 12, the conductive adhesive layer 8 is not formed.

The conductive adhesive layer 8 may be formed by, for example, a printing method in which a solder paste or a conductive adhesive paste is formed by printing using a metal mask, or a wire made of a solder material into a concave portion using a bonding device. A ball bonding method for forming, a dipping method for forming a semiconductor wafer in molten solder, an electroless plating method for growing solder by electroless plating on a barrier metal portion of a concave portion, or the like can be used. It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented in variously modified configurations without departing from the gist of the present invention.

[0043]

According to the present invention, a second semiconductor chip is provided on a semiconductor chip.
By forming the insulating layer and the barrier metal layer having a concave shape, a short circuit does not occur even when the connection electrode is fine in connection with the wiring board, and the connection with the conductive bonding material layer of the wiring board is performed. Cheap. Further, since the connection area is increased, the connection resistance can be kept low. Further, by increasing the depth of the opening of the concave portion, a connection electrode having a high aspect ratio can be formed, and a highly reliable semiconductor device can be obtained. Further, the manufacturing process is very simple, and the yield is good.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing an example of a semiconductor device of the present invention.

FIG. 2 is an enlarged view of the barrier metal layer of FIG. 1;

FIG. 3 is a diagram illustrating a state of a conductive bonding material layer before bonding a semiconductor chip.

FIG. 4 is a diagram showing one mode of a bonding state in a semiconductor device of the present invention.

FIG. 5 is a diagram showing another embodiment of the bonding state in the semiconductor device of the present invention.

FIG. 6 is a diagram showing still another form of the bonding state in the semiconductor device of the present invention.

FIG. 7 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 8 is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 9 is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 10 is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 11 is a view illustrating a method of manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 12 is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 13 is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 14 is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 15 is a diagram illustrating a manufacturing process of a conventional semiconductor device.

FIG. 16 is a diagram illustrating a manufacturing process of a conventional semiconductor device.

FIG. 17 is a diagram illustrating a manufacturing process of a conventional semiconductor device.

FIG. 18 is a diagram illustrating a manufacturing process of a conventional semiconductor device.

FIG. 19 is a view illustrating a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor chip 2 aluminum pad 3 first insulating layer 4 second insulating layer 5 barrier metal 6 wiring board 7 copper pad 8 conductive bonding material layer 9 flux 10 resin 11 barrier Metal sidewall 12 Opening 20 Semiconductor chip 21 Aluminum pad 22 First insulating film 23 Barrier metal 24 Metal and solder 25 Wiring board 26 Copper pad 27 Resin 30 Semiconductor chip portion having barrier metal layer 40 ... Wiring board part having connection pads 50. Semiconductor device 60. Sealing resin 101. Semiconductor wafer

Claims (5)

[Claims] 1. A semiconductor chip, a first connection pad provided on a surface of the semiconductor chip, a first insulating layer formed in a region excluding the first connection pad, and formed on the first insulating layer. A second insulating layer having an opening on the first connection pad, a concave-shaped barrier metal layer formed on the opened first connection pad and at least on an inner wall surface of the opening,
A conductive bonding material layer bonded in the recess of the barrier metal layer, a second connection pad bonded on the conductive bonding material layer, and a wiring board provided on the second connection pad. A semiconductor device, comprising: 2. When the diameter of the first connection pad is a, the inclination angle between the barrier metal layer formed on the inner wall surface of the opening and the semiconductor chip surface is θ, and the height of the recess is h, h / a Is 0.
2. The semiconductor device according to claim 1, wherein θ is 30 ° to 90 °. 3. A semiconductor chip having on its surface a first connection pad and a first insulating layer formed in a region excluding the first connection pad is provided, and the first connection pad is provided on the semiconductor chip. Forming a second insulating layer having an opening exposing at least a part of the connection pad, forming a barrier metal layer at least in the opening, and forming a semiconductor chip portion by obtaining a concave-shaped barrier metal layer; Preparing a wiring board having a second connection pad on the surface, forming a conductive bonding material layer on the second connection pad; and forming the conductive metal layer on the conductive bonding material layer. A method of manufacturing a semiconductor device, comprising a step of mounting the semiconductor chip part on the wiring board part by aligning and bonding a concave part. 4. The diameter of the first connection pad is a, the inclination angle between the barrier metal layer formed on the inner wall surface of the opening and the surface of the semiconductor chip is θ, the height of the recess is h, When the height of the conductive bonding material layer is H, h / a is 0.25 or more, θ is 30 ° or more and less than 90 °, and H is 4 times or less of h. Claim 3
13. The method for manufacturing a semiconductor device according to item 5. 5. A semiconductor chip having on its surface a first connection pad and a first insulating layer formed in a region excluding the first connection pad is provided, and the first chip is provided on the semiconductor chip. Forming a second insulating layer having an opening exposing at least a part of the connection pad; forming a barrier metal layer in at least the opening to obtain a concave-shaped barrier metal layer; Applying a conductive bonding material layer, preparing a wiring board having a second connection pad on the surface, and positioning the second connection pad and the concave portion of the barrier metal layer to which the conductive bonding material layer is applied. A method of manufacturing the semiconductor device, comprising a step of mounting the semiconductor chip portion on the wiring board by performing alignment and bonding.