JP2000100868A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JP2000100868A JP2000100868A JP10268569A JP26856998A JP2000100868A JP 2000100868 A JP2000100868 A JP 2000100868A JP 10268569 A JP10268569 A JP 10268569A JP 26856998 A JP26856998 A JP 26856998A JP 2000100868 A JP2000100868 A JP 2000100868A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating resin
- wiring
- resin layer
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11005—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for aligning the bump connector, e.g. marks, spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置および
その製造方法に係わり、特に配線基板に複数の半導体素
子が高密度でフリップチップ実装されたマルチチップモ
ジュール（ＭＣＭ）のような半導体装置と、そのような
半導体装置を製造する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device such as a multi-chip module (MCM) in which a plurality of semiconductor elements are mounted on a wiring board at high density by flip-chip. The present invention relates to a method for manufacturing such a semiconductor device.
【０００２】[0002]
【従来の技術】従来から、半導体チップを基板に搭載し
接続する実装技術の一つとして、フリップチップ接続が
ある。従来からのフリップチップ接続方法の一例を、以
下に説明する。2. Description of the Related Art Conventionally, there is a flip chip connection as one of mounting techniques for mounting and connecting a semiconductor chip on a substrate. An example of a conventional flip chip connection method will be described below.
【０００３】すなわち、従来の方法では、図４（ａ）に
示すように、絶縁基板１上に所定の配線層２が設けられ
た配線基板上に、半導体チップを接続するための配線パ
ッド部２ａを除いて、厚さ約10μm の絶縁樹脂層（ソル
ダーレジスト層）３を形成した後、その上に、配線パッ
ド部２ａを開孔４ａとするメタルマスク４を重ね、はん
だペースト５を供給する。そして、スキージ６によりは
んだペースト５をメタルマスク４の開孔４ａを通して押
し出し、配線パッド部２ａ上に約 100μm の厚さに印刷
・塗布した後、リフローさせて、図４（ｂ）に示すよう
に、高さが30〜50μm のはんだバンプ７を形成する。That is, in the conventional method, as shown in FIG. 4A, a wiring pad portion 2a for connecting a semiconductor chip is provided on a wiring board having a predetermined wiring layer 2 provided on an insulating substrate 1. After forming an insulating resin layer (solder resist layer) 3 having a thickness of about 10 .mu.m, a metal mask 4 having an opening 4a in the wiring pad 2a is overlaid thereon, and a solder paste 5 is supplied. Then, the solder paste 5 is extruded by the squeegee 6 through the opening 4a of the metal mask 4, printed and applied on the wiring pad portion 2a to a thickness of about 100 μm, and reflowed, as shown in FIG. Then, a solder bump 7 having a height of 30 to 50 μm is formed.
【０００４】一方、図４（ｃ）に示すように、半導体チ
ップ８の電極端子（図示を省略。）上に、先端に小突起
を有する金等のボール状バンプ９を形成し、この金バン
プ９を、基板側に形成されたはんだバンプ７に位置合わ
せし、加熱しながら圧接する。こうして、図４（ｄ）に
示すように、金バンプ９と配線パッド部２ａとを電気的
に接続するとともに、この接続部を、溶融し固化したは
んだバンプ７により機械的に固定する。なお、図示を省
略したが、金バンプ９と配線パッド部２ａとの接続部の
外側に、さらにエポキシ樹脂のような絶縁樹脂の封止層
を、ポッティング等により形成する。On the other hand, as shown in FIG. 4 (c), a ball-shaped bump 9 made of gold or the like having a small protrusion at the tip is formed on an electrode terminal (not shown) of the semiconductor chip 8, and the gold bump is formed. 9 is aligned with the solder bump 7 formed on the substrate side, and pressed while heating. In this way, as shown in FIG. 4D, the gold bumps 9 and the wiring pad portions 2a are electrically connected, and the connection portions are mechanically fixed by the solder bumps 7 that have been melted and solidified. Although not shown, a sealing layer of an insulating resin such as an epoxy resin is further formed outside the connection between the gold bump 9 and the wiring pad 2a by potting or the like.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、このよ
うな従来のフリップチップ接続方法では、配線基板側の
はんだバンプ７の形成において、メタルマスク４の開孔
４ａの内壁面にはんだペースト５が付着して、配線パッ
ド部２ａ上に十分な量のはんだペースト５が供給されな
いため、１回印刷・塗布するごとに、メタルマスク４の
開孔４ａを洗浄する必要があった。However, in such a conventional flip-chip connection method, when forming the solder bumps 7 on the wiring board side, the solder paste 5 adheres to the inner wall surface of the opening 4a of the metal mask 4. Therefore, since a sufficient amount of solder paste 5 is not supplied onto the wiring pad portion 2a, it is necessary to clean the opening 4a of the metal mask 4 every time printing and application is performed once.
【０００６】また、配線パッド部２ａごとにはんだペー
スト５の塗布量に差異が生じやすかった。そして、各配
線パッド部２ａではんだペースト５の塗布量が異なる
と、リフロー後のはんだバンプ７の高さに差異が生じ、
その結果、半導体チップ８に接続不良が生じるという問
題があった。Further, the amount of the solder paste 5 to be applied tends to be different for each wiring pad portion 2a. If the application amount of the solder paste 5 differs in each wiring pad portion 2a, a difference occurs in the height of the solder bump 7 after reflow,
As a result, there is a problem that a connection failure occurs in the semiconductor chip 8.
【０００７】本発明は、これらの問題を解決するために
なされたもので、基板側に十分な厚さのはんだ等の層が
形成され、信頼性が良好なフリップチップ接続が効率的
になされた半導体装置と、そのような半導体装置を製造
する方法を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve these problems. A sufficiently thick layer of solder or the like is formed on the substrate side, and a highly reliable flip-chip connection is efficiently performed. It is an object to provide a semiconductor device and a method for manufacturing such a semiconductor device.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体装置は、
絶縁基板の少なくとも一方の主面に配線層が設けられた
配線基板と、該配線基板の配線層形成面に形成された、
前記配線層のパッド部に開口部を有する絶縁樹脂層と、
前記絶縁樹脂層の開口部内に装填されたろう材層と、フ
ェースダウンに配置され、各電極端子上に設けられたバ
ンプを介して前記配線層のパッド部に接続され、かつ該
接続部が前記ろう材層により固定された半導体素子とを
備え、前記絶縁樹脂層により、前記半導体素子の電極端
子形成面が被覆・封止されていることを特徴とする。According to the present invention, there is provided a semiconductor device comprising:
A wiring board provided with a wiring layer on at least one main surface of the insulating substrate, formed on a wiring layer forming surface of the wiring board,
An insulating resin layer having an opening in a pad portion of the wiring layer,
A brazing material layer loaded in the opening of the insulating resin layer, a face-down, connected to a pad portion of the wiring layer via a bump provided on each electrode terminal, and the connection portion is connected to the brazing material layer; A semiconductor element fixed by a material layer, wherein the insulating resin layer covers and seals the electrode terminal forming surface of the semiconductor element.
【０００９】また、本発明の半導体装置の製造方法は、
絶縁基板の少なくとも一方の主面に配線層を形成する工
程と、前記配線層の形成面に絶縁樹脂層を形成する工程
と、前記配線層のパッド部上の絶縁樹脂層に開口部を形
成する工程と、前記絶縁樹脂層の開口部内にろう材層を
装填するろう材装填工程と、半導体素子の電極端子上に
バンプを形成する工程と、前記バンプを前記ろう材層に
位置合わせして加熱・圧接し、前記配線層のパッド部に
接合するフリップチップ接合工程と、前記絶縁樹脂層を
加熱軟化させ、この絶縁樹脂層により前記半導体素子の
電極端子形成面を被覆し封止する封止工程とを備えたこ
とを特徴とする。Further, a method for manufacturing a semiconductor device according to the present invention
A step of forming a wiring layer on at least one main surface of the insulating substrate, a step of forming an insulating resin layer on a surface on which the wiring layer is formed, and forming an opening in the insulating resin layer on a pad portion of the wiring layer A brazing material loading step of loading a brazing material layer into the opening of the insulating resin layer, a step of forming a bump on an electrode terminal of a semiconductor element, and positioning the bump with the brazing material layer and heating. A flip chip bonding step of pressing and bonding to a pad portion of the wiring layer, and a sealing step of heating and softening the insulating resin layer, and covering and sealing the electrode terminal forming surface of the semiconductor element with the insulating resin layer. And characterized in that:
【００１０】本発明に使用する絶縁基板としては、ガラ
ス基板、セラミック基板、あるいはガラスクロス−樹脂
含浸基板等が挙げられ、特にガラス基板の使用が望まし
い。すなわち、ケイ酸塩ガラス（シリケートガラス）、
ほうケイ酸塩ガラスのようなガラスから成る基板は、ガ
ラスクロス−樹脂含浸基板に比べて熱膨張係数が小さ
く、半導体素子を構成するシリコンに近い熱膨張係数を
有するので、絶縁基板としてガラス基板を使用した場合
には、半導体素子のフリップチップ接続部に加わる熱に
よる衝撃（熱的ストレス）を、低減することができる。Examples of the insulating substrate used in the present invention include a glass substrate, a ceramic substrate, a glass cloth-resin impregnated substrate, and the like, and the use of a glass substrate is particularly desirable. That is, silicate glass (silicate glass),
A substrate made of glass such as borosilicate glass has a smaller coefficient of thermal expansion than a glass cloth-resin impregnated substrate, and has a coefficient of thermal expansion close to that of silicon constituting a semiconductor element. When used, the impact (thermal stress) due to heat applied to the flip chip connection portion of the semiconductor element can be reduced.
【００１１】本発明においては、このような絶縁基板の
少なくとも一方の主面に、銅、銅系合金、金等から成る
配線層が配設される。配線層の形成は、ガラスクロス−
樹脂含浸基板では、銅箔のエッチング等により行なわ
れ、ガラス基板やセラミック基板のような無機系の絶縁
基板においては、真空蒸着やスパッタリング等の物理的
蒸着（ＰＶＤ）法や化学的蒸着（ＣＶＤ）法により薄膜
を形成した後、パターニングする方法で行なうことがで
きる。また、本発明では、銅配線層の接続用パッド部に
おいて、銅の酸化を防ぎ、後述する半導体素子の金バン
プと強固に接合するように、ニッケル層を介して金層
（Ｎｉ−Ａｕ層）を積層することが好ましい。なお、銅
配線層全体に亘って、Ｎｉ−Ａｕ層を積層形成しても良
いが、接続用パッド部以外の配線層は、絶縁樹脂層で覆
われるので、配線パッド部のみのＡｕ層の形成でも十分
な効果を上げることができる。In the present invention, a wiring layer made of copper, a copper-based alloy, gold or the like is provided on at least one main surface of such an insulating substrate. The wiring layer is formed using a glass cloth
In the case of a resin-impregnated substrate, etching is performed by copper foil or the like, and in the case of an inorganic insulating substrate such as a glass substrate or a ceramic substrate, a physical vapor deposition (PVD) method such as vacuum vapor deposition or sputtering or a chemical vapor deposition (CVD) After forming a thin film by the method, it can be performed by a method of patterning. Further, in the present invention, a gold layer (Ni-Au layer) is provided via a nickel layer so as to prevent oxidation of copper in a connection pad portion of a copper wiring layer and to firmly bond with a gold bump of a semiconductor element described later. Are preferably laminated. Note that a Ni—Au layer may be laminated over the entire copper wiring layer. However, since the wiring layer other than the connection pad portion is covered with the insulating resin layer, the formation of the Au layer only in the wiring pad portion is performed. However, a sufficient effect can be achieved.
【００１２】本発明において、このような配線基板の配
線層形成面に、所定の位置に開口部を有する絶縁樹脂層
が設けられる。絶縁樹脂としては、はんだ等のろう材層
形成時のリフロー温度（約 170℃）で溶融することがな
く、かつフリップチップ接合工程で変形軟化して半導体
素子に接着するような材料の使用が望ましく、例えばエ
ポキシ樹脂のような熱可塑性樹脂が挙げられる。また、
このような絶縁樹脂層において、半導体素子接続用の配
線パッド部上に開口部を形成するには、例えば感光性の
絶縁樹脂を配線基板の配線層形成面全体に被覆した後、
この被覆層を、配線パッド部のみが開口されるように、
マスクを用いて露光し現像する方法が採られる。さら
に、このような絶縁樹脂層の厚さは、開口部に装填され
るろう材層の厚さより厚くし、かつ後述する半導体素子
の電極端子上に形成されるバンプの高さとほぼ等しくす
ることが望ましい。In the present invention, an insulating resin layer having an opening at a predetermined position is provided on the wiring layer forming surface of such a wiring board. As the insulating resin, it is desirable to use a material that does not melt at a reflow temperature (about 170 ° C.) at the time of forming a brazing material layer such as a solder and is deformed and softened in a flip chip bonding process and adheres to a semiconductor element. And a thermoplastic resin such as an epoxy resin. Also,
In such an insulating resin layer, in order to form an opening on a wiring pad portion for connecting a semiconductor element, for example, after covering a photosensitive insulating resin over the entire wiring layer forming surface of the wiring board,
This covering layer is formed so that only the wiring pad portion is opened.
A method of exposing and developing using a mask is employed. Furthermore, the thickness of such an insulating resin layer should be greater than the thickness of the brazing material layer loaded in the opening, and should be substantially equal to the height of the bumps formed on the electrode terminals of the semiconductor element described later. desirable.
【００１３】さらに、このような絶縁樹脂層の開口部に
装填されるろう材としては、はんだ等の軟ろうの使用が
好ましく、特にＩｎ−Ｐｂ系のインジウム鉛はんだ（融
点約170℃）の使用が望ましい。このようなろう材層を
開口部に装填するには、必要かつ十分な体積を有するろ
う材のボールを絶縁樹脂層上に供給し、配線基板を振動
させて開口部に１個ずつろう材ボールを転がし入れ、あ
るいは吸引部材によりろう材ボールを吸引しながら運搬
して１個ずつ開口部に挿嵌した後、ろう材をリフローさ
せる方法を採ることが望ましい。このとき、ろう材ボー
ルのサイズ（直径）は、絶縁樹脂層の開口部にろう材ボ
ールが１個ずつかつ完全に嵌め込まれるように、調整す
ることが望ましい。Further, as a brazing material to be loaded into the opening of the insulating resin layer, use of a soft solder such as solder is preferable, and particularly, use of In-Pb-based indium lead solder (melting point: about 170 ° C.) Is desirable. In order to load such a brazing material layer into the opening, a brazing material ball having a necessary and sufficient volume is supplied onto the insulating resin layer, and the wiring board is vibrated so that the brazing material balls are individually placed in the opening. It is desirable to adopt a method in which the brazing material is reflowed after the brazing material balls are transported while being sucked or sucked by the suction member and inserted into the openings one by one. At this time, it is desirable to adjust the size (diameter) of the brazing material ball so that the brazing material ball is completely and individually fitted into the opening of the insulating resin layer.
【００１４】これらの方法では、予めボール状に整形さ
れたろう材が用いられるので、ろう材層の装填が簡素化
されるうえに、リフロー後のろう材層の厚さのばらつき
がなく、安定した高さの良好な接続が達成される。In these methods, since a brazing material shaped into a ball in advance is used, the loading of the brazing material layer is simplified, and there is no variation in the thickness of the brazing material layer after reflow, and the brazing material layer is stable. A good connection of height is achieved.
【００１５】またこれらの方法では、ろう材ボールを挿
嵌する前に、絶縁樹脂層の開口部内にペースト状のろう
付け用フラックスを塗布しておくことが望ましい。な
お、ろう付け用フラックスは、ろう材ボールとそれが接
合される配線パッド部の表面の酸化を防止し、これらを
活性化すると同時に、粘着力によりろう材ボールを仮固
定するために塗布される。フラックスの塗布は、例えば
開口部と同じ位置に複数の突起部を有する凸型版を使用
して転写する方法や、塗布用のピンを用いて転写する方
法、ディスペンサを使用しシリンジの先端からフラック
スを供給する方法、またはメタルマスクを使用し、スキ
ージによりマスクの開孔からフラックスを押し出して供
給する印刷方法などを用いて行なうことができる。[0015] In these methods, it is desirable to apply a paste-like brazing flux in the opening of the insulating resin layer before inserting the brazing filler metal ball. The brazing flux is applied to prevent oxidation of the surface of the brazing material ball and the wiring pad portion to which the brazing material ball is to be joined, to activate them, and to temporarily fix the brazing material ball by adhesive force. . The flux is applied by, for example, a method of transferring using a convex plate having a plurality of projections at the same position as the opening, a method of transferring using a coating pin, or a method of transferring flux from the tip of a syringe using a dispenser. Or a printing method using a metal mask and extruding a flux from the opening of the mask with a squeegee to supply the flux.
【００１６】さらに、ろう材層を絶縁樹脂層の開口部に
装填するには、絶縁樹脂層をマスクとして、配線パッド
部上にろう材を電解めっきする方法なども採ることがで
きる。Further, in order to load the brazing material layer into the opening of the insulating resin layer, a method of electrolytically plating the brazing material on the wiring pad portion using the insulating resin layer as a mask can be adopted.
【００１７】本発明において、半導体素子の電極端子上
に設けられるバンプとしては、金のボール状バンプが挙
げられる。金ボールバンプの形成は、例えばワイヤボン
ダのキャピラリー先端に形成された金ボールを、半導体
素子の電極端子上に接合し、キャピラリーでボールのネ
ック部を切断する方法により行なうことができる。In the present invention, the bumps provided on the electrode terminals of the semiconductor element include gold ball-shaped bumps. The gold ball bump can be formed by, for example, bonding a gold ball formed at the tip of a capillary of a wire bonder to an electrode terminal of a semiconductor element, and cutting the neck portion of the ball with the capillary.
【００１８】本発明の半導体装置およびその製造方法で
は、配線基板の配線層形成面に、配線パッド部に開口部
を有する調整された厚さの絶縁樹脂層が形成され、この
層をダムとして、各開口部にはんだのようなろう材の層
が装填されているので、十分な厚さのろう材層が形成さ
れ、半導体素子の安定した信頼性の高いフリップチップ
接続が実現される。また、このような絶縁樹脂層によ
り、半導体素子の電極端子形成面が被覆・封止されてい
るので、別に絶縁樹脂等による封止を行なう必要がな
く、効率的な製造が可能である。In the semiconductor device and the method of manufacturing the same according to the present invention, an insulating resin layer having an adjusted thickness having an opening in a wiring pad portion is formed on a wiring layer forming surface of a wiring board. Since a brazing material layer such as solder is loaded in each opening, a brazing material layer having a sufficient thickness is formed, and a stable and reliable flip-chip connection of the semiconductor element is realized. In addition, since the electrode terminal forming surface of the semiconductor element is covered and sealed with such an insulating resin layer, it is not necessary to separately perform sealing with an insulating resin or the like, and efficient manufacturing is possible.
【００１９】[0019]
【発明の実施の形態】以下、本発明の実施例を図面に基
づいて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００２０】図１は、本発明の半導体装置の一実施例で
あるＭＣＭの外観を斜視的に示す図であり、図２は、同
実施例の要部を断面的に示したものである。これらの図
において、符号１０は、ガラス基板のような絶縁基板
（厚さ約0.05mm）を示し、この絶縁基板１０の片面（図
では上面）には、銅（Ｃｕ）配線層１１が設けられ、こ
の配線層１１の半導体チップ接続用の配線パッド部１１
ａ上に、Ｎｉ−Ａｕ層（図示を省略。）が積層されてい
る。そして、このような配線基板の配線層形成面には、
前記した配線パッド部１１ａを開口部（直径 100μm ）
１２ａとするエポキシ樹脂等の絶縁樹脂層（厚さ50μm
）１２が設けられている。また、絶縁樹脂層１２の各
開口部１２ａは、内壁面がテーパー形状を呈しており、
このような開口部１２ａ内に、それぞれＩｎ−Ｐｂ系の
はんだ層１３が装填されている。FIG. 1 is a perspective view showing an appearance of an MCM which is an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a sectional view showing a main part of the embodiment. In these figures, reference numeral 10 denotes an insulating substrate (thickness: about 0.05 mm) such as a glass substrate. A wiring pad portion 11 for connecting a semiconductor chip of the wiring layer 11
A Ni-Au layer (not shown) is laminated on a. And, on the wiring layer forming surface of such a wiring board,
The above-mentioned wiring pad 11a is opened (diameter 100 μm).
12a insulating resin layer such as epoxy resin (thickness 50μm
) 12 are provided. In addition, each opening 12a of the insulating resin layer 12 has a tapered inner wall surface,
The In-Pb-based solder layer 13 is loaded in each of the openings 12a.
【００２１】一方、符号１４はシリコンの半導体チップ
を示し、そのＡｌ電極端子（図示を省略。）上には、先
端に小突起１５ａを有するボール状の金バンプ１５が形
成されている。そして、このような半導体チップ１４が
フェースダウンに配置されており、その金バンプ１５
が、前記した配線基板のはんだ層１３を介して、配線パ
ッド部１１ａに電気的に接続されている。すなわち、半
導体チップ１４のＡｌ電極端子上に形成された金バンプ
１５が、配線基板側のはんだ層１３に貫入され、下層の
配線パッド部１１ａ（Ｎｉ−Ａｕ層）に接合されてい
る。また、はんだ層１３により、金バンプ１５と配線パ
ッド部１１ａとのフリップチップ接合部の機械的固定が
なされている。さらに、半導体チップ１４の電極端子形
成面（下面）には、絶縁樹脂層１２の上面が接着されて
おり、この絶縁樹脂層１２により、半導体チップ１４の
電極端子形成面および前記したフリップチップ接合部が
封止されている。On the other hand, reference numeral 14 denotes a silicon semiconductor chip, and a ball-shaped gold bump 15 having a small projection 15a at the tip is formed on its Al electrode terminal (not shown). Such a semiconductor chip 14 is arranged face down, and its gold bump 15
Are electrically connected to the wiring pad 11a via the solder layer 13 of the wiring board. That is, the gold bump 15 formed on the Al electrode terminal of the semiconductor chip 14 penetrates the solder layer 13 on the wiring board side and is joined to the lower wiring pad portion 11a (Ni-Au layer). In addition, the solder layer 13 mechanically fixes the flip chip bonding portion between the gold bump 15 and the wiring pad portion 11a. Further, the upper surface of the insulating resin layer 12 is adhered to the electrode terminal forming surface (lower surface) of the semiconductor chip 14, and the insulating resin layer 12 allows the electrode terminal forming surface of the semiconductor chip 14 and the above-described flip chip bonding portion. Are sealed.
【００２２】このような構造を有する実施例の半導体装
置は、以下に示すようにして製造される。まず図３
（ａ）に示すように、ガラス基板のような絶縁基板１０
の上面に、Ｃｕの蒸着パターニング等の方法でＣｕ配線
層１１を形成した後、このＣｕ配線層１１の配線パッド
部１１ａ上に、蒸着、無電解めっき等の方法で、Ｎｉ−
Ａｕ層を積層して形成する。次いで、こうして得られた
配線基板の配線層形成面に、厚さ50μm のエポキシ樹脂
のような感光性の絶縁樹脂層１２を被覆・形成した後、
所定の形状のマスクを用いて露光、現像を行ない、配線
パッド部１１ａ上に直径 100μm の開口部１２ａを形成
する。The semiconductor device of the embodiment having such a structure is manufactured as described below. First, FIG.
As shown in (a), an insulating substrate 10 such as a glass substrate
After the Cu wiring layer 11 is formed on the upper surface of the Cu wiring layer by a method such as vapor deposition patterning of Cu, the Ni-layer is formed on the wiring pad portion 11a of the Cu wiring layer 11 by a method such as vapor deposition or electroless plating.
It is formed by stacking Au layers. Next, a photosensitive insulating resin layer 12 such as an epoxy resin having a thickness of 50 μm is coated and formed on the wiring layer forming surface of the wiring board thus obtained.
Exposure and development are performed using a mask having a predetermined shape to form an opening 12a having a diameter of 100 μm on the wiring pad 11a.
【００２３】次いで、こうして形成された絶縁樹脂層１
２の開口部１２ａ内に、はんだ付け用のフラックス１６
を、以下に示すようにして塗布する。すなわち、図３
（ｂ）に示すように、開口部１２ａと同じ位置に、直径
60μm で高さが 100μm 以上の複数の突起部１７ａを有
する凸型版１７を使用し、これらの突起部１７ａに、フ
ラックス１６を20μm の厚さに塗布した後、この凸型版
１７の突起部１７ａを絶縁樹脂層１２の開口部１２ａに
位置合わせして挿入し、突起部１７ａに塗布されたフラ
ックス１６を開口部１２ａの底部に転写する。Next, the insulating resin layer 1 thus formed is formed.
In the opening 12a, the flux 16 for soldering is used.
Is applied as shown below. That is, FIG.
As shown in (b), the diameter is set at the same position as the opening 12a.
A convex plate 17 having a plurality of protrusions 17a having a height of 60 μm and a height of 100 μm or more is used. A flux 16 is applied to these protrusions 17a to a thickness of 20 μm. 17a is positioned and inserted into the opening 12a of the insulating resin layer 12, and the flux 16 applied to the protrusion 17a is transferred to the bottom of the opening 12a.
【００２４】次に、図３（ｃ）に示すように、配線基板
上に複数個のはんだボール（直径80μm ）１８を供給
し、基板に振動を加えることにより、これらのはんだボ
ール１８を１個ずつ絶縁樹脂層１２の開口部１２ａ内に
転がし入れる。次いで、遠赤外リフロー炉内で空気中ま
たは窒素雰囲気で 170℃の温度に20秒間加熱することに
より、はんだボールをリフローさせ、図３（ｄ）に示す
ように、開口部１２ａ内に厚さ40μm のはんだ層１３を
形成した後、フラックス１６等を洗浄除去する。Next, as shown in FIG. 3C, a plurality of solder balls (diameter: 80 μm) 18 are supplied onto the wiring board, and vibration is applied to the board, whereby one of the solder balls 18 is formed. Roll into the opening 12 a of the insulating resin layer 12. Then, the solder ball is reflowed by heating in a far-infrared reflow furnace in air or a nitrogen atmosphere at a temperature of 170 ° C. for 20 seconds, and as shown in FIG. After the formation of the solder layer 13 of 40 μm, the flux 16 and the like are removed by washing.
【００２５】一方、図３（ｅ）に示すように、半導体チ
ップ１４のＡｌ電極端子上に、先端に小突起１５ａを有
するボール状の金バンプ１５（高さ50μm ）を、ワイヤ
ボンダにより１個ずつ形成する。それには、まずワイヤ
ボンダのキャピラリーの先端に金ワイヤでボールを形成
し、これを半導体チップ１４の電極端子上に接合した
後、キャピラリーを水平方向に移動させてボールのネッ
ク部を切断することで、金ボールを形成する。このと
き、キャピラリーをわずかに戻して切断部を押さえるこ
とで、金ボールの先端に小突起１５ａを形成する。On the other hand, as shown in FIG. 3 (e), ball-shaped gold bumps 15 (height: 50 μm) each having a small projection 15a at the tip are individually formed on the Al electrode terminals of the semiconductor chip 14 by a wire bonder. Form. First, a ball is formed with a gold wire at the tip of the capillary of the wire bonder, and this is joined to the electrode terminal of the semiconductor chip 14, and then the capillary is moved horizontally to cut the neck of the ball. Form a gold ball. At this time, a small projection 15a is formed at the tip of the gold ball by slightly returning the capillary and pressing the cut portion.
【００２６】次いで、こうして形成された金バンプ１５
を、絶縁樹脂層１２の開口部１２ａ内に装填・形成され
たはんだ層１３に位置合わせして圧接し、 180℃の温度
で20秒間加熱する。そして、図３（ｆ）に示すように、
溶融軟化したはんだ層１３に貫入した金バンプ１５を、
配線パッド部１１ａ（Ｎｉ−Ａｕ層）と当接させ、Ａｕ
−Ａｕ接合により電気的に接続すると同時に、軟化した
絶縁樹脂層１２の上面を半導体チップ１４の電極端子形
成面（下面）に密着させ、絶縁樹脂層１２により、半導
体チップ１４の金バンプ１５と配線パッド部１１ａとの
接合部を被覆・封止する。Next, the thus formed gold bump 15
Is positioned and pressed against the solder layer 13 loaded and formed in the opening 12a of the insulating resin layer 12, and heated at a temperature of 180 ° C. for 20 seconds. Then, as shown in FIG.
The gold bump 15 penetrating into the melt-softened solder layer 13 is
It is brought into contact with the wiring pad portion 11a (Ni-Au layer),
At the same time as the electrical connection by Au bonding, the upper surface of the softened insulating resin layer 12 is brought into close contact with the electrode terminal forming surface (lower surface) of the semiconductor chip 14, and the insulating resin layer 12 connects the gold bump 15 of the semiconductor chip 14 with the wiring. The joint with the pad 11a is covered and sealed.
【００２７】このように構成される実施例の半導体装置
およびその製造方法では、配線基板の配線層形成面に、
配線パッド部１１ａを開口部１２ａとする所定の厚さの
絶縁樹脂層１２が形成され、この層をダムとして各開口
部１２ａにはんだ層１３が装填されているので、はんだ
層１３の高さ（厚さ）を十分にとることができ、信頼性
の高い安定した接続を行なうことができる。また、この
ようにはんだダムとして用いられる絶縁樹脂層１２によ
り、半導体チップ１４の電極端子形成面およびフリップ
チップ接合部の封止が行なわれているので、別に絶縁樹
脂等により封止を行なう必要がなく、効率的な製造が可
能である。In the semiconductor device and the method of manufacturing the same according to the embodiment, the wiring layer forming surface of the wiring board is
Since the insulating resin layer 12 having a predetermined thickness with the wiring pad portion 11a as the opening 12a is formed, and this layer is used as a dam and the solder layer 13 is loaded into each opening 12a, the height of the solder layer 13 ( Thickness) can be sufficiently secured, and a highly reliable and stable connection can be performed. In addition, since the insulating resin layer 12 used as a solder dam seals the electrode terminal forming surface of the semiconductor chip 14 and the flip chip bonding portion, it is necessary to separately seal with an insulating resin or the like. And efficient production is possible.
【００２８】また、絶縁樹脂層１２の開口部１２ａ内へ
のはんだ層１３の装填・形成が、ボール状に整形された
はんだボール１８を開口部１２ａ内に転がし入れ、はん
だをリフローさせることにより行なわれているので、は
んだ層１３の形成が容易であるうえに、厚さにばらつき
が生じない。さらに、はんだは低融点であり、はんだ層
１３は、熱が加わった場合の半導体チップ１４と配線基
板との熱膨張係数の違いに起因するストレスを緩和する
働きをするが、本発明では、絶縁基板１０として、樹脂
含浸基板に比べて熱膨張係数が小さく、半導体チップ１
４を構成するシリコンに近い熱膨張係数を有するガラス
基板が使用されているので、はんだ層１３に加わる熱に
よる衝撃を小さくすることができ、接続不良を抑制する
ことができる。The loading and formation of the solder layer 13 in the opening 12a of the insulating resin layer 12 is performed by rolling the solder ball 18 shaped into a ball into the opening 12a and reflowing the solder. Therefore, the formation of the solder layer 13 is easy and the thickness does not vary. Further, the solder has a low melting point, and the solder layer 13 functions to relieve stress caused by a difference in thermal expansion coefficient between the semiconductor chip 14 and the wiring board when heat is applied. As the substrate 10, the semiconductor chip 1 has a smaller coefficient of thermal expansion than the resin-impregnated substrate.
Since a glass substrate having a coefficient of thermal expansion close to that of silicon constituting component 4 is used, the impact due to heat applied to solder layer 13 can be reduced, and poor connection can be suppressed.
【００２９】またさらに、半導体チップ１４側のバンプ
として、先端に小突起１５ａを有するボール形状の金バ
ンプ１５が設けられており、先端に付設された小突起１
５ａが高さのばらつきを緩衝する働きをするので、半導
体チップ１４に傾きが生じることがなく、金バンプ１５
と配線パッド部１１ａとの安定した信頼性の高い接続が
実現される。Further, a ball-shaped gold bump 15 having a small projection 15a at the tip is provided as a bump on the semiconductor chip 14 side, and the small projection 1 attached to the tip is provided.
5a functions to buffer height variations, so that the semiconductor chip 14 does not tilt and the gold bumps 15a do not.
A stable and highly reliable connection between the semiconductor device and the wiring pad portion 11a is realized.
【００３０】[0030]
【発明の効果】以上の説明から明らかなように、本発明
においては、配線基板の配線層形成面に、配線パッド部
に開口部を有する調整された厚さの絶縁樹脂層が形成さ
れ、この層をダムとして、各開口部内にろう材層が装填
・形成されているので、十分な厚さのろう材層が形成さ
れ、半導体素子の安定した信頼性の高い実装が実現され
る。また、このような絶縁樹脂層により、半導体素子の
フリップチップ接合部等が封止されているので、別に絶
縁樹脂等による封止を行なう必要がなく、効率的な製造
が可能である。As is apparent from the above description, according to the present invention, an insulating resin layer having an adjusted thickness having an opening in a wiring pad portion is formed on a wiring layer forming surface of a wiring board. Since the layer is a dam and the brazing material layer is loaded and formed in each opening, a brazing material layer having a sufficient thickness is formed, and stable and reliable mounting of the semiconductor element is realized. In addition, since the flip chip bonding portion of the semiconductor element and the like are sealed by such an insulating resin layer, there is no need to separately perform sealing with an insulating resin or the like, and efficient manufacturing is possible.
【００３１】したがって、本発明によれば、配線基板に
多数の半導体チップを高密度で歩留り良くフリップチッ
プ実装し、信頼性の高いマルチチップモジュール（ＭＣ
Ｍ）を得ることができる。Therefore, according to the present invention, a large number of semiconductor chips are flip-chip mounted on a wiring board at a high density with a high yield, and a highly reliable multi-chip module (MC
M) can be obtained.
【図１】本発明の半導体装置の一実施例であるＭＣＭの
外観を示す斜視図。FIG. 1 is a perspective view showing an appearance of an MCM which is one embodiment of a semiconductor device of the present invention.
【図２】同実施例の半導体装置の要部を示す断面図。FIG. 2 is a cross-sectional view showing a main part of the semiconductor device of the embodiment.
【図３】実施例の半導体装置を製造するための各工程を
順に示す断面図。FIG. 3 is a sectional view sequentially showing each step for manufacturing the semiconductor device of the embodiment.
【図４】従来からのフリップチップ接続方法の各工程を
順に示す断面図。FIG. 4 is a sectional view sequentially showing each step of a conventional flip chip connection method.
１０………絶縁基板 １１………Ｃｕ配線層 １１ａ………配線パッド部 １１………半導体チップ １２………絶縁樹脂層 １２ａ………開口部 １３………はんだ層 １４………半導体チップ １５………金バンプ １６………はんだ付け用フラックス １８………はんだボール Reference Signs List 10 Insulating substrate 11 Cu wiring layer 11a Wiring pad part 11 Semiconductor chip 12 Insulating resin layer 12a Opening 13 Solder layer 14 Semiconductor Chip 15: Gold bump 16: Soldering flux 18: Solder ball
Claims (5)
層が設けられた配線基板と、該配線基板の配線層形成面
に形成された、前記配線層のパッド部に開口部を有する
絶縁樹脂層と、前記絶縁樹脂層の開口部内に装填された
ろう材層と、フェースダウンに配置され、各電極端子上
に設けられたバンプを介して前記配線層のパッド部に接
続され、かつ該接続部が前記ろう材層により固定された
半導体素子とを備え、前記絶縁樹脂層により、前記半導
体素子の電極端子形成面が被覆・封止されていることを
特徴とする半導体装置。1. A wiring board having a wiring layer provided on at least one main surface of an insulating substrate, and an insulating resin formed on a wiring layer forming surface of the wiring board and having an opening in a pad portion of the wiring layer. Layer, a brazing material layer loaded in the opening of the insulating resin layer, and a face-down, connected to a pad portion of the wiring layer via a bump provided on each electrode terminal, and And a semiconductor element fixed by the brazing material layer, and the electrode terminal forming surface of the semiconductor element is covered and sealed by the insulating resin layer.
が設けられ、このバンプが前記配線層のパッド部に接合
されていることを特徴とする請求項１記載の半導体装
置。2. The semiconductor device according to claim 1, wherein a gold bump is provided on an electrode terminal of said semiconductor element, and said bump is joined to a pad portion of said wiring layer.
が、前記開口部内に装填されたろう材層の厚さより厚い
ことを特徴とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the thickness of the insulating resin layer having the opening is larger than the thickness of the brazing material layer loaded in the opening.
層を形成する工程と、前記配線層の形成面に絶縁樹脂層
を形成する工程と、前記配線層のパッド部上の絶縁樹脂
層に開口部を形成する工程と、前記絶縁樹脂層の開口部
内にろう材層を装填するろう材装填工程と、半導体素子
の電極端子上にバンプを形成する工程と、前記バンプを
前記ろう材層に位置合わせして加熱・圧接し、前記配線
層のパッド部に接合するフリップチップ接合工程と、前
記絶縁樹脂層を加熱軟化させ、この絶縁樹脂層により前
記半導体素子の電極端子形成面を被覆し封止する封止工
程とを備えたことを特徴とする半導体装置の製造方法。4. A step of forming a wiring layer on at least one main surface of the insulating substrate, a step of forming an insulating resin layer on a surface on which the wiring layer is formed, and a step of forming an insulating resin layer on a pad portion of the wiring layer. A step of forming an opening; a step of loading a brazing material layer into the opening of the insulating resin layer; a step of forming a bump on an electrode terminal of a semiconductor element; and A flip-chip bonding step of aligning and heating / pressing and bonding to the pad portion of the wiring layer, and heating and softening the insulating resin layer, covering the electrode terminal forming surface of the semiconductor element with the insulating resin layer and sealing the surface; A method of manufacturing a semiconductor device, comprising a sealing step of stopping.
前記封止工程を行なうことを特徴とする請求項６記載の
半導体装置の製造方法。5. Simultaneously with the flip chip bonding step,
7. The method according to claim 6, wherein the sealing step is performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10268569A JP2000100868A (en) | 1998-09-22 | 1998-09-22 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10268569A JP2000100868A (en) | 1998-09-22 | 1998-09-22 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000100868A true JP2000100868A (en) | 2000-04-07 |
Family
ID=17460351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10268569A Withdrawn JP2000100868A (en) | 1998-09-22 | 1998-09-22 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000100868A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006005112A (en) * | 2004-06-17 | 2006-01-05 | Shinko Electric Ind Co Ltd | Semiconductor device and circuit board used therefor |
| KR100809698B1 (en) * | 2006-08-21 | 2008-03-06 | 삼성전자주식회사 | Mounting structure of semiconductor device having soldering flux and under fill resin layer and method of mounting method of semiconductor device |
| US7611040B2 (en) | 2005-05-24 | 2009-11-03 | Panasonic Corporation | Method for forming solder bump and method for mounting semiconductor device using a solder powder resin composition |
| JP2013033803A (en) * | 2011-08-01 | 2013-02-14 | Ngk Spark Plug Co Ltd | Circuit board, semiconductor power module and manufacturing method |
-
1998
- 1998-09-22 JP JP10268569A patent/JP2000100868A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006005112A (en) * | 2004-06-17 | 2006-01-05 | Shinko Electric Ind Co Ltd | Semiconductor device and circuit board used therefor |
| US7611040B2 (en) | 2005-05-24 | 2009-11-03 | Panasonic Corporation | Method for forming solder bump and method for mounting semiconductor device using a solder powder resin composition |
| KR100809698B1 (en) * | 2006-08-21 | 2008-03-06 | 삼성전자주식회사 | Mounting structure of semiconductor device having soldering flux and under fill resin layer and method of mounting method of semiconductor device |
| JP2013033803A (en) * | 2011-08-01 | 2013-02-14 | Ngk Spark Plug Co Ltd | Circuit board, semiconductor power module and manufacturing method |
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Legal Events
| Date | Code | Title | Description |
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| A300 | Withdrawal of application because of no request for examination |
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