JP2002151801A - Circuit board structure and its manufacturing method - Google Patents

Circuit board structure and its manufacturing method

Info

Publication number
JP2002151801A
JP2002151801A JP2000342980A JP2000342980A JP2002151801A JP 2002151801 A JP2002151801 A JP 2002151801A JP 2000342980 A JP2000342980 A JP 2000342980A JP 2000342980 A JP2000342980 A JP 2000342980A JP 2002151801 A JP2002151801 A JP 2002151801A
Authority
JP
Japan
Prior art keywords
substrate
mounting
circuit board
semiconductor device
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000342980A
Other languages
Japanese (ja)
Inventor
Makoto Watanabe
真 渡邊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP2000342980A priority Critical patent/JP2002151801A/en
Publication of JP2002151801A publication Critical patent/JP2002151801A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a high-density three-dimensional mounting structure. SOLUTION: This three-dimensional mounting structure is formed, in such a way that recessed sections are formed on the surface of a silicon substrate through anisotropic etching or machining, and a semiconductor device and passive components are mounted on the substrate by arranging the device and parts in the recessed sections and forming circuit patterns above the device and components.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置、受動部
品の実装構造および製造方法に関する。
[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, a mounting structure of passive components, and a manufacturing method.

【0002】[0002]

【従来の技術】ガラスエポキシ基板上に回路配線を形成
し、該回路基板上に半導体装置やコンデンサーや抵抗等
の受動部品である実装部品を接続させる方法が実用化さ
れている。この従来技術における半導体装置の接続構造
を図5の実装工程を示す工程断面図、図6のワイヤーボ
ンディング法の工程を示す断面図を用いて説明する。
2. Description of the Related Art A method of forming circuit wiring on a glass epoxy substrate and connecting mounted components, such as semiconductor devices, passive components such as capacitors and resistors, to the circuit substrate has been put to practical use. The connection structure of a semiconductor device according to this conventional technique will be described with reference to a sectional view showing a mounting step in FIG. 5 and a sectional view showing a step of a wire bonding method in FIG.

【0003】図5(a)に示すようにガラスエポキシ基
板19は表面に形成した銅薄膜をパターンニングして銅
パターン20の回路配線が8〜20μmの高さで形成さ
れている。また、銅パターン20の表面酸化を防ぐた
め、銅パターン20上に0.01〜5μm程度の厚さの
金(Au)メッキ21を施す構造が一般的である。以下
ガラスエポキシ基板19上の銅パターン20と銅パター
ン20上のAuメッキ21をまとめて回路配線15とす
る。
As shown in FIG. 5A, a glass epoxy substrate 19 is formed by patterning a copper thin film formed on a surface thereof, and a circuit wiring of a copper pattern 20 is formed at a height of 8 to 20 μm. Further, in order to prevent surface oxidation of the copper pattern 20, a structure in which a gold (Au) plating 21 having a thickness of about 0.01 to 5 μm is provided on the copper pattern 20 is general. Hereinafter, the copper pattern 20 on the glass epoxy substrate 19 and the Au plating 21 on the copper pattern 20 are collectively referred to as the circuit wiring 15.

【0004】図5(b)に示すように、ガラスエポキシ
基板19の回路配線15と半導体装置12の電極パッド
上に電気メッキあるいはスクリーン印刷等で形成された
半田の突起電極14とをガラスエポキシ回路基板上に搭
載する。半田の組成は、錫と鉛の合金で錫:鉛=6:4
の組成比のものが一般的である。
[0005] As shown in FIG. 5 (b), a circuit wiring 15 on a glass epoxy substrate 19 and a solder bump electrode 14 formed by electroplating or screen printing on an electrode pad of a semiconductor device 12 are connected to a glass epoxy circuit. Mounted on a substrate. The composition of the solder is an alloy of tin and lead: tin: lead = 6: 4
The composition ratio is generally.

【0005】次に、図5(c)に示すように、半導体装
置12とガラスエポキシ基板19間の隙間に封止樹脂1
6を流し込み空隙を樹脂で充填し、封止樹脂16を加熱
硬化して半導体装置12とガラスエポキシ回路基板を接
着する。
Next, as shown in FIG. 5C, the sealing resin 1 is inserted into a gap between the semiconductor device 12 and the glass epoxy substrate 19.
6, the gap is filled with a resin, and the sealing resin 16 is heated and cured to bond the semiconductor device 12 and the glass epoxy circuit board.

【0006】コンデンサーや抵抗などの受動部品13の
実装には、まず図5(b)に示すように半田22をスク
リーン印刷またはディスペンス法により回路基板上に塗
布し、受動部品13を配置する。
To mount the passive components 13 such as capacitors and resistors, first, as shown in FIG. 5B, solder 22 is applied on a circuit board by screen printing or dispensing, and the passive components 13 are arranged.

【0007】その後、図5(c)に示すようにリフロー
により半田22を溶融させ受動部品13の固定と電気的
接続を行う方法が一般的である。
Then, as shown in FIG. 5C, a method of melting the solder 22 by reflow to fix the passive component 13 and electrically connect the same is general.

【0008】また、半導体装置12の実装においてはA
u線あるいはアルミニウム線を用いたワイヤーボンディ
ング法を用いて実装される場合もある。
In mounting the semiconductor device 12, A
In some cases, the semiconductor device is mounted using a wire bonding method using a u-line or an aluminum line.

【0009】その場合は、図6(a)に示すようにガラ
スエポキシ基板19上に接着剤24にて半導体装置12
を素子面を上にして固定する。半導体装置12の固定に
使用する接着剤24は、Ag粒子を混入したエポキシ樹
脂の接着剤24を使用して、半導体装置12と電気的に
回路配線15と接続され、アースと接続させているのが
一般的である。接着剤24はエポキシ樹脂が主成分であ
るので150℃から200℃に加熱した炉中にて10分
から1時間程度加熱硬化させる。
In this case, as shown in FIG. 6A, the semiconductor device 12 is placed on a glass epoxy substrate 19 with an adhesive 24.
Is fixed with the element surface facing up. The adhesive 24 used for fixing the semiconductor device 12 is electrically connected to the semiconductor device 12 and the circuit wiring 15 using an epoxy resin adhesive 24 containing Ag particles, and is connected to the ground. Is common. Since the adhesive 24 is mainly composed of an epoxy resin, the adhesive 24 is cured by heating for about 10 minutes to 1 hour in a furnace heated to 150 ° C. to 200 ° C.

【0010】次に図6(b)に示すように、半導体装置
12の電極とガラスエポキシ基板19の上に形成された
回路配線15とをワイヤー23を用いてワイヤーボンデ
ィング法にて接続する。
Next, as shown in FIG. 6B, the electrodes of the semiconductor device 12 and the circuit wiring 15 formed on the glass epoxy substrate 19 are connected by using a wire 23 by a wire bonding method.

【0011】次に図6(c)に示すように、ワイヤー2
3部と半導体装置12を完全に覆いかぶせる用にモール
ド剤25で封止する。モールド剤25の材料はエポキシ
樹脂を用いて、モールド剤25を塗布した後、130℃
から200℃に加熱した炉中で10分から1時間加熱し
て硬化させる。
Next, as shown in FIG.
The three parts and the semiconductor device 12 are sealed with a molding agent 25 so as to completely cover them. The epoxy resin is used for the material of the molding agent 25.
Curing is carried out by heating in a furnace heated from 10 to 200 ° C. for 10 minutes to 1 hour.

【0012】[0012]

【発明が解決しようとする課題】従来技術では、半導体
装置12や受動部品13の実装基板には、ガラスエポキ
シ基板19、セラミック基板などを使用するのが一般的
であるが、これらの基板材料は耐熱性や変形など寸法精
度が悪いため高精度で高密度な微細回路配線15の形成
が難しい。
In the prior art, a glass epoxy board 19, a ceramic board, or the like is generally used as a mounting board for the semiconductor device 12 or the passive component 13, but these board materials are used. Due to poor dimensional accuracy such as heat resistance and deformation, it is difficult to form high-precision and high-density fine circuit wiring 15.

【0013】また、高密度実装を行うためにガラスエポ
キシ基板19に多層に回路配線を形成し、基板表面での
実装密度を上げても、半導体装置12、受動部品13の
実装部品の占有する面積以下で実装する事は不可能であ
る。
In addition, even if the circuit wiring is formed in multiple layers on the glass epoxy substrate 19 in order to perform high-density mounting and the mounting density on the surface of the substrate is increased, the area occupied by the mounted components of the semiconductor device 12 and the passive components 13 is increased. It is impossible to implement below.

【0014】さらに、半導体装置12の材料のシリコン
とガラスエポキシ基板19の熱膨張係数の差が大きく、
実装後に使用される環境の温度変化が大きいと熱膨張と
熱収縮を繰り返し、接続界面に歪みが発生し界面が剥離
してしまう現象が発生し、電気導通が取れなくなってし
まうという問題がある。
Further, the difference between the thermal expansion coefficients of silicon as the material of the semiconductor device 12 and the glass epoxy substrate 19 is large,
If the temperature change of the environment used after mounting is large, thermal expansion and thermal contraction are repeated, and a phenomenon occurs in which the connection interface is distorted and the interface is peeled off, so that there is a problem that electrical conduction cannot be obtained.

【0015】本発明の目的は上記課題を解決するため
に、回路基板材料に半導体装置と同じ材質のシリコンを
用い、さらにシリコン基板に基板凹部と微細な回路パタ
ーンを形成することで、シリコン基板内部にも半導体装
置、受動部品等を実装できるので、実装密度が高く、さ
らに電気接続が安定で信頼性の高い実装構造を提供する
ことである。
An object of the present invention is to solve the above problems by using silicon of the same material as that of a semiconductor device as a circuit board material, and further forming a substrate concave portion and a fine circuit pattern on the silicon substrate, thereby forming an internal silicon substrate. Another object of the present invention is to provide a mounting structure having a high mounting density, a stable electric connection, and a high reliability, since a semiconductor device, passive components, and the like can be mounted.

【0016】[0016]

【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置、受動部品の実装構造は、下記
記載の構成を採用する。
In order to achieve the above object, a semiconductor device and a passive component mounting structure according to the present invention employ the following configurations.

【0017】半導体装置、受動部品の実装部品のいずれ
か又は両方が基板上に実装された回路基板において、該
基板がシリコン基板であり、所定の位置に少なくとも実
装部品の埋め込みが可能な任意の深さの基板凹部が形成
されており、そこで形成された該基板凹部及び基板凸部
を含む実装面に形成された回路配線に、実装部品が実装
されていることを特徴とし、前記基板凹部が任意の角度
のテーパー状傾斜面を有する事を特徴とし、基板凹部に
実装部品が配置された後、基板凹部を封止樹脂で平坦化
した実装面に形成された第2の回路配線に実装部品を実
装する事を特徴とする。
In a circuit board on which one or both of a semiconductor device and a mounted component of a passive component are mounted on a substrate, the substrate is a silicon substrate, and at least an arbitrary depth at which a mounted component can be embedded in a predetermined position. Substrate recesses are formed, and mounted components are mounted on circuit wiring formed on the mounting surface including the substrate recesses and the substrate projections formed therein. Characterized by having a tapered inclined surface at an angle of 、, after mounting components are disposed in the substrate recess, mounting the components to the second circuit wiring formed on the mounting surface flattened substrate sealing resin with sealing resin The feature is to implement.

【0018】また、半導体装置、受動部品の実装部品の
いずれか又は両方が基板上に実装された回路基板の製造
方法において、該基板にシリコン基板を用いて所定の位
置に任意の深さで基板凹部を形成する工程と、該基板凹
部及び基板凸部を含む実装面に回路配線を形成する工程
と、実装部品を基板凹部、基板凸部の所定の位置に実装
する工程を有する事を特徴とし、該実装部品を基板凹部
と基板凸部の任意の位置に実装する工程の後に、さらに
封止樹脂で基板凹部を平坦化する工程と第2の回路配線
形成する工程と、所定の位置に実装部品を実装する工程
を有する事を特徴とし、前記基板凹部を形成する工程
が、異方性エッチングまたは機械加工により行われる事
を特徴とする。
Further, in a method of manufacturing a circuit board in which one or both of a semiconductor device and a mounted component of a passive component are mounted on a substrate, the substrate is formed at a predetermined position at an arbitrary depth using a silicon substrate as the substrate. Forming a concave portion, forming circuit wiring on a mounting surface including the substrate concave portion and the substrate convex portion, and mounting the mounted component at a predetermined position of the substrate concave portion and the substrate convex portion. After the step of mounting the mounted component at an arbitrary position between the substrate concave portion and the substrate convex portion, further flattening the substrate concave portion with a sealing resin, forming a second circuit wiring, and mounting the component at a predetermined position. The method is characterized in that the method includes a step of mounting a component, and the step of forming the concave portion of the substrate is performed by anisotropic etching or machining.

【0019】(作用)本発明では、回路基板の材料に半
導体装置と同じシリコン基板を用いることで、フォトリ
ソ法による微細回路配線の形成、異方性エッチングによ
る基板凹部の加工が可能になり高密度な実装構造を形成
する事ができる。
(Function) In the present invention, by using the same silicon substrate as that of the semiconductor device as the material of the circuit board, it is possible to form fine circuit wiring by the photolithography method and to process the substrate recess by anisotropic etching. A simple mounting structure can be formed.

【0020】さらに半導体装置とシリコン基板の熱膨張
が同じであることから実装後も安定な接続を維持でき
る。
Further, since the semiconductor device and the silicon substrate have the same thermal expansion, stable connection can be maintained even after mounting.

【0021】また、半導体装置とシリコン基板を研磨す
ることで、ごく薄い実装モジュールを作製することが可
能となる。
Further, by polishing the semiconductor device and the silicon substrate, a very thin mounting module can be manufactured.

【0022】したがって、従来構造よりも接続信頼性が
高く、薄型で高密度な3次元の実装構造を得ることがで
きる。
Therefore, a thin, high-density three-dimensional mounting structure having higher connection reliability than the conventional structure can be obtained.

【0023】[0023]

【発明の実施の形態】以下図面を用いて本発明の実施形
態における半導体装置の実装方法を説明する。図1は本
発明の実装構造の断面図、図2はシリコン基板の回路形
成工程断面図、図3はシリコン基板11上への実装工程
を示した断面図、図4は異方性エッチングの説明図であ
る。以下図1、図2、図3、図4を用いて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for mounting a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a mounting structure of the present invention, FIG. 2 is a cross-sectional view of a circuit forming step of a silicon substrate, FIG. 3 is a cross-sectional view showing a mounting step on a silicon substrate 11, and FIG. FIG. Hereinafter, description will be made with reference to FIGS. 1, 2, 3, and 4.

【0024】図1に示す本発明の実装構造に用いるシリ
コン基板11は、シリコンを材料とした基板に異方性エ
ッチングにより実装部品の埋め込みが可能な任意の深さ
の基板凹部を作製し、さらに回路配線を配する構造とし
た。さらにその基板凹部の中に半導体装置12やコンデ
ンサー、抵抗などの受動部品13(図示していない)を
半田22あるいはワイヤーボンディング法を用いてワイ
ヤー23で接続し、さらにその上に第2の回路配線1
5′を形成し、さらにその上に半導体装置12や受動部
品13の実装部品を配置し、それぞれの実装部品を電気
的に接続して回路基板を構造した。
The silicon substrate 11 used in the mounting structure of the present invention shown in FIG. 1 is formed by forming an indentation of an arbitrary depth in which a mounting component can be embedded in a substrate made of silicon by anisotropic etching. The circuit wiring is arranged. Further, a passive component 13 (not shown) such as a semiconductor device 12, a capacitor, and a resistor is connected to the substrate recess by a wire 22 using a solder 22 or a wire bonding method, and a second circuit wiring is further provided thereon. 1
5 'was formed, and further, mounted components of the semiconductor device 12 and the passive component 13 were arranged thereon, and each mounted component was electrically connected to form a circuit board.

【0025】図2に回路基板に用いるシリコン基板11
の加工工程を示す。まず、図2(a)に示すように、結
晶方位が(100)面になっているシリコン基板11の
表面にSiO2膜17を形成したものを用いた。そのS
iO2膜17上に感光性レジスト18を塗布し、フォト
リソ法にて基板凹部1を形成する位置にレジスト開口部
を形成した。
FIG. 2 shows a silicon substrate 11 used as a circuit board.
Shows the processing steps. First, as shown in FIG. 2A, a silicon substrate 11 having a (100) crystal orientation and a SiO 2 film 17 formed on the surface was used. That S
A photosensitive resist 18 was applied on the iO 2 film 17, and a resist opening was formed at a position where the substrate recess 1 was formed by a photolithography method.

【0026】次に図2(b)に示すようにAr雰囲気中
でドライエッチングを行い、SiO 2膜17を所定のパ
ターン形状に開口させる。さらにSiO2膜17表面に
残っているレジストを酸素雰囲気中のRIE法(リアク
ティブイオンエッチング法)にて除去した。
Next, as shown in FIG.
Dry etching with SiO TwoThe film 17 is
Open in the shape of a turn. Furthermore, SiOTwoOn the surface of membrane 17
The remaining resist is removed by an RIE method (reactor) in an oxygen atmosphere.
(Active ion etching method).

【0027】図2(c)に示すように、50〜70℃程
度に加熱した30%KOH中に、2〜6時間浸し、Si
2膜17をマスクとしてシリコン基板11をエッチン
グした。
As shown in FIG. 2C, the substrate is immersed in 30% KOH heated to about 50 to 70 ° C. for 2 to 6 hours,
The silicon substrate 11 was etched using the O 2 film 17 as a mask.

【0028】さらに図2(d)に示すように、残ったS
iO2膜17をArガスを用いたRIE法により除去
し、基板凹部1と基板凸部2を有するシリコン基板11
を形成した。
Further, as shown in FIG.
The iO 2 film 17 is removed by RIE using Ar gas, and the silicon substrate 11 having the substrate concave portion 1 and the substrate convex portion 2 is removed.
Was formed.

【0029】最後に図2(e)に示すように、表面に絶
縁層としてSiO2膜17を全面に形成し、その上にス
パッタ法や蒸着法によりアルミニウム(Al)、銅(C
u)もしくは金(Au)などを用い導電性の膜を形成
し、フォトリソ法により回路配線15を形成した。
Finally, as shown in FIG. 2E, an SiO 2 film 17 is formed on the entire surface as an insulating layer on the surface, and aluminum (Al), copper (C) is formed thereon by sputtering or vapor deposition.
u) or gold (Au) to form a conductive film, and the circuit wiring 15 was formed by photolithography.

【0030】多層の回路配線にする場合は、ポリイミド
やSiN等の絶縁膜を形成し、フォトリソグラフィを繰
り返し、回路配線15を形成すればよい。
In the case of forming a multilayer circuit wiring, an insulating film such as polyimide or SiN may be formed, and photolithography may be repeated to form the circuit wiring 15.

【0031】次に、図3(a)に示すように、作製した
シリコン基板11の基板凹部1の内側に半導体装置12
やコンデンサー抵抗等の受動部品13(図示していな
い)を接続した。
Next, as shown in FIG. 3A, the semiconductor device 12 is
And a passive component 13 (not shown) such as a capacitor resistor.

【0032】半導体装置12と回路配線15との接続方
法は実装部品に合わせて、ワイヤーボンディング法、ま
たは半田や導電接着剤を用いたフリップチップ法により
接続した。ワイヤーボンディング法は直径20μmから
50μm程度のAu線やアルミニウム線を超音波と圧力
で半導体装置12の電極部とシリコン基板11の回路配
線15それぞれに溶着させることで接続した。
The semiconductor device 12 and the circuit wiring 15 were connected by a wire bonding method or a flip chip method using a solder or a conductive adhesive according to a mounted component. In the wire bonding method, connection was made by welding an Au wire or an aluminum wire having a diameter of about 20 μm to 50 μm to the electrode portion of the semiconductor device 12 and the circuit wiring 15 of the silicon substrate 11 by ultrasonic waves and pressure.

【0033】半田を用いたフリップチップ法を用いて実
装する場合は、電極部にメッキ法やスクリーン印刷法に
て錫:鉛=6:4組成の半田材料の突起電極14が形成
された半導体装置12を配置し、加熱炉にて加熱し半田
を溶融させ接合させた。半田の組成が錫:鉛=6:4の
場合は、溶融温度は183℃であるので、加熱炉にて1
83℃から240℃程度に加熱して半田を溶融させた。
In the case of mounting using a flip-chip method using solder, a semiconductor device in which a bump electrode 14 of a solder material of tin: lead = 6: 4 is formed on an electrode portion by plating or screen printing. 12 was arranged and heated in a heating furnace to melt and join the solder. When the composition of the solder is tin: lead = 6: 4, the melting temperature is 183 ° C.
The solder was melted by heating from about 83 ° C. to about 240 ° C.

【0034】導電接着剤を用いる場合は、半導体装置1
2の電極部にメッキ法にて金の突起電極14を形成し、
その突起電極14上にエポキシ樹脂にAg粒子を混入さ
せた導電接着剤を塗布し、突起電極14上に導電接着剤
を塗布した半導体装置12を回路配線15上に配置し、
100℃から170℃に加熱した炉中にて10分から1
時間加熱して導電接着剤を硬化させた。
When a conductive adhesive is used, the semiconductor device 1
A gold projecting electrode 14 is formed on the electrode portion 2 by plating.
A conductive adhesive in which Ag particles are mixed into an epoxy resin is applied on the protruding electrodes 14, and the semiconductor device 12 in which the conductive adhesive is applied on the protruding electrodes 14 is arranged on the circuit wiring 15,
10 minutes to 1 in a furnace heated from 100 ° C to 170 ° C
The conductive adhesive was cured by heating for a period of time.

【0035】コンデンサーや抵抗などの受動部品13
は、半田22をスクリーン印刷かディスペンスにより回
路配線15上に塗布し、その上に受動部品13を配置
し、加熱により溶融接合させる。
Passive components 13 such as capacitors and resistors
Is to apply the solder 22 on the circuit wiring 15 by screen printing or dispensing, dispose the passive component 13 thereon, and perform fusion bonding by heating.

【0036】次に図3(b)に示すように、基板凹部1
に絶縁性の樹脂からなる封止樹脂16を注入し封止し、
さらに表面を研磨して、基板凹部1を平坦化した。基板
凹部1に注入する封止樹脂16は、絶縁性の樹脂であれ
ば何でもよいが、本実施例においてはエポキシ樹脂を用
いて平坦化を行った。その後、100℃から170℃に
加熱した炉中に10分から30分投入し封止樹脂16を
硬化させた。
Next, as shown in FIG.
A sealing resin 16 made of an insulating resin is injected into and sealed.
The surface was further polished to flatten the substrate recess 1. The sealing resin 16 to be injected into the substrate concave portion 1 may be any resin as long as it is an insulating resin. In the present embodiment, flattening was performed using an epoxy resin. Thereafter, the mixture was put into a furnace heated from 100 ° C. to 170 ° C. for 10 minutes to 30 minutes to cure the sealing resin 16.

【0037】さらにその上に図3(c)に示すように、
再度フォトリソ法により第2の回路回路配線15′を形
成し、該第2の回路配線15′に半導体装置12やコン
デンサーや抵抗等の受動部品13等の実装部品をフリッ
プチップ法、ワイヤーボンディング法、もしくは半田印
刷法により実装した。該実装部品を配置する箇所は、下
段の実装部品の上部(封止樹脂表面)でもよく、基板凸
部に実装部品を実装しても良い。
Further, as shown in FIG.
A second circuit wiring 15 'is formed again by the photolithography method, and mounted components such as the semiconductor device 12 and passive components 13 such as a capacitor and a resistor are mounted on the second circuit wiring 15' by a flip chip method, a wire bonding method, or the like. Alternatively, it was mounted by a solder printing method. The mounting component may be placed on the upper part (the surface of the sealing resin) of the lower mounting component, or the mounting component may be mounted on the protrusion of the substrate.

【0038】シリコン基板11上に搭載する半導体装置
12、受動部品13が複数の場合は、上記実装工程を繰
り返し、複数の半導体装置12、受動部品13を実装す
る。
When there are a plurality of semiconductor devices 12 and passive components 13 mounted on the silicon substrate 11, the above mounting process is repeated, and a plurality of semiconductor devices 12 and passive components 13 are mounted.

【0039】上記実施例では基板凹部1の形成に異方性
エッチングを用いた方法を示したが、切削加工等の機械
加工により基板凹部1を形成して、上記回路構造を作製
する事ができる。
In the above embodiment, the method using anisotropic etching for forming the substrate concave portion 1 has been described. However, the substrate concave portion 1 can be formed by machining such as cutting to form the circuit structure. .

【0040】本発明においては、半導体装置12とシリ
コン基板11が同じ材質であり、熱膨張係数などの物理
的特性が同じであることから、実装後の使用環境の温度
変化などが生じても接合界面に熱膨張の差による歪みが
発生しにくく、安定な接続を維持することができた。
In the present invention, since the semiconductor device 12 and the silicon substrate 11 are made of the same material and have the same physical characteristics such as a coefficient of thermal expansion, the bonding is performed even if a temperature change in the use environment after mounting occurs. Distortion due to the difference in thermal expansion did not easily occur at the interface, and a stable connection could be maintained.

【0041】また、半導体装置12と基板の材質が同じ
シリコンであるため、熱衝撃試験等の信頼性試験を行っ
ても、半導体装置12とシリコン基板11間には熱膨張
の差が生じないので、接合部にも歪みが生じず安定な接
続を得ることができた。
Further, since the semiconductor device 12 and the substrate are made of the same silicon material, there is no difference in thermal expansion between the semiconductor device 12 and the silicon substrate 11 even when a reliability test such as a thermal shock test is performed. Thus, a stable connection could be obtained without any distortion at the joint.

【0042】シリコン基板11は熱膨張が小さく平坦性
が良いので、フォトリソグラフィ法によるパターン形成
が高精度で行う事ができた。具体的には10μmピッチ
の回路配線15を形成することも可能であることが判っ
た。
Since the silicon substrate 11 has low thermal expansion and good flatness, pattern formation by photolithography could be performed with high precision. Specifically, it has been found that it is also possible to form the circuit wiring 15 having a pitch of 10 μm.

【0043】さらに、シリコン基板11を研磨して厚さ
を薄くすることが可能であり、基板の厚さを100μm
程度に研磨して、さらに半導体装置12も研磨して10
0μm程度とすることで、実装部と配線層の厚みを入れ
ても総厚0.3mm程度の薄い回路基板構造を作製する
ことが可能である。
Further, it is possible to reduce the thickness by polishing the silicon substrate 11 and to reduce the thickness of the substrate to 100 μm.
And then the semiconductor device 12 is also polished to 10
By setting the thickness to about 0 μm, a thin circuit board structure having a total thickness of about 0.3 mm can be manufactured even when the thickness of the mounting portion and the wiring layer is taken into account.

【0044】また、結晶方位(100)のシリコン基板
11に対してKOHでエッチングを行い、基板凹部1と
基板凸部2を形成した。図4に示すように、エッチング
が底面(100)が速くエッチングが進行し、(11
1)面はエッチング速度が遅いため、(100)面と比
べて(111)の結晶方位面が多く残るため、(11
1)面が任意の角度のテーパー状傾斜面とした基板凹部
1を形成する事ができた。
The silicon substrate 11 having the crystal orientation (100) was etched with KOH to form the concave portions 1 and the convex portions 2 of the substrate. As shown in FIG. 4, the etching proceeds rapidly at the bottom surface (100), and (11)
Since the (1) plane has a lower etching rate, a larger number of (111) crystal orientation planes remain than the (100) plane.
1) It was possible to form the substrate concave portion 1 whose surface was a tapered inclined surface having an arbitrary angle.

【0045】したがって、スパッタ法や蒸着法で回路配
線15を形成しする場合にもステップカバレッジが良好
で、回路配線の膜形成時に断線等が起こりにくい。
Therefore, even when the circuit wiring 15 is formed by a sputtering method or a vapor deposition method, the step coverage is good, and disconnection or the like is unlikely to occur when the circuit wiring film is formed.

【0046】[0046]

【発明の効果】以上の説明より明らかなように本発明に
おいては、シリコン基板上に半導体装置を実装すること
で、より安定で微細な接続が可能となり、さらに超薄型
に加工することが可能で、微細配線を用いた高信頼性の
小型薄型の3次元実装回路を得ることができた。
As is clear from the above description, according to the present invention, by mounting a semiconductor device on a silicon substrate, more stable and fine connection can be achieved, and furthermore, it is possible to work ultra-thin. Thus, a highly reliable small and thin three-dimensional mounting circuit using fine wiring could be obtained.

【0047】なお、図面3bで2段積層型の高密度の回
路基板構造について説明したが、シリコン基板11に更
に深い基板凹部1を形成し、3段、4段と積層して3次
元構造の回路基板構造としても良い事は言うまでもな
い。
Although the two-stage stacked type high-density circuit board structure has been described with reference to FIG. 3B, a deeper substrate recess 1 is formed in the silicon substrate 11, and the three-stage and four-stage stacked structures are formed. It goes without saying that a circuit board structure may be used.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実装構造の断面図FIG. 1 is a cross-sectional view of a mounting structure according to the present invention.

【図2】本発明のシリコン基板の加工工程断面図FIG. 2 is a sectional view of a processing step of the silicon substrate of the present invention.

【図3】本発明の実装工程断面図FIG. 3 is a sectional view of a mounting process according to the present invention.

【図4】本発明の異方性エッチングの説明図FIG. 4 is an explanatory view of anisotropic etching of the present invention.

【図5】従来技術での実装工程の断面図FIG. 5 is a cross-sectional view of a mounting process according to the related art.

【図6】従来技術でのワイヤーボンディング方による実
装工程断面図
FIG. 6 is a sectional view of a mounting process by a wire bonding method according to a conventional technique.

【符号の説明】[Explanation of symbols]

1 基板凹部 2 基板凸部 11 シリコン基板 12 半導体装置 13 受動部品 14 突起電極 15 回路配線 15′第2の回路配線 16 封止樹脂 17 SiO2膜 18 感光性レジスト 19 ガラスエポキシ基板 20 銅パターン 21 金メッキ 22 半田 23 ワイヤー 24 接着剤 25 モールド剤1 substrate recess 2 substrate protrusions 11 a silicon substrate 12 semiconductor device 13 passive component 14 projecting electrode 15 circuit wiring 15 'the second circuit interconnection 16 sealing resin 17 SiO 2 film 18 photoresist 19 glass epoxy substrate 20 copper pattern 21 gilding 22 Solder 23 Wire 24 Adhesive 25 Molding agent

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 半導体装置、受動部品の実装部品のいず
れか又は両方が基板上に実装された回路基板において、
該基板がシリコン基板であり、所定の位置に少なくとも
実装部品の埋め込みが可能な任意の深さの基板凹部が形
成されており、該基板凹部及び基板凸部を含む実装面に
形成された回路配線に、該実装部品が実装されているこ
とを特徴とする回路基板構造。
1. A circuit board having one or both of a semiconductor device and a mounted component of a passive component mounted on the substrate,
The substrate is a silicon substrate, a substrate recess of an arbitrary depth capable of embedding at least a mounting component is formed at a predetermined position, and a circuit wiring formed on a mounting surface including the substrate recess and the substrate protrusion. A circuit board structure on which the mounting component is mounted.
【請求項2】 前記基板凹部が任意の角度のテーパー状
傾斜面を有する事を特徴とする請求項1に記載の回路基
板構造。
2. The circuit board structure according to claim 1, wherein said substrate recess has a tapered inclined surface having an arbitrary angle.
【請求項3】 前記基板凹部に実装部品が配置された
後、該基板凹部を封止樹脂で平坦化した実装面に形成さ
れた第2の回路配線に実装部品を実装する事を特徴とす
る請求項1または2項のいずれかに記載の回路基板構
造。
3. A mounting component is mounted on a second circuit wiring formed on a mounting surface in which the substrate recess is flattened with a sealing resin after the mounting component is arranged in the substrate recess. The circuit board structure according to claim 1.
【請求項4】 半導体装置、受動部品の実装部品のいず
れか又は両方が基板上に実装された回路基板の製造方法
において、該基板にシリコン基板を用いて所定の位置に
任意の深さで基板凹部を形成する工程と、該基板凹部及
び基板凸部を含む実装面に回路配線を形成する工程と、
基板凹部、基板凸部の所定の位置に該実装部品を実装す
る工程を有する事を特徴とする回路基板構造の製造方
法。
4. A method of manufacturing a circuit board in which one or both of a semiconductor device and a mounted component of a passive component are mounted on a substrate, wherein the substrate is provided at a predetermined position at an arbitrary depth by using a silicon substrate as the substrate. Forming a recess, and forming circuit wiring on a mounting surface including the substrate recess and the substrate projection,
A method of manufacturing a circuit board structure, comprising a step of mounting the mounted component at predetermined positions of a substrate concave portion and a substrate convex portion.
【請求項5】 前記基板凹部と基板凸部の任意の位置に
実装部品を実装する工程の後に、さらに封止樹脂で基板
凹部を平坦化する工程と、第2の回路配線形成する工程
と、所定の位置に実装部品を実装する工程を有する事を
特徴とする請求項4に記載の回路基板構造の製造方法。
5. After the step of mounting a mounting component at an arbitrary position between the substrate concave portion and the substrate convex portion, further flattening the substrate concave portion with a sealing resin, and forming a second circuit wiring; The method for manufacturing a circuit board structure according to claim 4, further comprising a step of mounting a mounting component at a predetermined position.
【請求項6】 前記基板凹部を形成する工程が、異方性
エッチングにより行われる事を特徴とする請求項4また
は5項のいずれかに記載の回路基板構造の製造方法。
6. The method according to claim 4, wherein the step of forming the substrate recess is performed by anisotropic etching.
【請求項7】 前記基板凹部を形成する工程が、機械加
工により行われる事を特徴とする請求項4または5項の
いずれかに記載の回路基板構造の製造方法。
7. The method of manufacturing a circuit board structure according to claim 4, wherein the step of forming the substrate recess is performed by machining.
JP2000342980A 2000-11-10 2000-11-10 Circuit board structure and its manufacturing method Pending JP2002151801A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
JP2002151801A true JP2002151801A (en) 2002-05-24

Family

ID=18817426

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2002151801A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010165921A (en) * 2009-01-16 2010-07-29 Kinko Denshi Kofun Yugenkoshi Semiconductor process, and silicon substrate and chip package structure to which the same is applied
KR101079429B1 (en) * 2009-09-11 2011-11-02 삼성전기주식회사 Device package substrate and manufacturing method of the same
US8951835B2 (en) 2010-04-08 2015-02-10 Samsung Electro-Mechanics Co., Ltd. Method of fabricating a package substrate
JP2016031967A (en) * 2014-07-28 2016-03-07 ローム株式会社 Semiconductor device and method of manufacturing the same
JP2017201659A (en) * 2016-05-02 2017-11-09 ローム株式会社 Electronic component and manufacturing method for the same
US10734355B2 (en) 2015-06-25 2020-08-04 Olympus Corporation Electronic circuit board, laminated board, and method of manufacturing electronic circuit board
US10861759B2 (en) 2016-10-25 2020-12-08 Murata Manufacturing Co., Ltd. Circuit module

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010165921A (en) * 2009-01-16 2010-07-29 Kinko Denshi Kofun Yugenkoshi Semiconductor process, and silicon substrate and chip package structure to which the same is applied
KR101079429B1 (en) * 2009-09-11 2011-11-02 삼성전기주식회사 Device package substrate and manufacturing method of the same
US8951835B2 (en) 2010-04-08 2015-02-10 Samsung Electro-Mechanics Co., Ltd. Method of fabricating a package substrate
JP2016031967A (en) * 2014-07-28 2016-03-07 ローム株式会社 Semiconductor device and method of manufacturing the same
US10734355B2 (en) 2015-06-25 2020-08-04 Olympus Corporation Electronic circuit board, laminated board, and method of manufacturing electronic circuit board
JP2017201659A (en) * 2016-05-02 2017-11-09 ローム株式会社 Electronic component and manufacturing method for the same
US10861759B2 (en) 2016-10-25 2020-12-08 Murata Manufacturing Co., Ltd. Circuit module

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