JP2010165921A - Semiconductor process, and silicon substrate and chip package structure to which the same is applied - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon substrate and a chip package structure formed by applying a semiconductor process. <P>SOLUTION: A surface of a silicon substrate 110 is partially exposed, and at least a step-like structure is formed on the silicon substrate 110 by etching the surface of the silicon substrate 110. The step-like structure contains a first notch 142 having a first depth and a second notch 144 having a second depth. The first depth is shallower than the second depth, and a diameter of the first notch 142 is larger than that of the second notch 144. A final insulating layer 160 and a metal seed layer 170 are successively formed on the step-like structure. A patterned photoresist layer is formed on the metal seed layer 170. A circuit layer 190 which covers the exposed part of the metal seed layer 170 positioned on the first notch 142 (coving for forming a curved concave surface) is formed. Then a patterned photoresist layer and the part of the metal seed layer 170 arranged under the patterned photoresist layer are removed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to semiconductor processes, and more particularly to silicon substrates and chip package structures formed by applying the semiconductor processes.

  2. Description of Related Art As semiconductor technology advances, integrated circuit (IC) chips are now equipped with a number of closely arranged transistors and a plurality of signal pads disposed on the surface of the chip. Chips are often placed on a chip package carrier to form a chip package structure for packaging purposes. Here, by applying the packaging process, sufficient signal paths, heat dissipating paths, and structural protection can be provided to the chip. .

  At this current stage, packaging technology has evolved and various chip packaging structures have been continuously developed. By way of example, the chip is attached to the inner (inner) lead or die pad of the lead frame to form a thin small outline package (TSOP). Instead, the chips are attached to form a ball grid array (BGA) package against a printed circuit board (printed circuit board).

  In the TSOP structure, the chip is attached to the inner lead or die pad of the lead frame, and a plurality of outer (outer) leads for external devices to be electrically connected are arranged at the edge of the TSOP structure. Since the outer lead is not covered by the molding compound (molding compound), it can happen that the outer lead is affected by the external environment or destroyed by the excessive length of the outer lead, which further affects the signal transmission. To raise.

  On the other hand, in a BGA package structure, an organic substrate (substrate) or ceramic substrate often serves as a carrier for the chip, and the chip has a chip internal signal (downward on the bottom surface of the carrier, the carrier internal ( The electrical signal placed and sent behind the carrier so that it can be sent through the (internal) circuit can finally be transmitted through the solder balls of the carrier to the external electrical device. Since the solder balls are formed in an area array fashion on the bottom surface of the carrier, the aforementioned BGA package structure is used in high frequency and high pin count semiconductor devices. Nevertheless, the overall height of the BGA package structure is approximately 1.0-1.4 mm, which is not compliant with miniaturization requirements (ie, the height is lower than 0.5 mm).

  SUMMARY OF THE INVENTION The present invention is directed to a semiconductor process for manufacturing a silicon substrate (silicon substrate) that serves as a chip carrier for wire bonding.

  The present invention is further directed to a silicon substrate that serves as a chip carrier for wire bonding.

  The present invention is further directed to a chip package structure having a reduced thickness.

  In the present invention, a semiconductor process is provided. First, a silicon base (silicon substrate) is provided. Next, the surface of the silicon substrate is partially exposed and at least a stair structure is formed on the silicon substrate by etching the surface of the silicon substrate. The staircase structure has a first notch (stage, notch) having a first depth and a second notch having a second depth. The first depth is smaller (shallow) than the second depth, and the diameter of the first notch is larger (longer) than the diameter of the second notch. A final insulating layer (insulating layer) is then formed on the stepped structure. A metal seed layer is formed on the final insulating layer. A patterned photoresist layer is formed on the metal seed layer. Here, the patterned (patterned) photoresist layer covers the portion of the metal seed layer where the circuit layer (circuit layer) is not formed (should not be formed), and the patterned photoresist layer is formed with the circuit layer ( Expose other parts of the metal seed layer (to be formed). Next, a circuit layer is formed and the circuit layer covers the exposed portion of the metal seed layer. Thereafter, the covered portion of the patterned photoresist layer and the metal seed layer disposed under the patterned photoresist layer is removed.

  In accordance with an embodiment of the present invention, the stepped structure is formed by first forming a first insulating layer on a silicon substrate. Next, a first patterned photoresist mask is formed on the first insulating layer. The portion of the first insulating layer exposed by the first patterned photoresist mask is etched to form the patterned first insulating layer with the use of the first patterned photoresist mask as an etching mask. The first patterned photoresist mask is then removed. A first notch having a first depth is then formed on the silicon substrate by etching the silicon substrate exposed by the patterned first insulating layer with use of the patterned first insulating layer as an etching mask. To do. Thereafter, the first insulating layer is removed. A second insulating layer is then formed at the first notch, and the second insulating layer covers the first notch. A second patterned photoresist mask is formed on the second insulating layer. The portion of the second insulating layer exposed by the second patterned photoresist mask is etched to form a patterned second insulating layer, with the use of the second patterned photoresist mask as an etching mask. The second patterned photoresist mask is then removed. Thereafter, a second notch having a second depth is etched on the silicon substrate with the use of the patterned second insulating layer as an etching mask on the silicon substrate exposed by the patterned second insulating layer. Form. Next, the second insulating layer is removed and a stepped structure is formed.

  In accordance with an embodiment of the present invention, the circuit layer includes a first metal layer and a second metal layer. The first metal layer covers the exposed portion of the metal seed layer positioned on the first notch. The second metal layer covers the first metal layer.

  In accordance with an embodiment of the present invention, after the coated photoresist layer and the coated portion of the metal seed layer disposed under the patterned photoresist layer are removed, the semiconductor process further includes at least a chip first in the second notch. It is included to be arranged. The upper surface of the chip is lower than the second metal layer of the circuit layer located at the first notch. Next, a wire bonding process is performed to connect the chip to the second metal layer of the circuit layer through a plurality of conductive wires (conductive wires, conductive wires). The stepped structure is then filled with a molding compound, which encapsulates the final insulating layer, circuit layer, metal seed layer, chip, and lead. Thereafter, a portion of the molding material and a portion of the circuit layer are thinned (thinned) so that the molding material and the first metal layer are substantially aligned with each other (aligned in a row). Thereafter, the silicon substrate and chip are thinned so that the lower surface of the chip is exposed. Finally, at least a metal pad is formed on the first metal layer of the circuit layer.

  In the present invention, there is provided a silicon substrate formed by applying the semiconductor process, wherein the final insulating layer covers the stepped structure, and the circuit layer is a metal seed layer positioned on the first notch. The exposed part is covered and the second notch is used to accommodate the chip.

  In accordance with an embodiment of the present invention, the chip is electrically connected to the circuit layer through a plurality of wires.

  The present invention provides a chip package structure including a silicon substrate, an insulating layer, a metal seed layer, a circuit layer, a chip, a molding material, and at least a metal pad. The silicon substrate has a stepped structure. The stepped structure has a first notch having a first depth and a second notch having a second depth. The first depth is shallower than the second depth, and the diameter of the first notch is longer than the diameter of the second notch. The insulating layer is disposed on the silicon substrate and covers the first notch and the second notch. The metal seed layer covers an insulating layer positioned on the first notch. The circuit layer covers a metal seed layer positioned on the first notch. The chip is positioned at the second notch, where the upper surface of the chip is lower than the circuit layer, and the chip is electrically connected to the circuit layer through a plurality of leads. The molding material encapsulates the insulating layer, metal seed layer, circuit layer, chip, and lead. The molding material and the circuit layer are substantially aligned with each other. At least the metal pads are disposed on the circuit layer and are exposed by the molding material.

  In accordance with an embodiment of the present invention, the circuit layer includes a first metal layer and a second metal layer. The first metal layer covers the metal seed layer and the second metal layer covers the first metal layer.

  Based on the above, the silicon substrate formed by executing the semiconductor process of the present invention has a stepped structure. Therefore, when the chip is placed in the second notch of the stepped structure, the chip is electrically connected to the silicon substrate through the execution of a wire bonding process, and the chip is encapsulated to form a package structure with the molding material Is done. The silicon substrate and chip are then thinned so that the chip package structure can have a reduced thickness.

  In order to make the above and other features and advantages of the present invention more comprehensible, specific examples accompanied with figures are described in detail below.

  The accompanying drawings constitute a part of this specification and are incorporated herein to provide a further understanding of the invention. Here, the drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. 1 is a schematic cross-sectional view illustrating a semiconductor process according to an embodiment of the invention. FIG. 2 is a schematic cross-sectional view of performing a packaging process on a chip with use of a silicon substrate formed by application of a semiconductor process depicted in FIG. 1P. FIG. 2 is a schematic cross-sectional view of performing a packaging process on a chip with use of a silicon substrate formed by application of a semiconductor process depicted in FIG. 1P. FIG. 2 is a schematic cross-sectional view of performing a packaging process on a chip with use of a silicon substrate formed by application of a semiconductor process depicted in FIG. 1P. FIG. 2 is a schematic cross-sectional view of performing a packaging process on a chip with use of a silicon substrate formed by application of a semiconductor process depicted in FIG. 1P. FIG. 2 is a schematic cross-sectional view of performing a packaging process on a chip with use of a silicon substrate formed by application of a semiconductor process depicted in FIG. 1P. FIG. 2 is a schematic cross-sectional view of performing a packaging process on a chip with use of a silicon substrate formed by application of a semiconductor process depicted in FIG. 1P. FIG. 2 is a schematic cross-sectional view of performing a packaging process on a chip with use of a silicon substrate formed by application of a semiconductor process depicted in FIG. 1P. FIG. 2G is a schematic plan view of the chip package structure depicted in FIG. 2G.

  DESCRIPTION OF EMBODIMENTS FIGS. 1A through 1P are schematic cross-sectional views illustrating a semiconductor process according to an embodiment of the present invention. Referring to FIG. 1A, in the semiconductor process of this example, a silicon substrate 110 is first provided, and a first insulating layer 120 is formed on the silicon substrate 110. In this specific example, the material of the first insulating layer 120 includes silicon oxide and silicon nitride.

  Referring to FIG. 1B, a first patterned photoresist mask 130 a is then formed on the first insulating layer 120. Next, at least a stepped structure 140 (shown in FIG. 1L) is formed on the silicon substrate 110. Specifically, referring to FIGS. 1C and 1D, at least the stepped structure 140 is formed, and a portion of the first insulating layer 120 exposed by the first patterned photoresist mask 130a is etched into the first patterned photoresist mask 130a. First, the patterned first insulating layer 120a is formed by etching. Next, the first patterned photoresist mask 130a is removed to expose the patterned first insulating layer 120a positioned under the first patterned photoresist mask 130a. Thereafter, referring to FIG. 1E, a first notch 142 having at least a first depth d1 is formed on the silicon substrate 110 by exposing the silicon substrate 110 exposed by the patterned first insulation layer 120a to the patterned first insulation layer 120a. It is formed by etching with use as an etching mask. In FIG. 1E, only two first notches 142 are schematically illustrated. In this example, the silicon substrate 110 exposed by the patterned first insulating layer 120a is obtained by performing a wet etching process with the use of potassium hydroxide (KOH) as an etchant. Etch.

  Thereafter, referring to FIG. 1F, the patterned first insulating layer 120a is removed to expose the silicon substrate 110. Referring to FIG. 1G, a second insulating layer 150 is then formed at the first notch 142 and covers the first notch 142. According to this example, the material of the second insulating layer 150 is substantially the same as the material of the first insulating layer 120, for example, silicon nitride or silicon oxide. In addition, the second insulating layer 150 is formed in substantially the same manner as the first insulating layer 120.

  Referring to FIG. 1H, a second patterned photoresist mask 130 b is then formed on the second insulating layer 150. As shown in FIGS. 1I and 1J, the second insulating layer 150 exposed by the second patterned photoresist mask 130b is first used as an etching mask for the second patterned photoresist mask 130b. Etching is performed to form the insulating layer 150a. Next, the second patterned photoresist mask 130b is removed to expose the patterned second insulating layer 150a positioned under the second patterned photoresist mask 130b. Referring to FIGS. 1K and 1L, at least a second notch 144 having a second depth d2 is formed on the silicon substrate 110, and the silicon substrate 110 exposed by the patterned second insulation layer 150a is patterned to the second insulation layer. It is formed by etching with the use of 150a as an etching mask. In FIG. 1K, only two second notches 144 are schematically illustrated. Thereafter, the patterned second insulating layer 150a is removed and a stepped structure is formed.

  In particular, in this example, the second notches 144 are each connected to the first notches 142, and the first depth d1 is shallower than the second depth d2. In addition, the diameters of the first notches 142 are each longer than the diameter of the second notches 144. In other words, compared to the first notch 142, the second notch 144 has a relatively small diameter and rather deep depth. In this example, the method of etching the second insulating layer 150 underlying the second insulating layer 150 and the silicon substrate 110 exposed by the second patterned photoresist mask 130b is the first patterned photoresist mask 130a. Is the same as that for etching the first insulating layer 120 and the first insulating layer 120 under which the silicon substrate 110 is exposed, i.e. by performing with the use of KOH as a corrosive in a wet etching process.

  Referring to FIG. 1L, in this specific example, the second insulating layer 150 is removed so as to form at least the stepped structure 140. In FIG. 1L, only two stepped structures 140 are drawn. Here, the method of etching the first insulating layer 120 and the second insulating layer 150 is, for example, performing a wet etching process. Thereby, the step-like structure 140 is sufficiently formed on the silicon substrate 110.

Referring to FIG. 1M, a final insulating layer 160 is then formed on the stepped structure. here,
The final insulating layer 160 covers the first notch 142 and the second notch 144 so as to insulate the silicon substrate 110. In this specific example, the material of the final insulating layer 160 includes silicon oxide, and the final insulating layer 160 is formed by heating the silicon substrate 110 to oxidize the surface of the silicon substrate 110. To do. The oxidized portion of the silicon substrate 110 is a so-called final insulating layer 160.

  Thereafter, a metal seed layer 170 is formed on the final insulating layer 160, as indicated in FIG. 1N. In accordance with this example, the metal seed layer 170 is, for example, a titanium-nickel (Ti / Ni) composite layer, and methods for forming the metal seed layer 170 include sputtering or physical vapor deposition (physical vapor deposition). Law) (PVD).

  Referring to FIG. 1O, a patterned photoresist layer 180 is formed on the metal seed layer 170. Here, the patterned photoresist layer 180 covers portions of the metal seed layer 170 where the circuit layer 190 is not formed and the patterned photoresist layer 180 exposes other portions of the metal seed layer 170 where A circuit layer 190 is formed. Thereafter, the circuit layer 190 is formed to cover the exposed portion of the metal seed layer 170. Here, the circuit layer 190 includes a first metal layer 192 and a second metal layer 194. In this specific example, the first metal layer 192 is, for example, a Ni layer, and the second metal layer 194 is, for example, an Au (gold) layer.

  Next, as shown in FIG. 1P, the patterned insulating layer 180 and the coated portion of the metal seed layer 170 disposed under the patterned photoresist layer 180 are positioned on the second notch 144 as a final insulating layer. The portion 160 is removed so as to be exposed. In this example, the patterned photoresist layer 180 is removed, for example, by using a solvent that dissolves the patterned photoresist layer. In addition, the coated portion of the metal seed layer 170 disposed under the patterned photoresist layer 180 is removed, for example, by performing an etching process. Up to now, the silicon substrate 100 is sufficiently formed on the silicon substrate 110 by performing the semiconductor process of this example.

  Briefly, the silicon substrate 100 of this example is formed by performing a semiconductor process. A patterned first insulating layer 120a and a patterned second insulating layer 150a are formed, which involves an etching process involving the use of the first patterned photoresist mask 130a and the second patterned photoresist mask 130b as an etching mask. To execute on. The staircase structure 140 includes a first notch 142 having a first depth d1 and a second notch 144 having a second depth d2, and then includes a patterned first insulating layer 120a and a patterned second insulating layer 150a. It is formed by using it as an etching mask. Thereafter, the final insulating layer 160, metal seed layer 170, and circuit layer 190 are formed on the silicon substrate 110 so as to form the silicon substrate 100 having the stepped structure 140.

  In addition, in the step-like structure 140 formed in this example, the first depth d1 of the first notch 142 is shallower than the second depth d2 of the second notch 144. Thus, when the silicon substrate 100 serves as a chip carrier (not shown) for wire bonding, the second notch 144 of the stepped structure 140 can accommodate multiple chips and through the implementation of the wire bonding process. The chip can be electrically connected to a circuit layer 190 disposed at the first notch 142. Thereby, the capacity of the silicon substrate 100 and the wire bonding distance between the silicon substrate 100 and the chip can be reduced.

  2A to 2G are schematic cross-sectional views performed with the use of a silicon substrate formed by applying the packaging process to the semiconductor process depicted in FIG. 1P on a chip. FIG. 2H is a schematic plan view of the chip package structure depicted in FIG. 2G. It is noted that some components are omitted in FIG. 2H for purposes of illustration and better understanding. In this example, the silicon substrate 100 formed by performing the semiconductor process is suitable for accommodating the chip 210.

In particular, in subsequent processing of the silicon substrate 100, referring to FIG. 2A, at least the chip 210 is first placed in the second notch 144 of the stepped structure 140. In FIG. 2A, only two chips 210 are schematically depicted. Here, the upper surface 210a of the chip 210 is lower than the second metal layer 194 of the circuit layer 190 at the first notch 142, respectively.

  As shown in FIG. 2B, a wire bonding process is then performed to connect the chip 210 to the second metal layer 194 of the circuit layer 190 through a plurality of conductors 220. Specifically, in this example, chip 210 is electrically connected to second metal layer 194 of circuit layer 190 through conductor 220.

  Referring to FIG. 2C, the stepped structure 140 is filled with a molding material 230 that encapsulates the circuit layer 190, the metal seed layer 170, the final insulating layer 160, the chip 210, and the conductor 220. Next, as indicated in FIG. 2D, a portion of the molding material 230 and a portion of the circuit layer 190 are thinned so that the molding material 230 and the first metal layer 192 are substantially aligned with each other. According to this example, the method of thinning the molding material 230 and the circuit layer 190 includes polishing.

  As shown in FIG. 2E, the back surface of the silicon substrate 110 is exposed for thinning the bottom surface 210b of the chip 210 to meet the requirements for package miniaturization. Here, the method of thinning the silicon substrate 110 includes performing a polishing process or an etching process. Referring to FIG. 2F, at least a metal pad 240 is then formed on the first metal layer 192 of the circuit layer 190 and exposed by the molding material 230. In FIG. 2F, only four metal pads 240 are schematically depicted. Here, the method of forming the metal pad 240 is, for example, electroless plating. According to a specific example, the thickness of each of the metal pads 240 is approximately 0.1 μm. 2G and 2H, a cutting process (thermal cutting) is then performed to cut and separate the silicon substrate 100 along a predetermined path with the use of a cutting tool. Thereby, a plurality of individual chip package structures 200 can be formed. In FIG. 2G, only two chip package structures 200 are schematically illustrated.

  Briefly, according to the manufacturing process of the chip package structure 200 in this example, the silicon substrate 100 formed by performing a semiconductor process serves as a carrier for the chip 210, and the chip 210 is attached to the circuit layer 190 to the silicon substrate 110. Electrical connection through wire bonding above. Further, the molding process is performed to form the chip package structure 200 in order to seal the chip 210 in the molding material 230. Each of the chips 210 is disposed at the second notch 144 of the stepped structure 140, and thus the chip package structure 200 constituted by the silicon substrate 100 and the chip 210 has a reduced thickness.

  Based on the above, in the silicon substrate formed by performing the semiconductor process of the present invention, the first depth of the first notch is shallower than the second depth of the second notch in the stepped structure. In addition, the diameter of the first notch is longer than the diameter of the second notch. Here, when the chip is electrically connected to form a chip package structure through wire bonding to the silicon substrate, the silicon substrate and the back of the chip are simultaneously polished to reduce the size of the chip package structure. . As such, the chip package structure can have a reduced thickness. In conclusion, the thickness of the package can be effectively reduced according to the present invention.

  It will be apparent to those skilled in the art that various modifications and variations can be made to the structure according to the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they come within the scope of the following claims and their equivalents.

Claims (8)

A semiconductor process comprising: providing a silicon substrate;
Partially exposing the surface of the silicon substrate and forming at least a stepped structure on the silicon substrate by etching the surface of the silicon substrate, wherein the stepped structure has a first depth. Having a first notch having a second notch having a second depth, the first depth being shallower than the second depth, and the diameter of the first notch being longer than the diameter of the second notch;
Forming a final insulating layer on the stepped structure and forming a metal seed layer on the final insulating layer;
Forming a patterned photoresist layer on the metal seed layer, wherein the patterned photoresist layer covers a portion of the metal seed layer where the circuit layer is not formed, and the patterned photoresist layer is a metal on which the circuit layer is formed Exposing other portions of the seed layer;
Forming a circuit layer overlying the exposed portion of the metal seed layer; and removing the patterned photoresist layer and the covered portion of the metal seed layer disposed under the patterned photoresist layer. . The step of forming at least the step-like structure is the following, that is, the step of forming the first insulating layer on the silicon substrate,
Forming a first patterned photoresist mask on the first insulating layer;
Etching a portion of the first insulating layer exposed by the first patterned photoresist mask with use of the first patterned photoresist mask as an etching mask, and forming a patterned first insulating layer;
Removing the first patterned photoresist mask;
Forming a first notch having a first depth on a silicon substrate by etching the silicon substrate exposed by the patterned first insulating layer with use of the patterned first insulating layer as an etching mask; ,
Removing the patterned first insulating layer;
Forming a second insulating layer in the first notch and a second insulating layer covering the first notch;
Forming a second patterned photoresist mask on the second insulating layer;
Etching a portion of the second insulating layer exposed by the second patterned photoresist mask with use of the second patterned photoresist mask as an etching mask, and forming a patterned second insulating layer;
Removing the second patterned photoresist mask;
Forming a second notch having a second depth by etching a silicon substrate exposed by the patterned second insulating layer with use of the patterned second insulating layer as an etching mask; and The semiconductor process of claim 1, comprising removing two insulating layers and forming a stepped structure.   The circuit layer includes a first metal layer and a second metal layer, the first metal layer covers an exposed portion of the metal seed layer positioned on the first notch, and the second metal layer is the first metal layer. The semiconductor process according to claim 1, wherein the semiconductor process is covered. After removing the covered portion of the patterned photoresist layer and the metal seed layer located under the patterned photoresist layer, the next step is to place at least the chip in the second notch, where the chip's The upper surface is lower than the second metal layer of the circuit layer positioned at the first notch;
Performing a wire bonding process to connect the chip to the second metal layer of the circuit layer through a plurality of conductors;
Filling the stepped structure with a molding material, wherein the molding material encapsulates the final insulating layer, circuit layer, metal seed layer, chip, and a plurality of conductors;
Thinning a portion of the molding material and a portion of the circuit layer such that the molding material and the first metal layer are substantially aligned with each other, thinning the silicon substrate and the chip, and exposing a lower surface of the chip; 4. The semiconductor process according to claim 3, comprising the step of forming at least a metal pad on the first metal layer of the circuit layer.   A silicon substrate formed by applying a semiconductor process according to claim 1, wherein the final insulating layer covers the stepped structure and the circuit layer is exposed of a metal seed layer positioned on the first notch. A silicon substrate that covers the surface and the second notch accommodates the chip.   The silicon substrate according to claim 5, wherein the chip is electrically connected to the circuit layer through a plurality of conductive wires. A chip package structure comprising: a silicon substrate with a stepped structure, wherein the stepped structure includes a first notch having a first depth and a second notch having a second depth. The first depth is less than the second depth, and the diameter of the first notch is longer than the diameter of the second notch,
An insulating layer that is disposed on the silicon substrate and covers the first and second notches;
A metal seed layer covering an insulating layer positioned on the first notch;
A circuit layer covering a metal seed layer positioned on the first notch;
A chip, disposed at the second notch, wherein the upper surface of the chip is lower than the circuit layer, and the chip is electrically connected to the circuit layer through a plurality of conductors;
A molding material that encapsulates an insulating layer, a metal seed layer, a circuit layer, a chip, and a plurality of wires, wherein the molding material and the circuit layer are substantially aligned with each other, and at least a metal pad on the circuit layer A chip package structure comprising: a chip package structure disposed on the substrate and exposed by the molding material.   The chip package structure according to claim 7, wherein the circuit layer includes a first metal layer and a second metal layer, the first metal layer covers the metal seed layer, and the second metal layer covers the first metal layer.

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