JP3320932B2 - Chip package mount, circuit board on which chip package is mounted, and method of forming circuit board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip package mounted body having a chip package mounted on a circuit board, a circuit board on which the chip package is mounted, and a method of forming the circuit board.

[0002]

2. Description of the Related Art In recent years, the degree of integration of LSI has been remarkably improved.
Accordingly, the number of pins of the package of the LSI chip has also increased. Further, there is a strong demand for downsizing and thinning of electronic devices on which LSI chip packages are mounted. For this reason, development of a high-density mounting technology for mounting an LSI chip on a circuit board with high density has been promoted.
Various shapes and structures have been proposed for I-chip packages (Nikkei Electronics 8-2, 1993 n-2
o.587, “Pushing for High-density Packaging at the Front Line of LSI Packages”, pp. 93-99).

[0003] In the following description, a substrate provided with terminal electrodes connected to the electrodes of an LSI chip and contact electrodes connected to a circuit board is called a "chip carrier". The one on which is mounted is referred to as a “chip package”. Then, such a chip package is mounted on a circuit board.

Hereinafter, a conventional mounting of a chip package on a circuit board will be briefly described.

[0005] First, via holes are formed on a printed board or a ceramic board having terminal electrodes formed on both sides by laser or die punching. Thereafter, the substrate internal conductor and the terminal electrode are electrically connected by plating or the like. After bonding the face-up LSI chip to the upper surface of the chip carrier by die bonding, the electrode pads of the LSI chip and the terminal electrodes on the upper surface of the chip carrier are connected by bonding wires. Next, sealing with a mold resin is performed so as to cover the LSI chip and the bonding wires, thereby obtaining a chip package.

Next, after solder is fixed on the terminal electrodes on the lower surface of the printed circuit board (the surface facing the circuit board) by printing or the like, the solder is melted by infrared reflow or the like.
It is formed into a solder ball (about 700 μm in diameter). Alternatively, there is a method in which a solder ball prepared in advance is bonded to a terminal electrode of a chip carrier with a flux or the like.

Further, after positioning the chip package so that the solder balls of the chip package are aligned with predetermined positions of the terminal electrodes of the circuit board, the chip package is mounted on the circuit board. Thereafter, the solder balls are melted by infrared reflow or the like, and the terminal electrodes on the lower surface of the chip package are joined to the terminal electrodes on the circuit board. Thus, a chip package mounted body is obtained.

[0008]

However, the above-described conventional chip package and chip package mounting body have the following problems.

1. Since the connection between the terminal electrode of the chip carrier and the electrode pad of the LSI chip is performed by wire bonding, the chip carrier area is larger than the LSI chip area only at the wire bonding connection portion. In addition, since the encapsulation is performed with the mold resin after the wire bonding connection, the thickness of the chip package is increased by the bonding wires to a level higher than the loop height of the bonding wires. This hinders the miniaturization and thinning of the chip package.

[0010] 2. Input and output signal delays occur because signals are transmitted by relatively long bonding wires.
For this reason, the high-frequency characteristics deteriorate, and noise is picked up.

3. The spherical solder balls arranged in an array on the lower surface of the chip package make it difficult to reduce the pitch of the terminals. The arrangement pitch of the solder balls is typically about 1 mm.

4. The size of the solder ball determines the distance between the chip package and the circuit board. Therefore, the distance between the chip package and the circuit board cannot be made smaller than the size of the solder ball.

5. If the material of the substrate of the chip carrier and the material of the circuit board are different, stress is concentrated on the solder joint due to thermal shock, cracks (cracks) are likely to occur, and the electric resistance of the solder joint is reduced due to the cracks. Increase.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a chip package mounted body suitable for miniaturization and thinning, which has excellent high-frequency characteristics, An object of the present invention is to provide a circuit board suitable for a chip package that is connected stably to a substrate and a method of forming the same, and a chip package mounting body in which the chip package is mounted on a circuit board.

[0015]

According to a first aspect of the present invention, there is provided a chip package mounted body in which a chip package is mounted on a circuit board. Has a chip carrier and an LSI chip, the chip carrier has an upper surface and a lower surface, and is formed on a carrier substrate including an internal conductor and an upper surface of the carrier substrate, and electrically connects the LSI chip to the internal conductor. A plurality of terminal electrodes, and a plurality of contact electrodes formed on the lower surface of the carrier substrate, the plurality of contact electrodes electrically connecting the circuit board to the internal conductor, the plurality of contact electrodes are formed by a conductive adhesive, the carrier The circuit board is embedded in a plurality of recesses provided on the lower surface of the board, and the circuit board is connected to a contact electrode of the chip carrier. Comprises a terminal electrode of the protrusion shape, the terminal electrodes of the two-stage projection shape is characterized in that protrudes into the recess of the carrier substrate.

Further, according to a second aspect of the present invention, there is provided the chip package mounted body according to the first aspect, wherein an electrode pad provided on the LSI chip and a protruding electrode formed on the electrode pad are provided. Wherein the protruding electrode is electrically connected to a terminal electrode of the chip carrier via a bonding layer, and a gap between the LSI chip and the chip carrier is filled and sealed with a mold resin. And

According to a third aspect of the present invention, there is provided a circuit board on which a chip package is mounted, wherein, in a terminal electrode formed on the circuit board, a lower portion and an upper portion formed on the lower portion are provided. And a terminal electrode having a two-stage protrusion shape having a portion.

Further, in the circuit board according to a fourth aspect of the present invention, in the circuit board according to the third aspect, the terminal electrode having a two-stage projection has a cross-sectional area in a plane parallel to a chip package mounting surface of the circuit board in the upper stage. However, it is characterized in that its cross-sectional area in a plane parallel to the chip package mounting surface in the lower part is smaller.

According to a fifth aspect of the present invention, a first resist film having a first opening is formed on an electrode pad of a circuit board by a first photolithography step. Forming a lower step of the terminal electrode in the first opening of the first resist film;
Forming a second resist film having a second opening smaller than the first opening of the first resist film and located on a lower step of the terminal electrode on the circuit substrate by a second photolithography step; Performing a step of forming an upper step portion of the terminal electrode in the second opening of the second resist film; removing the first resist film and the second resist film to expose the terminal electrode; Forming a terminal electrode having a stepped shape.

[0020]

According to the chip carrier package of the present invention, LS
A terminal electrode for mounting the I-chip on a flip-chip is provided on the upper surface of the carrier substrate, and a lower surface of the carrier substrate is provided with a contact electrode for connecting to an electrode on the circuit substrate; The LSI chip and the circuit on the circuit board are connected via a chip carrier in which the contact electrodes are connected in a circuit manner by internal conductors provided in the carrier board, and the LSI chip and the circuit on the circuit board are compactly connected. . That is, the electric signal propagates along a relatively short path between the LSI chip and the circuit board, and the resistance component and the parasitic capacitance are reduced, so that the high-frequency characteristics are improved.

Further, the carrier substrate and the circuit board are mechanically bonded to each other by a conductive adhesive embedded in the concave portion on the lower surface of the carrier substrate, and the inner conductor of the carrier substrate and the terminal electrode of the circuit board are electrically connected. Connecting. In addition, since the contact electrode is formed from the conductive adhesive, the connection with the circuit board is stabilized and the reliability is improved, and particularly, a connection resistant to thermal shock is obtained. In addition, the contact electrodes located in the recesses on the lower surface of the carrier substrate are connected to the contact electrodes of the circuit substrate.
By inserting the step-shaped terminal electrode, the gap between the carrier substrate and the circuit substrate is reduced, and the height of the mounted chip package is suppressed.

Further, according to the circuit board of the present invention, since the terminal electrode has a two-step projection shape, the terminal electrode can be easily inserted into the contact electrode in the concave portion of the chip carrier, and mechanically. And an electrically stable connection is obtained.

Further, according to the method for forming a circuit board having terminal electrodes of the present invention, fine projection electrodes having a two-step projection shape can be easily formed with high yield by employing photolithography technology.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view schematically showing a chip package as a first reference example for explaining an embodiment of the present invention. The chip package 19 of the first reference example includes the chip carrier 12 and the LSI chip 7 mounted on the chip carrier 12 by flip chip mounting.

The LSI chip 7 includes a plurality of electrode pads 8
And a protruding electrode 11 formed on each electrode pad 8. Known LSI chips 7 can be used as appropriate. The size of the LSI chip used in the first reference example is typically 10 mm × 10 mm × 0.5 mm. The electrode pads 8 and the protruding electrodes 11 are provided in a region near the periphery of the lower surface of the LSI chip 7 and are used for connecting wiring of an integrated circuit formed on the LSI chip 7 to an external circuit. The arrangement pitch of the protruding electrodes 11 is currently from 0.200 mm to 0.1
It is about 20 mm and tends to become smaller in the future. The protruding electrode 11 is electrically connected to the terminal electrode 6 of the chip carrier 12 via a conductive adhesive 9 as a bonding layer. The protruding electrode 11 is connected to the terminal electrode 6 of the chip carrier 12.
It is preferable to have a two-step projection shape in order to perform stable connection with the substrate. The bonding layer may be formed of an anisotropic conductive material or solder instead of the conductive adhesive. The gap between the LSI chip 7 and the chip carrier 12 is filled and sealed with a mold resin 10.

FIG. 3 is a sectional view schematically showing a chip carrier in the chip package of the first reference example. The details of the chip carrier 12 in the chip package 19 will be described with reference to FIG. The chip carrier 12 is a multilayer ceramic substrate including internal conductors.
bstrate) as a carrier substrate. A plurality of terminal electrodes 6 for electrically connecting the protruding electrodes 11 of the LSI chip 7 to internal conductors are provided on the upper surface of the carrier substrate 1.
Are formed. On the other hand, on the lower surface of the carrier substrate 1,
A plurality of recesses for electrically connecting electrodes of a circuit board, which will be described later, to internal conductors are formed. The depth of this recess is
It is about 20 μm to 100 μm, and the inner diameter is about 200 μm.
A plurality of contact electrodes 5 that are in contact with the electrodes on the circuit board are embedded in the recess. In the first reference example, the contact electrode 5 is 10 μm to 2 μm from the lower surface of the carrier substrate 1.
It protrudes by about 0 μm. However, when the electrodes of the circuit board have a two-step projection shape as described later, it is not necessary to make the contact electrodes 5 protrude from the lower surface of the carrier substrate 1.

The contact electrode 5 and the terminal electrode 6 are interconnected in a circuit manner via an internal conductor. as a result,
The electrical connection between the LSI chip 7 of FIG. 1 and the circuit of the circuit board is achieved without any intervening bonding wires, and excellent high-frequency characteristics can be obtained. In the case of the first reference example,
The internal conductor of the carrier substrate 1 is formed from vias 3 buried in the via holes 2 of the carrier substrate 1 and the wiring 4 inside the substrate. The internal conductor electrically connects the terminal electrodes 6 arranged at a relatively small pitch on the periphery of the upper surface of the carrier substrate 1 to the contact electrodes 5 arranged at a relatively large pitch on the lower surface of the carrier substrate 1. It fulfills the function of doing. The electrode pads 8 of the LSI chip 7 are located in a region near the periphery of the lower surface of the chip, so that the position of the terminal electrodes 6 on the chip carrier 12 is also limited to a region near the periphery of the upper surface of the carrier substrate 1. On the other hand, the arrangement position of the contact electrode 5 is
The arrangement pitch of the contact electrodes 5 can be increased by arranging the contact electrodes 5 by effectively utilizing the entire lower surface of the carrier substrate 1 without being limited to the vicinity of the periphery of the lower surface of the carrier substrate 1. If the arrangement pitch is increased, short-circuiting between adjacent contact electrodes 5 can be easily suppressed. If the arrangement pitch is increased, the size of the contact electrode 5 can be increased. As a result, highly reliable electrical and mechanical connection between the contact electrode 5 and the circuit board is ensured. In the first reference example, the minimum arrangement pitch of the contact electrodes 5 is about 400 μm. Note that a circuit element such as a resistor or a capacitor may be provided on a part of the substrate inner layer wiring 4.

In the chip package 19 of the first reference example, the LSI chip 7 is mounted on the chip carrier 12 as described below. First, after a bump electrode 11 having a two-step Au shape is formed on the electrode pad 8 of the LSI chip 7 by a ball bonding method, the conductive adhesive 9 is transferred to the tip thereof. Next, after aligning the position of the protruding electrode 11 with the terminal electrode 6 of the chip carrier 12, the LSI
The chip 7 is placed on the chip carrier 12, and the conductive adhesive 9 is cured by heat. Next, the gap between the LSI chip 7 and the chip carrier 12 is filled with the mold resin 10, and the mold resin 10 is thermally cured. The bump electrodes 11 formed on the LSI chip 7 may have a structure suitable for flip-chip mounting, such as a plated Au bump, a plated solder bump, or a solder ball bump.

One of the important features of the chip package 19 of the first reference example is that the contact electrode 5 of the chip carrier 12 is formed by a conductive adhesive embedded in a concave portion of the carrier substrate 1. As the conductive adhesive, for example, a polymer conductive adhesive (product number 8250) manufactured by Ave Stick Co., Ltd. is used. Since the contact electrode 5 is formed of the conductive adhesive embedded in the concave portion, the following effects are produced.

The gap between the chip package 19 and the circuit board is significantly reduced as compared with an electrode such as a solder ball. Further, connection with the protruding electrodes of the circuit board is facilitated.
If the projecting electrodes of the circuit board are inserted into the contact electrodes 5 of the chip package 19, it is possible to prevent the conductive adhesive from rising and short-circuiting between adjacent projecting electrodes.
In addition, since the contact area between the protruding electrode of the circuit board and the conductive adhesive is large, a large adhesive strength is secured and reliability is improved. In particular, when the conductive adhesive has flexibility, cracks are less likely to occur in the contact electrode 5 even when subjected to thermal shock, and an increase in resistance due to the cracks can be prevented.

FIG. 2 is a sectional view schematically showing a chip package according to a second reference example, and FIG. 4 is a sectional view schematically showing a chip carrier in the chip package according to the second reference example. The members corresponding to those described above are denoted by the same reference numerals and description thereof will be omitted. Second
In the chip package 20 of the reference example, the one in which the contact electrode 5 and the terminal electrode 6 were directly electrically connected by the via 3 as shown in FIG. Then, the chip package 20 is mounted on the carrier substrate 22 in the same manner as in the first embodiment.
The SI chip 7 is mounted with a flip-flop. The carrier substrate 22 is not provided with the substrate inner layer wiring, but is provided with a lead line (not shown) extending from the terminal electrode 6 on the upper surface of the carrier substrate 22 so that a position different from the position of the terminal electrode 6 is provided. Can be provided with via holes 2 and vias 3. Therefore, in the case of the chip carrier 21, the degree of freedom in design is reduced as compared with the chip carrier 12 shown in FIG. 3, but the arrangement pattern of the contact electrodes 5 and the arrangement pattern of the terminal electrodes 6 can be made different.

FIG. 5 is a process sectional view for explaining a method of manufacturing a chip carrier, and FIGS. 5A to 5I show states of the chip carrier in different manufacturing steps.

When manufacturing the chip carrier 12 shown in FIG. 3, first, as shown in FIG. 5 (a), a plurality of ceramic green sheets 1a and 1b before firing are formed in the via holes 2a by laser or die punching. And 2b. When forming the carrier substrate 1, the via holes 2a
And 2b are different for each ceramic green sheet 1a and 1b.
In order to simplify the description, via holes 2a and 2b are all shown at the same position.

As the ceramic green sheets 1a and 1b, for example, glass ceramic green sheets (MLS-1000 main component) manufactured by NEC Corporation are used. In order to form one carrier substrate 1, for example, ceramic green sheets 1a and 1b having a thickness of about 200 μm are
Laminate about 10 sheets. Even if the thickness of each ceramic green sheet 1a or 1b is 200 μm before firing,
Since the carrier substrate 1 contracts to about μm, the final thickness of the carrier substrate 1 becomes about 0.7 mm to 1.5 mm. In order to reduce the thickness of the chip package 19 by reducing the thickness of the chip carrier 12, it is preferable that the carrier substrate 1 be thin.

Next, as shown in FIG. 5B, a conductive material is embedded in the via hole 2a of the ceramic green sheet 1a by printing to form a via 3a, and then as shown in FIG. 5F. The substrate inner layer wiring 4 is formed by printing. Thus, the components of the inner conductor are formed.
As a material for the internal conductor, for example, a CuO paste is used.

After laminating a plurality of other ceramic green sheets 1a on a ceramic green sheet 1b having no via 3a formed in the via hole 2b, these laminated structures are pressed while heating. Next, FIG.
As shown in (2), the laminated ceramic green sheets 1a and 1b are fired to form a carrier substrate 1 having a plurality of concave portions formed on the lower surface. The recess is formed in the via 3a of the lowermost ceramic green sheet 1b of the carrier substrate 1.
Is formed by the unfilled via hole 2b. In addition, as the manufacturing method of the carrier substrate 1 so far, another conventional manufacturing method may be used.

After the firing, the terminal electrodes 6 are formed on the upper surface of the carrier substrate 1 as shown in FIG. Next, as shown in FIG.
The print mask 14 is set on the surface facing the circuit board, and the conductive adhesive is printed through the print mask 14 on the plurality of recesses formed by the via holes 2b. At this time, a conductive adhesive is printed on the via hole 2b using the squeegee 13. Thus, the conductive adhesive is buried in the via hole 2b of the carrier substrate 1, whereby the contact electrode 5 is formed. It is preferable to use a flexible adhesive as the conductive adhesive. The conductive adhesive forming the contact electrode 5 contains conductive particles, and the conductive particles are AgPd, A
It is preferable to be formed from any of u, Ag, Cu and their composite alloy powder.

The contact electrode 5 embedded in the via hole 2 b may or may not project from the carrier substrate 1.
If it does not project from the carrier board, the electrode on the circuit board needs to have a projecting shape that can be inserted into the via hole 2b of the carrier board 1.

The carrier substrate 1 is replaced with the above-mentioned FIG.
When formed by the method shown in (b), (f), (g), (h) and (i), the size (length) of the contact electrode 5 in the direction perpendicular to the lower surface of the carrier substrate 1 is 1 is determined depending on the thickness of the lowermost ceramic green sheet 1b. For example, when the fired thickness of the ceramic green sheet 1b is 150 μm, the length of the contact electrode 5 is 150 μm.
It is regulated to about 170 μm. When the length of the contact electrode 5 is increased, the relatively large electric resistance component of the contact electrode 5 cannot be ignored. For this reason,
The length of the contact electrode 5 is preferably about 200 μm or less.

When the inner conductor is non-metal,
Before filling the via holes 2b of the ceramic green sheet 1b with the conductive adhesive, the sidewalls in the unfilled via holes 2b may be plated with a non-oxidizing conductor such as Au. According to this plating, the electrical contact area between the conductive adhesive and the internal conductor increases, so that the contact electrode 5
Electrical resistance between the wire and the internal conductor can be reduced.

The step of forming the contact electrode 5 may be before or after the LSI chip 7 is mounted on the terminal electrode 6 of the carrier substrate 1. It is conceivable that the chip package 19 in which the LSI chip 7 is mounted and the contact electrode 5 is not formed is sold to the user. In that case, the chip package
Before mounting the circuit board 19 on the circuit board, the contact electrode 5 is buried in the via hole 2b on the lower surface of the carrier substrate 1. Note that the material of the carrier substrate 1 may be alumina having good heat dissipation properties, other than glass ceramic.

In the case of manufacturing the chip carrier 21 shown in FIG.
And 2b are common to all of the ceramic green sheets 1a and 1b, and the formation of the wiring 4 in the substrate is omitted, so that the steps shown in FIGS. Is performed to form the carrier substrate 22. Here, the steps shown in FIGS. 5C to 5E correspond to the steps shown in FIG.
To (i).

FIG. 6 is a cross-sectional view schematically showing a first embodiment of a circuit board provided with terminal electrodes according to the present invention. This circuit board includes a chip package 19 shown in FIG. 1 or a chip package shown in FIG. 20 has an electrode structure suitable for mounting. The circuit board 30 has a terminal electrode 31 having a two-stage protrusion shape.
It has. The terminal electrodes 31 are connected to the carrier substrates 1 and 22
This is preferably used when the contact electrode 5 does not substantially protrude from the lower surfaces of the carrier substrates 1 and 22.

In the circuit board 30, the chip package 19,
An electrode pad 32 is formed on the mounting surface 30 a facing the surface 20, and a terminal electrode 31 having a two-step projection is formed on the electrode pad 32. This terminal electrode 31 is an electrode pad
It has a lower portion 31a formed directly on the upper portion 32 and an upper portion 31b formed on the lower portion 31a. The shape of the cross section of the terminal electrode 31 parallel to the mounting surface 30a may be circular or square. Also, the mounting surface 30
The cross-sectional area of the upper portion 31b in a plane parallel to a is the lower portion 31a
Smaller than the cross-sectional area of The terminal electrode 31 having the two-step protrusion shape can be formed of a metal that can be plated, such as Au, Cu, Ag, or solder. The material of the electrode pad 32 is also A
Any material that can be plated, such as u or Cu, may be used. Also,
The circuit board 30 has a laminated structure similarly to the carrier boards 1 and 22, and has via holes 33, vias 34 and board inner layer wirings 35 arranged therein.

FIGS. 7A to 7D are process sectional views for explaining a method of manufacturing a circuit board having terminal electrodes according to the first embodiment of the present invention. FIGS. 7A to 7D show different manufacturing steps. 2 shows the state of the terminal electrode and the resist film.

Next, a method of manufacturing the terminal electrode 31 on the circuit board will be described with reference to FIG. First, as shown in FIG. 7A, a resist film A is formed on the mounting surface 30a of the circuit board 30 by a photolithography process. The resist film A is
Among the plurality of electrode pads 32 on the mounting surface 30a, an opening (inner diameter: about 250 μm) is provided on an electrode pad to be connected to the contact electrode 5 of the chip carrier 12, 21.

Next, as shown in FIG. 7B, a lower portion 31a (thickness: about several tens μm) of the terminal electrode 31 is deposited in the opening of the resist film A. In this manner, the terminal electrode is selectively formed on the area of the circuit board 30 which is not covered with the resist film A.
The lower part 31a of the 31 is formed. The shape and size of the lower portion 31a of the terminal electrode 31 are defined by the shape and size of the opening of the resist film A. The arrangement pattern of the lower portion 31a of the terminal electrode 31 is defined by the arrangement pattern of the openings of the resist film A.

Next, as shown in FIG. 7C, a resist film B is formed on the resist film A by a photolithography process. The resist film B is formed on the lower portion 31 of the terminal electrode 31.
An opening (inner diameter: about 100 μm) is provided near the center of a. This opening is formed smaller than the opening of the resist film A. Next, as shown in FIG. 7D, the upper part 31b (height: about several tens μm) of the terminal electrode 31 is formed by plating.
Is precipitated.

Finally, the resist film A and the resist film B are dissolved or peeled off from the circuit board 30 to expose the terminal electrode 31 having a two-step projection on the electrode pad 32 of the circuit board 30. Cleans the circuit board 30 and the terminal electrodes 31.

In the circuit board 30 of the first embodiment, the terminal electrodes
The plating material for forming 31 is not particularly limited.
Any material that can be plated, such as u, Cu, Ag, and solder, may be used.

FIG. 8 is a cross-sectional view schematically showing a chip package mounted body according to the second embodiment of the present invention. The chip package mounted body according to the second embodiment has a chip package 19 shown in FIG. It is mounted on a circuit board 30.

Next, a method of mounting the chip package 19 on the circuit board 30 of the present invention and a chip package mounted body of the second embodiment will be described with reference to FIG. Chip package 19
After the contact electrodes 5 are formed by using a conductive adhesive, alignment is performed so that the position of each contact electrode 5 matches the position of the corresponding terminal electrode 31 on the circuit board 30.
The circuit board 30 used here includes the via holes 33, the vias 34, and the substrate inner layer electrodes 35 as described above.

After that, the upper part 3 of the terminal electrode 31 is inserted into the via hole 2b, which is a recess in which the contact electrode 5 is embedded.
Insert 1b. Next, the contact electrode 5 made of a conductive adhesive is cured at 50 to 150 ° C. In this way, the contact electrode 5 and the terminal electrode 31 are electrically and mechanically joined, and the chip package 19 is mounted on the circuit board 30. The chip package mounted body mounted as described above has the following effects.

Contact electrode 5 and terminal electrode of circuit board 30
Since the connection with the contact electrode 31 is strong, the contact electrode 5
And the terminal electrode 31 are mechanically and electrically stably connected. Further, the thermal expansion coefficient of the circuit board 30 and the carrier board 1
Cracks are unlikely to occur on the carrier substrate 1 even if the thermal expansion coefficient of the carrier substrate 1 is different from that of the carrier substrate 1. In particular, by using a flexible conductive adhesive for forming the contact electrode 5, reliability against thermal shock and the like can be improved. Can be made very good. Further, as a result of the distance between the carrier substrate 1 and the circuit substrate 30 being shortened, the thickness of the chip package mounted body can be reduced as a whole.

FIG. 9 is a cross-sectional view schematically showing a chip package mounting body according to the third embodiment of the present invention. A circuit board 40 in this chip package mounting body has terminal electrodes 31 from the circuit board 30 shown in FIG. It is omitted. Third
The chip package mounted body of the embodiment is obtained by mounting the chip package 19 shown in FIG.

Next, a method of mounting the chip package 19 on the circuit board 40 of the present invention and a chip package mounted body of the third embodiment will be described with reference to FIG. In the third embodiment, the contact electrode 5 is directly adhered onto the electrode pad 32 of the circuit board 40, and the contact electrode 5 and the electrode pad 32 are electrically and mechanically joined to each other.
Are mounted on the circuit board 40.

According to the chip package mounted body of the third embodiment, L is equal to that of the chip package mounted body of the second embodiment.
Since the SI chip 7 is flip-chip mounted on the chip carrier 12, the chip package 19 has a small area and a small thickness. Further, since the wiring distance in the chip package is short, very good frequency characteristics can be obtained. Further, since it is not necessary to provide the terminal electrodes 31 on the circuit board 40, the configuration of the circuit board 40 can be simplified, and the overall thickness after mounting the chip package 19 can be reduced.

[0059]

As described above, the chip package mounting body in which the LSI chip is flip-chip mounted on the chip carrier of the present invention is thin from the circuit board, and therefore is most suitable for high-density mounting.

Further, in the circuit board of the present invention, the contact electrode of the chip package is formed of a flexible conductive adhesive, so that the two-step protruding electrode formed on the terminal electrode on the circuit board side is contacted. By inserting and connecting the electrodes, the thickness of the mounted circuit module can be reduced and the wiring distance can be shortened, so that good frequency characteristics can be obtained.

Further, when the two-stage projecting terminal electrode formed on the circuit board is inserted into the contact electrode of the chip package, the terminal electrode is of a convex type, so that the adhesive rises and the space between the adjacent parts is increased. Short-circuit, the probability of contact with the conductive adhesive is high, and the bonding area is large, so that a large bonding strength can be secured and the reliability is improved.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a chip package as a first reference example for explaining an embodiment of the present invention.

FIG. 2 is a cross-sectional view schematically showing a chip package as a second reference example for explaining an embodiment of the present invention.

FIG. 3 is a sectional view schematically showing a chip carrier in a chip package according to a first reference example of the present invention.

FIG. 4 is a sectional view schematically showing a chip carrier in a chip package according to a second reference example of the present invention.

FIG. 5 is a process sectional view for describing the method for manufacturing the chip carrier.

FIG. 6 is a cross-sectional view schematically showing a first embodiment of a circuit board provided with a terminal electrode according to the present invention.

FIG. 7 is a process cross-sectional view for explaining the method for manufacturing the circuit board provided with the terminal electrodes in the first embodiment of the present invention.

FIG. 8 is a sectional view schematically showing a chip package mounted body according to a second embodiment of the present invention.

FIG. 9 is a sectional view schematically showing a chip package mounted body according to a third embodiment of the present invention.

[Explanation of symbols]

1,22: Carrier substrate, 1a, 1b: Ceramic green sheet, 2, 2a, 2b, 33: Via hole, 3,
34 ... via, 4,35 ... substrate inner layer wiring, 5 ... contact electrode, 6,31 ... terminal electrode, 7 ... LSI chip,
8, 32 ... electrode pad, 9 ... conductive adhesive, 10 ... mold resin, 11 ... projecting electrode, 12, 21 ... chip carrier, 19, 20 ... chip package, 30, 40 ... circuit board, 30a ... mounting surface, 31a ... lower part, 31b ... upper part,
A, B: resist film.

──────────────────────────────────────────────────続 き Continued on the front page (31) Priority claim number Japanese Patent Application No. 5-320126 (32) Priority date December 20, 1993 (December 20, 1993) (33) Priority claim country Japan (JP) (56) reference Patent flat 5-74973 (JP, a) JP Akira 63-229842 (JP, a) JP Akira 63-127557 (JP, a) (58 ) investigated the field (Int.Cl. ⁷ , DB name) H01L 23/12 H05K 1/18

Claims (5)

(57) [Claims] A chip package is mounted on a circuit board.
And a chip package mounting body, said chip package, chip carrier and an LSI chip
And a flop, said chip carrier has an upper surface and a lower surface, and the carrier substrate including an inner conductor, formed on the upper surface of the carrier <br/> A substrate, electricity LSI chip to the internal conductor a plurality of terminal electrodes connected to, said formed on the lower surface of the carrier <br/> a substrate, wherein the circuit board inner conductor
Contact and a plurality of contact electrodes electrically connected to the
The plurality of contact electrodes are connected by a conductive adhesive.
Formed on the lower surface of the carrier substrate and embedded in a plurality of recesses provided on the lower surface of the carrier substrate , wherein the circuit substrate is provided with the contact of the chip carrier.
A two-stage projection-shaped terminal electrode connected to the electrode;
The terminal electrode of the two-stage protrusion is provided on the carrier substrate.
Chip package characterized by projecting into a recess
The mounting body . 2. The method according to claim 1, wherein the LSI chip includes an LSI chip.
An electrode pad provided on the electrode pad;
And a projecting electrode formed, wherein the projecting electrode is
Electricity is applied to the terminal electrodes of the chip carrier through a laminated layer.
The LSI chip and the chip carrier
Is filled and sealed with mold resin.
Claim 1, wherein the chip package fruit, characterized in that that
Body . 3. A circuit board on which a chip package is mounted.
Wherein the terminal electrode formed on the circuit board,
A lower portion, and an upper portion formed on the lower portion.
Characterized by having a terminal electrode having a two-step projection shape
Circuit board . 4. A terminal electrode having a two-stage projection shape.
The chip package of the circuit board in the upper part.
The cross-sectional area in a plane parallel to the mounting surface is
Smaller than the cross-sectional area in the plane parallel to the chip package mounting surface
4. The circuit board according to claim 3 , wherein: 5. A first opening on an electrode pad of a circuit board.
A first register strike film having a first photolithographic
Forming a first electrode on the circuit board by a contacting step, and connecting a terminal electrode in the first opening of the first resist film.
Forming a lower portion of the first resist film;
A lower portion of the terminal electrode than the first opening;
Resist film having a second opening located on the portion
By a second photolithography step
Forming the second resist film in the second opening in the second resist film.
Forming an upper portion of the electrode, removing the first resist film and the second resist film
Then, the terminal electrode is exposed to form a two-stage projection-shaped terminal electrode.
Circuit board, characterized in that it includes a step of forming a pole
Formation method .