JP2004342802A - Printed board with bump electrode and manufacturing method thereof - Google Patents

Printed board with bump electrode and manufacturing method thereof Download PDF

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Publication number
JP2004342802A
JP2004342802A JP2003137032A JP2003137032A JP2004342802A JP 2004342802 A JP2004342802 A JP 2004342802A JP 2003137032 A JP2003137032 A JP 2003137032A JP 2003137032 A JP2003137032 A JP 2003137032A JP 2004342802 A JP2004342802 A JP 2004342802A
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circuit board
printed circuit
conductor layer
layer portion
printed
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Naoki Sakota
直樹 迫田
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Sharp Corp
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Sharp Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13609—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed board with a bump electrode by which the miniaturization and an increase in the density of a system-in-package are attained, the reliability is ensured while the productivity is enhanced, the equipment cost is reduced extremely and the manufacturing cost can be reduced, and a manufacturing method for the printed board. <P>SOLUTION: Since a second conductor layer section 25 having the low melting point in first and second conductor layer sections 24 and 25 has a constitution in which the conductor layer section 25 is melted and joined with the printed board 20a, not only the bump electrode 21 can be joined simply with the printed board 20a at a comparatively low heating temperature but also a damage at a time when the bump electrode 21 is joined with the printed board 20a by a heating and a pressing can be reduced, and the reliability of printed board itself is ensured. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、突起電極付きプリント基板およびその製造方法に関し、たとえば携帯電話および携帯情報端末などに好適に用いられる技術に関する。
【０００２】
【従来の技術】
携帯電話および携帯情報端末の急速な普及の原動力の一つとして、機器の飛躍的な小形化がある。その背景には、従来、複数の大規模集積回路（ＬＳＩ：Ｌａｒｇｅ Ｓｃａｌｅ Ｉｎｔｅｇｒａｔｉｏｎ ）で構成されていたシステムおよび機能を、一つの半導体素子に集約するシステムオンチップ（ＳＯＣ：Ｓｙｓｔｅｍ ｏｎ Ｃｈｉｐ）化の技術の進歩がある。その一方で、必要な複数の半導体素子を組合わせて、プリント基板上に直接搭載し、一パッケージ化したシステムインパッケージ（ＳＩＰ：Ｓｙｓｔｅｍ Ｉｎ Ｐａｃｋａｇｅ）が近年、注目を集めている。
【０００３】
近年、携帯電話に代表される携帯情報機器においては、高機能化が進むのに伴って商品サイクルが短くなってきており、携帯情報機器の開発期間を極力短縮することが切望されている。たとえば、携帯電話において一つの機能変更が生じた場合、ＳＯＣにおいては、半導体素子の設計からプロセスまでのすべてに影響を与える変更が必要になるので、その開発に膨大な費用と時間を要するのに対し、ＳＩＰにおいては、一部の半導体素子の種類を変更または追加したり、プリント基板の若干の変更を行うなどによって対応することが可能になるため、ＳＩＰは、ＳＯＣと比べて開発期間の大幅な短縮と開発コストの大幅な低減を図ることができる。
【０００４】
前記ＳＩＰの小形化、高密度化を図るためには、ショート防止を図るためのバンプなどの突起電極が設けられたベアチップ半導体素子を、その能動素子面を下に向けて電気的に接続するいわゆるフェースダウンでもって、プリント基板にフリップチップボンディング法にて実装する手法が有効である。しかし、このＳＩＰは、複数の半導体素子を組合わせて一つのシステムを構成するため、前記複数の半導体素子のうち、自社製以外の他社製半導体素子を搭載しなければならない場合がある。つまり、ＳＩＰにおいて、突起電極が設けられていない他社製半導体素子を必要とする場合には、フリップチップボンディング法以外のたとえばワイヤーボンディング法などの実装手法を用いる必要があり、それ故、半導体素子と、プリント基板の電極部との間の距離が実質的に広がりＳＩＰの小形化に支障をきたす。
【０００５】
従来プリント基板にバンプなどの突起電極を形成したうえで突起電極が設けられていない半導体素子つまりベアチップ半導体素子などを搭載する技術（特許文献１）が開示されている。図６は、前記特許文献１に開示された突起電極付きプリント基板１の製造方法を段階的に示す説明図である。図６（ａ）に示すように、内層導体２を形成してあるプリント基板１に、スルーホールおよびバイヤホールなどの貫通導通穴３を形成する。またプリント基板１の表面部に、外層導体４，５、および電極端子６をメッキ法にて形成する。さらに所定の箇所にソルダーレジスト層７を形成する。
【０００６】
次に、図６（ｂ）に示すように、メッキレジスト８をプリント基板１に形成し、ベアチップ半導体素子１０を接続する電極端子６に、フォト法および炭酸ガスレーザにて微小な穴を開け、その後、メッキ法にて、所定の金属を析出することによって、電極端子６上に突起電極９を形成する。次に、図６（ｃ）に示すように、メッキレジスト７を剥離した後、ベアチップ半導体素子１０を、フリップチップボンディング法にて突起電極９を介してプリント基板１に接続する。
【０００７】
【特許文献１】
特開２０００−２０８９１０号公報
【０００８】
【発明が解決しようとする課題】
前記特許文献１に記載の従来技術では、プリント基板１の表面部の外層導体４，５などの回路を形成するためのメッキプロセスとは別に、突起電極９を形成するための専用のメッキプロセスが必要になるうえ、突起電極９を、たとえば無電解銅メッキを約２０μｍ以上３０μｍ以下積層し、無電解ニッケルメッキを約１０μｍ積層し、さらに無電解金メッキを約０．５μｍ積層して形成するので、メッキプロセスが複雑化する。また、各金属を析出するために多大な処理時間が必要になる。それ故、タクトタイムおよび工数が大きくなり生産性が低くなる。また、メッキプロセスが複雑化する分、その設備費用も高くなり製造コストが高くつく。
【０００９】
したがって本発明の目的は、システムインパッケージの小形化および高密度化を図り、信頼性を確保するとともに、生産性向上を図り、設備費用を極力抑え、製造コストを低減することができる突起電極付きプリント基板およびその製造方法を提供することである。
【００１０】
【課題を解決するための手段】
本発明は、突起電極が形成されるプリント基板であって、
突起電極は、それぞれ融点の異なる二層以上の導体層部分が一体的に積層されて成り、それら導体層部分のうち、最も低い融点の導体層部分がプリント基板に溶融接合されていることを特徴とする突起電極付きプリント基板である。
【００１１】
本発明に従えば、二層以上の導体層部分のうち、最も低い融点の導体層部分がプリント基板に溶融接合される構成であるので、突起電極を比較的低い加熱温度でもってプリント基板に簡単に接合することができるだけでなく、プリント基板に加熱、加圧によって突起電極を接合する際のダメージを極力小さくすることが可能になり、プリント基板自体の信頼性を確保することができる。また、前記公報に記載の従来のものと比べて製造コストの低減を図ることができる。
【００１２】
また本発明は、前記二層以上の導体層部分のうち、プリント基板に溶融接合されている導体層部分以外の導体層部分は、プリント基板に溶融接合されている導体層部分の厚さよりも大きく形成されることを特徴とする。
【００１３】
本発明に従えば、プリント基板に溶融接合されている導体層部分以外の導体層部分の厚さを、上述したように大きく形成することによって、突起電極をプリント基板に溶融接合するときの熱応力による突起電極の形状変化を極力防止することができる。それ故、プリント基板上において、隣接する突起電極のピッチを狭くすることが可能となる。
【００１４】
また本発明は、前記二層以上の導体層部分から成る突起電極は、プリント基板に溶融接合されている導体層部分以外の導体層部分が、金、銅およびニッケルのうち少なくともいずれか一つから成る金属、または不可避不純物を含む前記金属によって構成され、プリント基板に溶融接合されている導体層部分が、インジウム、銀、錫、ビスマスおよび亜鉛のうち少なくともいずれか一つから成る金属、または不可避不純物を含む前記金属によって構成されることを特徴とする。
【００１５】
本発明に従えば、プリント基板に溶融接合されている導体層部分と、この導体層部分以外の導体層部分とをそれぞれ上述した金属によって構成することで、フリップチップボンディング法を用いることが可能となり、システムインパッケージの小形化および高密度化を図ることができるとともに、突起電極をプリント基板に簡単に接合することができる突起電極付きプリント基板を容易に実現することができる。
【００１６】
また本発明は、プリント基板に溶融接合されている導体層部分において、プリント基板に臨む表面積は、プリント基板の表面積よりも小さく形成されることを特徴とする。
【００１７】
本発明に従えば、突起電極をプリント基板に形成する際、プリント基板に対して突起電極の高精度な位置合わせが不要になる。つまり、導体層部分のプリント基板に臨む表面積が、プリント基板の表面積よりも小さく形成されているので、プリント基板に対する前記導体層部分の相対位置の許容範囲が広がる。それ故、プリント基板に対し、突起電極を高精度に位置合わせする必要がなくなるので、突起電極の形成を簡単化することができるとともにタクトタイムを短縮することができる。
【００１８】
また本発明は、前記突起電極を介してベアチップ半導体素子を搭載可能なプリント基板において、
プリント基板に接合材を介して接合する電子部品を含み、接合材の融点は、ベアチップ半導体素子を搭載するための突起電極のプリント基板に溶融接合される導体層部分の融点よりも低く設定されることを特徴とする。
【００１９】
本発明に従えば、プリント基板に、所定の加熱温度でもって溶融接合された突起電極を介して、ベアチップ半導体素子を搭載した後、プリント基板に接合材を介して電子部品を接合する。接合材の融点は、ベアチップ半導体素子をプリント基板に溶融接合する導体層部分の融点よりも低く設定されているので、電子部品をプリント基板に接合する際、前記所定の加熱温度よりも低い加熱温度に設定することができる。それ故、プリント基板に一旦接合された突起電極の導体層が再溶融するのを未然に防止することができ、安定した接続信頼性を保持することができる。
【００２０】
また本発明は、前記接合材は、導電性接着材および錫を含む合金から成ることを特徴とする。
【００２１】
本発明に従えば、プリント基板に一旦接合された突起電極の導体層が再溶融するのを未然に防止することができる接合材を、容易に実現することができる。
【００２２】
また本発明は、突起電極形成用基板に、それぞれ融点の異なる二層以上の導体層部分を一体的に積層して、突起電極形成用基板から剥離可能に、突起電極を形成する工程と、
プリント基板に突起電極を転写する工程とを含むことを特徴とする突起電極付きプリント基板の製造方法である。
【００２３】
本発明に従えば、突起電極を剥離可能に形成する工程においては、突起電極形成用基板に、それぞれ融点の異なる二層以上の導体層部分を一体的に積層する。次工程において、突起電極をプリント基板に転写することができる。したがって、プリント基板に、必要な箇所のみ突起電極を転写によって形成することが可能になる。前記公報に記載の従来技術においては、突起電極をプリント基板に形成する際のメッキプロセスが複雑化し、各金属を析出するため多大な処理時間が必要になるのに対し、本発明においては、突起電極を突起電極形成用基板に設けるプロセスと、プリント基板を形成するプロセスとを並行してまたは略並行して行うことが可能となる。それ故、プリント基板単体でのプロセスを簡単化することができる。
【００２４】
また本発明は、プリント基板に突起電極を転写する工程は、
前記二層以上の導体層部分のうち、突起電極形成用基板から最も遠い最表層の導体層部分を溶融してプリント基板側の接合部と接合する段階と、
突起電極を突起電極形成用基板から剥離する段階とを含むことを特徴とする。
【００２５】
本発明に従えば、突起電極形成用基板に、それぞれ融点の異なる二層以上の導体層部分を一体的に積層して突起電極を剥離可能に形成した後、二層以上の導体層部分のうち、突起電極形成用基板から最も遠い最表層の導体層部分を溶融してプリント基板側の接合部と接合し、その後、突起電極を突起電極形成用基板から剥離する。突起電極形成用基板から最も遠い前記最表層の導体層部分を溶融してプリント基板側の接合部と接合するため、プリント基板に突起電極を確実にかつ簡単に形成することができる。
【００２６】
【発明の実施の形態】
図１は、本発明の実施形態に係る突起電極付きプリント基板２０の要部断面図である。本実施形態は、たとえば携帯電話および携帯情報端末などに好適に用いられる突起電極付きプリント基板に本発明の突起電極付きプリント基板を適用した場合の一例を示す。以下の説明は、突起電極付きプリント基板の製造方法についての説明をも含む。なお、図１には、プリント基板２０の厚み方向一方が上方に、厚み方向他方が下方に示され、突起電極２１の並び方向一方が左方に、並び方向他方が右方に示される。
【００２７】
突起電極２１付きプリント基板２０は、プリント基板２０ａと、複数の突起電極２１とを含んでいる。プリント基板２０ａは、たとえば、ガラス布エポキシ樹脂またはアラミド繊維不織布エポキシ樹脂などの絶縁基板材料から平板状に形成されている。このプリント基板２０ａの上面部２２には、べアチップ半導体素子（以下、単に半導体素子と呼ぶこともある）を搭載するための複数の接合ランド部２３が、後述する半導体素子の電極部のピッチ、または、電子部品の電極部のピッチに合わせて所定間隔おきに付設されている。これら接合部としての接合ランド部２３は、プリント基板２０ａの上面部２２に銅メッキが施された後、順次、ニッケル無電解メッキ、金の無電解メッキが施されて成り、各接合ランド部２３はプリント基板２０ａに含まれている。
【００２８】
各接合ランド部２３には、それぞれ融点の異なる第１および第２の導体層部分２４，２５が一体的に積層されて成る突起電極２１が溶融接続されている。また、それら導体層部分２４，２５のうち、融点が低い方の導体層部分２５（後述する）が接合ランド部２３に溶融接合されている。すなわち、接合ランド部２３の上面部には、突起電極２１の下段部に位置する第２の導体層部分２５が、突起電極２１全体の厚さのたとえば約１／８の厚さに積層されている。この下段部に位置する第２の導体層部分２５は接合ランド部２３の上面部に臨み、かつ、前記上面部に臨む第２の導体層部分２５の表面積Ｓ１は、接合ランド部２３の上面部の表面積Ｓ２よりもやや小さく形成されている。この約１／８の厚さに積層された第２の導体層部分２５の上面部に、第１の導体層部分２４が積層され、突起電極２１全体の厚さのたとえば約７／８の厚さに積層されている。
【００２９】
第１の導体層部分２４は、金、銅およびニッケルのうち少なくともいずれか一つから成る金属、または不可避不純物を含む前記金属によって構成される。本実施形態において、第１の導電層部分２４は、具体的にはたとえば融点が約１０６３℃である金を用いて構成される。第２の導体層部分２５は、インジウム、銀、錫、ビスマスおよび亜鉛のうち少なくともいずれか一つから成る金属、または不可避不純物を含む前記金属によって構成される。本実施形態において、第２の導体層部分２５は、具体的にはたとえば融点が約１３８℃である錫およびビスマスなどの合金などを用いて構成される。第１の導体層部分２４の厚さＴｍは、下段部に位置する第２の導体層部分２５であってプリント基板２０ａに溶融接合されている第２の導体層部分２５の厚さＴｄよりも大きく形成されている。
【００３０】
図２は、プリント基板２０ａに突起電極２１を転写する工程を段階的に示す説明図であり、図３は、プリント基板２０ａに突起電極２１を形成する工程を示すフローチャートである。ここで、Ｓｉ（ｉ＝１，２，３）はステップを示す。プリント基板２０ａに突起電極２１を転写する際には、図２（ａ）および図３のステップ１に示すように、たとえばガラス基板などの絶縁基板である突起電極形成用基板２６の厚み方向一方の表面部に、たとえばＩＴＯである導体層２７を蒸着によって形成する。次に、導体層２７上にメッキレジスト２８を塗布し、半導体素子２９の電極部３０のピッチＰ（図４参照）に合わせて所定間隔おきに、複数の開口部２８ａを露光現像およびエッチングによってパターニングする。各開口部２８ａは、突起電極形成用基板２６の厚み方向に平行な軸線をもつ上端開放状でたとえば直径約６０μｍの円筒形状に形成され、かつ、接合ランド部２３の上面部に臨む第２の導体層部分２５の表面積Ｓ１が、接合ランド部２３の上面部の表面積Ｓ２よりもやや小さくなるように、メッキレジスト２８用マスクの開口径を適宜調整することによって形成される。導体層２７としては、たとえば、金、白金、チタンタングステン、クロム、上述したＩＴＯなどのうちのいずれかを使用する。
【００３１】
次に、図２（ｂ）に示すように、各開口部２８ａに、順次、第１の導体層２４、第２の導体層２５をメッキ法によって形成する。前記メッキ法としては、電解メッキ法、無電解メッキ法などの湿式メッキ法または蒸着などの乾式メッキ法が適用可能である。なお、突起電極２１を形成した後、メッキレジスト２８を除去してもよい。以上説明した工程によって、二層の導体層部分２４，２５から成る突起電極２１が、突起電極形成用基板２６に形成される。
【００３２】
次に、図２（ｃ）および図３のステップ２に示すように、プリント基板２０ａの複数の接合ランド部２３に対して、複数の突起電極２１が対向するように配置したうえで、搭載対象である所望の半導体素子２９を搭載するのに必要な接合ランド部２３に対して複数の突起電極２１をそれぞれ相対的に位置決めする。その後、複数の突起電極２１を、突起電極形成用基板２６側から図示外のツールを用いて加圧しつつ、前記下段部に位置する第２の導体層部分２５だけが溶融するたとえば約２４０℃の温度まで加熱して、下段部に位置する第２の導体層部分２５を溶融する。
【００３３】
プリント基板２０ａに溶融接合される第２の導体層部分２５において、プリント基板２０ａに臨む表面積Ｓ１は、接合ランド部２３の上面部の表面積Ｓ２よりもやや小さくなるように形成されているので、突起電極２１をプリント基板２０ａに形成する際、プリント基板２０ａに対して突起電極２１の高精度な位置合わせが不要になる。つまり、第２の導体層部分２５の接合ランド部２３に臨む表面積Ｓ１が、接合ランド部２３の表面積Ｓ２よりもやや小さくなるように形成されているので、プリント基板２０ａに対する前記導体層部分２５の相対位置の許容範囲が広がる。それ故、プリント基板２０ａに対し、突起電極２１を高精度に位置合わせする必要がなくなるので、突起電極２１の形成を簡単化することができるとともにタクトタイムを短縮することができる。
【００３４】
その後、図３のステップ３に示すように、前記ツールおよび突起電極形成用基板２６を、プリント基板２０ａから離隔することによって、突起電極２１が突起電極形成用基板２６から剥離して、プリント基板２０ａの接合ランド部２３上に突起電極２１を転写する。プリント基板２０ａの接合ランド部２３上に、複数の突起電極２１を転写、形成する際には、第２の導体層部分２５を溶融させるとともに、第１の導体層部分２４は溶融しない条件において実施する。すなわち、第２の導体層部分２５を溶融させ、接合ランド部２３の材料と溶融接合させることで、図１に示すように、突起電極形成用基板２６上の突起電極２１を、プリント基板２０ａの接合ランド部２３上に確実に転写、形成することができる。
【００３５】
以上説明した突起電極２１付きプリント基板２０によれば、第１および第２の導体層部分２４，２５が一体的に積層されて成る突起電極２１がプリント基板２０に溶融接合されているので、搭載対象のたとえばベアチップ半導体素子２９を、プリント基板２０ａに接続する場合に、ベアチップ半導体素子２９に、突起電極を形成するなどの接続前処理を施す必要がなくなる。それ故、搭載対象となる半導体素子２９の形態上の制限を極力解消することが可能となる。また、フリップチップボンディング法を用いることが可能となり、システムインパッケージの小形化および高密度化を図ることができる。また、第１および第２の導体層部分２４，２５のうち、融点の低い第２の導体層部分２５がプリント基板２０ａに溶融接合される構成であるので、突起電極２１を比較的低い加熱温度でもってプリント基板２０ａに簡単に接合することができるだけでなく、プリント基板２０ａに加熱、加圧によって突起電極２１を接合する際のダメージを極力小さくすることが可能になり、プリント基板自体の信頼性を確保することができる。また、前記公報に記載の従来のものと比べて製造コストの低減を図ることができる。
【００３６】
また、プリント基板２０ａに溶融接合されている第２の導体層部分２５以外の第１導体層部分２４の厚さＴｍを、上述したように大きく形成することによって、突起電極２１をプリント基板２０ａに溶融接合するときの熱応力による突起電極２１の形状変化を極力防止することができる。それ故、プリント基板２０ａ上において、隣接する突起電極２１のピッチを狭くすることが可能となり、システムインパッケージの小形化および高密度化を一層図ることができる。また、突起電極２１付きプリント基板２０の製造方法によれば、突起電極２１を形成する工程においては、突起電極形成用基板２６に、それぞれ融点の異なる第１および第２の導体層部分２４，２５を一体的に積層し、次工程において、突起電極２１をプリント基板２０ａに転写することができる。したがって、プリント基板２０ａに、必要な箇所のみ突起電極２１を転写によって形成することが可能になる。前記公報に記載の従来技術においては、突起電極をプリント基板に形成する際のメッキプロセスが複雑化し、各金属を析出するため多大な処理時間が必要になるのに対し、本実施形態においては、突起電極２１を突起電極形成用基板２６に設けるプロセスと、プリント基板２０ａを形成するプロセスとを並行してまたは略並行して行うことが可能となる。それ故、プリント基板単体でのプロセスを簡単化することができる。突起電極形成用基板２６から最も遠い前記最表層の導体層部分を溶融してプリント基板２０ａ側の接合ランド部２３と接合するため、プリント基板２０ａに突起電極２１を確実にかつ簡単に形成することができる。
【００３７】
図４は、突起電極２１付きプリント基板２０に半導体素子２９を搭載する工程を段階的に示す説明図であり、図５は、突起電極２１付きプリント基板２０にチップ部品３１を接合した状態の断面図である。ただし、前記実施形態と同一の部材には同一の符号を付し、その説明は適宜省略する。ベアチップ半導体素子２９において、その複数の電極部３０は所定間隔おきに付設されている。プリント基板２０ａにおいて、これら電極部３０の所定間隔に合わせて突起電極２１が形成されている。
【００３８】
突起電極２１付きプリント基板２０に半導体素子２９を搭載する場合、図４（ａ）に示すように、半導体素子２９の複数の電極部３０と、プリント基板２０ａ上の複数の突起電極２１とを位置合わせし、半導体素子２９の厚み方向一方から所定の超音波と圧力、場合によりさらに温度を付加させた超音波接合の条件下で、各接合ランド部２３上の突起電極２１と半導体素子２９の電極部３０とを接続する。突起電極２１において、半導体素子２９に臨む厚み方向一方の表面積Ｓ３は、半導体素子２９の電極部３０の表面積Ｓ４よりもやや小さく形成されているので、各電極部３０と突起電極２１とを位置合わせする場合、プリント基板２０ａの突起電極２１に対して、半導体素子２９の高精度な位置合わせが不要になる。つまり、突起電極２１の半導体素子２９に臨む厚み方向一方の表面積Ｓ３が、電極部３０の表面積Ｓ４よりもやや小さく形成されているので、突起電極２１に対する半導体素子２９の相対位置の許容範囲が広がるので、半導体素子２９の高精度な位置合わせが不要になる。したがって、半導体素子２９の実装を簡単化することができるとともにタクトタイムを短縮することができる。
【００３９】
次に図４（ｂ）に示すように、突起電極２１が形成されている部分を除き、接続後の半導体素子２９とプリント基板２０ａとの間にアンダーフィル３２を注入する。これによって、プリント基板２０ａの突起電極２１に対し、半導体素子２９を強固に接続することができ、良好な接続信頼性を得ることができる。突起電極２１と半導体素子２９の電極部３０とを接続する手法として、たとえば、異方性導電フィルム、異方性導電性ペーストによる熱圧着接続や熱と加圧による固層拡散接続などによる他の手法も適用することができる。また、突起電極２１と半導体素子２９の電極部３０とを接続する前に、突起電極２１付きプリント基板２０上に、アンダーフィル３２を予め塗布しておいてもよい。
【００４０】
半導体素子２９をプリント基板２０ａに搭載した後、このプリント基板２０ａに、電子部品３１であるチップ抵抗およびチップコンデンサを搭載する場合、電子部品３１をプリント基板２０ａに接合するための接合材３３は、接合ランド部２３に溶融接合される上述した第２の導体層部分２５の融点よりも低い融点に設定されている。前記接合材３３は、導電性接着材および錫を含む合金、具体的にはたとえば、錫とビスマスとの合金、錫とインジウムとの合金、錫と亜鉛との合金などから構成されている。したがって、プリント基板２０ａに、接合材３３を介して、第２の導体層部分２５の融点よりも低い融点付近の加熱温度でもって、チップ抵抗およびチップコンデンサを接合する。このように、電子部品３１をプリント基板２０ａに接合するための接合材３３は、接合ランド部２３に溶融接合される第２の導体層部分２５の融点よりも低い融点に設定されているので、プリント基板２０ａに、半導体素子２９を搭載した後、電子部品３１を搭載する際、プリント基板２０ａ上に接合した突起電極２１の導体層部分２５が再溶融せず、安定した接続信頼性を保持することができる。
【００４１】
本発明の実施の他の形態として、三層以上の導体層部分が一体的に積層されて成る突起電極を適用することも可能である。銅、ニッケル、または、銅ニッケルなどの合金を用いて第１の導体層部分を構成してもよい。インジウム、銀、錫、ビスマス、亜鉛、または、錫および銀、錫および亜鉛などの合金などを用いて第２の導体層部分を構成してもよい。突起電極形成用基板は、ガラス基板に必ずしも限定されるものではなく、たとえば、石英基板、ポリイミドなどの絶縁基板を用いてもよい。本実施形態においては、円筒形状の突起電極について説明したが、突起電極は、必ずしも円筒形状に限定されるものではなく、円錐形状または多角形状の突起電極を適用可能である。電子部品を接合する接合材は、上述したものの他に、金属粉を含んだ導電性接着剤および錫を含む合金、すなわち、錫−銀系に融点降下元素であるインジウム、ビスマス、亜鉛などを添加した三元系以上の接合材も適用可能である。その他、前記実施形態に、特許請求の範囲を逸脱しない範囲において種々の部分的変更を行う場合もある。
【００４２】
【発明の効果】
以上のように本発明によれば、二層以上の導体層部分のうち、最も低い融点の導体層部分がプリント基板に溶融接合される構成であるので、突起電極を比較的低い加熱温度でもってプリント基板に簡単に接合することができるだけでなく、プリント基板に加熱、加圧によって突起電極を接合する際のダメージを極力小さくすることが可能になり、プリント基板自体の信頼性を確保することができる。また、前記公報に記載の従来のものと比べて製造コストの低減を図ることができる。
【００４３】
また本発明によれば、プリント基板に溶融接合されている導体層部分以外の導体層部分の厚さを、上述したように大きく形成することによって、突起電極をプリント基板に溶融接合するときの熱応力による突起電極の形状変化を極力防止することができる。それ故、プリント基板上において、隣接する突起電極のピッチを狭くすることが可能となり、システムインパッケージの小形化および高密度化を一層図ることができる。
【００４４】
また本発明によれば、プリント基板に溶融接合されている導体層部分と、この導体層部分以外の導体層部分とをそれぞれ上述した金属によって構成することで、フリップチップボンディング法を用いることが可能となり、システムインパッケージの小形化および高密度化を図ることができるとともに、突起電極をプリント基板に簡単に接合することができる突起電極付きプリント基板を容易に実現することができる。
【００４５】
また本発明によれば、突起電極をプリント基板に形成する際、プリント基板に対して突起電極の高精度な位置合わせが不要になる。つまり、導体層部分のプリント基板に臨む表面積が、プリント基板の表面積よりも小さく形成されているので、プリント基板に対する前記導体層部分の相対位置の許容範囲が広がる。それ故、突起電極の形成を簡単化することができるとともにタクトタイムを短縮することができる。
【００４６】
また本発明によれば、プリント基板に、所定の加熱温度でもって溶融接合された突起電極を介して、ベアチップ半導体素子を搭載した後、プリント基板に接合材を介して電子部品を接合する。接合材の融点は、ベアチップ半導体素子をプリント基板に溶融接合する導体層部分の融点よりも低く設定されているので、電子部品をプリント基板に接合する際、前記所定の加熱温度よりも低い加熱温度に設定することができる。それ故、プリント基板に一旦接合された突起電極の導体層が再溶融するのを未然に防止することができ、安定した接続信頼性を保持することができる。
【００４７】
また、本発明によれば、プリント基板に一旦接合された突起電極の導体層が再溶融するのを未然に防止することができる接合材を、容易に実現することができる。
【００４８】
また、本発明によれば、突起電極を剥離可能に形成する工程においては、突起電極形成用基板に、それぞれ融点の異なる二層以上の導体層部分を一体的に積層する。次工程において、突起電極をプリント基板に転写することができる。したがって、プリント基板に、必要な箇所のみ突起電極を転写によって形成することが可能になる。前記公報に記載の従来技術においては、突起電極をプリント基板に形成する際のメッキプロセスが複雑化し、各金属を析出するため多大な処理時間が必要になるのに対し、突起電極を突起電極形成用基板に設けるプロセスと、プリント基板を形成するプロセスとを並行してまたは略並行して行うことが可能となる。それ故、プリント基板単体でのプロセスを簡単化することができる。
【００４９】
また、本発明によれば、突起電極形成用基板に、それぞれ融点の異なる二層以上の導体層部分を一体的に積層して突起電極を剥離可能に形成した後、二層以上の導体層部分のうち、突起電極形成用基板から最も遠い最表層の導体層部分を溶融してプリント基板側の接合部と接合し、その後、突起電極を突起電極形成用基板から剥離することができる。突起電極形成用基板から最も遠い前記最表層の導体層部分を溶融してプリント基板側の接合部と接合するため、プリント基板に突起電極を確実にかつ簡単に形成することができる。
【図面の簡単な説明】
【図１】本発明の実施形態に係る突起電極付きプリント基板の要部断面図である。
【図２】プリント基板に突起電極を転写する工程を段階的に示す説明図である。
【図３】プリント基板に突起電極を形成する工程を示すフローチャートである。
【図４】突起電極付きプリント基板に半導体素子を搭載する工程を段階的に示す説明図である。
【図５】突起電極付きプリント基板にチップ部品を接合した状態の断面図である。
【図６】従来の突起電極付きプリント基板を製造する方法を段階的に示す説明図である。
【符号の説明】
２０ プリント基板
２１ 突起電極
２３ 接合ランド部
２４ 第１の導体層部分
２５ 第２の導体層部分
２６ 突起電極形成用基板
２９ 半導体素子
３１ 電子部品[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a printed circuit board with a protruding electrode and a method for manufacturing the same, and relates to a technique suitably used for, for example, a mobile phone and a portable information terminal.
[0002]
[Prior art]
One of the driving forces for the rapid spread of mobile phones and portable information terminals is the dramatic miniaturization of devices. Behind this is a system-on-chip (SOC) technology for consolidating systems and functions conventionally configured from a plurality of large-scale integrated circuits (LSIs: Large Scale Integration) into one semiconductor element. There is progress. On the other hand, in recent years, a system in package (SIP: System In Package) in which a plurality of necessary semiconductor elements are combined and directly mounted on a printed circuit board to form a single package has attracted attention.
[0003]
2. Description of the Related Art In recent years, with respect to portable information devices represented by mobile phones, the product cycle has been shortened with the advancement of functions, and it has been desired to shorten the development period of portable information devices as much as possible. For example, if a single function change occurs in a mobile phone, the SOC requires a change that affects everything from the design of the semiconductor device to the process. On the other hand, SIP can respond by changing or adding some types of semiconductor elements or making a slight change in the printed circuit board. Therefore, SIP has a much longer development period than SOC. It is possible to achieve a significant reduction in development time and a significant reduction in development costs.
[0004]
In order to reduce the size and increase the density of the SIP, a so-called so-called electrically connecting bare chip semiconductor element provided with a protruding electrode such as a bump for preventing short-circuit with its active element surface facing downward is used. It is effective to use a flip-chip bonding method on a printed circuit board with the face down. However, since the SIP configures one system by combining a plurality of semiconductor elements, among the plurality of semiconductor elements, it may be necessary to mount a semiconductor element manufactured by another company other than its own. That is, in the case of SIP, when a semiconductor device manufactured by another company without a protruding electrode is required, it is necessary to use a mounting method such as a wire bonding method other than the flip chip bonding method. In addition, the distance between the electrode and the printed circuit board is substantially widened, which hinders miniaturization of the SIP.
[0005]
2. Description of the Related Art Conventionally, a technique has been disclosed in which a protruding electrode such as a bump is formed on a printed circuit board, and a semiconductor element having no protruding electrode, that is, a bare chip semiconductor element is mounted (Patent Document 1). FIG. 6 is an explanatory diagram showing step by step the method of manufacturing the printed circuit board 1 with the protruding electrodes disclosed in Patent Document 1. As shown in FIG. 6A, through-holes 3 such as through holes and via holes are formed in the printed circuit board 1 on which the inner conductor 2 is formed. The outer layer conductors 4 and 5 and the electrode terminals 6 are formed on the surface of the printed circuit board 1 by plating. Further, a solder resist layer 7 is formed at a predetermined location.
[0006]
Next, as shown in FIG. 6 (b), a plating resist 8 is formed on the printed circuit board 1, and minute holes are formed in the electrode terminals 6 for connecting the bare chip semiconductor elements 10 by a photo method and a carbon dioxide gas laser. A protruding electrode 9 is formed on the electrode terminal 6 by depositing a predetermined metal by plating. Next, as shown in FIG. 6C, after the plating resist 7 is peeled off, the bare chip semiconductor element 10 is connected to the printed board 1 via the bump electrodes 9 by a flip chip bonding method.
[0007]
[Patent Document 1]
JP 2000-208910 A
[0008]
[Problems to be solved by the invention]
In the prior art described in Patent Document 1, a dedicated plating process for forming the bump electrodes 9 is performed separately from a plating process for forming circuits such as the outer layer conductors 4 and 5 on the surface of the printed circuit board 1. In addition to the necessity, the protruding electrode 9 is formed by laminating, for example, about 20 μm or more and 30 μm or less of electroless copper plating, laminating about 10 μm of electroless nickel plating, and laminating about 0.5 μm of electroless gold plating. The plating process is complicated. In addition, a great deal of processing time is required to deposit each metal. Therefore, tact time and man-hours increase, and productivity decreases. Further, as the plating process becomes more complicated, the equipment cost increases and the manufacturing cost increases.
[0009]
Accordingly, an object of the present invention is to provide a system-in-package with a protruding electrode capable of miniaturizing and increasing the density, securing reliability, improving productivity, minimizing equipment costs, and reducing manufacturing costs. An object of the present invention is to provide a printed circuit board and a method for manufacturing the same.
[0010]
[Means for Solving the Problems]
The present invention is a printed circuit board on which protruding electrodes are formed,
The protruding electrode is formed by integrally laminating two or more conductor layer portions each having a different melting point, and among the conductor layer portions, the conductor layer portion having the lowest melting point is melt-bonded to the printed circuit board. Printed circuit board with projection electrodes.
[0011]
According to the present invention, since the conductor layer portion having the lowest melting point among the two or more conductor layer portions is melt-bonded to the printed board, the projecting electrodes can be easily attached to the printed board at a relatively low heating temperature. In addition to this, it is possible to minimize damage when joining the protruding electrodes to the printed board by heating and pressurizing, and the reliability of the printed board itself can be ensured. Further, the manufacturing cost can be reduced as compared with the related art described in the above publication.
[0012]
Further, according to the present invention, among the two or more conductive layer portions, the conductive layer portion other than the conductive layer portion that is melt-bonded to the printed board is larger than the thickness of the conductive layer portion that is melt-bonded to the printed board. It is characterized by being formed.
[0013]
According to the present invention, the thickness of the conductor layer portion other than the conductor layer portion that is melt-bonded to the printed board is formed to be large as described above, so that the thermal stress when the bump electrode is melt-bonded to the printed board is formed. Thus, a change in the shape of the protruding electrode due to this can be prevented as much as possible. Therefore, it is possible to narrow the pitch between the adjacent protruding electrodes on the printed board.
[0014]
Further, according to the present invention, the projecting electrode composed of the two or more conductive layer portions has a conductive layer portion other than the conductive layer portion that is melt-bonded to the printed circuit board, and is formed of at least one of gold, copper, and nickel. The conductive layer portion, which is formed of the above-mentioned metal or the above-mentioned metal containing unavoidable impurities, and which is melt-bonded to the printed circuit board, is made of at least one of indium, silver, tin, bismuth, and zinc; It is characterized by being comprised by the above-mentioned metal containing.
[0015]
According to the present invention, it is possible to use the flip-chip bonding method by configuring the conductor layer portion that is melt-bonded to the printed board and the conductor layer portion other than the conductor layer portion with the above-described metals, respectively. In addition, it is possible to reduce the size and increase the density of the system-in-package, and to easily realize a printed circuit board with projecting electrodes that can easily bond the projecting electrodes to the printed circuit board.
[0016]
Further, the present invention is characterized in that the surface area facing the printed board is formed to be smaller than the surface area of the printed board in the conductor layer portion which is melt-bonded to the printed board.
[0017]
ADVANTAGE OF THE INVENTION According to this invention, when forming a protruding electrode on a printed circuit board, highly accurate positioning of the protruding electrode with respect to the printed circuit board becomes unnecessary. That is, since the surface area of the conductor layer facing the printed board is formed smaller than the surface area of the printed board, the allowable range of the relative position of the conductor layer to the printed board is increased. Therefore, it is not necessary to position the projecting electrodes with high precision on the printed circuit board, so that the formation of the projecting electrodes can be simplified and the tact time can be shortened.
[0018]
Further, the present invention provides a printed circuit board on which a bare chip semiconductor element can be mounted via the bump electrode.
Including an electronic component bonded to a printed board via a bonding material, the melting point of the bonding material is set to be lower than the melting point of the conductive layer portion of the protruding electrode for mounting the bare chip semiconductor element which is melt bonded to the printed board. It is characterized by the following.
[0019]
According to the present invention, the bare chip semiconductor element is mounted on the printed board via the protruding electrode fused at a predetermined heating temperature, and then the electronic component is bonded to the printed board via the bonding material. Since the melting point of the bonding material is set lower than the melting point of the conductor layer portion for melting and bonding the bare chip semiconductor element to the printed circuit board, when the electronic component is bonded to the printed circuit board, the heating temperature is lower than the predetermined heating temperature. Can be set to Therefore, it is possible to prevent the conductor layer of the protruding electrode once bonded to the printed board from being re-melted, and to maintain stable connection reliability.
[0020]
Further, the present invention is characterized in that the joining material is made of an alloy containing a conductive adhesive and tin.
[0021]
ADVANTAGE OF THE INVENTION According to this invention, the joining material which can prevent the conductor layer of the projecting electrode once joined to the printed board from re-melting can be easily realized.
[0022]
In addition, the present invention, the projecting electrode forming substrate, two or more conductor layers having different melting points are laminated integrally, respectively, and a step of forming a projecting electrode so as to be peelable from the projecting electrode forming substrate,
Transferring a protruding electrode to a printed circuit board.
[0023]
According to the present invention, in the step of forming the protruding electrodes in a releasable manner, two or more conductor layer portions having different melting points are integrally laminated on the protruding electrode forming substrate. In the next step, the bump electrodes can be transferred to the printed circuit board. Therefore, it is possible to form the protruding electrodes on the printed circuit board only at necessary positions by transfer. In the prior art described in the above publication, the plating process for forming the protruding electrodes on the printed circuit board is complicated, and a great amount of processing time is required for depositing each metal. The process of providing the electrodes on the protruding electrode forming substrate and the process of forming the printed circuit board can be performed in parallel or substantially in parallel. Therefore, the process using only the printed circuit board can be simplified.
[0024]
Also, in the present invention, the step of transferring the protruding electrode to the printed board,
Of the two or more conductive layer portions, the step of melting the outermost conductive layer portion farthest from the protruding electrode forming substrate and bonding it to the bonding portion on the printed circuit board side,
Separating the protruding electrode from the substrate for forming a protruding electrode.
[0025]
According to the present invention, after two or more conductor layer portions having different melting points are integrally laminated on the bump electrode formation substrate to form the bump electrodes in a releasable manner, the two or more conductor layer portions Then, the outermost conductor layer portion farthest from the projecting electrode forming substrate is melted and joined to the joining portion on the printed board side, and then the projecting electrode is peeled off from the projecting electrode forming substrate. Since the outermost conductor layer portion farthest from the projecting electrode forming substrate is melted and joined to the joining portion on the printed circuit board side, the projecting electrode can be reliably and easily formed on the printed circuit board.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a cross-sectional view of a main part of a printed circuit board 20 with bump electrodes according to an embodiment of the present invention. The present embodiment shows an example in which the printed circuit board with a protruding electrode of the present invention is applied to a printed circuit board with a protruding electrode suitably used for, for example, a mobile phone and a portable information terminal. The following description also includes a description of a method of manufacturing a printed circuit board with bump electrodes. In FIG. 1, one side in the thickness direction of the printed circuit board 20 is shown above, the other side in the thickness direction is shown below, one direction in which the protruding electrodes 21 are arranged is shown on the left, and the other direction is shown on the right.
[0027]
The printed board 20 with the protruding electrodes 21 includes a printed board 20a and a plurality of protruding electrodes 21. The printed circuit board 20a is formed in a flat plate shape from an insulating substrate material such as a glass cloth epoxy resin or an aramid fiber nonwoven cloth epoxy resin. A plurality of bonding lands 23 for mounting a bear chip semiconductor element (hereinafter, sometimes simply referred to as a semiconductor element) are formed on an upper surface 22 of the printed board 20a. Alternatively, they are provided at predetermined intervals in accordance with the pitch of the electrode portion of the electronic component. The bonding lands 23 serving as these bonding portions are formed by plating the upper surface portion 22 of the printed circuit board 20a with copper, and then performing electroless plating with nickel and electroless plating with gold. Are included in the printed circuit board 20a.
[0028]
A protruding electrode 21 formed by integrally laminating first and second conductor layer portions 24 and 25 having different melting points is fusion-connected to each joint land portion 23. Further, of the conductor layers 24 and 25, the conductor layer 25 having a lower melting point (described later) is fusion-bonded to the joint land 23. That is, the second conductor layer portion 25 located at the lower part of the protruding electrode 21 is laminated on the upper surface of the bonding land portion 23 to a thickness of, for example, about ８ of the entire thickness of the protruding electrode 21. I have. The second conductor layer portion 25 located at the lower stage faces the upper surface of the bonding land portion 23, and the surface area S1 of the second conductor layer portion 25 facing the upper surface portion is equal to the upper surface portion of the bonding land portion 23. Is formed to be slightly smaller than the surface area S2. The first conductor layer portion 24 is laminated on the upper surface of the second conductor layer portion 25 laminated to a thickness of about 1/8, and the thickness of the entire bump electrode 21 is, for example, about 7/8. It is laminated on.
[0029]
The first conductor layer portion 24 is made of a metal made of at least one of gold, copper and nickel, or the above-mentioned metal containing unavoidable impurities. In the present embodiment, the first conductive layer portion 24 is specifically made of, for example, gold having a melting point of about 1063 ° C. The second conductor layer portion 25 is made of a metal made of at least one of indium, silver, tin, bismuth and zinc, or the above-mentioned metal containing unavoidable impurities. In the present embodiment, the second conductor layer portion 25 is specifically made of, for example, an alloy such as tin and bismuth having a melting point of about 138 ° C. The thickness Tm of the first conductor layer portion 24 is larger than the thickness Td of the second conductor layer portion 25 which is the second conductor layer portion 25 located at the lower stage and is fusion-bonded to the printed circuit board 20a. It is formed large.
[0030]
FIG. 2 is an explanatory diagram showing a step of transferring the bump electrode 21 to the printed board 20a, and FIG. 3 is a flowchart showing a step of forming the bump electrode 21 on the printed board 20a. Here, Si (i = 1, 2, 3) indicates a step. When transferring the protruding electrode 21 to the printed board 20a, as shown in step 1 of FIG. 2A and FIG. 3, one of the thickness direction of the protruding electrode forming substrate 26 which is an insulating substrate such as a glass substrate, for example. A conductor layer 27 of, for example, ITO is formed on the surface by vapor deposition. Next, a plating resist 28 is applied on the conductor layer 27, and a plurality of openings 28a are patterned at predetermined intervals according to the pitch P (see FIG. 4) of the electrode portions 30 of the semiconductor element 29 by exposure and development and etching. I do. Each of the openings 28 a is formed in a cylindrical shape having an open top end having an axis parallel to the thickness direction of the bump electrode forming substrate 26 and having a diameter of, for example, about 60 μm. The opening diameter of the plating resist 28 mask is appropriately adjusted so that the surface area S1 of the conductor layer portion 25 is slightly smaller than the surface area S2 of the upper surface portion of the bonding land portion 23. As the conductor layer 27, for example, any one of gold, platinum, titanium tungsten, chromium, and the above-described ITO is used.
[0031]
Next, as shown in FIG. 2B, a first conductor layer 24 and a second conductor layer 25 are sequentially formed in each opening 28a by a plating method. As the plating method, a wet plating method such as an electrolytic plating method or an electroless plating method, or a dry plating method such as evaporation can be applied. After forming the protruding electrodes 21, the plating resist 28 may be removed. Through the steps described above, the bump electrode 21 including the two conductor layer portions 24 and 25 is formed on the bump electrode forming substrate 26.
[0032]
Next, as shown in FIG. 2C and step 2 of FIG. 3, the plurality of projecting electrodes 21 are arranged so as to face the plurality of bonding lands 23 of the printed circuit board 20a, and The plurality of protruding electrodes 21 are relatively positioned with respect to the joint lands 23 necessary for mounting the desired semiconductor element 29. Then, while pressing the plurality of bump electrodes 21 from the bump electrode forming substrate 26 side using a tool (not shown), only the second conductor layer portion 25 located at the lower stage is melted, for example, at about 240 ° C. By heating to the temperature, the second conductor layer portion 25 located at the lower part is melted.
[0033]
Since the surface area S1 facing the printed circuit board 20a in the second conductor layer portion 25 that is melt-bonded to the printed circuit board 20a is formed to be slightly smaller than the surface area S2 of the upper surface of the bonding land 23, the protrusions are formed. When the electrodes 21 are formed on the printed circuit board 20a, it is not necessary to precisely position the protruding electrodes 21 with respect to the printed circuit board 20a. That is, since the surface area S1 of the second conductor layer portion 25 facing the bonding land portion 23 is formed to be slightly smaller than the surface area S2 of the bonding land portion 23, the conductor layer portion 25 with respect to the printed circuit board 20a is formed. The permissible range of the relative position is expanded. Therefore, it is not necessary to position the protruding electrode 21 with high precision with respect to the printed board 20a, so that the formation of the protruding electrode 21 can be simplified and the tact time can be shortened.
[0034]
Thereafter, as shown in Step 3 of FIG. 3, the tool and the protruding electrode forming substrate 26 are separated from the printed circuit board 20a, so that the protruding electrodes 21 are separated from the protruding electrode forming substrate 26, and the printed circuit board 20a The projection electrode 21 is transferred onto the bonding land 23 of FIG. When transferring and forming the plurality of protruding electrodes 21 on the joint lands 23 of the printed circuit board 20a, the second conductive layer 25 is melted and the first conductive layer 24 is not melted. I do. That is, the second conductive layer portion 25 is melted and melt-bonded to the material of the bonding land portion 23, so that the protruding electrodes 21 on the protruding electrode forming substrate 26 are formed on the printed board 20a as shown in FIG. Transfer and formation can be reliably performed on the joining land portion 23.
[0035]
According to the printed board 20 with the projecting electrodes 21 described above, the projecting electrodes 21 formed by integrally laminating the first and second conductor layer portions 24 and 25 are melt-bonded to the printed board 20. When the target, for example, the bare chip semiconductor element 29 is connected to the printed circuit board 20a, it is not necessary to perform a connection pretreatment such as forming a protruding electrode on the bare chip semiconductor element 29. Therefore, it is possible to eliminate restrictions on the form of the semiconductor element 29 to be mounted as much as possible. Further, the flip-chip bonding method can be used, so that the size of the system-in-package can be reduced and the density thereof can be increased. In addition, since the second conductor layer portion 25 having a lower melting point among the first and second conductor layer portions 24 and 25 is configured to be melt-bonded to the printed circuit board 20a, the projection electrode 21 is heated at a relatively low heating temperature. Thus, not only can it be easily joined to the printed circuit board 20a, but also the damage when joining the protruding electrodes 21 to the printed circuit board 20a by heating and pressing can be minimized, and the reliability of the printed circuit board itself can be reduced. Can be secured. Further, the manufacturing cost can be reduced as compared with the related art described in the above publication.
[0036]
Also, by forming the thickness Tm of the first conductor layer portion 24 other than the second conductor layer portion 25 melt-bonded to the printed board 20a to be large as described above, the projecting electrodes 21 are formed on the printed board 20a. A change in the shape of the protruding electrode 21 due to thermal stress during fusion bonding can be prevented as much as possible. Therefore, the pitch between the adjacent protruding electrodes 21 on the printed circuit board 20a can be reduced, and the size and density of the system-in-package can be further reduced. According to the method of manufacturing the printed board 20 with the bump electrodes 21, in the step of forming the bump electrodes 21, the first and second conductor layer portions 24, 25 having different melting points are formed on the bump electrode forming substrate 26, respectively. Can be integrally laminated, and in the next step, the bump electrodes 21 can be transferred to the printed circuit board 20a. Therefore, it is possible to form the protruding electrodes 21 on the printed circuit board 20a only at necessary positions by transfer. In the prior art described in the above publication, the plating process when forming the protruding electrodes on the printed circuit board is complicated, and a great amount of processing time is required for depositing each metal, whereas in the present embodiment, The process of providing the bump electrodes 21 on the bump electrode forming substrate 26 and the process of forming the printed board 20a can be performed in parallel or substantially in parallel. Therefore, the process using only the printed circuit board can be simplified. Since the outermost conductor layer portion farthest from the protruding electrode forming substrate 26 is melted and bonded to the bonding land portion 23 on the printed circuit board 20a side, the protruding electrodes 21 are reliably and easily formed on the printed circuit board 20a. Can be.
[0037]
FIG. 4 is an explanatory view showing a step of mounting the semiconductor element 29 on the printed board 20 with the protruding electrodes 21. FIG. 5 is a cross-sectional view of a state where the chip component 31 is joined to the printed board 20 with the protruding electrodes 21. FIG. However, the same members as those in the above embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. In the bare chip semiconductor element 29, the plurality of electrode portions 30 are provided at predetermined intervals. On the printed circuit board 20a, projecting electrodes 21 are formed at predetermined intervals of the electrode portions 30.
[0038]
When the semiconductor element 29 is mounted on the printed board 20 with the protruding electrodes 21, as shown in FIG. 4A, the plurality of electrode portions 30 of the semiconductor element 29 and the plurality of protruding electrodes 21 on the printed board 20 a are positioned. Under the conditions of ultrasonic bonding in which predetermined ultrasonic waves and pressure, and in some cases, additional temperature are applied from one side in the thickness direction of the semiconductor element 29, the protruding electrodes 21 on the bonding lands 23 and the electrodes of the semiconductor element 29 Unit 30 is connected. In the protruding electrode 21, the surface area S3 in the thickness direction facing the semiconductor element 29 is formed to be slightly smaller than the surface area S4 of the electrode section 30 of the semiconductor element 29, so that each electrode section 30 and the protruding electrode 21 are aligned. In this case, it is not necessary to precisely position the semiconductor element 29 with respect to the protruding electrodes 21 of the printed circuit board 20a. That is, since the surface area S3 of the protruding electrode 21 in the thickness direction facing the semiconductor element 29 is formed slightly smaller than the surface area S4 of the electrode section 30, the allowable range of the relative position of the semiconductor element 29 with respect to the protruding electrode 21 is widened. Therefore, highly accurate positioning of the semiconductor element 29 is not required. Therefore, the mounting of the semiconductor element 29 can be simplified and the tact time can be reduced.
[0039]
Next, as shown in FIG. 4B, an underfill 32 is injected between the connected semiconductor element 29 and the printed circuit board 20a except for the portion where the protruding electrodes 21 are formed. Thus, the semiconductor element 29 can be firmly connected to the protruding electrodes 21 of the printed circuit board 20a, and good connection reliability can be obtained. As a method of connecting the protruding electrode 21 and the electrode portion 30 of the semiconductor element 29, for example, other methods such as thermocompression connection using an anisotropic conductive film or an anisotropic conductive paste or solid layer diffusion connection using heat and pressure are used. Techniques can also be applied. Further, before connecting the bump electrode 21 and the electrode portion 30 of the semiconductor element 29, an underfill 32 may be applied on the printed board 20 with the bump electrode 21 in advance.
[0040]
After the semiconductor element 29 is mounted on the printed circuit board 20a, when a chip resistor and a chip capacitor as the electronic component 31 are mounted on the printed circuit board 20a, a bonding material 33 for bonding the electronic component 31 to the printed circuit board 20a is as follows. The melting point is set lower than the melting point of the above-described second conductor layer portion 25 that is melt-bonded to the bonding land portion 23. The bonding material 33 is made of an alloy containing a conductive adhesive and tin, specifically, for example, an alloy of tin and bismuth, an alloy of tin and indium, and an alloy of tin and zinc. Therefore, the chip resistor and the chip capacitor are joined to the printed circuit board 20a via the joining material 33 at a heating temperature near the melting point lower than the melting point of the second conductor layer portion 25. As described above, since the bonding material 33 for bonding the electronic component 31 to the printed board 20a is set to a melting point lower than the melting point of the second conductor layer portion 25 that is melt-bonded to the bonding land portion 23, When mounting the electronic component 31 after mounting the semiconductor element 29 on the printed circuit board 20a, the conductor layer portion 25 of the protruding electrode 21 bonded on the printed circuit board 20a does not re-melt and maintains stable connection reliability. be able to.
[0041]
As another embodiment of the present invention, it is also possible to apply a bump electrode in which three or more conductor layer portions are integrally laminated. The first conductor layer portion may be formed using copper, nickel, or an alloy such as copper nickel. The second conductor layer portion may be formed using indium, silver, tin, bismuth, zinc, or an alloy of tin and silver, tin and zinc, or the like. The substrate for forming the protruding electrodes is not necessarily limited to a glass substrate, and for example, an insulating substrate such as a quartz substrate or polyimide may be used. In the present embodiment, the cylindrical protruding electrode has been described, but the protruding electrode is not necessarily limited to the cylindrical shape, and a conical or polygonal protruding electrode can be applied. The bonding material for bonding electronic components is, in addition to the above, a conductive adhesive containing metal powder and an alloy containing tin, i.e., tin-silver, indium, bismuth, zinc, etc., which are melting point lowering elements added. A ternary or higher joining material can also be used. In addition, various partial changes may be made to the embodiment without departing from the scope of the claims.
[0042]
【The invention's effect】
As described above, according to the present invention, the conductor layer portion having the lowest melting point among the two or more conductor layer portions is configured to be melt-bonded to the printed circuit board. Not only can it be easily bonded to a printed circuit board, but it is also possible to minimize the damage when connecting protruding electrodes to the printed circuit board by heating and applying pressure, thereby ensuring the reliability of the printed circuit board itself. it can. Further, the manufacturing cost can be reduced as compared with the related art described in the above publication.
[0043]
Further, according to the present invention, the thickness of the conductor layer portion other than the conductor layer portion fusion-bonded to the printed board is formed to be large as described above, so that the heat generated when the bump electrode is fusion-bonded to the printed board is formed. A change in shape of the protruding electrode due to stress can be prevented as much as possible. Therefore, it is possible to narrow the pitch of the adjacent protruding electrodes on the printed board, and it is possible to further reduce the size and density of the system-in-package.
[0044]
Further, according to the present invention, it is possible to use the flip-chip bonding method by configuring the conductor layer portion that is melt-bonded to the printed board and the conductor layer portion other than the conductor layer portion with the above-described metals, respectively. As a result, the size of the system-in-package can be reduced and the density thereof can be increased, and a printed circuit board with projecting electrodes that can easily bond the projecting electrodes to the printed circuit board can be easily realized.
[0045]
Further, according to the present invention, when forming the protruding electrodes on the printed circuit board, it is not necessary to precisely position the protruding electrodes on the printed circuit board. That is, since the surface area of the conductor layer facing the printed board is formed smaller than the surface area of the printed board, the allowable range of the relative position of the conductor layer to the printed board is increased. Therefore, the formation of the protruding electrodes can be simplified and the tact time can be shortened.
[0046]
Further, according to the present invention, after mounting the bare chip semiconductor element on the printed board via the protruding electrode fused at a predetermined heating temperature, the electronic component is bonded to the printed board via the bonding material. Since the melting point of the bonding material is set lower than the melting point of the conductor layer portion for melting and bonding the bare chip semiconductor element to the printed circuit board, when the electronic component is bonded to the printed circuit board, the heating temperature is lower than the predetermined heating temperature. Can be set to Therefore, it is possible to prevent the conductor layer of the protruding electrode once bonded to the printed board from being re-melted, and to maintain stable connection reliability.
[0047]
Further, according to the present invention, it is possible to easily realize a bonding material capable of preventing the conductor layer of the protruding electrode once bonded to the printed board from remelting.
[0048]
Further, according to the present invention, in the step of forming the protruding electrode in a releasable manner, two or more conductor layers having different melting points are integrally laminated on the protruding electrode forming substrate. In the next step, the bump electrodes can be transferred to the printed circuit board. Therefore, it is possible to form the protruding electrodes on the printed circuit board only at necessary positions by transfer. In the prior art described in the above publication, the plating process for forming the protruding electrodes on the printed circuit board is complicated, and a great amount of processing time is required for depositing each metal. It is possible to perform the process of forming the printed circuit board and the process of forming the printed circuit board in parallel or substantially in parallel. Therefore, the process using only the printed circuit board can be simplified.
[0049]
Further, according to the present invention, two or more conductor layer portions each having a different melting point are integrally laminated on the projection electrode formation substrate to form the projecting electrode in a releasable manner, and then the two or more conductor layer portions are formed. Among them, the outermost conductor layer portion farthest from the projecting electrode forming substrate is melted and joined to the joining portion on the printed circuit board side, and then the projecting electrode can be peeled off from the projecting electrode forming substrate. Since the outermost conductor layer portion farthest from the projecting electrode forming substrate is melted and joined to the joining portion on the printed circuit board side, the projecting electrode can be reliably and easily formed on the printed circuit board.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a main part of a printed circuit board with bump electrodes according to an embodiment of the present invention.
FIG. 2 is an explanatory view showing a step of transferring a protruding electrode to a printed board in a stepwise manner.
FIG. 3 is a flowchart illustrating a process of forming a bump electrode on a printed board.
FIG. 4 is an explanatory view showing step by step a step of mounting a semiconductor element on a printed circuit board with bump electrodes.
FIG. 5 is a cross-sectional view showing a state in which a chip component is bonded to a printed circuit board with a protruding electrode.
FIG. 6 is an explanatory view showing step by step a method of manufacturing a conventional printed circuit board with bump electrodes.
[Explanation of symbols]
20 Printed circuit board
21 protruding electrode
23 Joining land
24 First conductor layer portion
25 Second conductor layer portion
26 Projection electrode formation substrate
29 Semiconductor elements
31 Electronic components

Claims (8)

突起電極が形成されるプリント基板であって、
突起電極は、それぞれ融点の異なる二層以上の導体層部分が一体的に積層されて成り、それら導体層部分のうち、最も低い融点の導体層部分がプリント基板に溶融接合されていることを特徴とする突起電極付きプリント基板。A printed circuit board on which protruding electrodes are formed,
The protruding electrode is formed by integrally laminating two or more conductor layer portions each having a different melting point, and among the conductor layer portions, the conductor layer portion having the lowest melting point is melt-bonded to the printed circuit board. Printed circuit board with protruding electrodes. 前記二層以上の導体層部分のうち、プリント基板に溶融接合されている導体層部分以外の導体層部分は、プリント基板に溶融接合されている導体層部分の厚さよりも大きく形成されることを特徴とする請求項１に記載の突起電極付きプリント基板。Of the two or more conductive layer portions, the conductive layer portion other than the conductive layer portion that is melt-bonded to the printed board is formed to be larger than the thickness of the conductive layer portion that is melt-bonded to the printed board. The printed circuit board with a protruding electrode according to claim 1. 前記二層以上の導体層部分から成る突起電極は、プリント基板に溶融接合されている導体層部分以外の導体層部分が、金、銅およびニッケルのうち少なくともいずれか一つから成る金属、または不可避不純物を含む前記金属によって構成され、プリント基板に溶融接合されている導体層部分が、インジウム、銀、錫、ビスマスおよび亜鉛のうち少なくともいずれか一つから成る金属、または不可避不純物を含む前記金属によって構成されることを特徴とする請求項１または２に記載の突起電極付きプリント基板。The projecting electrode comprising the two or more conductive layer portions is such that the conductive layer portion other than the conductive layer portion fused and bonded to the printed circuit board is made of a metal made of at least one of gold, copper and nickel, or an unavoidable metal. The conductor layer portion formed of the metal containing impurities and melt-bonded to the printed circuit board is formed of at least one of indium, silver, tin, bismuth and zinc, or the metal containing unavoidable impurities. The printed circuit board with a protruding electrode according to claim 1, wherein the printed circuit board is configured. プリント基板に溶融接合されている導体層部分において、プリント基板に臨む表面積は、プリント基板の表面積よりも小さく形成されることを特徴とする請求項１〜３のいずれかに記載の突起電極付きプリント基板。The printed surface with a protruding electrode according to any one of claims 1 to 3, wherein a surface area facing the printed circuit board is formed smaller than a surface area of the printed circuit board in the conductor layer portion that is melt-bonded to the printed circuit board. substrate. 前記突起電極を介してベアチップ半導体素子を搭載可能なプリント基板において、
プリント基板に接合材を介して接合する電子部品を含み、接合材の融点は、ベアチップ半導体素子を搭載するための突起電極のプリント基板に溶融接合される導体層部分の融点よりも低く設定されることを特徴とする請求項１に記載の突起電極付きプリント基板。In a printed circuit board capable of mounting a bare chip semiconductor element via the protruding electrode,
Including an electronic component bonded to a printed board via a bonding material, the melting point of the bonding material is set to be lower than the melting point of the conductive layer portion of the protruding electrode for mounting the bare chip semiconductor element which is melt bonded to the printed board. The printed circuit board with a protruding electrode according to claim 1. 前記接合材は、導電性接着材および錫を含む合金から成ることを特徴とする請求項５に記載の突起電極付プリント基板。The printed circuit board according to claim 5, wherein the bonding material is made of an alloy containing a conductive adhesive and tin. 突起電極形成用基板に、それぞれ融点の異なる二層以上の導体層部分を一体的に積層して、突起電極形成用基板から剥離可能に、突起電極を形成する工程と、
プリント基板に突起電極を転写する工程とを含むことを特徴とする突起電極付きプリント基板の製造方法。A step of integrally forming two or more conductor layer portions having different melting points on the projecting electrode forming substrate, and forming a projecting electrode so as to be peelable from the projecting electrode forming substrate;
Transferring a protruding electrode to a printed circuit board. プリント基板に突起電極を転写する工程は、
前記二層以上の導体層部分のうち、突起電極形成用基板から最も遠い最表層の導体層部分を溶融してプリント基板側の接合部と接合する段階と、
突起電極を突起電極形成用基板から剥離する段階とを含むことを特徴とする請求項７に記載の突起電極付きプリント基板の製造方法。The process of transferring the protruding electrodes to the printed board
Of the two or more conductive layer portions, the step of melting the outermost conductive layer portion farthest from the protruding electrode forming substrate and bonding it to the bonding portion on the printed circuit board side,
8. The method of manufacturing a printed circuit board with projecting electrodes according to claim 7, further comprising the step of: separating the projecting electrodes from the projecting electrode forming substrate.
JP2003137032A 2003-05-15 2003-05-15 Printed board with bump electrode and manufacturing method thereof Pending JP2004342802A (en)

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Cited By (10)

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JP2013141042A (en) * 2013-04-23 2013-07-18 Invensys Corp Bump structure and method of manufacturing the same
JP2014183100A (en) * 2013-03-18 2014-09-29 Fujitsu Ltd Method for joining electronic components and electronic device
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US8884448B2 (en) 2007-09-28 2014-11-11 Tessera, Inc. Flip chip interconnection with double post
JP2014236022A (en) * 2013-05-30 2014-12-15 新光電気工業株式会社 Method of manufacturing semiconductor device
US9030001B2 (en) 2010-07-27 2015-05-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10535626B2 (en) 2015-07-10 2020-01-14 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US11973056B2 (en) 2016-10-27 2024-04-30 Adeia Semiconductor Technologies Llc Methods for low temperature bonding using nanoparticles
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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8884448B2 (en) 2007-09-28 2014-11-11 Tessera, Inc. Flip chip interconnection with double post
US9030001B2 (en) 2010-07-27 2015-05-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US9397063B2 (en) 2010-07-27 2016-07-19 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US9496236B2 (en) 2010-12-10 2016-11-15 Tessera, Inc. Interconnect structure
JP2014183100A (en) * 2013-03-18 2014-09-29 Fujitsu Ltd Method for joining electronic components and electronic device
JP2013141042A (en) * 2013-04-23 2013-07-18 Invensys Corp Bump structure and method of manufacturing the same
JP2014236022A (en) * 2013-05-30 2014-12-15 新光電気工業株式会社 Method of manufacturing semiconductor device
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9818713B2 (en) 2015-07-10 2017-11-14 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10535626B2 (en) 2015-07-10 2020-01-14 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10892246B2 (en) 2015-07-10 2021-01-12 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US11710718B2 (en) 2015-07-10 2023-07-25 Adeia Semiconductor Technologies Llc Structures and methods for low temperature bonding using nanoparticles
US11973056B2 (en) 2016-10-27 2024-04-30 Adeia Semiconductor Technologies Llc Methods for low temperature bonding using nanoparticles
US12027487B2 (en) 2022-12-22 2024-07-02 Adeia Semiconductor Technologies Llc Structures for low temperature bonding using nanoparticles

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