JP2014236022A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device in which an exothermic reaction can be caused only at a desired place.SOLUTION: A method of manufacturing a semiconductor device includes the processes of: forming a reaction layer to be subjected to an exothermic reaction when supplied with energy to become an alloy on a plurality of first pads formed on a first substrate in a mutually electrically independent state; forming a conductive layer which electrically connects reaction layers to one another; arranging a second substrate, which has a plurality of second pads formed at positions corresponding to the first pads, opposite the first substrate so that the second pads and first pads come into contact with each other through the conductive layer and reaction layers; and supplying the energy to the conductive layer to alloy the reaction layers into alloy layers, and joining the first pads and second pads together through the alloy layers.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Conventionally, a method using a reactive multilayer foil is known as a method of connecting two connection objects. The reactive multilayer foil is a film-like member having a predetermined thickness by alternately laminating thin metal layers made of a reactive material that generates an exothermic reaction when supplied with energy.

  Specifically, a joining member having a structure in which both surfaces of a film-like reactive multilayer foil are sandwiched between molten metal layers (solder or the like) is prepared, and two connection objects are stacked via the joining member. Then, it is disclosed that energy is supplied to the reactive multilayer foil to generate heat, the molten metal layer is melted by this heat generation, and two connection objects are joined.

JP 2012-186214 A

  However, in the above technique, since a film-like reactive multilayer foil made separately from the object to be joined is used, an exothermic reaction occurs in a place other than a place where reaction is desired (a place where heat is desired), An alloy is formed from the reactive multilayer foil. Therefore, a plurality of terminals formed on the object to be bonded are locally bonded via a reactive multilayer foil, or a predetermined region such as a semiconductor substrate is locally heated (annealed) using a reactive multilayer foil. I could n’t.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can cause an exothermic reaction only at a desired location.

  In this method of manufacturing a semiconductor device, reaction layers that cause an exothermic reaction and are alloyed by being supplied with energy on a plurality of first pads formed on a first substrate are electrically independent from each other. A step of forming, a step of forming a conductive layer that electrically connects the reaction layers, and a second substrate having a plurality of second pads formed at positions corresponding to the plurality of first pads, A step of disposing the second pad and the first pad so as to be in contact with each other via the conductive layer and the reaction layer; and supplying energy to the conductive layer to form the reaction layer. And forming an alloy layer by alloying and joining the plurality of first pads and the plurality of second pads via the alloy layer.

  According to the disclosed technology, it is possible to provide a method for manufacturing a semiconductor device that can cause an exothermic reaction only at a desired location.

1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. 6 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device according to the first embodiment; FIG. FIG. 6 is a second diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a diagram (part 3) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 8 is a diagram (No. 4) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; It is a top view which illustrates the seed layer concerning the modification of a 1st embodiment. 6 is a cross-sectional view illustrating a semiconductor device according to a second embodiment; FIG. FIG. 10 is a diagram (part 1) illustrating a manufacturing process of a semiconductor device according to the second embodiment; FIG. 10 is a second diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment; FIG. 10 is a diagram (No. 3) for exemplifying the manufacturing process for the semiconductor device according to the second embodiment; FIG. 14 is a diagram (No. 4) for exemplifying the manufacturing process for the semiconductor device according to the second embodiment; 6 is a cross-sectional view illustrating a semiconductor device according to a modification of the second embodiment; FIG. It is a figure which illustrates the manufacturing process of the semiconductor device which concerns on the modification of 2nd Embodiment. 6 is a cross-sectional view illustrating a semiconductor device according to a third embodiment; FIG. FIG. 11 is a first diagram illustrating a manufacturing process of a semiconductor device according to a third embodiment; FIG. 10 is a second diagram illustrating a manufacturing process of the semiconductor device according to the third embodiment;

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and the overlapping description may be abbreviate | omitted.

<First Embodiment>
[Structure of Semiconductor Device According to First Embodiment]
First, the structure of the semiconductor device according to the first embodiment will be described. FIG. 1 is a cross-sectional view illustrating the semiconductor device according to the first embodiment.

  Referring to FIG. 1, the semiconductor device 1 includes a substrate 10, a semiconductor element 20, and an alloy layer 30.

  The substrate 10 includes a substrate body 11 and a plurality of pads 12. As a material of the substrate body 11, for example, silicon, ceramics, insulating resin, or the like can be used. The thickness of the substrate body 11 can be, for example, about several mm. A wiring layer (not shown) is formed in the upper and lower surfaces of the substrate body 11 or in the substrate body 11. External connection terminals may be formed on the lower surface of the substrate body 11.

  For example, the pads 12 are arranged vertically and horizontally on the upper surface of the substrate body 11. The pad 12 is electrically connected to a wiring layer (not shown) formed on the substrate body 11. The planar shape of the pad 12 can be a circular shape having a diameter of about several tens of μm, for example. However, the planar shape of the pad 12 may be an elliptical shape, a rectangular shape, a polygonal shape, or the like. The pitch of the pads 12 can be set to, for example, about 50 to 100 μm.

  For example, the pad 12 has a structure in which a metal layer 12a and a metal layer 12b are stacked. As a material of the metal layer 12a, for example, titanium (Ti) or the like can be used. The thickness of the metal layer 12a can be about 40 to 60 nm, for example. As the material of the metal layer 12b, for example, palladium (Pd) or the like can be used. The thickness of the metal layer 12b can be, for example, about 20 to 40 nm. However, the pad 12 does not necessarily have a two-layer structure, and may have a one-layer structure or a structure having three or more layers. The pad 12 is a typical example of the pad and the second pad according to the present invention.

  The semiconductor element 20 includes a semiconductor substrate 21 and a plurality of pads 22. The semiconductor substrate 21 is a substrate mainly composed of a semiconductor material such as silicon or gallium arsenide. The thickness of the semiconductor substrate 21 can be, for example, about several tens to several hundreds of μm. A semiconductor integrated circuit (not shown) is formed on the semiconductor substrate 21.

  The pad 22 is formed at a position facing the pad 12 of the substrate 10 on the circuit formation surface of the semiconductor substrate 21. The pad 22 is electrically connected to a semiconductor integrated circuit (not shown) formed on the semiconductor substrate 21. The planar shape of the pad 22 can be a circular shape having a diameter of about several tens of μm, for example. However, the planar shape of the pad 22 may be an elliptical shape, a rectangular shape, a polygonal shape, or the like. The pitch of the pads 22 can be set to, for example, about 50 to 100 μm. As a material of the pad 22, for example, aluminum (Al), copper (Cu), or the like can be used. The thickness of the pad 22 can be set to, for example, about 50 to 100 nm. The pad 22 may have a structure in which a plurality of layers are stacked. The pad 22 is a typical example of the first pad according to the present invention.

  The alloy layer 30 is sandwiched between the pad 12 of the substrate 10 and the pad 22 of the semiconductor element 20 and joins (electrically connects) the two. The planar shape of the alloy layer 30 can be, for example, a circular shape having a diameter of about several tens of μm. However, the planar shape of the alloy layer 30 may be an elliptical shape, a rectangular shape, a polygonal shape, or the like. The pitch of the alloy layer 30 can be about 50-100 micrometers, for example. The alloy layer 30 may be, for example, an aluminum / palladium alloy (AlPd alloy) layer containing titanium (Ti) and gold (Au). The thickness of the alloy layer 30 can be set to about several μm, for example.

[Method of Manufacturing Semiconductor Device According to First Embodiment]
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 2 to 5 are diagrams illustrating the manufacturing process of the semiconductor device according to the first embodiment. Note that in this embodiment, an example of a process in which a part to be a plurality of semiconductor devices is manufactured using a silicon wafer or the like and then separated into individual semiconductor devices is illustrated; however, as a process for manufacturing a single semiconductor device Also good.

  First, in the process shown in FIG. 2A, a semiconductor wafer 210 in which pads 22 are formed in a plurality of regions to be the semiconductor substrate 21 is prepared. As the semiconductor wafer 210, for example, a silicon wafer of 6 inches (about 150 mm), 8 inches (about 200 mm), 12 inches (about 300 mm), or the like can be used. As the pad 22, for example, aluminum (Al), copper (Cu), or the like can be used. For example, the pads 22 are arranged vertically and horizontally.

  The thickness of the silicon wafer is, for example, 0.625 mm (in the case of 6 inches), 0.725 mm (in the case of 8 inches), 0.775 mm (in the case of 12 inches), etc. The thickness can be appropriately reduced. Note that a gallium arsenide wafer or the like may be used instead of the silicon wafer. C indicates a position where the semiconductor wafer 210 is finally cut (hereinafter referred to as a cutting position C).

  Next, in the step shown in FIG. 2B, a resist 300 having an opening 300x exposing the pad 22 is formed on the circuit formation surface of the semiconductor wafer 210. Specifically, first, a resist 300 that covers the pad 22 is formed on the entire surface of the circuit formation surface of the semiconductor wafer 210. As the resist 300, for example, a photosensitive resin or the like can be used. Thereafter, the resist 300 is exposed and developed to remove the resist 300 on the pad 22 to form an opening 300x.

  Next, in the step shown in FIG. 2C, the reaction layer 31 is formed on the pad 22 exposed in the opening 300 x and on the resist 300. The reaction layer 31 may be formed on the inner wall surface of the opening 300x of the resist 300. The reaction layer 31 is a layer that undergoes a reaction that generates heat (exothermic reaction) and is alloyed when energy is supplied in a subsequent process. The reaction layer 31 is a layer formed by stacking a plurality of stacked layers in which a plurality of metal layers are stacked. Specifically, as shown in FIG. 3A, the reaction layer 31 is a first metal layer. A stacked body 31c in which the second metal layer 31b is stacked on 31a is stacked in multiple layers.

  As the material of the first metal layer 31a, for example, aluminum (Al) can be used, and as the material of the second metal layer 31b, for example, palladium (Pd) can be used. Each thickness of the 1st metal layer 31a and the 2nd metal layer 31b can be about 20-60 nm, for example. The first metal layer 31a and the second metal layer 31b can be formed by, for example, sputtering.

  When the first metal layer 31a is an aluminum (Al) layer having a thickness of about 40 nm and the second metal layer 31b is a palladium (Pd) layer having a thickness of about 40 nm, the number of stacked layers 31c is about 25. (The total thickness of the reaction layer 31 can be about 2 μm). Thereby, when the reaction layer 31 is reacted, a predetermined calorific value (in this case, about 1500 ° C.) can be obtained.

  As the first metal layer 31a / second metal layer 31b, instead of aluminum (Al) / palladium (Pd), aluminum (Al) / nickel (Ni), aluminum (Al) / titanium (Ti), nickel ( Ni) / silicon (Si) or the like may be used. These layers can be appropriately selected according to the purpose, but the first metal layer 31a / second metal layer 31b are made of aluminum (Al) / palladium (Pd) in that a predetermined calorific value can be obtained with a small number of layers. Is preferred.

  The first metal layer 31a / second metal layer 31b can be made of palladium (Pd) / aluminum (Al) (even if the stacking order is changed), and the same effect can be obtained. That is, it is preferable that one of the first metal layer 31a and the second metal layer 31b is aluminum and the other is palladium.

  Next, in the step shown in FIG. 3B, the resist 300 shown in FIG. 2C is peeled off (lift-off method). As a result, the reaction layers 31 are formed on the plurality of pads 22 formed on the semiconductor wafer 210 in a state of being electrically independent from each other. For example, if the pads 12 are arranged vertically and horizontally, the reaction layers 31 are also arranged vertically and horizontally.

  Next, in the step shown in FIG. 3C, a seed layer 310, which is a conductive layer that electrically connects the reaction layers 31 to each other, is formed. More specifically, a seed layer 310 is formed to cover the side surface of the pad 22, the upper and side surfaces of the reaction layer 31, and the entire circuit formation surface (excluding the pad 22 formation portion) of the semiconductor wafer 210. As the seed layer 310, for example, a titanium (Ti) layer can be formed by a sputtering method or the like. The thickness of the seed layer 310 can be about 30 nm, for example. As the seed layer 310, a copper (Cu) layer, an aluminum (Al) layer, or the like may be used instead of the titanium (Ti) layer.

  Next, in the step shown in FIG. 4A, a substrate 110 having a plurality of pads 120 formed at positions corresponding to the plurality of pads 22 is prepared. Then, the substrate 110 is disposed opposite to the semiconductor wafer 210 so that the pad 120 and the pad 22 are in contact with each other through the seed layer 310 and the reaction layer 31. As a material of the substrate 110, for example, silicon, ceramics, insulating resin, or the like can be used. The thickness of the substrate 110 can be, for example, about several mm.

  The pad 120 has, for example, a structure in which a metal layer 12a, a metal layer 12b, and a metal layer 12c are stacked. As a material of the metal layer 12a, for example, titanium (Ti) or the like can be used. The thickness of the metal layer 12a can be about 40 to 60 nm, for example. As the material of the metal layer 12b, for example, palladium (Pd) or the like can be used. The thickness of the metal layer 12b can be, for example, about 20 to 40 nm. As a material of the metal layer 12c, for example, gold (Au) or the like can be used. The thickness of the metal layer 12c can be about 5 to 20 nm, for example.

  Next, in the step shown in FIG. 4B, energy is supplied to, for example, the arrowed portion of the seed layer 310. As a method of supplying energy, for example, a method of sparking by applying an electric pulse, a method of irradiating laser light, or the like can be used. By supplying energy to the seed layer 310, the reaction layer 31 causes an exothermic reaction to be alloyed, and the alloy layer 30 is formed as shown in FIG. During the alloying reaction, the vicinity of the reaction layer 31 is locally heated to about 1500 ° C.

  The reaction layers 31 electrically connected by the seed layer 310 react in a chain manner, and all the reaction layers 31 become the alloy layers 30. That is, energy is supplied to the seed layer 310 and one reaction layer 31 causes an exothermic reaction. The energy propagates to the other reaction layer 31 through the seed layer 310, and the other reaction layers 31 generate heat in a chain. Cause a reaction.

  Note that when the reaction layer 31 is alloyed, a part of the seed layer 310 (a portion sandwiched between the reaction layer 31 and the metal layer 12 c) and the metal layer 12 c are taken into the alloy layer 30. Further, the other part of the seed layer 310 remains around the alloy layer 30. Thus, the pad 120 becomes a pad 12 having a structure in which the metal layer 12a and the metal layer 12b are laminated. For example, when the reaction layer 31 has a structure in which an aluminum layer and a palladium layer are laminated, the seed layer 310 is titanium, and the metal layer 12c is gold, the alloy layer 30 contains titanium and gold. It becomes a layer of an aluminum-palladium alloy (AlPd alloy).

  Next, in the step shown in FIG. 5B, the unnecessary seed layer 310 (the other part of the seed layer 310 remaining around the alloy layer 30) is removed by etching. As a result, a structure in which the pads 12 of the substrate 110 and the pads 22 of the semiconductor wafer 210 are joined (electrically connected) via the alloy layer 30 is completed. After that, the structure shown in FIG. 5B is cut into pieces by cutting at a cutting position C, whereby the pads 12 of the substrate 10 and the pads 22 of the semiconductor element 20 are joined (electrically) via the alloy layer 30. A plurality of connected semiconductor devices 1 (see FIG. 1) are manufactured.

  After the step shown in FIG. 5A, the structure shown in FIG. 5A is cut into pieces by cutting at a cutting position C, and an unnecessary seed layer 310 is etched for each piece of the separated structure. It is good also as a process of removing by doing. Such a process is preferable in that the etching solution can easily reach each part of the seed layer 310 and the seed layer 310 can be etched reliably.

  As described above, in the first embodiment, the reaction layers 31 are formed between a plurality of terminals (pads) to be connected in an electrically independent state, and the reaction layers 31 are electrically connected to each other by the seed layer 310. Connecting. Then, energy is supplied to the seed layer 310 to cause the reaction layers 31 electrically connected by the seed layer 310 to react in a chain manner, and the alloy layer 30 is formed from the reaction layers 31.

  Thereby, between a plurality of terminals (between pads) can be joined almost simultaneously by the alloy layer 30 (parts other than between the terminals are not joined). In addition, in the conventional technique, since a film-like reactive multilayer foil made separately from an object to be joined is used, an exothermic reaction occurs in a place other than a place where a reaction is desired (a place where heat is desired), An alloy is formed from the reactive multilayer foil. Therefore, as in the present embodiment, it has not been possible to connect a plurality of terminals (between pads) individually (locally) and substantially simultaneously.

  Further, since the reaction layer 31 can be formed by combining, for example, a sputtering method, a lift-off method, or the like, it can be formed on each terminal (pad) with high accuracy even when a plurality of terminals (pads) have a narrow pitch. In addition, since the exothermic reaction occurs only in the reaction layer 31, the thermal effect on the semiconductor element 20 and the like can be greatly reduced as compared with the case where a film-like reactive multilayer foil is used. In addition, since the terminals (pads) are joined by the high melting point alloy layer 30, for example, the connection reliability (electromigration resistance and mechanical properties) can be improved as compared with the case of joining with a low melting point metal such as solder. Strength, etc.) can be improved.

  In addition, the film-like reactive multilayer foil is expensive (because it is laminated more than necessary) because a laminate of two different types of metal layers is laminated (more than necessary), and the amount of generated heat can be controlled. Have difficulty. On the other hand, in the present embodiment, two different metal layers can be stacked with a required thickness and a required number of layers so as to obtain a required calorific value, so that the manufacturing cost can be reduced and the calorific value can be controlled. Is easy. In particular, when a pair of an aluminum layer and a palladium layer having a thickness of about 40 nm is used as two different metal layers, a predetermined calorific value can be obtained with a small number of laminations of about 25 layers, thereby reducing the manufacturing cost. It can contribute greatly.

  Even if a resin substrate, a ceramic substrate, or the like is used instead of the semiconductor substrate 21, the pad 12 of the substrate 10 and the pad of the resin substrate, the ceramic substrate, or the like can be bonded by the alloy layer 30 by the method described above.

<Modification of First Embodiment>
In the modification of the first embodiment, an example in which a seed layer having a different form from the seed layer 310 is formed in the step shown in FIG. 3C of the first embodiment. In the modification of the first embodiment, the description of the same components as those of the already described embodiment is omitted.

  FIG. 6 is a plan view illustrating a seed layer according to a modification of the first embodiment. In FIG. 6, for convenience, the seed layers 320 and 330 are shown in a satin pattern.

  FIG. 6A is a first example, and FIG. 6B is a second example. In the first example shown in FIG. 6A, the seed layer 320 which is a conductive layer is formed in a lattice shape so as to intersect on the reaction layer 31. In other words, the lattice-like seed layer 320 is formed on the semiconductor wafer 210 so as to be electrically connected to each reaction layer 31 at the intersection. That is, in the process shown in FIG. 3C of the first embodiment, the seed layer 310 covering the entire circuit forming surface of the semiconductor wafer 210 is formed. However, as shown in FIG. A seed layer 320 that partially covers the circuit forming surface of the wafer 210 may be formed. However, the seed layer 320 must be formed so as to be in conduction with the reaction layer 31 without fail.

  Thus, by forming the seed layer 320 that partially covers the circuit formation surface of the semiconductor wafer 210, the seed layer 320 can be formed thin, so that the current density of the seed layer 320 can be improved. As a result, there is an effect that the reaction layer 31 is easily caused to react by the energy supplied to the seed layer 320.

  As in the second example shown in FIG. 6B, when a seed layer 330 in which a portion passing through the reaction layer 31 is formed thinner than other portions is used, the seed of the portion passing through the reaction layer 31 is used. The current density of the layer 330 can be further improved. As a result, there is an effect that the reaction layer 31 is more easily caused to react by the energy supplied to the seed layer 330.

<Second Embodiment>
In the second embodiment, an example of a method for manufacturing a semiconductor device in which a predetermined region of a semiconductor substrate is locally heated (annealed) using a reaction layer will be described. In the second embodiment, the description of the same components as those of the already described embodiments is omitted.

[Structure of Semiconductor Device According to Second Embodiment]
First, the structure of the semiconductor device according to the second embodiment will be described. FIG. 7 is a cross-sectional view illustrating a semiconductor device according to the second embodiment.

  Referring to FIG. 7, a semiconductor device 2 includes a semiconductor substrate 41, an impurity doped region 42, an insulating film 43, an insulating film 44, a through electrode 46, an alloy layer 47, a wiring layer 48, and a wiring layer. 49, a seed layer 360, and a seed layer 370.

  A plurality of impurity doped regions 42 are formed on one side of the semiconductor substrate 41. The semiconductor substrate 41 is, for example, silicon. The impurity doped region 42 is, for example, a region where impurities such as phosphorus (n-type dopant) and boron (p-type dopant) are added to the semiconductor substrate 41. The semiconductor substrate 41 is provided with a through hole 41x. An insulating film 43 is formed on one surface of the semiconductor substrate 41. An insulating film 44 is formed on the other surface of the semiconductor substrate 41 and the inner wall surface of the through hole 41x. A through electrode 46 is formed in the through hole 41x in which the insulating film 44 is formed on the inner wall surface.

  The upper end surface of the through electrode 46 is exposed from the insulating film 43, and the lower end surface of the through electrode 46 is exposed from the insulating film 44. A seed layer 360 and a wiring layer 48 are stacked on the upper end surface of the through electrode 46. A seed layer 370 and a wiring layer 49 are stacked on the lower end surface of the through electrode 46. In the insulating film 43, an opening 43x exposing the impurity doped region 42 is formed. The alloy layer 47 is formed on the insulating film 43 and is electrically connected to the impurity doped region 42 through the opening 43x. A wiring layer 48 is laminated on the alloy layer 47.

  The alloy layer 47 can be, for example, an aluminum / palladium alloy (AlPd alloy) layer containing titanium (Ti). The thickness of the alloy layer 47 can be, for example, about several μm. In the wiring layer 48, for example, a metal layer 48a (eg, copper), a metal layer 48b (eg, nickel), and a metal layer 48c (eg, gold) are sequentially laminated on the alloy layer 47 or the seed layer 360. The structure can be made. The wiring layer 49 has a structure in which, for example, a metal layer 49a (for example, copper), a metal layer 49b (for example, nickel), and a metal layer 49c (for example, gold) are sequentially stacked on the seed layer 370. Can do.

[Method of Manufacturing Semiconductor Device According to Second Embodiment]
Next, a method for manufacturing a semiconductor device according to the second embodiment will be described. 8 to 11 are diagrams illustrating a manufacturing process of the semiconductor device according to the second embodiment. Note that in this embodiment, an example of a process in which a part to be a plurality of semiconductor devices is manufactured using a silicon wafer or the like and then separated into individual semiconductor devices is illustrated; however, as a process for manufacturing a single semiconductor device Also good.

  First, in the process shown in FIG. 8A, a semiconductor wafer 410 having a plurality of regions to be the semiconductor substrate 41 is prepared, and a plurality of impurity doped regions 42 (active regions) on one side of each region to be the semiconductor substrate 41 are prepared. Layer). Then, the insulating film 43 is formed on the circuit formation surface of the semiconductor wafer 410.

  As the semiconductor wafer 410, for example, the same semiconductor wafer 210 as that of the first embodiment can be used. As the insulating film 43, for example, a silicon nitride film (SiN film) or the like can be used. The impurity doped region 42 can be formed by adding an impurity such as phosphorus (n-type dopant) or boron (p-type dopant) by an ion implantation method or the like, for example. The insulating film 43 can be formed by, for example, sputtering. The thickness of the insulating film 43 can be about 1 μm, for example. C indicates a position at which the semiconductor wafer 410 is finally cut (hereinafter referred to as a cutting position C).

  Next, in the step shown in FIG. 8B, the through hole 41 x is formed in the semiconductor wafer 410. The through hole 41x can be formed by, for example, RIE (Reactive Ion Etching) or the like. The planar shape of the through hole 41x can be, for example, a circular shape having a diameter of about several tens of μm. The pitch of the through holes 41x can be set to about 50 to 100 μm, for example.

Next, in the step shown in FIG. 8C, the insulating film 44 is formed on the inner wall surface of the through hole 41x and the back surface of the semiconductor wafer 410 (surface opposite to the circuit formation surface). As the insulating film 44, for example, a thermal oxide film (SiO ₂ film) or the like can be used. The insulating film 44 can be formed by thermal oxidation using a wet thermal oxidation method in which the temperature in the vicinity of the surface of the semiconductor wafer 410 is, for example, about 1100 ° C. The thickness of the insulating film 44 can be set to about 1 μm, for example.

  Next, in the step shown in FIG. 9A, a resist 340 having an opening 340 x exposing a part of the insulating film 43 covering the impurity doped region 42 is formed on the insulating film 43. Specifically, first, a resist 340 made of a photosensitive resin or the like is formed on the entire surface of the insulating film 43. Thereafter, the resist 340 is exposed and developed to remove the resist 340 covering a part of the insulating film 43 covering the impurity doped region 42, thereby forming an opening 340x. Thereafter, the insulating film 43 exposed in the opening 340 x is removed by etching using the resist 340 as a mask, and the opening 43 x is formed in the insulating film 43. A part of the impurity doped region 42 is exposed in the opening 43x. Thereafter, the resist 340 is removed.

  Next, in the step shown in FIG. 9B, a resist 350 having an opening portion 350 x that exposes the opening portion 43 x and the insulating film 43 in the periphery thereof is formed on the insulating film 43. Specifically, first, a resist 350 made of a photosensitive resin or the like is formed on the entire surface of the insulating film 43. Thereafter, the resist 350 is exposed and developed to remove the resist 350 covering the opening 43x and the insulating film 43 in the periphery thereof, thereby forming the opening 350x.

  Next, in the step shown in FIG. 9C, the reaction layer 45 is formed on the impurity doped region 42 exposed in the opening 43x, the insulating film 43 exposed in the opening 350x, and the resist 350. . The reaction layer 45 may be formed on the inner wall surface of the opening 350x of the resist 350. The structure of the reaction layer 45 can be the same as the structure of the reaction layer 31 shown in FIG.

  Next, in the step shown in FIG. 10A, the resist 350 shown in FIG. 9C is peeled off (lift-off method). As a result, the reaction layer 45 is formed on the plurality of impurity doped regions 42 formed on one side of the semiconductor wafer 410 in a state of being electrically independent from each other. More specifically, a reaction layer 45 extending from the impurity doped region 42 exposed in the opening 43x to the insulating film 43 around the opening 43x is formed. The reaction layer 45 is electrically connected to the impurity doped region 42.

  Next, in the step shown in FIG. 10B, the through electrode 46 is formed in the through hole 41x. The through electrode 46 can be formed, for example, by filling the through hole 41x with a copper paste. The through electrode 46 may be formed by an electroless plating method, an electrolytic plating method, or the like.

  Next, in a step shown in FIG. 10C, a seed layer 360 that is a conductive layer that electrically connects the reaction layers 45 to each other is formed. More specifically, a seed layer 360 that covers the upper and side surfaces of the reaction layer 45, the upper end surface of the through electrode 46, and the upper surface of the insulating film 43 that is not covered with the reaction layer 45 is formed. Further, a seed layer 370 that covers the lower end surface of the through electrode 46 and the lower surface of the insulating film 44 is formed. The material, formation method, and the like of the seed layers 360 and 370 can be the same as those of the seed layer 310, for example.

  Next, in the step shown in FIG. 11A, the wiring layer 48 is formed on the seed layer 360 covering the upper surface of the reaction layer 45 and on the seed layer 360 covering the upper end surface of the through electrode 46. Further, the wiring layer 49 is formed on the seed layer 370 that covers the lower end surface of the through electrode 46. The wiring layer 48 has, for example, a structure in which a metal layer 48a (for example, copper), a metal layer 48b (for example, nickel), and a metal layer 48c (for example, gold) are sequentially stacked on the seed layer 360. Can do. The wiring layer 49 has a structure in which, for example, a metal layer 49a (for example, copper), a metal layer 49b (for example, nickel), and a metal layer 49c (for example, gold) are sequentially stacked on the seed layer 370. Can do. The wiring layers 48 and 49 can be formed by, for example, a semi-additive method. At this time, the seed layers 360 and 370 can be used as a power feeding layer when electrolytic plating is performed.

  After the wiring layers 48 and 49 are formed, energy is supplied to the seed layer 360, for example, in the direction of the arrow in the same manner as in the step shown in FIG. By supplying energy to the seed layer 360, the reaction layer 45 causes an exothermic reaction to be alloyed, and an alloy layer 47 is formed as shown in FIG. During the alloying reaction, the vicinity of the reaction layer 45 is locally heated to about 1500 ° C.

  The reaction layers 45 electrically connected by the seed layer 360 react in a chain manner, and all the reaction layers 45 become the alloy layers 47. That is, when energy is supplied to the seed layer 360, one reaction layer 45 causes an exothermic reaction, the energy propagates to the other reaction layer 45 through the seed layer 360, and the other reaction layers 45 generate heat in a chain. Cause a reaction. Due to the heat generated when the reaction layer 45 is alloyed, the plurality of impurity doped regions 42 are annealed and activated substantially simultaneously.

  In addition, when the reaction layer 45 is alloyed, a part of the seed layer 360 (a portion sandwiched between the reaction layer 45 and the metal layer 48 a) is taken into the alloy layer 47. Further, the other part of the seed layer 360 remains around the alloy layer 47. For example, when the reaction layer 45 has a structure in which an aluminum (Al) layer and a palladium (Pd) layer are stacked and the seed layer 360 is titanium (Ti), the alloy layer 47 contains titanium (Ti). It becomes a layer of an aluminum-palladium alloy (AlPd alloy).

  Next, in the step shown in FIG. 11C, unnecessary seed layers 360 and 370 are removed by etching. Note that the portion of the seed layer 360 covered with the wiring layer 48 and the portion of the seed layer 370 covered with the wiring layer 49 remain because they are not etched. Thereafter, the structure shown in FIG. 11C is cut into pieces by cutting at the cutting position C, whereby a plurality of semiconductor devices 2 (see FIG. 7) are manufactured.

  After the step shown in FIG. 11B, the structure shown in FIG. 11B is cut into pieces by cutting at a cutting position C. Unnecessary seed layers 360 and 370 are separated for each of the pieces. It is good also as a process of removing by etching.

  As described above, in the second embodiment, the reaction layers 45 are formed in the plurality of impurity doped regions 42 in an electrically independent state, and the reaction layers 45 are electrically connected by the seed layer 360. Then, energy is supplied to the seed layer 360 to cause the reaction layers 45 electrically connected by the seed layer 360 to react in a chain manner, and the alloy layer 47 is formed from the reaction layers 45. At this time, the plurality of impurity doped regions 42 can be annealed and activated substantially simultaneously by heat generated when the reaction layer 45 is alloyed.

  In the conventional annealing, for example, the entire object (semiconductor device or the like) is heated using a heater (heater annealing). Further, the entire object (semiconductor device or the like) was heated using a flash lamp (flash lamp annealing). Further, a portion of the object (semiconductor device, etc.) to be annealed is irradiated with laser light and locally heated (laser annealing).

  In heater annealing and flash lamp annealing, the entire object (semiconductor device, etc.) is heated, so if a material with a different thermal expansion coefficient from a semiconductor substrate such as a through electrode or wiring is formed, the difference in thermal expansion coefficient Electrode disconnection or wiring peeling occurs. In addition, although the laser annealing can be locally heated, there are problems that an expensive facility is required and that it takes time to individually heat the target portion. In any of these methods, when a through electrode or a wiring is formed after the activation process by annealing, it is necessary to remove the oxide film of the metal layer formed by the activation process or the adhesion is deteriorated. There was a risk of such problems.

  On the other hand, in this embodiment, since only the portion where the reaction layer 45 is formed can be locally heated, there is no problem with the through electrode, the wiring, or the like, unlike the conventional heater annealing or flash lamp annealing. Further, by reacting the plurality of impurity doped regions 42 substantially simultaneously, the activation process can be speeded up as compared with the conventional laser annealing. Further, the reaction of the reaction layer 45 forms an alloy layer 47 that is electrically connected to the impurity-doped region 42. The alloy layer 47 is characterized by excellent heat resistance and peel strength.

<Modification of Second Embodiment>
In the modification of the second embodiment, an example is shown in which annealing is performed on a semiconductor device in which impurity doped regions are formed on one side and the other side of a semiconductor substrate. In the modification of the second embodiment, the description of the same components as those of the already described embodiment is omitted.

  FIG. 12 is a cross-sectional view illustrating a semiconductor device according to a variation of the second embodiment. Referring to FIG. 12, in the semiconductor device 3, the semiconductor device 2 according to the second embodiment (see FIG. 7) is that the impurity doped region 52 and the alloy layer 57 are formed on the other side of the semiconductor substrate 41. ) Is different. The impurity doped region 52 is a typical example of the second impurity doped region according to the present invention.

  In the insulating film 44, an opening 44x exposing the impurity doped region 52 is formed. The alloy layer 57 is formed on the insulating film 44 and is electrically connected to the impurity doped region 52 through the opening 44x. A wiring layer 49 is laminated on the alloy layer 57. The material and the like of the impurity doped region 52 and the alloy layer 57 can be the same as the material of the impurity doped region 42 and the alloy layer 47, for example.

  When the impurity doped region 52 is formed on the other side of the semiconductor substrate 41, it is necessary to activate the other side of the semiconductor substrate 41 by annealing. In order to anneal the other side of the semiconductor substrate 41, the reaction layer 55 is formed on the plurality of impurity doped regions 52 formed on the other side of the semiconductor wafer 410 by the same process as in the second embodiment. It is formed in an electrically independent state. More specifically, a reaction layer 55 extending from the impurity doped region 52 exposed in the opening 44x to the insulating film 44 around the opening 44x is formed. Reaction layer 55 is electrically connected to impurity doped region 52.

  Then, a seed layer 370 that is a second conductive layer that electrically connects the reaction layers 55 to each other is formed. More specifically, a seed layer 370 that covers the lower surface and side surfaces of the reaction layer 55, the lower end surface of the through electrode 46, and the lower surface of the insulating film 44 not covered with the reaction layer 55 is formed. The reaction layer 55 is a typical example of the second reaction layer according to the present invention.

  Next, as shown in FIG. 13, the wiring layer 48 is formed on the seed layer 360 covering the upper surface of the reaction layer 45 and on the seed layer 360 covering the upper end surface of the through electrode 46. In addition, the wiring layer 49 is formed on the seed layer 370 that covers the lower surface of the reaction layer 55 and on the seed layer 370 that covers the lower end surface of the through electrode 46. Then, energy is supplied to the seed layers 360 and 370 in the same manner as in the step shown in FIG. Due to the heat generated when the reaction layer 45 is alloyed, the plurality of impurity doped regions 42 are annealed and activated substantially simultaneously. Further, the plurality of impurity doped regions 52 are annealed and activated substantially simultaneously by heat generated when the reaction layer 55 is alloyed. Further, after performing the same process as in FIG. 11C, the semiconductor device 3 (see FIG. 12) is manufactured in a plurality of pieces by dividing into pieces.

  As described above, even when annealing is performed on a semiconductor device in which impurity doped regions are formed on both sides of the semiconductor substrate, the same effects as those of the second embodiment can be obtained.

<Third Embodiment>
In the third embodiment, an example in which the connection between the substrate and the semiconductor device and annealing are performed substantially simultaneously will be described. In the third embodiment, the description of the same components as those of the already described embodiments is omitted.

  FIG. 14 is a cross-sectional view illustrating a semiconductor device according to the third embodiment. Referring to FIG. 14, the semiconductor device 4 includes a substrate 10 and a semiconductor device 2A, and the pad 12 of the substrate 10 and the alloy layer 47 of the semiconductor device 2A are bonded. The semiconductor device 2 </ b> A has the same structure as the semiconductor device 2 shown in FIG. 7 except that the wiring layer 48 is not formed on the alloy layer 47.

  15 and 16 are diagrams illustrating the manufacturing process of the semiconductor device according to the third embodiment. Note that in this embodiment, an example of a process in which a part to be a plurality of semiconductor devices is manufactured using a silicon wafer or the like and then separated into individual semiconductor devices is illustrated; however, as a process for manufacturing a single semiconductor device Also good.

  First, in the step shown in FIG. 15A, a structure similar to that shown in FIG. 11A is manufactured by the same steps as those shown in FIGS. 8A to 11A. However, the wiring layer 48 is not formed on the seed layer 360 that covers the upper surface of the reaction layer 45. 4A, the substrate 110 on which the plurality of pads 120 are formed at positions corresponding to the plurality of reaction layers 45 is converted into a seed layer 360 in which the reaction layers 45 and the pads 120 are conductive layers. The semiconductor wafer 410 is disposed so as to be in contact with each other.

  Next, in the step shown in FIG. 15B, energy is supplied to the seed layer 360 in the same manner as the step shown in FIG. By supplying energy to the seed layer 360, the reaction layer 45 causes an exothermic reaction to be alloyed, and an alloy layer 47 is formed as shown in FIG. During the alloying reaction, the vicinity of the reaction layer 45 is locally heated to about 1500 ° C.

  The reaction layers 45 electrically connected by the seed layer 360 react in a chain manner, and all the reaction layers 45 become the alloy layers 47. That is, when energy is supplied to the seed layer 360, one reaction layer 45 causes an exothermic reaction, the energy propagates to the other reaction layer 45 through the seed layer 360, and the other reaction layers 45 generate heat in a chain. Cause a reaction. Due to the heat generated when the reaction layer 45 is alloyed, the plurality of impurity doped regions 42 are annealed and activated substantially simultaneously.

  Note that when the reaction layer 45 is alloyed, a part of the seed layer 360 (a portion sandwiched between the reaction layer 45 and the metal layer 12 c) and the metal layer 12 c are taken into the alloy layer 47. Further, the other part of the seed layer 360 remains around the alloy layer 47. Thus, the pad 120 becomes a pad 12 having a structure in which the metal layer 12a and the metal layer 12b are laminated. For example, when the reaction layer 45 has a structure in which an aluminum layer and a palladium layer are laminated, the seed layer 360 is titanium, and the metal layer 12c is gold, the alloy layer 47 contains titanium and gold. It becomes a layer of aluminum-palladium alloy.

  In this way, energy is supplied to the seed layer 360 to alloy the reaction layer 45 to form the alloy layer 47, and the plurality of impurity doped regions 42 and the plurality of pads 12 are joined via the alloy layer 47, A plurality of impurity doped regions 42 can be activated.

  Next, in the step shown in FIG. 16B, unnecessary seed layers 360 and 370 are removed by etching. Thereby, a structure in which the pad 12 of the substrate 110 and the alloy layer 47 of the semiconductor wafer 410 are joined is completed. Thereafter, the structure shown in FIG. 16B is cut into pieces by cutting at a cutting position C, whereby the semiconductor device 4 in which the pad 12 of the substrate 10 and the alloy layer 47 of the semiconductor device 2A are joined (see FIG. 14). ) Are produced.

  After the step shown in FIG. 16A, the structure shown in FIG. 16A is cut into pieces by cutting at a cutting position C. Unnecessary seed layers 360 and 370 are separated for each piece of the separated structure. It is good also as a process of removing by etching. Such a process is preferable in that the etching solution can easily reach each part of the seed layers 360 and 370 and the seed layers 360 and 370 can be reliably etched.

  As described above, in the third embodiment, in addition to the effects in the first and second embodiments, the following effects are further achieved. That is, the impurity doped regions 42 and the pads 12 can be joined to each other by the alloy layer 47 substantially simultaneously with the activation of the impurity doped regions 42 by annealing.

  The preferred embodiment and its modification have been described in detail above, but the present invention is not limited to the above-described embodiment and its modification, and the above-described implementation is performed without departing from the scope described in the claims. Various modifications and substitutions can be added to the embodiment and its modifications.

  For example, the seed layer may be formed on the substrate side. For example, the seed layer 310 shown in FIG. 4A may be formed on the substrate 110 so as to cover the pad 120. Also in this case, since the seed layer 310 is in contact with each reaction layer 31 in the step shown in FIG. 4B, the reaction layers 31 are electrically connected to each other by the seed layer 310. Thereafter, by supplying energy to the seed layer 310, the reaction layers 31 electrically connected by the seed layer 310 react in a chain manner, and all the reaction layers 31 become the alloy layers 30.

  If the pitch between the terminals to be connected (between pads) is not narrow, obtain a film-like reactive multilayer foil and process the obtained film-like reactive multilayer foil into the shape of the terminal (pad). It may be placed on each terminal. For example, when the pitch between the pads 22 is not narrow, instead of the steps shown in FIGS. 2B to 3B, the obtained reactive multilayer foil is processed into the shape of the pads 22 by punching or the like, It is good also as a process of mounting on each pad 22. Alternatively, the obtained film-like reactive multilayer foil may be disposed on the circuit forming surface of the semiconductor wafer 210 including the pads 22 and the portions other than the portions disposed on the pads 22 may be removed by etching or the like. In any case, the steps after FIG. 3C can be as described above.

1, 2, 2A, 3, 4 Semiconductor device 10, 110 Substrate 11 Substrate body 12, 22, 120 Pad 12a, 12b, 48a, 48b, 48c, 49a, 49b, 49c Metal layer 20 Semiconductor element 21, 41 Semiconductor substrate 30 , 47, 57 Alloy layer 31, 45, 55 Reaction layer 31a First metal layer 31b Second metal layer 31c Laminate 41x Through hole 42, 52 Impurity doped region 43, 44 Insulating film 43x, 44x, 300x, 340x, 350x Opening Part 46 Through electrode 48, 49 Wiring layer 210, 410 Semiconductor wafer 300, 340, 350 Resist 310, 320, 330, 360, 370 Seed layer

Claims (9)

Forming a reaction layer that causes an exothermic reaction and is alloyed by being supplied with energy on a plurality of first pads formed on the first substrate in an electrically independent state; and
Forming a conductive layer that electrically connects the reaction layers;
A second substrate having a plurality of second pads formed at positions corresponding to the plurality of first pads, the second pad and the first pad being in contact with each other via the conductive layer and the reaction layer. A step of disposing the first substrate opposite to the first substrate;
Supplying energy to the conductive layer to alloy the reaction layer to form an alloy layer, and bonding the plurality of first pads and the plurality of second pads via the alloy layer. A method for manufacturing a semiconductor device. Forming a reaction layer that causes an exothermic reaction and is alloyed by being supplied with energy on a plurality of impurity-doped regions formed on a semiconductor substrate that is a first substrate in an electrically independent state; ,
Forming a conductive layer that electrically connects the reaction layers;
A step of supplying energy to the conductive layer to alloy the reaction layer to form an alloy layer, and activating a plurality of the impurity-doped regions by heat generated during the alloying. Production method. Forming, on the plurality of impurity doped regions formed on the first substrate, reaction layers that cause an exothermic reaction and are alloyed by being supplied with energy in an electrically independent state;
Forming a conductive layer that electrically connects the reaction layers;
A second substrate having a plurality of pads formed at positions corresponding to the plurality of reaction layers is disposed opposite to the first substrate so that the reaction layer and the pads are in contact with each other through the conductive layer. And a process of
Energy is supplied to the conductive layer to alloy the reaction layer to form an alloy layer, and a plurality of the impurity doped regions and a plurality of the pads are joined via the alloy layer, and a plurality of the impurity doped The method for manufacturing a semiconductor device according to claim 2, further comprising a step of activating the region. The reaction layers are arranged vertically and horizontally,
4. The grid-like conductive layer is formed on the first substrate so that the conductive layer is electrically connected to the reaction layer at an intersection point in the step of forming the conductive layer. 5. A method for manufacturing a semiconductor device according to one item. In the step of forming the alloy layer, a part of the conductive layer is taken into the alloy layer, the other part of the conductive layer remains around the alloy layer,
5. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing another portion of the conductive layer after the step of forming the alloy layer.   6. The method for manufacturing a semiconductor device according to claim 1, wherein the reaction layer is formed by stacking a plurality of stacked bodies in which a second metal layer is stacked on a first metal layer. 7. Either one of the first metal layer and the second metal layer is aluminum, the other is palladium,
The method of manufacturing a semiconductor device according to claim 6, wherein the first metal layer and the second metal layer are formed by a sputtering method.   In the step of forming the alloy layer, energy is supplied to the conductive layer, one reaction layer causes an exothermic reaction, and the energy propagates to the other reaction layer through the conductive layer, and the other reaction The method for manufacturing a semiconductor device according to claim 1, wherein the layers cause an exothermic reaction in a chain manner.   9. The semiconductor device according to claim 1, wherein the method of supplying energy to the conductive layer is a method of applying an electric pulse to the conductive layer, or a method of irradiating the conductive layer with laser light. Manufacturing method.

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