JP5003812B2 - Printed wiring board and printed wiring board manufacturing method - Google Patents

Printed wiring board and printed wiring board manufacturing method Download PDF

Info

Publication number
JP5003812B2
JP5003812B2 JP2010248324A JP2010248324A JP5003812B2 JP 5003812 B2 JP5003812 B2 JP 5003812B2 JP 2010248324 A JP2010248324 A JP 2010248324A JP 2010248324 A JP2010248324 A JP 2010248324A JP 5003812 B2 JP5003812 B2 JP 5003812B2
Authority
JP
Japan
Prior art keywords
insulating layer
film
wiring board
printed wiring
conductor circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010248324A
Other languages
Japanese (ja)
Other versions
JP2011124555A (en
Inventor
雅敏 国枝
吉川　　和弘
剛士 古澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Publication of JP2011124555A publication Critical patent/JP2011124555A/en
Application granted granted Critical
Publication of JP5003812B2 publication Critical patent/JP5003812B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Description

本発明は、半導体素子を実装する薄型のプリント配線板、及び、その製造方法に関するものである。 The present invention relates to a thin printed wiring board on which a semiconductor element is mounted, and a manufacturing method thereof.

半導体素子を実装する樹脂製プリント配線板には、放熱性を高めるために薄く形成することが望まれる。特許文献１には、薄型化を目的とし、コア基板を用いない多層回路基板の製造方法が開示されている。 It is desired that the resin printed wiring board on which the semiconductor element is mounted be formed thin in order to improve heat dissipation. Patent Document 1 discloses a method of manufacturing a multilayer circuit board that aims to reduce the thickness and does not use a core board.

特開２０００−３２３６１３号公報JP 2000-323613 A

しかしながら、特許文献１では、厚みのある金属板をエッチング除去するため、製造時間が長くなる傾向があった。また、片側に積層するため、絶縁層の熱膨張係数が導体回路の熱膨張係数と異なることにより、多層回路基板が反り易い。さらに、多層化していくことにより、外部接続端子側の表面のうねりが顕著に成る。半導体素子用パッドが底面に露出するので、層間樹脂層で覆う必要があり、全体の層間樹脂層が厚くなる。 However, in Patent Document 1, since the thick metal plate is removed by etching, the manufacturing time tends to be long. In addition, since it is laminated on one side, the multilayer circuit board tends to warp because the thermal expansion coefficient of the insulating layer is different from the thermal expansion coefficient of the conductor circuit. Furthermore, the undulation of the surface on the external connection terminal side becomes conspicuous by increasing the number of layers. Since the semiconductor element pad is exposed on the bottom surface, it is necessary to cover it with an interlayer resin layer, and the entire interlayer resin layer becomes thick.

本発明は、上述した課題を解決するためになされたものであり、その目的とするところは、表面が平坦で厚みの薄いプリント配線板、及び、該プリント配線板の製造方法を提供することにある。 The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board having a flat surface and a thin thickness, and a method for manufacturing the printed wiring board. is there.

請求項１に記載のプリント配線板は、第１面、該第１面の反対側の第２面とを有し、第２面に開口を備え、層間樹脂絶縁材から成る絶縁層と、
前記絶縁層の第１面側に埋め込まれ、絶縁層の第１面と同一平面に位置するめっき膜の表面側の第１面と、該第１面とは反対側で、前記開口部により露出される該めっき膜の裏面側の第２面とを備える当該めっき膜から成る導体回路と、
前記導体回路の第１面上に形成されている第１表面処理膜と、
前記開口により露出される前記導体回路の第２面上に形成されている第２表面処理膜とを備えることを技術的特徴とする。
The printed wiring board according to claim 1 has a first surface, a second surface opposite to the first surface, an opening on the second surface, and an insulating layer made of an interlayer resin insulating material;
A first surface on the surface side of the plating film embedded in the first surface side of the insulating layer and located in the same plane as the first surface of the insulating layer, and exposed by the opening on the side opposite to the first surface A conductor circuit made of the plating film provided with a second surface on the back side of the plating film ;
A first surface treatment film formed on the first surface of the conductor circuit;
And a second surface treatment film formed on the second surface of the conductor circuit exposed through the opening.

請求項１の発明では、絶縁層が層間樹脂絶縁材からなるため、薄く、搭載する半導体素子からの熱を効率的に逃がすことができる。導体回路が、絶縁層の第１面側に埋め込まれ、絶縁層の第１面と同一平面に位置し、絶縁層上に凹凸が無くフラットであるため、半導体素子を信頼性高く搭載することができる。 In the first aspect of the invention, since the insulating layer is made of an interlayer resin insulating material, the insulating layer is thin and heat from the semiconductor element to be mounted can be efficiently released. Since the conductor circuit is embedded on the first surface side of the insulating layer, is located on the same plane as the first surface of the insulating layer, and is flat without unevenness on the insulating layer, the semiconductor element can be mounted with high reliability. it can.

本発明の第１実施形態に係るプリント配線板の製造工程図である。It is a manufacturing process figure of the printed wiring board concerning a 1st embodiment of the present invention. 第１実施形態のプリント配線板の製造工程図である。It is a manufacturing-process figure of the printed wiring board of 1st Embodiment. 第１実施形態のプリント配線板の製造工程図である。It is a manufacturing-process figure of the printed wiring board of 1st Embodiment. 第１実施形態のプリント配線板の製造工程図である。It is a manufacturing-process figure of the printed wiring board of 1st Embodiment. 第１実施形態のプリント配線板の断面図である。It is sectional drawing of the printed wiring board of 1st Embodiment. 図６（Ａ）は図５中のサイクルＣで囲んだ部位を更に拡大して示し、図６（Ｂ）は、図６（Ａ）の導体回路のＢ矢視図である。6A is an enlarged view of the portion surrounded by the cycle C in FIG. 5, and FIG. 6B is a view taken along the arrow B of the conductor circuit in FIG. 6A. 本発明の第２実施形態に係るプリント配線板の製造工程図である。It is a manufacturing process figure of the printed wiring board concerning a 2nd embodiment of the present invention. 第２実施形態のプリント配線板の製造工程図である。It is a manufacturing-process figure of the printed wiring board of 2nd Embodiment. 第２実施形態のプリント配線板の製造工程図である。It is a manufacturing-process figure of the printed wiring board of 2nd Embodiment. 第２実施形態のプリント配線板の製造工程図である。It is a manufacturing-process figure of the printed wiring board of 2nd Embodiment. 第２実施形態のプリント配線板の断面図である。It is sectional drawing of the printed wiring board of 2nd Embodiment. 図１２（Ａ）は図１１中のサイクルＣで囲んだ部位を更に拡大して示し、図１２（Ｂ）は、図１２（Ａ）の導体回路のＢ矢視図である。12A is an enlarged view of a portion surrounded by the cycle C in FIG. 11, and FIG. 12B is a view taken along the arrow B of the conductor circuit in FIG.

[第１実施形態]
図５、図６を参照して第１実施形態に係るプリント配線板について説明する。図５はプリント配線板の一部断面を示し、図６（Ａ）は図５中のサイクルＣで囲んだ部位を更に拡大して示し、図６（Ｂ）は、図６（Ａ）の導体回路のＢ矢視図である。
プリント配線板１０は、単層の樹脂製の絶縁層４２から成り、上面（第１面４２Ｕ）側に、パッド用導体回路４０Ａと、配線用導体回路４０Ｂとが形成されている。パッド用導体回路４０Ａと配線用導体回路４０Ｂとの上面（第１面４０Ｕ）は、絶縁層４２の上面と同一平面になるように形成されている。パッド用導体回路４０Ａの上面には、図６（Ａ）中に示すように、ニッケル膜５４、パラジウム膜５５、金膜５６からなる表面処理膜を有するボンディングパッド５７Ｕが形成されている。図６（Ｂ）に示すようにボンディングパッド５７Ｕは矩形に形成されている。 [First embodiment]
The printed wiring board according to the first embodiment will be described with reference to FIGS. 5 and 6. FIG. 5 shows a partial cross section of the printed wiring board, FIG. 6 (A) shows an enlarged view of a portion surrounded by the cycle C in FIG. 5, and FIG. 6 (B) shows the conductor of FIG. 6 (A). It is a B arrow view of a circuit.
The printed wiring board 10 is composed of a single-layer resin insulating layer 42, and a pad conductor circuit 40A and a wiring conductor circuit 40B are formed on the upper surface (first surface 42U) side. The upper surface (first surface 40U) of the pad conductor circuit 40A and the wiring conductor circuit 40B is formed to be flush with the upper surface of the insulating layer 42. As shown in FIG. 6A, a bonding pad 57U having a surface treatment film made of a nickel film 54, a palladium film 55, and a gold film 56 is formed on the upper surface of the pad conductor circuit 40A. As shown in FIG. 6B, the bonding pad 57U is formed in a rectangular shape.

一方、絶縁層４２の下面（第２面４２Ｄ）側には、パッド用導体回路４０Ａの下面（第２面４０Ｄ）側を露出させる開口４２ａが形成されている。該開口４２ａ内のパッド用導体回路４０Ａの下面には、ニッケル膜４４、パラジウム膜４５、金膜５６が順次形成されている。パッド５７Ｄには、ワイヤボンディングが可能であるが、半田バンプを形成することもできる。 On the other hand, an opening 42a is formed on the lower surface (second surface 42D) side of the insulating layer 42 to expose the lower surface (second surface 40D) side of the pad conductor circuit 40A. A nickel film 44, a palladium film 45, and a gold film 56 are sequentially formed on the lower surface of the pad conductor circuit 40A in the opening 42a. Wire bonding is possible for the pad 57D, but solder bumps can also be formed.

図５に示すように、絶縁層４２の第１面４２Ｕ上であって、パッド用導体回路４０Ａの一部及び配線用導体回路４０Ｂの第１面上にＤＡＦ（Die Attach Film）６４を介してメモリー用ＩＣチップ６０が搭載されている。ボンディングパッド５７ＵとＩＣチップ６０の端子６２とは金線からなるボンディングワイヤ６６で接続されている。絶縁層４２の第１面４２Ｕ上に、ＩＣチップ６０を覆うモールド樹脂６８が設けられている。 As shown in FIG. 5, a DAF (Die Attach Film) 64 is provided on the first surface 42U of the insulating layer 42 and on a part of the pad conductor circuit 40A and the first surface of the wiring conductor circuit 40B. A memory IC chip 60 is mounted. The bonding pad 57U and the terminal 62 of the IC chip 60 are connected by a bonding wire 66 made of a gold wire. On the first surface 42U of the insulating layer 42, a mold resin 68 that covers the IC chip 60 is provided.

図６（Ａ）に示すように絶縁層４２は厚みｅ（３０μｍ）に形成されている。導体回路４０Ａ、４０Ｂは厚みｄ（１０μｍ）に形成されている。ボンディングパッド５７Ｕを構成するニッケル膜５４は厚みａ（３μｍ）に、パラジウム膜５５は厚みｂ（０．３μｍ）に、金膜５６は厚みｃ（０．４μｍ）に形成されている。パッド５７Ｄを構成するニッケル膜４４は厚みａ’（３μｍ）に、パラジウム膜４５は厚みｂ’（０．３μｍ）に、金膜４６は厚みｃ’（０．４μｍ）に形成されている。 As shown in FIG. 6A, the insulating layer 42 is formed to a thickness e (30 μm). The conductor circuits 40A and 40B are formed with a thickness d (10 μm). The nickel film 54 constituting the bonding pad 57U is formed to a thickness a (3 μm), the palladium film 55 is formed to a thickness b (0.3 μm), and the gold film 56 is formed to a thickness c (0.4 μm). The nickel film 44 constituting the pad 57D has a thickness a '(3 μm), the palladium film 45 has a thickness b ′ (0.3 μm), and the gold film 46 has a thickness c ′ (0.4 μm).

第１実施形態のプリント配線板では、端子を構成するボンディングパッド５７Ｕ、パッド５７Ｄ（表面処理膜）が無電解ニッケル／パラジウム／金膜からなるため、金線でワイヤボンディングした際の接続信頼性が高い。 In the printed wiring board of the first embodiment, since the bonding pads 57U and the pads 57D (surface treatment film) constituting the terminals are made of electroless nickel / palladium / gold film, the connection reliability when wire bonding with gold wires is performed. high.

次に、第１実施形態のプリント配線板の製造方法について、図１〜図４の製造工程図を参照して説明する。
厚さ０．２〜０．８ｍｍのガラスエポキシ樹脂またはＢＴ（ビスマレイミドトリアジン）樹脂からなる絶縁性基板３０の両面に５〜２５０μｍの銅箔３２がラミネートされている両面銅張積層板３０Ａを出発材料とし、銅箔３２に厚み１００μｍのキャリア銅箔３４を超音波溶接する（図１（Ａ））。キャリア銅箔３４上にＮｉ膜３６をスパッタリングで形成する（図１（Ｂ））。そして、めっきレジスト組成物を被覆し、露光・現像によりパターニングしてめっきレジスト３８を形成する（図１（Ｃ））。めっきレジスト非形成部に電解銅めっきにより導体回路４０Ａ、４０Ｂを形成し、めっきレジストを剥離する（図１（Ｄ））。 Next, the manufacturing method of the printed wiring board of 1st Embodiment is demonstrated with reference to the manufacturing-process figure of FIGS. 1-4.
Starting from a double-sided copper clad laminate 30A in which a 5-250 μm copper foil 32 is laminated on both sides of an insulating substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.2-0.8 mm As a material, carrier copper foil 34 having a thickness of 100 μm is ultrasonically welded to copper foil 32 (FIG. 1A). A Ni film 36 is formed on the carrier copper foil 34 by sputtering (FIG. 1B). Then, a plating resist composition is coated and patterned by exposure and development to form a plating resist 38 (FIG. 1C). Conductor circuits 40A and 40B are formed on the plating resist non-forming portion by electrolytic copper plating, and the plating resist is peeled off (FIG. 1D).

導体回路４０Ａ、４０Ｂを埋設するように、Ｎｉ膜３６上にビルドアップ多層配線板の層間樹脂絶縁層を形成するための層間樹脂絶縁層用樹脂フィルム（味の素社製：商品名；ＡＢＦ−４５ＳＨ）を載置し、仮圧着して裁断した後、真空ラミネーター装置を用いて貼り付けることにより厚さ３０μｍの絶縁層４２を形成した後、レーザにより導体回路４０Ａを露出させる開口４２ａを設ける（図２（Ａ））。ここでは、レーザにより開口を設けたが、露光・現像により開口を設けることもできる。 Resin film for interlayer resin insulation layer for forming an interlayer resin insulation layer of a build-up multilayer wiring board on Ni film 36 so as to embed conductor circuits 40A and 40B (Ajinomoto Co., Inc .; trade name; ABF-45SH) After the insulating layer 42 having a thickness of 30 μm is formed by pasting using a vacuum laminator device, an opening 42a for exposing the conductor circuit 40A is provided by a laser (FIG. 2). (A)). Here, an opening is provided by a laser, but an opening can also be provided by exposure and development.

Ｏ2プラズマにより、開口内の残滓を除去した後、開口４２ａで露出された導体回路４０ａ上に無電解ニッケルめっき、無電解パラジウムめっき、無電解金めっきにより、ニッケル膜５４、パラジウム膜５５、金膜５６を形成する（図２（Ｂ））。 After the residue in the opening is removed by O2 plasma, the nickel film 54, the palladium film 55, and the gold film are formed on the conductor circuit 40a exposed at the opening 42a by electroless nickel plating, electroless palladium plating, and electroless gold plating. 56 is formed (FIG. 2B).

樹脂、金属、セラミックのいずれからなる支持体５０を、剥離層４８を介在させて絶縁層４２上に貼り付ける（図２（Ｃ））。キャリア銅箔３４を剥離する（図３（Ａ））。本実施形態では、両面銅張積層板３０Ａを用いて、両面に絶縁層４２を形成するため、上下で応力の加わりかたが均等になり、平坦に絶縁層４２を形成することができる。 A support 50 made of any one of resin, metal, and ceramic is attached to the insulating layer 42 with a release layer 48 interposed therebetween (FIG. 2C). The carrier copper foil 34 is peeled off (FIG. 3A). In this embodiment, since the insulating layer 42 is formed on both surfaces using the double-sided copper clad laminate 30A, the stress is applied in the vertical direction, and the insulating layer 42 can be formed flat.

銅エッチングにより、キャリア銅箔３４を除去した後、更に、ニッケルエッチングでＮｉスパッタ膜３６を除去し、絶縁層４２を露出させる（図３（Ｂ））。 After the carrier copper foil 34 is removed by copper etching, the Ni sputtered film 36 is further removed by nickel etching to expose the insulating layer 42 (FIG. 3B).

絶縁層４２上に、めっきレジスト膜５２を形成した後、めっきレジスト膜５２の開口５２ａで露出された導体回路４０上に無電解ニッケルめっき、無電解パラジウムめっき、無電解金めっきにより、ニッケル膜５４、パラジウム膜５５、金膜５６を形成する（図３（Ｃ））。その後、めっきレジスト膜５２を除去する（図３（Ｄ））。なお、金膜５６は、置換めっき及び還元めっきにより形成されることが好ましい。これによれば、ニッケル膜５４の腐食を抑制しつつ金膜の厚付けも可能となる。 After the plating resist film 52 is formed on the insulating layer 42, the nickel film 54 is formed by electroless nickel plating, electroless palladium plating, or electroless gold plating on the conductor circuit 40 exposed through the opening 52a of the plating resist film 52. Then, a palladium film 55 and a gold film 56 are formed (FIG. 3C). Thereafter, the plating resist film 52 is removed (FIG. 3D). The gold film 56 is preferably formed by displacement plating and reduction plating. According to this, the thickness of the gold film can be increased while the corrosion of the nickel film 54 is suppressed.

絶縁層４２の第１面上であって、パッド用導体回路４０Ａの一部及び配線用導体回路４０Ｂの第１面上にＤＡＦ（Die Attach Film）６４を介してメモリー用ＩＣチップ６０を搭載する（図４（Ａ））。導体回路４０Ａ上のニッケル膜５４、パラジウム膜５５、金膜５６からなるボンディングパッド５７Ｕと、ＩＣチップの端子６２とをボンディングワイヤ６６により接続する。絶縁層４２の第１面４２Ｕ上に、ＩＣチップ６０を覆うモールド樹脂６８を設ける（図４（Ｃ））。そして、剥離層４８により支持体５０を分離し、プリント配線板を完成する（図５）。 The memory IC chip 60 is mounted on the first surface of the insulating layer 42 and on a part of the pad conductor circuit 40A and the first surface of the wiring conductor circuit 40B via a DAF (Die Attach Film) 64. (FIG. 4 (A)). Bonding pads 57U made of nickel film 54, palladium film 55, and gold film 56 on conductor circuit 40A are connected to terminals 62 of the IC chip by bonding wires 66. A mold resin 68 that covers the IC chip 60 is provided on the first surface 42U of the insulating layer 42 (FIG. 4C). And the support body 50 is isolate | separated by the peeling layer 48, and a printed wiring board is completed (FIG. 5).

第１実施形態のプリント配線板の製造方法では、両面銅張積層板３０Ａ上のＮｉスパッタ膜３６に導体回路４０Ａ、４０Ｂを形成し、該Ｎｉスパッタ膜３６上に層間樹脂絶縁材を用いて絶縁層４２を形成し、支持体５０を貼り付ける。両面銅張積層板３０Ａと支持体５０とでサンドイッチした状態で硬化させるので、薄い層間樹脂絶縁材からフラットな絶縁層４２を形成することが可能である。そして、両面銅張積層板３０Ａを剥離し支持体５０で支持した状態で、絶縁層４２上にＩＣチップ６０を搭載し、絶縁層４２上にＩＣチップ６０を覆うモールド樹脂６８を設け、モールド樹脂６８及びＩＣチップ６０で強度が取れる状態にしてから、支持体５０を剥離する。このため、機械的な強度の無い薄い絶縁層４２を設けることが可能となり、更に、表面の強度を保つためのソルダーレジスト層が不要に成り、プリント配線板の厚みを薄くすることで、ＩＣチップ６０からの熱を効率的に逃がすことができる。導体回路４０Ａ、４０Ｂが、絶縁層４２の第１面側に埋め込まれ、絶縁層４２の第１面と同一平面に位置し、絶縁層４２上に凹凸が無くフラットであるため、ＩＣチップ６０を信頼性高く搭載することができる。 In the printed wiring board manufacturing method of the first embodiment, conductor circuits 40A and 40B are formed on the Ni sputtered film 36 on the double-sided copper clad laminate 30A, and insulation is performed on the Ni sputtered film 36 using an interlayer resin insulating material. Layer 42 is formed and support 50 is affixed. Since it is cured while sandwiched between the double-sided copper-clad laminate 30A and the support 50, it is possible to form a flat insulating layer 42 from a thin interlayer resin insulating material. Then, with the double-sided copper-clad laminate 30A peeled off and supported by the support 50, the IC chip 60 is mounted on the insulating layer 42, and the mold resin 68 covering the IC chip 60 is provided on the insulating layer 42. 68 and the IC chip 60, the support 50 is peeled off. For this reason, it is possible to provide a thin insulating layer 42 without mechanical strength, and further, a solder resist layer for maintaining the strength of the surface becomes unnecessary, and by reducing the thickness of the printed wiring board, the IC chip Heat from 60 can be efficiently released. Since the conductor circuits 40A and 40B are embedded on the first surface side of the insulating layer 42, are located on the same plane as the first surface of the insulating layer 42, and are flat with no irregularities on the insulating layer 42, the IC chip 60 is formed. It can be mounted with high reliability.

[第２実施形態]
図１１、図１２を参照して第２実施形態に係るプリント配線板について説明する。図１１はプリント配線板の一部断面を示し、図１２（Ａ）は図１１中のサイクルＣで囲んだ部位を更に拡大して示し、図１２（Ｂ）は、図１２（Ａ）の導体回路のＢ矢視図である。
プリント配線板１０は、単層の樹脂製の絶縁層４２から成り、上面（第１面４２Ｕ）側に、パッド用導体回路４０Ａと、配線用導体回路４０Ｂとが形成されている。パッド用導体回路４０Ａと配線用導体回路４０Ｂとの上面（第１面４０Ｕ）は、絶縁層４２の上面と同一平面になるように形成されている。パッド用導体回路４０Ａの上面には、図１２（Ａ）中に示すように、ニッケル膜５４、パラジウム膜５５、金膜５６からなる表面処理膜が形成されている。ボンディングパッド５７Ｕの上面は、パッド用導体回路４０Ａの上面（第１面４０Ｕ）、及び、絶縁層４２の上面と同一平面になるように形成されている。図１２（Ｂ）に示すようにボンディングパッド５７Ｕは矩形に形成されている。 [Second Embodiment]
A printed wiring board according to the second embodiment will be described with reference to FIGS. 11 and 12. 11 shows a partial cross section of the printed wiring board, FIG. 12A shows an enlarged view of a portion surrounded by the cycle C in FIG. 11, and FIG. 12B shows the conductor of FIG. It is a B arrow view of a circuit.
The printed wiring board 10 is composed of a single-layer resin insulating layer 42, and a pad conductor circuit 40A and a wiring conductor circuit 40B are formed on the upper surface (first surface 42U) side. The upper surface (first surface 40U) of the pad conductor circuit 40A and the wiring conductor circuit 40B is formed to be flush with the upper surface of the insulating layer 42. As shown in FIG. 12A, a surface treatment film made of a nickel film 54, a palladium film 55, and a gold film 56 is formed on the upper surface of the pad conductor circuit 40A. The upper surface of the bonding pad 57U is formed so as to be flush with the upper surface (first surface 40U) of the pad conductor circuit 40A and the upper surface of the insulating layer 42. As shown in FIG. 12B, the bonding pad 57U is formed in a rectangular shape.

一方、絶縁層４２の下面（第２面４２Ｄ）側には、パッド用導体回路４０Ａの下面（第２面４０Ｄ）側を露出させる開口４２ａが形成されている。該開口４２ａ内のパッド用導体回路４０Ａの下面には、ニッケル膜４４、パラジウム膜４５、金膜４６からなる表面処理膜を有するパッド５７Ｄが形成されている。パッド５７Ｄは、ワイヤボンディングが可能であるが、半田バンプを形成することもできる。 On the other hand, an opening 42a is formed on the lower surface (second surface 42D) side of the insulating layer 42 to expose the lower surface (second surface 40D) side of the pad conductor circuit 40A. A pad 57D having a surface treatment film made of a nickel film 44, a palladium film 45, and a gold film 46 is formed on the lower surface of the pad conductor circuit 40A in the opening 42a. The pad 57D can be wire-bonded, but can also form a solder bump.

図１１に示すように、絶縁層４２の第１面上であって、パッド用導体回路４０Ａの一部及び配線用導体回路４０Ｂの第１面上にＤＡＦ（Die Attach Film）６４を介してメモリー用ＩＣチップ６０が搭載されている。ボンディングパッド５７ＵとＩＣチップ６０の端子６２とは金線からなるボンディングワイヤ６６で接続されている。絶縁層４２の第１面４２Ｕ上に、ＩＣチップ６０を覆うモールド樹脂６８が設けられている。 As shown in FIG. 11, a memory is provided on the first surface of the insulating layer 42 on a part of the pad conductor circuit 40A and the first surface of the wiring conductor circuit 40B via a DAF (Die Attach Film) 64. IC chip 60 is mounted. The bonding pad 57U and the terminal 62 of the IC chip 60 are connected by a bonding wire 66 made of a gold wire. On the first surface 42U of the insulating layer 42, a mold resin 68 that covers the IC chip 60 is provided.

図１２（Ａ）に示すように絶縁層４２は厚みｅ（３０μｍ）に形成されている。導体回路４０Ａ、４０Ｂは厚みｄ（１０μｍ）に形成されている。ボンディングパッド５７Ｕを構成するニッケル膜５４は厚みａ（３μｍ）に、パラジウム膜５５は厚みｂ（０．３μｍ）に、金膜５６は厚みｃ（０．４μｍ）に形成されている。パッド５７Ｄを構成するニッケル膜４４は厚みａ’（３μｍ）に、パラジウム膜４５は厚みｂ’（０．３μｍ）に、金膜４６は厚みｃ’（０．４μｍ）に形成されている。 As shown in FIG. 12A, the insulating layer 42 is formed to a thickness e (30 μm). The conductor circuits 40A and 40B are formed with a thickness d (10 μm). The nickel film 54 constituting the bonding pad 57U is formed to a thickness a (3 μm), the palladium film 55 is formed to a thickness b (0.3 μm), and the gold film 56 is formed to a thickness c (0.4 μm). The nickel film 44 constituting the pad 57D has a thickness a '(3 μm), the palladium film 45 has a thickness b ′ (0.3 μm), and the gold film 46 has a thickness c ′ (0.4 μm).

第２実施形態のプリント配線板では、絶縁層４２が層間樹脂絶縁材からなるため、薄く、搭載するＩＣチップ６０からの熱を効率的に逃がすことができる。導体回路４０Ａ、４０Ｂが、絶縁層４２の第１面４２Ｕ側に埋め込まれ、絶縁層４２の第１面と同一平面に位置し、絶縁層上に凸凹が無くフラットであるため、ＩＣチップを信頼性高く搭載することができる。 In the printed wiring board of the second embodiment, since the insulating layer 42 is made of an interlayer resin insulating material, the insulating layer 42 is thin, and heat from the mounted IC chip 60 can be efficiently released. Since the conductor circuits 40A and 40B are embedded on the first surface 42U side of the insulating layer 42, are located on the same plane as the first surface of the insulating layer 42, and are flat with no irregularities on the insulating layer, the IC chip is trusted. It can be mounted with high performance.

第２実施形態のプリント配線板では、ニッケル膜５４、パラジウム膜５５、金膜５６からなるボンディングパッド５７Ｕが導体回路４０Ａの第１面と同一平面に位置し、絶縁層４２上に凸凹が無くフラットであるため、ＩＣチップ等の半導体素子を信頼性高く搭載することができる。 In the printed wiring board of the second embodiment, the bonding pad 57U composed of the nickel film 54, the palladium film 55, and the gold film 56 is located on the same plane as the first surface of the conductor circuit 40A, and is flat on the insulating layer 42 without unevenness. Therefore, a semiconductor element such as an IC chip can be mounted with high reliability.

次に、第２実施形態のプリント配線板の製造方法について、図７〜図１０の製造工程図を参照して説明する。
厚さ０．２〜０．８ｍｍのガラスエポキシ樹脂またはＢＴ（ビスマレイミドトリアジン）樹脂からなる絶縁性基板３０の両面に５〜２５０μｍの銅箔３２がラミネートされている両面銅張積層板３０Ａを出発材料とし、銅箔３２に厚み１００μｍのキャリア銅箔３４を超音波溶接する（図７（Ａ））。キャリア銅箔３４上にＮｉ膜３６をスパッタリングで形成する（図７（Ｂ））。 Next, the manufacturing method of the printed wiring board of 2nd Embodiment is demonstrated with reference to the manufacturing-process figure of FIGS.
Starting from a double-sided copper clad laminate 30A in which a 5-250 μm copper foil 32 is laminated on both sides of an insulating substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.2-0.8 mm As a material, a carrier copper foil 34 having a thickness of 100 μm is ultrasonically welded to the copper foil 32 (FIG. 7A). A Ni film 36 is formed on the carrier copper foil 34 by sputtering (FIG. 7B).

Ｎｉ膜３６上に、開口を備えるめっきレジスト膜を形成した後、めっきレジスト膜の開口で露出されたＮｉ膜３６上に無電解ニッケルめっき、無電解パラジウムめっき、無電解金めっきにより、ニッケル膜５４、パラジウム膜５５、金膜５６を形成し、めっきレジスト膜５２を除去する（図７（Ｃ））。 After a plating resist film having an opening is formed on the Ni film 36, the nickel film 54 is formed on the Ni film 36 exposed through the opening of the plating resist film by electroless nickel plating, electroless palladium plating, or electroless gold plating. Then, a palladium film 55 and a gold film 56 are formed, and the plating resist film 52 is removed (FIG. 7C).

そして、めっきレジスト組成物を被覆し、露光・現像によりパターニングしてめっきレジスト３８を形成する（図７（Ｄ））。めっきレジスト非形成部に電解銅めっきにより導体回路４０Ａ、４０Ｂを形成し、めっきレジストを剥離する（図８（Ａ））。 Then, a plating resist composition is coated and patterned by exposure and development to form a plating resist 38 (FIG. 7D). Conductor circuits 40A and 40B are formed on the plating resist non-forming portion by electrolytic copper plating, and the plating resist is peeled off (FIG. 8A).

導体回路４０Ａ、４０Ｂを埋設するように、Ｎｉ膜３６上に層間樹脂絶縁層用樹脂フィルム（味の素社製：商品名；ＡＢＦ−４５ＳＨ）を載置し、仮圧着して裁断した後、真空ラミネーター装置を用いて貼り付けることにより厚さ３０μｍの絶縁層４２を形成した後、レーザにより導体回路４０Ａを露出させる開口４２ａを設ける（図８（Ｂ））。ここでは、レーザにより開口を設けたが、露光・現像により開口を設けることもできる。 A resin film for interlayer resin insulation layer (manufactured by Ajinomoto Co., Inc .; trade name: ABF-45SH) is placed on the Ni film 36 so as to embed the conductor circuits 40A and 40B, and after temporarily crimping and cutting, a vacuum laminator After an insulating layer 42 having a thickness of 30 μm is formed by pasting using an apparatus, an opening 42a for exposing the conductor circuit 40A is provided by a laser (FIG. 8B). Here, an opening is provided by a laser, but an opening can also be provided by exposure and development.

Ｏ2プラズマにより、開口内の残滓を除去した後、開口４２ａで露出された導体回路４０ａ上に無電解ニッケルめっき、無電解パラジウムめっき、無電解金めっきにより、ニッケル膜５４、パラジウム膜５５、金膜５６を形成する（図８（Ｃ））。 After the residue in the opening is removed by O2 plasma, the nickel film 54, the palladium film 55, and the gold film are formed on the conductor circuit 40a exposed at the opening 42a by electroless nickel plating, electroless palladium plating, and electroless gold plating. 56 is formed (FIG. 8C).

樹脂、金属、セラミックのいずれからなる支持体５０を、剥離層４８を介在させて絶縁層４２上に貼り付ける（図９（Ａ））。キャリア銅箔３４を剥離する（図９（Ｂ））。第２実施形態では、両面銅張積層板３０Ａを用いて、両面に絶縁層４２を形成するため、上下で応力の加わりかたが均等になり、平坦に絶縁層４２を形成することができる。 A support 50 made of any one of resin, metal, and ceramic is attached onto the insulating layer 42 with a release layer 48 interposed therebetween (FIG. 9A). The carrier copper foil 34 is peeled off (FIG. 9B). In the second embodiment, since the insulating layer 42 is formed on both surfaces using the double-sided copper clad laminate 30A, the stress is applied evenly in the vertical direction, and the insulating layer 42 can be formed flat.

銅エッチングにより、キャリア銅箔３４を除去した後、更に、ニッケルエッチングでＮｉスパッタ膜３６を除去し、絶縁層４２を露出させる（図９（Ｃ））。 After removing the carrier copper foil 34 by copper etching, the Ni sputtered film 36 is further removed by nickel etching to expose the insulating layer 42 (FIG. 9C).

絶縁層４２の第１面上であって、パッド用導体回路４０Ａの一部及び配線用導体回路４０Ｂの第１面上にＤＡＦ（Die Attach Film）６４を介してメモリー用ＩＣチップ６０を搭載する（図１０（Ａ））。導体回路４０Ａ上のニッケル膜５４、パラジウム膜５５、金膜５６からなるボンディングパッド５７Ｕと、ＩＣチップの端子６２とをボンディングワイヤ６６により接続する。絶縁層４２の第１面４２Ｕ上に、ＩＣチップ６０を覆うモールド樹脂６８を設ける（図１０（Ｃ））。そして、剥離層４８により支持体５０を分離し、プリント配線板を完成する（図１１）。 The memory IC chip 60 is mounted on the first surface of the insulating layer 42 and on a part of the pad conductor circuit 40A and the first surface of the wiring conductor circuit 40B via a DAF (Die Attach Film) 64. (FIG. 10A). Bonding pads 57U made of nickel film 54, palladium film 55, and gold film 56 on conductor circuit 40A are connected to terminals 62 of the IC chip by bonding wires 66. A mold resin 68 that covers the IC chip 60 is provided on the first surface 42U of the insulating layer 42 (FIG. 10C). And the support body 50 is isolate | separated by the peeling layer 48, and a printed wiring board is completed (FIG. 11).

第２実施形態のプリント配線板の製造方法では、第１表面処理膜（ニッケル膜５４、パラジウム膜５５、金膜５６）を形成した後、一面側表面処理膜を覆うように導体回路４０を形成するので、第１表面処理膜（ニッケル膜５４、パラジウム膜５５、金膜５６）が導体回路の第１面と同一平面に位置する。このため、絶縁層上に凹凸が無くフラットになり、半導体素子を信頼性高く搭載することができる。 In the method for manufacturing a printed wiring board according to the second embodiment, after forming the first surface treatment film (nickel film 54, palladium film 55, gold film 56), the conductor circuit 40 is formed so as to cover the one surface side surface treatment film. Therefore, the first surface treatment film (nickel film 54, palladium film 55, gold film 56) is located on the same plane as the first surface of the conductor circuit. Therefore, the insulating layer is flat without unevenness, and the semiconductor element can be mounted with high reliability.

上述した実施形態では、ＩＣチップを一つ乗せるプリント配線板を例示したが、本願発明の構成は、複数個のＩＣチップを乗せる場合にも好適に利用できる。 In the above-described embodiment, the printed wiring board on which one IC chip is placed has been illustrated, but the configuration of the present invention can also be suitably used when a plurality of IC chips are placed.

１０ プリント配線板
３０ 絶縁基板
３２ 銅箔
３４ キャリア銅箔
４０Ａ パッド用導体回路
４０Ｂ 配線用導体回路
４０Ｕ 第１面
４０Ｄ 第２面
４２ 樹脂層
４２Ｕ 第１面
４２Ｄ 第２面
４４ ニッケル膜
４５ パラジウム膜
４６ 金膜
５０ 支持体
５４ ニッケル膜
５５ パラジウム膜
５６ 金膜
５７Ｄ ボンディングパッド
６０ ＩＣチップ
６６ ボンディングワイヤ
６８ モールド樹脂 DESCRIPTION OF SYMBOLS 10 Printed wiring board 30 Insulation board 32 Copper foil 34 Carrier copper foil 40A Pad conductor circuit 40B Wiring conductor circuit 40U 1st surface 40D 2nd surface 42 Resin layer 42U 1st surface 42D 2nd surface 44 Nickel film 45 Palladium film 46 Gold film 50 Support 54 Nickel film 55 Palladium film 56 Gold film 57D Bonding pad 60 IC chip 66 Bonding wire 68 Mold resin

Claims (10)

第１面、該第１面の反対側の第２面とを有し、第２面に開口する開口部を備える絶縁層と、
前記絶縁層の第１面側に埋め込まれ、絶縁層の第１面と同一平面に位置するめっき膜の表面側の第１面と、該第１面とは反対側で、前記開口部により露出される該めっき膜の裏面側の第２面とを備える当該めっき膜から成る導体回路と、
前記導体回路の第１面側に形成されている第１表面処理膜と、
前記開口により露出される前記導体回路の第２面上に形成されている第２表面処理膜とを備えるプリント配線板。 An insulating layer having a first surface, a second surface opposite to the first surface, and having an opening opening in the second surface;
A first surface on the surface side of the plating film embedded in the first surface side of the insulating layer and located in the same plane as the first surface of the insulating layer, and exposed by the opening on the side opposite to the first surface A conductor circuit made of the plating film provided with a second surface on the back side of the plating film ;
A first surface treatment film formed on the first surface side of the conductor circuit;
A printed wiring board comprising: a second surface treatment film formed on a second surface of the conductor circuit exposed through the opening. 前記第１表面処理膜は、前記導体回路の第１面上に形成されていることを特徴とする請求項１のプリント配線板。 The printed wiring board according to claim 1, wherein the first surface treatment film is formed on a first surface of the conductor circuit. 前記第１表面処理膜の表面は、前記導体回路の第１面と同一平面に位置することを特徴とする請求項１のプリント配線板。 The printed wiring board according to claim 1, wherein the surface of the first surface treatment film is located on the same plane as the first surface of the conductor circuit. 前記第１表面処理膜及び前記第２表面処理膜は、無電解めっき膜からなる請求項１のプリント配線板。 The printed wiring board according to claim 1, wherein the first surface treatment film and the second surface treatment film are made of an electroless plating film. 前記第１表面処理膜及び前記第２表面処理膜は、ニッケル、パラジウム及び金からなる請求項１のプリント配線板。 The printed wiring board according to claim 1, wherein the first surface treatment film and the second surface treatment film are made of nickel, palladium, and gold. 前記導体回路が１層設けられている請求項１のプリント配線板。 The printed wiring board according to claim 1, wherein one layer of the conductor circuit is provided. 前記導体回路の厚みをａとし、前記絶縁層の厚みをｂとしたとき、０．２＜ａ／ｂ＜０．８となる請求項１のプリント配線板。 The printed wiring board according to claim 1, wherein 0.2 <a / b <0.8, where a is a thickness of the conductor circuit and b is a thickness of the insulating layer. 以下の工程を備えるプリント配線板の製造方法：
第１支持体上に導体回路を形成することと、
前記導体回路を覆うように前記第１支持体上に絶縁層を形成することと、
前記導体回路の表面の一部を露出させる開口部を前記絶縁層の内部に形成することと、
前記絶縁層の開口部から露出された前記導体回路の表面上に第１表面処理膜を形成することと、
前記絶縁層上に第２支持体を貼り付けることと、
前記第１支持体を前記絶縁層から剥離することと、
前記第１支持体を剥離した後に露出された前記導体回路の表面上に第２表面処理膜を形成することと、
前記第２支持体を前記絶縁層から剥離することと、
を有するプリント配線板の製造方法。 A method for producing a printed wiring board comprising the following steps:
Forming a conductor circuit on the first support;
Forming an insulating layer on the first support so as to cover the conductor circuit;
Forming an opening in the insulating layer to expose a part of the surface of the conductor circuit;
Forming a first surface treatment film on the surface of the conductor circuit exposed from the opening of the insulating layer;
Affixing a second support on the insulating layer;
Peeling the first support from the insulating layer;
Forming a second surface treatment film on the surface of the conductor circuit exposed after peeling off the first support;
Peeling the second support from the insulating layer;
The manufacturing method of the printed wiring board which has this. 前記第１表面処理膜及び前記第２表面処理膜は無電解めっきにより形成される請求項８のプリント配線板の製造方法。 The method for manufacturing a printed wiring board according to claim 8, wherein the first surface treatment film and the second surface treatment film are formed by electroless plating. 以下の工程を備えるプリント配線板の製造方法：
第１支持体上に第１表面処理膜を形成することと、
前記第１表面処理膜を覆うようにして前記第１支持体上に導体回路を形成することと、
前記導体回路を覆うようにして前記第１支持体上に絶縁層を形成することと、
前記導体回路の表面の一部を露出させる開口部を前記絶縁層の内部に形成することと、
前記絶縁層の開口部から露出された前記導体回路の表面上に第２表面処理膜を形成することと、
前記絶縁層上に第２支持体を貼り付けることと、
前記第１支持体を前記絶縁層から剥離することと、
を有するプリント配線板の製造方法。 A method for producing a printed wiring board comprising the following steps:
Forming a first surface treatment film on the first support;
Forming a conductor circuit on the first support so as to cover the first surface treatment film;
Forming an insulating layer on the first support so as to cover the conductor circuit;
Forming an opening in the insulating layer to expose a part of the surface of the conductor circuit;
Forming a second surface treatment film on the surface of the conductor circuit exposed from the opening of the insulating layer;
Affixing a second support on the insulating layer;
Peeling the first support from the insulating layer;
The manufacturing method of the printed wiring board which has this.
JP2010248324A 2009-12-10 2010-11-05 Printed wiring board and printed wiring board manufacturing method Active JP5003812B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US28536209P 2009-12-10 2009-12-10
US61/285,362 2009-12-10

Publications (2)

Publication Number Publication Date
JP2011124555A JP2011124555A (en) 2011-06-23
JP5003812B2 true JP5003812B2 (en) 2012-08-15

Family

ID=44141658

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010248324A Active JP5003812B2 (en) 2009-12-10 2010-11-05 Printed wiring board and printed wiring board manufacturing method

Country Status (2)

Country Link
US (1) US8487192B2 (en)
JP (1) JP5003812B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8923008B2 (en) 2011-03-08 2014-12-30 Ibiden Co., Ltd. Circuit board and method for manufacturing circuit board
JP6166879B2 (en) * 2011-09-06 2017-07-19 株式会社 大昌電子 Single-sided printed wiring board and manufacturing method thereof
KR102005487B1 (en) * 2011-12-21 2019-07-30 엘지이노텍 주식회사 Memory card, pcb for the memory card and method for manufacturing the same
KR102014088B1 (en) * 2012-03-20 2019-08-26 엘지이노텍 주식회사 Memory card, pcb for the memory card and method for manufacturing the same
JP6626687B2 (en) 2015-10-28 2019-12-25 新光電気工業株式会社 Wiring board, semiconductor device, and method of manufacturing wiring board
JP6623056B2 (en) * 2015-12-16 2019-12-18 新光電気工業株式会社 Wiring board, semiconductor device
JP6689691B2 (en) 2016-07-12 2020-04-28 新光電気工業株式会社 Wiring board and manufacturing method thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3635219B2 (en) 1999-03-11 2005-04-06 新光電気工業株式会社 Multilayer substrate for semiconductor device and manufacturing method thereof
JP3537400B2 (en) * 2000-03-17 2004-06-14 松下電器産業株式会社 Semiconductor built-in module and method of manufacturing the same
JP2006324542A (en) * 2005-05-20 2006-11-30 Cmk Corp Printed wiring board and its manufacturing method
WO2008001915A1 (en) * 2006-06-30 2008-01-03 Nec Corporation Wiring board, semiconductor device using wiring board and their manufacturing methods
KR100867148B1 (en) * 2007-09-28 2008-11-06 삼성전기주식회사 Printed circuit board and manufacturing method of the same
TWI390692B (en) * 2009-06-23 2013-03-21 Unimicron Technology Corp Package substrate and base therefor and fabrication method thereof
KR101140982B1 (en) * 2010-09-07 2012-05-03 삼성전기주식회사 Single layer printed circuit board and manufacturing method thereof

Also Published As

Publication number Publication date
US8487192B2 (en) 2013-07-16
JP2011124555A (en) 2011-06-23
US20110139498A1 (en) 2011-06-16

Similar Documents

Publication Publication Date Title
JP3619395B2 (en) Semiconductor device built-in wiring board and manufacturing method thereof
US7923367B2 (en) Multilayer wiring substrate mounted with electronic component and method for manufacturing the same
JP3908157B2 (en) Method of manufacturing flip chip type semiconductor device
TWI436717B (en) Wiring board capable of having built-in functional element and method for manufacturing the same
JP5003812B2 (en) Printed wiring board and printed wiring board manufacturing method
JP4171499B2 (en) Electronic device substrate and manufacturing method thereof, and electronic device and manufacturing method thereof
JP2012191204A (en) Manufacturing method of printed wiring board
WO2007126090A1 (en) Circuit board, electronic device and method for manufacturing circuit board
JP2002016173A (en) Semiconductor device
JP2015028986A (en) Printed wiring board and printed wiring board manufacturing method
JP2015211194A (en) Printed wiring board, semiconductor package and printed wiring board manufacturing method
JP4070470B2 (en) Multilayer circuit board for semiconductor device, manufacturing method thereof, and semiconductor device
JP2000100987A (en) Semiconductor chip module multilayer circuit board and manufacture thereof
JP2015225895A (en) Printed wiring board, semiconductor package and printed wiring board manufacturing method
JP2018032660A (en) Printed wiring board and method for manufacturing the same
JP2008124247A (en) Substrate with built-in component and its manufacturing method
JP4460341B2 (en) Wiring board and manufacturing method thereof
JP5007164B2 (en) Multilayer wiring board and multilayer wiring board manufacturing method
JP2004119729A (en) Method of manufacturing circuit device
JP4086607B2 (en) Circuit device manufacturing method
JP2016025281A (en) Semiconductor device and method for manufacturing the same
JP4679000B2 (en) Plate
KR101109287B1 (en) Printed circuit board with electronic components embedded therein and method for fabricating the same
JP2005072085A (en) Method of manufacturing wiring board and wiring board
JP4549693B2 (en) Wiring board manufacturing method

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111213

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20111215

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120118

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120424

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120507

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150601

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 5003812

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250