JP2002016173A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for enabling high density wiring and preventing peeling at the time of reflow. SOLUTION: A substrate 1 is composed of a bottom plate 11 composed of a metal and a frame material 12 composed of a resin composite material and is provided with a recessed part 22. A semiconductor chip 2 is buried in the recessed part 22, an insulation layer 3 provided with an inter-layer conductive part 42 on the terminal of the semiconductor chip 2 is provided on it and the insulation layer 3 is provided with conductor wiring 41 in continuity with the inter-layer conductive part. Further, the insulation layer provided with a stud via and a conductor wiring pattern are laminated on the conductor wiring 41 by a build-up method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device on which electronic parts such as semiconductor chips are mounted.

[0002]

2. Description of the Related Art Conventionally, the connection between a chip of a package including a semiconductor interposer substrate and an interposer substrate is performed by wire bonding or bump connection. However, there is a limit in alignment accuracy and miniaturization of electrodes. It is considered difficult to cope with a pitch of 4 mm or less.

As a countermeasure, a method of embedding a high-density wiring semiconductor chip face-up in a substrate and pulling out outer bumps is described in the following patent publication. That is,
JP-A-4-25038 discloses that a chip provided with external connection terminals on its surface is embedded in a concave portion of a base material, an insulating layer is provided thereon, a via hole is formed in the external connection terminal portion, and then an upper layer circuit is formed. And a bump formed, and a solder resist formed in other areas. The base material is a metal such as aluminum, and a concave portion is provided by etching or mechanical cutting, or a thermosetting resin. And that the concave portion is provided by mechanical cutting or injection molding.

Japanese Patent Application Laid-Open No. Hei 9-321408 discloses a semiconductor device in which a semiconductor chip is embedded and multi-layered by build-up in the same manner as in the above-mentioned publication, and a stud bump is used as an external connection terminal of the semiconductor chip. The concave portion is formed by cutting or punched.

Japanese Patent Application Laid-Open No. HEI 1-175297 discloses a method in which a substrate is used in which two substrates in which through holes each having the size of a semiconductor chip are formed at the same position on both surfaces of a single substrate are used. A high-density mounting is performed by embedding a semiconductor chip in a through hole, and a substrate using a copper-clad laminate such as glass epoxy is described as the substrate.

[0006]

However, in the device disclosed in Japanese Patent Application Laid-Open No. 4-25038, the wiring is more developed, so that it cannot be routed sufficiently, and a concave portion is formed on the surface of the metal substrate as a measure against heat radiation. Although it is used, high cost is required for processing, and at the time of reflow, separation occurs between the metal base and the insulating layer due to the difference in thermal expansion between the metal base and the insulating layer provided thereon. There were challenges. In addition, the base material made of resin is obtained by machining the resin or by injection molding a thermoplastic resin, but the former is expensive, and the latter contains a release agent and is coated from above. Poor adhesion to the insulating layer and large thermal expansion coefficient of the base material itself, resulting in a large difference in thermal expansion coefficient from the semiconductor chip, causing the semiconductor chip to break during reflow or peeling off from the semiconductor chip There was a problem that it was easy. Further, in the latter case, the heat radiation of the chip is poor, which causes a malfunction of the chip.

The one disclosed in Japanese Patent Application Laid-Open No. 9-321408 is not suitable for high-density wiring routing since a stud via structure is difficult to obtain since a stud bump is used. Since the material of the substrate is not taken into consideration, there is a problem that peeling is likely to occur between the semiconductor chips at the time of reflow and heat dissipation of the chips is insufficient, as in the above case.

[0008] Japanese Unexamined Patent Publication No. 1-175297 uses a copper-clad laminate such as glass epoxy as the first and second substrates (corresponding to a bottom plate and a frame material). There was a problem in heat dissipation.

SUMMARY OF THE INVENTION The present invention has been made in order to solve such a problem, and it is possible to obtain a semiconductor device which is excellent in heat dissipation and in which peeling during reflow is prevented.

[0010]

According to a first aspect of the present invention, there is provided a semiconductor device having a substrate having a concave portion, a semiconductor chip embedded in the concave portion, covering the semiconductor chip and the surface of the substrate, and connecting terminals of the semiconductor chip. An insulating layer having an opening in the portion, an interlayer conductive portion in which the opening is made conductive with a conductive material,
A semiconductor device provided on the insulating layer and provided with a conductor wiring that is electrically connected to the interlayer conductive portion, wherein the substrate is bonded to a bottom plate made of a resin composite material or a metal on which a thermal buyer is formed; And a frame material having a through hole larger than the semiconductor chip and made of a polyimide or resin composite material.

According to a second semiconductor device of the present invention, in the above first semiconductor device, an insulating layer having a stud via filled with a conductive material on the conductive wiring by a build-up method on the conductive wiring and the conductive wiring are provided. Are sequentially laminated.

In a third semiconductor device according to the present invention, in the first or second semiconductor device, the resin composite material is composed of a resin and glass cloth, glass nonwoven fabric, polyamide nonwoven fabric or liquid crystal polymer nonwoven fabric. Is what it is.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 (a)-
(H) is an explanatory view showing a step of manufacturing the semiconductor device according to the embodiment of the present invention, wherein 1 is a substrate, and 1 is a bottom plate;
, Frame member 12, 2 is a semiconductor chip, 22 is a concave portion,
Reference numeral 3 denotes an insulating layer, 31 denotes an opening, 4 denotes a conductor layer, 41 denotes a conductor wiring, 42 denotes an interlayer conductive portion, 5 denotes a bump, and 6 denotes a solder resist.

A substrate 1 having a concave portion according to an embodiment of the present invention comprises a bottom plate 11 and a frame member 12, and a concave portion 22 is formed in the substrate 1 by the frame member 12, and the frame member 12 connects the semiconductor chip 2 to the bottom plate 11. It has a through hole larger than the semiconductor chip 2 that can be mounted face up.

The bottom plate 11 is made of a metal such as copper, 42 alloy or aluminum, or a resin composite material formed with a thermal buyer, and has an effect of being excellent in heat dissipation. As the resin component of the resin composite material, epoxy, polyparaphenylene resin or BT resin is used,
As the reinforcing component, a liquid crystal polymer nonwoven fabric, a polyamide fiber nonwoven fabric, a glass cloth or a glass nonwoven fabric is used. Thermal buyers are through holes formed to allow heat generated at the top of the bottom plate (chip mounting side) to escape to the back of the bottom plate.
Is drilled with a drill or the like, and the hole wall or the entire hole is filled with metal plating or a high heat conductive material. The high thermal conductive material is a material in which metal particles or ceramic particles are filled in an organic resin and has a thermal conductivity of 1.0 W / mK or more. When using a resin composite material with copper foil attached to the bottom side of the bottom plate and providing a thermal buyer, the heat transferred to the back side through the thermal buyer is further transferred to the copper foil on the back side of the bottom plate and from there in the air Heat is efficiently dissipated
By providing a radiating fin or a fan on the copper foil, the radiating property is further enhanced. When using a resin composite material in which copper foil is attached to both sides of the bottom plate, a thermal buyer is formed at the position where the semiconductor chip is provided to maintain heat dissipation, and the metal layer at the position where the frame material is provided is excluded. Thereby, the adhesion to the frame material can be improved. In addition, when a metal is used for the bottom plate 11, heat dissipation is excellent, and
Since the difference in thermal expansion coefficient with the semiconductor chip 2 is small, peeling during reflow can be prevented.

As the frame member 12, a polyimide film or a liquid crystal polymer film is used in addition to the resin composite material prepreg. The polyimide film has excellent heat resistance, a small coefficient of thermal expansion, and a close contact with the insulating layer. Because of good properties, peeling during reflow can be prevented.

Further, in the semiconductor package according to the present invention, the insulating layer and the conductor wiring are stacked on one side of the bottom plate. Therefore, it is preferable to use a bottom plate or a frame plate having a relatively high rigidity to prevent warpage in a later step. When copper is used, a copper plate having a thickness of 0.5 mm or more is preferable, and the thickness of the frame plate is preferably about the same as the thickness of the semiconductor chip used.

When a multilayer wiring is formed by laminating an insulating layer and a conductor wiring by a build-up method, heat generated from a chip can be efficiently radiated to the outside by using the substrate according to the present embodiment. Therefore, the effect of suppressing the temperature rise of the chip and preventing malfunction and destruction of the chip can be obtained.

Next, steps for manufacturing the semiconductor device according to the embodiment of the present invention will be described with reference to FIG. First, the substrate 1 having the concave portion 22 is obtained by bonding the frame member 12 and the bottom plate 11 {FIG. 1 (a)}. For bonding, a hot press or a hot laminator is preferable in terms of mass productivity. If the frame material is a composite prepreg, it can be attached as it is, but if it is a resin film, an adhesive must be used.

Next, a semiconductor chip is attached face-up to the recess 22 of the substrate 1 obtained as described above {FIG. 1 (b)}. It is preferable to use a die-bonding agent having high thermal conductivity for the attachment from the viewpoint of high heat dissipation. The die bond material having high thermal conductivity is a material in which a filler such as copper, silver, alumina, diamond, silicon nitride, or boron nitride is highly filled in an epoxy resin or a polyimide resin, and has a thermal conductivity of 2.0 W / m. -K or more is preferable.

Next, a first insulating layer 3 is formed from the top (FIG. 1C).
Any of RCC (Resin Coated Copper) may be used, but the flatness of the upper layer is important from the viewpoint of laminating a multilayer, and in view of this, the film or R
CC is preferable, and the figure shows a case where RCC is used as the insulating layer, and the conductor layer 4 is attached to the insulating layer. The insulation layer is R
In the case of CC, lamination uses a hot press or a vacuum laminator, and in the case of a film, a vacuum laminator is used.

The opening 31 (via hole) is formed in the insulating layer 3 (FIG. 1D). If the insulating layer has photosensitivity, the via hole can be formed by exposure and development at once. If it is possible, and if it has no photosensitivity, a via hole is formed using laser light. As the laser light, a harmonic of a carbon dioxide laser, an excimer laser, or a YAG laser is preferable. Excimer lasers can perform area batch exposure using a mask, and other lasers emit beams one hole at a time. In addition, when a via hole is formed by a laser, an insulating film residue remains at the bottom of the via hole, and when the insulating film does not have a copper foil, the insulating film is formed to have copper plating adhesion. After the patterning step, it is necessary to perform one of a permanganic acid treatment step, a plasma treatment step, and an ozone water treatment step.

The obtained via hole 31 is filled with a conductive material to form an interlayer conductive portion 42 (FIG. 1E). Since the interlayer conductive portion 42 is formed by filling the opening 31 with a conductive material, a stud via can be formed, and high-density mounting is possible. As a filling method, there are a method using copper plating and a method using a conductive paste. When RCC is used for the insulating layer, wiring can be formed without plating by filling via holes with a conductive paste. When filling via holes with conductive paste, it is preferable to use screen printing which can be printed under reduced pressure.However, even if printing under reduced pressure is not possible due to equipment, filling the voidless by curing under pressure Is possible. When no copper foil is attached to the insulating layer, a method of filling via holes by plating is preferable in that the process can be shortened. When filling via holes by copper plating, it is necessary to use a special electrolytic plating solution for via-fill copper plating after ordinary electroless plating, but these are commercially available and can be easily obtained. However, when vias are filled with via fill copper plating, thick C
In some cases, u-plating is formed. In such a case, it is necessary to reduce the thickness of the surface copper plating by half-etching or polishing as necessary.

Next, a conductor wiring 41 is formed on the obtained conductor layer 4 by a normal sub-trust method (FIG. 1F). In the case of forming fine wiring, a semi-additive copper plating method may be applied. This method uses electroless plating
After forming a plating resist pattern, stacking electrolytic plating in the opening, forming the wiring, peeling the resist,
The purpose is to obtain a fine and thick copper wiring pattern by removing the electroless plating remaining between the patterns by soft etching.

Further, by repeating formation of an insulating layer, formation of a via hole, connection (or filling) of a via-hole conductor, and formation of a wiring, a multilayered build-up wiring layer is achieved, and a semiconductor device according to an embodiment of the present invention is obtained. Further, a solder resist 6 is formed on the outermost layer pattern {FIG. 1 (g)}, and bumps 5 and balls for connection are formed (FIG. 1 (h)).

[0026]

[Embodiment 1] 405mm × 3 with 0.5mm thickness
A 40 mm copper plate is used as the bottom plate 11, and after the oxide film removal treatment, a silane coupling agent treatment is performed. Next, a 250 μm thick FR-
5 ｛Product name: Epoxy Multi R-1766, manufactured by Matsushita Electric Works, Ltd. に 15m to glass cloth / epoxy prepreg
A frame material 12 having 28 m-square holes (4 rows vertically and 7 rows horizontally) is formed as a frame material 12 and press-laminated on the copper plate to obtain the substrate 1 provided with the concave portion 22.

A high heat conductive adhesive sheet (trade name: T-gon2000, manufactured by Thermogon Inc.) is formed in the recess 22.
After attaching, a 14 mm square semiconductor chip 2 ｛pin
Number 2025, pad (surface-treated copper) diameter φ100μ
m, a staggered arrangement の having a minimum pitch of 370 μm is pressed face-up. Next, a photosensitive dry film (abbreviated as DF) having a thickness of 68 μm (trade name: ViaLux, Dupo)
｝ manufactured by nt Co., Ltd. is laminated from above with a vacuum laminator, and patterned using ultraviolet rays in accordance with the terminal portion of the chip to form a φ75 μm via hole. Next, after performing a permanganate process (swelling / permanganate treatment / reduction) to roughen the surface of the DF, electroless plating and via-fill electrolytic copper plating. 2) The conductor layer is formed on the DF at the same time that the via hole is filled by performing the manufacturing process. At this time, the thickness of the conductor layer was 25 μm. Next, the conductor layer was half-etched to make the thickness of the conductor layer 10 μm, and then the conductor layer was patterned with an etching dry film. Land diameter on via is φ100 μm, wiring L / S is 30 μm / 3
It was set to 0 μm.

The obtained wiring on the substrate is subjected to a surface treatment (CZ treatment) (trade name: H. Bond, manufactured by Mec Co., Ltd.)
0 μm-thick photosensitive dry film ｛Product name: ViaLu
After laminating x, manufactured by Dupont Co., Ltd., via-hole plated via holes and a conductor layer having a thickness of 10 μm are formed as in the previous step, and a wiring pattern is formed by etching. Thereafter, in a similar process, the conductor layers are sequentially stacked so as to have a total of nine layers, and a solder resist having a terminal portion opened in the uppermost layer is formed. Finally, 28 semiconductor packages were obtained per substrate by cutting into individual pieces. When the thermal resistance between the chip and the bottom surface of the bottom plate of the obtained package was measured, it was 0.1 ° C./W.

Embodiment 2 FIG. 405mm × 0.5mm thick
A 340 mm 42 alloy plate was used as the bottom plate 11 and treated with a silane coupling agent. Thereafter, a 250 μm thick liquid crystal polymer nonwoven fabric / epoxy prepreg having 28 holes of 15 mm square (4 rows and 7 rows) was used as the frame material 12, and the frame material 12 was press-laminated on the alloy plate to form a substrate having a recess 22. 1 was obtained. Highly heat conductive adhesive sheet in recess 22
After attaching T-gon2000, manufactured by Thermagon INC, a 14 mm square semiconductor chip 2 with 202 pins
5. A staggered arrangement の with a pad (surface-treated copper) diameter of φ100 μm and a minimum pitch of 370 μm is pressure-bonded face-up.

Next, RCC (resin thickness 100 μm, copper foil thickness 12 μm) (trade name: R-0870, Matsushita Electric Works, Ltd.)
The product is laminated from above with a hot press, and patterned using a carbon dioxide laser according to the terminal of the chip.
A φ75 μm via hole was formed. However, after this, hole cleaning was performed with oxygen plasma to remove the resin residue remaining on the via bottom. Next, a conductive paste containing a silver-coated copper filler in an epoxy resin (trade name: manufactured by Kyoto Elex Co., Ltd.) is embedded in the via hole using a vacuum screen printer, and after thermosetting, the protruding portion is polished. Removed.

Next, the conductor layer was patterned using an etching dry film. Land diameter on via is φ10
0 μm, and the wiring L / S was 30 μm / 30 μm. The wiring on the obtained substrate is subjected to a blackening treatment, and a 50 μm thick R
After laminating the CCs, laser holes are formed as in the previous step, and via holes and a wiring pattern filled with the conductive paste are formed by etching. Thereafter, in a similar process, the conductor layers are sequentially stacked so as to have a total of nine layers, and a solder resist having a terminal portion opened in the uppermost layer is formed. Finally, 28 semiconductor packages were obtained per substrate by cutting into individual pieces. When the thermal resistance between the chip and the back surface of the bottom plate of the obtained package was measured, it was 0.2 W / ° C.

Embodiment 3 FIG. 405mm x 0.7mm thick
A 340 mm copper plate is used as the bottom plate 11, which is subjected to an oxide film removal treatment and a silane coupling agent treatment. A 150 μm-thick plasma-treated polyimide film with a single-sided adhesive having 28 holes of 15 mm square (4 rows and 7 rows) was thermocompressed to the bottom plate 11 as a frame material 12 to obtain a substrate having a concave portion. Formed. After attaching a high heat conductive adhesive sheet (trade name: T-gon2000, manufactured by Thermogon Inc.) to the concave portion, a 14 mm square semiconductor chip 2 ｛20 pins
25. A staggered arrangement の having a pad (surface-treated copper) diameter of φ100 μm and a minimum pitch of 370 μm is pressure-bonded face-up.

Next, a photosensitive dry film (DF) having a thickness of 68 μm (trade name: ViaLux, Dupont Co., Ltd.)
The product was laminated from above with a vacuum laminator and patterned using ultraviolet light in accordance with the terminal of the chip to form a via hole hole of φ75 μm. Next, perform the permanganate process (swelling, permanganate treatment, reduction)
After surface roughening of the DF, electroless plating and via-fill electrolytic copper plating (trade name: Cubelite, manufactured by Ebara Uzylight Co., Ltd.) are performed to fill the via holes and simultaneously form a conductor layer on the DF. At this time, the conductor layer thickness is 25μ.
m. Next, the conductor layer was half-etched to make the thickness of the conductor layer 10 μm, and then the conductor layer was patterned with an etching dry film. The land diameter on the via was φ100 μm, and the L / S of the wiring was 30 μm / 30 μm. The obtained wiring on the substrate is subjected to a CZ process to be 50 μm
Thick DF @ Trade name: ViaLux, Dupont
After lamination, a via-hole plated via hole and a conductive layer having a thickness of 10 μm are prepared as in the previous step, and a wiring pattern is formed by etching. Thereafter, in a similar process, the conductor layers are sequentially stacked so as to have a total of nine layers, and a solder resist having a terminal portion opened in the uppermost layer is formed. Finally, 28 semiconductor packages were obtained per substrate by cutting into individual pieces. When the thermal resistance between the chip and the back surface of the bottom plate of the obtained package was measured, it was 0.1 W / ° C.

Embodiment 4 FIG. 1mm thick and 18μm thick on both sides
405 mm x 340 mm glass epoxy laminated plate with copper foil attached. (Product name: Epoxy Multi, manufactured by Matsushita Electric Works, Ltd.) Drill four through-holes of φ0.3 mm in advance on the part where the semiconductor chip is mounted. Then, after desmearing, through-hole plating with a thickness of 20 μm is performed to form a thermal buyer hole, which is used as the bottom plate 11.

28 holes of 15 mm square (4 rows vertically, 7 rows horizontally)
Row) Opened 250μm thick glass epoxy prepreg F
R-4 (manufactured by Matsushita Electric Works, Ltd.) was used as the frame member 12 and press-laminated on the bottom plate 11 to form a substrate having a concave portion.
At this time, the thermal buyer hole is exposed in the recess. After attaching a high heat conductive adhesive sheet (trade name: T-gon2000, manufactured by Thermogon Inc.) to the recess, a semiconductor chip 2 of 14 mm square and 20 pins
25. A staggered arrangement の having a pad (surface-treated copper) diameter of φ100 μm and a minimum pitch of 370 μm is pressure-bonded face-up.

Next, a photosensitive dry film (DF) having a thickness of 68 μm (trade name: ViaLux, Dupont Co., Ltd.)
The product was laminated from above with a vacuum laminator and patterned using ultraviolet light in accordance with the terminal of the chip to form a via hole hole of φ75 μm. Next, perform the permanganate process (swelling, permanganate treatment, reduction)
After surface roughening of the DF, electroless plating and via-fill electrolytic copper plating (trade name: Cubelite, manufactured by Ebara Uzylight Co., Ltd.) are performed to fill the via holes and simultaneously form a conductor layer on the DF. At this time, the inside of the thermal buyer is also exposed and plated on the lower surface. At this time, the thickness of the conductor layer was 25 μm. Next, half-etch the conductor layer,
After the thickness of the conductor layer was 10 μm, patterning of the conductor layer was performed using an etching dry film. Land diameter on via is 100 μm, L / S of wiring is 30 μm / 30 μm
And The wiring on the obtained substrate is subjected to CZ processing,
μm-thick DF Product name: ViaLux, Dupont
After laminating｝, a via hole plated with via-fill and a conductor layer having a thickness of 10 μm are formed in the same manner as in the previous step, and a wiring pattern is formed by etching.
Thereafter, in a similar process, the conductor layers are sequentially stacked so as to have a total of nine layers, and a solder resist having a terminal portion opened in the uppermost layer is formed. Finally, 28 semiconductor packages were obtained per substrate by cutting into individual pieces. The thermal resistance between the chip and the bottom surface of the bottom plate of the obtained package was measured and found to be 0.9 W / ° C.

COMPARATIVE EXAMPLE 1. 14 mm square semiconductor chip (pin number: 2025) mounted on a 30 mm square, 5 mm thick glass epoxy laminate (trade name: FR-4, manufactured by Matsushita Electric Works)
A concave portion having the same shape as that of the above was formed by a mechanical cutting method, and the chip was bonded face-up to the substrate concave portion with a silicone die bonding agent. Further, a photosensitive epoxy-based interlayer insulating film (trade name: XP-9500 cc, manufactured by Shipley Far East Co., Ltd.) was applied thereon so as to have a cured thickness of 50 μm, and dried at 90 ° C. for 45 minutes. Perform patterning using ultraviolet light according to the terminal of the chip.
An m via hole was formed. Next, a permanganic acid process (swelling / permanganic acid treatment / reduction) was performed, the surface was roughened, and then electroless copper plating / electrolytic copper plating was performed. Was. Then, copper patterning (L / S = 3
0 μm / 30 μm). Next, a multi-layer wiring was formed by a photo-via build-up method by a similar process for wiring routing. At this time, the via holes in the upper and lower layers were slightly shifted from each other, so that a tear-drop type land was used because the stat via structure could not be obtained. Therefore, two wirings could not be passed between the bumps, and a total of 17 layers had to be stacked. Furthermore, the completed package tried DBA (direct bonding attach) connection with gold bumps when connecting the motherboard, but the terminals settled down when pressed,
No good connection could be obtained. Further, the thermal resistance between the chip and the back surface of the bottom plate of the obtained package was measured.
8 W / ° C., and with this configuration, heat generated from the chip could not be efficiently released.

Comparative Example 2. On a 30 mm square, 1 mm thick copper plate,
14 mm square semiconductor chip (pin number 202)
A concave portion having the same shape as in 5) was formed by a mechanical cutting method, and the chip was bonded face-up to the substrate concave portion with a silicone die bonding agent. Further, a photosensitive epoxy-based interlayer insulating film (trade name: XP-9500 cc, manufactured by Shipley Co., Ltd.) was applied thereon so as to have a cured thickness of 50 μm, and dried at 90 ° C. for 45 minutes. Patterning was performed using ultraviolet light in accordance with the terminal portion of the chip to form a via hole hole of φ75 μm. Next, the permanganate process (swelling /
(Permanganic acid treatment / reduction), surface roughening was performed, and then electroless copper plating / electrolytic copper plating was performed. As a result, plating was formed along the shape of the via hole. Then, patterning of copper by photo etching (L / S = 30)
μm / 30 μm). Next, a multi-layer wiring was formed by a photo-via build-up method by a similar process for wiring routing. At this time, the via holes in the upper and lower layers were slightly shifted from each other, so that a tear-drop type land was used because the stat via structure could not be obtained. Therefore, two wirings could not be passed between the bumps, and a total of 17 layers had to be stacked. When the thermal resistance between the chip and the bottom surface of the bottom plate of the obtained package was measured, it was good. However, for the completed semiconductor package, DBA connection was attempted with gold bumps when connecting the motherboard. Sedimentation occurred, and a good connection was not obtained. When the obtained package was subjected to a solder reflow test, peeling occurred between the metal base portion and the epoxy interlayer insulating film. This is because a large stress is generated due to a difference in thermal expansion between the metal and the interlayer insulating film and a large number of build-up layers.

[0039]

According to the first semiconductor device of the present invention, a substrate having a concave portion, a semiconductor chip embedded in the concave portion, the semiconductor chip and the surface of the substrate are covered, and an opening is provided in a connection terminal portion of the semiconductor chip. An insulating layer, an interlayer conductive portion in which the opening is electrically conductive with a conductive material, and a semiconductor device provided in the insulating layer and provided with a conductor wiring that is conductive to the interlayer conductive portion, wherein the substrate is a thermal buyer. It has a bottom plate made of a resin composite material or metal formed, and a frame material made of polyimide or a resin composite material that has a through hole that is bonded to the bottom plate and that is larger than the semiconductor chip and has excellent heat dissipation. This has the effect that peeling during reflow can be prevented.

According to a second semiconductor device of the present invention, in the above first semiconductor device, an insulating layer having a stud via whose inside is filled with a conductive material and a conductive wiring are formed on the conductive wiring by a build-up method. Since the layers are sequentially stacked, there is an effect that high-density wiring is possible.

According to a third semiconductor device of the present invention, in the first or second semiconductor device, the resin composite material is composed of a resin and a glass cloth, a glass nonwoven fabric, a polyamide nonwoven fabric, or a liquid crystal polymer nonwoven fabric. This has the effect of preventing peeling during reflow and having excellent heat resistance.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a step of manufacturing a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

1 substrate, 11 bottom plate, 12 frame material, 2 semiconductor chip,
22 recess, 3 insulating layer, 4 conductor layer, 41 conductor wiring, 4
2 Interlayer conduction part.

Claims (3)

[Claims] 1. A substrate having a concave portion, a semiconductor chip embedded in the concave portion, an insulating layer covering the surface of the semiconductor chip and the substrate, having an opening in a connection terminal portion of the semiconductor chip, and filling the opening with a conductive material. A semiconductor device provided with an interlayer conductive portion having conductivity, and a conductor wiring provided on the insulating layer and conductive with the interlayer conductive portion, wherein the substrate is made of a resin composite material forming a thermal buyer, or a metal. A semiconductor device comprising: a bottom plate formed of a polyimide or a resin composite material, the bottom plate being bonded to the bottom plate and having a through hole larger than the semiconductor chip. 2. The semiconductor device according to claim 1, wherein an insulating layer having a stud via whose inside is filled with a conductive material and a conductive wiring are sequentially laminated on the conductive wiring by a build-up method. . 3. A resin composite material comprising: a resin; a glass cloth;
2. A nonwoven fabric comprising a glass nonwoven fabric, a polyamide nonwoven fabric or a liquid crystal polymer nonwoven fabric.
Alternatively, the semiconductor device according to claim 2.