JPH11233678A - Manufacture of ic package - Google Patents

Manufacture of ic package

Info

Publication number
JPH11233678A
JPH11233678A JP10033130A JP3313098A JPH11233678A JP H11233678 A JPH11233678 A JP H11233678A JP 10033130 A JP10033130 A JP 10033130A JP 3313098 A JP3313098 A JP 3313098A JP H11233678 A JPH11233678 A JP H11233678A
Authority
JP
Japan
Prior art keywords
chip
build
photosensitive resin
layer
core material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10033130A
Other languages
Japanese (ja)
Inventor
Kazunori Akaho
和則 赤穂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal SMI Electronics Device Inc
Original Assignee
Sumitomo Metal SMI Electronics Device Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal SMI Electronics Device Inc filed Critical Sumitomo Metal SMI Electronics Device Inc
Priority to JP10033130A priority Critical patent/JPH11233678A/en
Publication of JPH11233678A publication Critical patent/JPH11233678A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To avoid connection defects between a build-up multilayer board to an IC chip. SOLUTION: An insulation layer 15 of the same depth as that of an IC chip 11 is formed on a core 13, the IC chip is fitted in a cavity 16 of the insulation layer 15 with its surface up at pads 12, and adhered to the core 13. A photosensitive resin layer 18 is formed on the same plane, formed by the surface of the IC chip 11 at the pads 12 and top surface of the insulation layer 15, and photoetched to form vias, via-conductors 20 and inner layer wiring pattern 21 are formed by plating from above them. Forming of the photosensitive resin layer 18, forming of the vias, and forming of the via-conductors 20 and inner layer wiring pattern 21 are repeated to form a build-up multilayer board 17 on the IC chip 11. A solder paste is printed on the top end portions of the via-conductors 20 of the topmost layer and molten by the reflow to form solder bumps 22.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ビルドアップ多層
基板を用いて構成するＩＣパッケージの製造方法に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an IC package using a build-up multilayer substrate.

【０００２】[0002]

【従来の技術】近年のＩＣチップの高性能化・小型化に
伴い、ＩＣチップを搭載する基板の配線密度の高密度
化、多ピン化が重要な技術的課題となっている。現在、
実用化されている高密度実装基板の一例としてビルドア
ップ多層基板がある。このものは、コア基板となるガラ
スエポキシ基板上にエポキシ系の感光性樹脂層を形成
し、この感光性樹脂層にフォトエッチング法でビアホー
ルを形成した後、その上から、銅めっきで内層導体パタ
ーンやビア導体を形成し、以後、同様の工程を順次繰り
返して多層化するものである。2. Description of the Related Art With the recent increase in performance and miniaturization of IC chips, increasing the wiring density and increasing the number of pins of a substrate on which the IC chip is mounted have become important technical issues. Current,
An example of a high-density mounting board that has been put into practical use is a build-up multilayer board. In this method, an epoxy-based photosensitive resin layer is formed on a glass epoxy substrate serving as a core substrate, a via hole is formed in the photosensitive resin layer by a photo-etching method, and then an inner conductor pattern is formed thereon by copper plating. And via conductors, and thereafter, the same steps are sequentially repeated to form a multilayer.

【０００３】[0003]

【発明が解決しようとする課題】近年のＩＣチップの高
性能化に伴い、ビルドアップ多層基板の積層数が増加す
る傾向があり、それに伴って、内層導体パターンの厚み
によって生じる基板表面の凹凸が大きくなる傾向があ
る。このため、積層数の多いビルドアップ多層基板上に
ＩＣチップをフリップチップボンディング（Ｃ４）で表
面実装すると、基板表面の凹凸によって接続不良が発生
しやすくなる。このため、現状のビルドアップ多層基板
は、基板表面の凹凸を少なくする必要性から積層数が制
限されてしまい、高密度配線化が制限される結果となっ
ていた。With the recent increase in the performance of IC chips, the number of build-up multilayer substrates tends to increase. As a result, unevenness on the surface of the substrate caused by the thickness of the inner conductor pattern is caused. Tends to be larger. For this reason, when an IC chip is surface-mounted by flip chip bonding (C4) on a build-up multilayer substrate having a large number of stacked layers, a connection failure is likely to occur due to unevenness on the substrate surface. For this reason, in the current build-up multilayer substrate, the number of laminations is limited due to the necessity of reducing the unevenness of the substrate surface, and as a result, high-density wiring is limited.

【０００４】本発明はこのような事情を考慮してなされ
たものであり、従ってその目的は、ビルドアップ多層基
板の積層数増加、高密度配線化に対応しつつ、ＩＣチッ
プの接続不良を防止できるＩＣパッケージの製造方法を
提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and accordingly, it is an object of the present invention to prevent a defective connection of an IC chip while coping with an increase in the number of layers of a build-up multi-layer substrate and high-density wiring. An object of the present invention is to provide a method of manufacturing an IC package that can be performed.

【０００５】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明の請求項１のＩＣパッケージの製造方法はＩ
Ｃチップのパッド面を上向きにして、そのパッド面上に
感光性樹脂層を形成し、この感光性樹脂層をフォトエッ
チングしてビアホールを形成した後、その上からめっき
にて配線層を形成し、以後、これら感光性樹脂層の形
成、ビアホールの形成及び配線層の形成を順次繰り返し
て、前記ＩＣチップ上にビルドアップ多層基板を形成す
るものである。このようにすれば、ビルドアップ多層基
板の積層数が何層になっても、ＩＣチップに対するビル
ドアップ多層基板の実装面（最下面）は、凹凸のない平
面となり、ＩＣチップとビルドアップ多層基板との接続
不良が無くなる。According to a first aspect of the present invention, there is provided a method of manufacturing an IC package, comprising the steps of:
With the pad surface of the C chip facing upward, a photosensitive resin layer is formed on the pad surface, the photosensitive resin layer is photoetched to form a via hole, and then a wiring layer is formed by plating from above. Thereafter, the formation of the photosensitive resin layer, the formation of the via hole, and the formation of the wiring layer are sequentially repeated to form a build-up multilayer substrate on the IC chip. In this way, no matter how many layers of the build-up multilayer substrate are stacked, the mounting surface (the lowermost surface) of the build-up multilayer substrate with respect to the IC chip becomes a flat surface without unevenness, and the IC chip and the build-up multilayer substrate Eliminates connection failure.

【０００６】この場合、請求項２のように、コア材上
に、ＩＣチップと同じ厚みの絶縁層を形成すると共に、
この絶縁層にＩＣチップを嵌め込むキャビティを形成
し、ＩＣチップをパッド面を上向きにして前記キャビテ
ィ内に嵌め込んで前記コア材の上面に接合した後、ＩＣ
チップのパッド面と前記絶縁層の上面とで形成される同
一平面上にビルドアップ多層基板を形成すると良い。こ
のようにすれば、ＩＣチップの外周囲に形成した絶縁層
によってビルドアップ多層基板の面積を拡大できると共
に、ＩＣチップをビルドアップ多層基板、絶縁層及びコ
ア材によって封止することができる。また、コア材は、
感光性樹脂層の硬化収縮によるビルドアップ多層基板の
反りを抑える役割を果たす。In this case, an insulating layer having the same thickness as the IC chip is formed on the core material.
After forming a cavity in which the IC chip is fitted in the insulating layer, the IC chip is fitted into the cavity with the pad surface facing upward, and bonded to the upper surface of the core material.
It is preferable to form the build-up multilayer substrate on the same plane formed by the pad surface of the chip and the upper surface of the insulating layer. With this configuration, the area of the build-up multilayer substrate can be increased by the insulating layer formed around the IC chip, and the IC chip can be sealed with the build-up multilayer substrate, the insulating layer, and the core material. The core material is
It plays a role in suppressing the warpage of the build-up multilayer substrate due to the curing shrinkage of the photosensitive resin layer.

【０００７】更に、請求項３のように、ビルドアップ多
層基板の表面に半田バンプを形成し、この半田バンプを
用いて配線基板に搭載するようにしても良い。このよう
にすれば、ビルドアップ多層基板と配線基板との配線距
離が最短となり、低インピーダンス化され、信号の高速
化や高密度配線化にも対応しやすい。Further, a solder bump may be formed on the surface of the build-up multilayer board, and the solder bump may be mounted on the wiring board using the solder bump. By doing so, the wiring distance between the build-up multilayer board and the wiring board is minimized, the impedance is reduced, and it is easy to cope with a high-speed signal and a high-density wiring.

【０００８】また、コア材は、例えばセラミックを用い
ても良いが、請求項４のように、金属板を用いるように
しても良い。金属板のコア材は、ビルドアップ多層基板
の反りを抑えるのに十分な強度を有すると共に、放熱性
が良いため、放熱部材としても利用できる。The core material may be made of, for example, ceramic, but may be made of a metal plate. Since the core material of the metal plate has sufficient strength to suppress the warpage of the build-up multilayer substrate and has good heat dissipation, it can be used as a heat dissipation member.

【０００９】[0009]

【発明の実施の形態】以下、本発明をＢＧＡ(Ball Grid
Array) パッケージに適用した一実施形態を説明する。
まず、図１に基づいてＢＧＡパッケージ２４全体の構造
を説明する。ＩＣチップ１１は、パッド１２側の面を上
向きにして金属板製のコア材１３の上面中央部に接着剤
１４により接着されている。コア材１３上には、ＩＣチ
ップ１１と同じ厚みのエポキシ樹脂の絶縁層１５がＩＣ
チップ１１を取り巻くように形成されている。ＩＣチッ
プ１１のパッド１２側の面と絶縁層１５の上面とで形成
される同一平面上にビルドアップ多層基板１７が形成さ
れている。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be referred to as BGA (Ball Grid).
Array) An embodiment applied to a package will be described.
First, the overall structure of the BGA package 24 will be described with reference to FIG. The IC chip 11 is bonded to the center of the upper surface of a core member 13 made of a metal plate with an adhesive 14 with the surface on the pad 12 side facing upward. An insulating layer 15 of epoxy resin having the same thickness as the IC chip 11 is formed on the core material 13.
It is formed so as to surround the chip 11. A build-up multilayer substrate 17 is formed on the same plane formed by the surface of the IC chip 11 on the pad 12 side and the upper surface of the insulating layer 15.

【００１０】ビルドアップ多層基板１７は、各層の絶縁
層が感光性樹脂層１８で形成され、各感光性樹脂層１８
には、層間を接続するビア導体２０と内層配線パターン
２１（配線層）が形成されている。ビルドアップ多層基
板１７の表面には、半田バンプ２２（半田ボール）が形
成され、この半田バンプ２２以外の部分はソルダーレジ
スト２３で覆われている。以上のように構成されたＢＧ
Ａパッケージ２４は、図２に示すように、半田バンプ２
２を配線基板２５（ドータボード）のパッド２６に位置
合わせしてリフロー半田付けされる。ＢＧＡパッケージ
２４と配線基板２５との間の隙間には、モールド樹脂が
含浸され、このモールド樹脂がＢＧＡパッケージ２４と
配線基板２５とを接合する役割を果たす。In the build-up multilayer substrate 17, the insulating layers of each layer are formed of a photosensitive resin layer 18, and each of the photosensitive resin layers 18
, A via conductor 20 connecting the layers and an inner wiring pattern 21 (wiring layer) are formed. Solder bumps 22 (solder balls) are formed on the surface of the build-up multilayer board 17, and portions other than the solder bumps 22 are covered with a solder resist 23. BG configured as above
The A package 24 is, as shown in FIG.
2 is aligned with the pad 26 of the wiring board 25 (daughter board) and reflow soldered. A gap between the BGA package 24 and the wiring board 25 is impregnated with a mold resin, and this mold resin plays a role in joining the BGA package 24 and the wiring board 25.

【００１１】次に、上記構成のマルチチップモジュール
（ＭＣＭ）の製造方法を図３の工程フローチャートに従
って説明する。コア材１３として、銅板、ステンレス鋼
板等の金属板を用い、その表面に金めっきを施す。この
後、コア材１３上に、エポキシ系の感光性樹脂をスピン
コーター等で塗布して、ＩＣチップ１１と同じ厚みの感
光性の絶縁層１５を形成する。次に、絶縁層１５の中央
部にキャビティ１６をフォトエッチングにより形成する
ために、絶縁層１５に露光（１５００ｍｊ）し、これを
アルカリ現像液（ＮａＯＨ：３％）に例えば８０秒間浸
漬して現像して、この絶縁層１５に、ＩＣチップ１１を
嵌合するためのキャビティ１６を形成する。この後、絶
縁層１５を硬化させるために、ＵＶキュアーを１０００
ｍｊで行い、更に、この絶縁層１５を１５０℃で２時間
加熱して熱硬化させる。Next, a method of manufacturing the multi-chip module (MCM) having the above configuration will be described with reference to the flowchart of FIG. A metal plate such as a copper plate or a stainless steel plate is used as the core material 13 and its surface is plated with gold. Thereafter, an epoxy-based photosensitive resin is applied on the core material 13 by using a spin coater or the like to form a photosensitive insulating layer 15 having the same thickness as the IC chip 11. Next, in order to form a cavity 16 in the central portion of the insulating layer 15 by photoetching, the insulating layer 15 is exposed (1500 mj) and immersed in an alkali developing solution (NaOH: 3%) for, for example, 80 seconds for development. Then, a cavity 16 for fitting the IC chip 11 is formed in the insulating layer 15. Thereafter, in order to cure the insulating layer 15, UV curing is performed for 1000 times.
mj, and the insulating layer 15 is heated at 150 ° C. for 2 hours to be thermally cured.

【００１２】この後、ＩＣチップ１１の下面（パッド１
２側とは反対側の面）に接着剤を塗布して、ＩＣチップ
１１をパッド１２側の面を上向きにしてキャビティ１６
内に嵌め込み、１５０℃で７時間、熱乾燥してＩＣチッ
プ１１をコア材１３の上面に接合する。これにより、Ｉ
Ｃチップ１１のパッド１２側の面と絶縁層１５の上面と
で同一の平面が形成され、この平面上にビルドアップ多
層基板１７を通常のセミアディティブ法により次のよう
にして形成する。Thereafter, the lower surface of IC chip 11 (pad 1
An adhesive is applied to the surface opposite to the second side) so that the IC chip 11 faces the pad 12 side upward and the cavity 16
The IC chip 11 is bonded to the upper surface of the core material 13 by heat drying at 150 ° C. for 7 hours. This allows I
The same plane is formed on the surface of the C chip 11 on the pad 12 side and the upper surface of the insulating layer 15, and a build-up multilayer substrate 17 is formed on this plane by the usual semi-additive method as follows.

【００１３】まず、ＩＣチップ１１のパッド１２側の面
と絶縁層１５の上面とで形成される同一平面にエポキシ
系の感光性樹脂をスピンコーター等で塗布して、９０℃
で３０分間、プリベークして感光性樹脂層１８を形成す
る。この後、感光性樹脂層１８にビアホールをフォトエ
ッチングにより形成するために、感光性樹脂層１８に平
行光を使用して露光（１５００ｍｊ）し、露光後に、再
度９０℃で３０分間、ベークする。次に、この感光性樹
脂層１８をアルカリ現像液（ＮａＯＨ：３％）に例えば
８０秒間浸漬して現像し、感光性樹脂層１８にビアホー
ルを形成する。この後、再度、ＵＶキュアーを１０００
ｍｊで行い、更に、１７５℃で２時間加熱して熱硬化さ
せる。これにより、１層目の感光性樹脂層１８を形成す
る。First, an epoxy-based photosensitive resin is applied on the same plane formed by the surface of the IC chip 11 on the pad 12 side and the upper surface of the insulating layer 15 by a spin coater or the like.
For 30 minutes to form a photosensitive resin layer 18. Thereafter, in order to form a via hole in the photosensitive resin layer 18 by photoetching, the photosensitive resin layer 18 is exposed (1500 mj) using parallel light, and after the exposure, baked again at 90 ° C. for 30 minutes. Next, the photosensitive resin layer 18 is immersed in an alkali developing solution (NaOH: 3%), for example, for 80 seconds to develop, thereby forming a via hole in the photosensitive resin layer 18. Thereafter, the UV cure is again performed for 1000 times.
mj, and further heat at 175 ° C. for 2 hours for thermosetting. Thus, the first photosensitive resin layer 18 is formed.

【００１４】次に、感光性樹脂層１８を７０℃で３分
間、膨潤させた後、感光性樹脂層１８の表面をＫＭｎＯ
4 により８０℃で３分間、ソフトエッチングして粗化す
る。この後、感光性樹脂層１８の粗化表面を水洗し、中
和した後、感光性樹脂層１８の粗化表面全体に無電解Ｃ
ｕめっきを施す。めっき後、無電解Ｃｕめっき被膜の表
面にドライフィルム（感光性フィルム）を１１０℃、４
ｋｇｆ／ｃｍ2 でラミネートする。この後、ドライフィ
ルムのうちのビア・配線パターン形成部分のみを露光
（８０ｍｊ）し、これをアルカリ現像液（炭酸ソーダ：
１％）に浸漬して現像し、ドライフィルムのうちのビア
・配線パターン形成部を除去する。Next, after swelling the photosensitive resin layer 18 at 70 ° C. for 3 minutes, the surface of the photosensitive resin layer 18 is treated with KMnO.
Roughening by soft etching at 80 ° C for 3 minutes according to 4 . Thereafter, the roughened surface of the photosensitive resin layer 18 is washed with water and neutralized.
Apply u plating. After plating, a dry film (photosensitive film) is placed on the surface of the electroless Cu plating film at 110 ° C. for 4 hours.
Laminate at kgf / cm 2 . Thereafter, only the via / wiring pattern forming portion of the dry film is exposed (80 mj), and the exposed portion is exposed to an alkali developing solution (sodium carbonate:
1%) and developed to remove the via / wiring pattern forming portion of the dry film.

【００１５】この後、ドライフィルムの上から電解Ｃｕ
めっきを施して、ビア導体２０と内層配線パターン２１
に対応する部分に電解Ｃｕめっきパターンを形成する。
めっき後、アセトンでドライフィルムを剥離した後、電
解Ｃｕめっきパターンをエッチングレジスト（マスク）
として用いて、無電解Ｃｕめっき被膜の不要部分をエッ
チングにより取り除く。これにより、感光性樹脂層１８
のビアホールにビア導体２０を形成し、このビア導体２
０をＩＣチップ１１のパッド１２に導通させると共に、
感光性樹脂層１８の上面に内層配線パターン２１を形成
する。Thereafter, electrolytic Cu is applied on the dry film.
Plating is applied to the via conductor 20 and the inner wiring pattern 21.
An electrolytic Cu plating pattern is formed in a portion corresponding to.
After plating, the dry film is peeled off with acetone, and then the electrolytic Cu plating pattern is etched with a resist (mask).
The unnecessary portion of the electroless Cu plating film is removed by etching. Thereby, the photosensitive resin layer 18
A via conductor 20 is formed in the via hole of
0 is conducted to the pad 12 of the IC chip 11 and
An inner wiring pattern 21 is formed on the upper surface of the photosensitive resin layer 18.

【００１６】以上の工程で、１層目の感光性樹脂層１８
の形成、ビアホールの形成及びビア導体２０と内層配線
パターン２１の形成を終了し、以後、これらの工程を必
要な積層数になるまで順次繰り返して、ＩＣチップ１１
上にビルドアップ多層基板１７を形成する。In the above steps, the first photosensitive resin layer 18
And the formation of the via hole and the formation of the via conductor 20 and the inner layer wiring pattern 21 are completed. Thereafter, these steps are sequentially repeated until the required number of laminations is obtained.
The build-up multilayer substrate 17 is formed thereon.

【００１７】このようにして、ＩＣチップ１１上にビル
ドアップ多層基板１７を形成すれば、ＩＣチップ１１の
パッド１２に半田（Ｐｂ）バンプを形成しなくても、パ
ッド１２にビア導体２０を直接接続することが可能とな
り、Ｐｂ不使用（Ｐｂフリー化）の要求を満たすことが
できる。If the build-up multilayer board 17 is formed on the IC chip 11 in this manner, the via conductor 20 can be directly applied to the pad 12 without forming a solder (Pb) bump on the pad 12 of the IC chip 11. The connection can be established, and the requirement of Pb non-use (Pb free) can be satisfied.

【００１８】ビルドアップ多層基板１７の形成後、ビル
ドアップ多層基板１７の上面全体に感光性のソルダーレ
ジスト２３をスピンコーター等で塗布し、これを露光、
現像して、最上層のビア導体２０の上端部分をビルドア
ップ多層基板１７の上面のソルダーレジスト２３の被膜
から露出させる。そして、ソルダーレジスト２３を熱硬
化させた後、最上層のビア導体２０の上端露出部分に半
田ペーストをスクリーン印刷し、これをリフローにより
溶融させて半田バンプ２２を形成する。以上の工程によ
り、図１に示す構造のＢＧＡパッケージ２４が形成され
る。After the formation of the build-up multilayer substrate 17, a photosensitive solder resist 23 is applied to the entire upper surface of the build-up multilayer substrate 17 with a spin coater or the like, and this is exposed,
By developing, the upper end portion of the uppermost via conductor 20 is exposed from the coating of the solder resist 23 on the upper surface of the build-up multilayer substrate 17. Then, after the solder resist 23 is thermally cured, a solder paste is screen-printed on an exposed upper end portion of the uppermost via conductor 20, and the solder paste is melted by reflow to form a solder bump 22. Through the above steps, the BGA package 24 having the structure shown in FIG. 1 is formed.

【００１９】この後、ＢＧＡパッケージ２４の半田バン
プ２２を配線基板２５のパッド２６に位置合わせしてリ
フロー半田付けした後、ＢＧＡパッケージ２４と配線基
板２５との間の隙間にモールド樹脂を含浸して、ＢＧＡ
パッケージ２４と配線基板２５とを接合する。これによ
り、図２に示す構造のマルチチップモジュール（ＭＣ
Ｍ）が製造される。Thereafter, the solder bumps 22 of the BGA package 24 are aligned with the pads 26 of the wiring board 25, and reflow soldering is performed. , BGA
The package 24 and the wiring board 25 are joined. Thereby, the multi-chip module (MC) having the structure shown in FIG.
M) is manufactured.

【００２０】ところで、ビルドアップ多層基板１７は、
感光性樹脂層１８の硬化収縮によって反りが生じやすい
が、図１の構造では、コア材１３がこの基板の反りを抑
える役割を果たす。Incidentally, the build-up multilayer substrate 17
Although warpage is likely to occur due to curing shrinkage of the photosensitive resin layer 18, in the structure of FIG. 1, the core material 13 plays a role in suppressing the warpage of the substrate.

【００２１】本発明者は、コア材１３が基板の反りを抑
える効果を評価する試験を行ったので、その試験結果を
次の表１に示す。The present inventor conducted a test for evaluating the effect of the core material 13 on suppressing the warpage of the substrate. The test results are shown in Table 1 below.

【００２２】[0022]

【表１】 [Table 1]

【００２３】この試験に用いた各サンプルのサイズは、
縦８８ｍｍ×横８８ｍｍ×厚さ８００μｍである。サン
プルＮＯ．１は、コア材として樹脂板を用い、サンプル
ＮＯ．２は、コア材として厚さ０．４ｍｍのＣｕ板を用
い、サンプルＮＯ．３は、コア材として厚さ１．０ｍｍ
のＣｕ板を用いた。各サンプルについて、それぞれ１０
個ずつ反り量を測定したところ、サンプルＮＯ．１（樹
脂板）は反り量が５０００±１５０μｍであったのに対
し、サンプルＮＯ．２（厚さ０．４ｍｍのＣｕ板）は、
反り量が１０００±１５０μｍであり、反り量がサンプ
ルＮＯ．１の１／５に減少した。更に、サンプルＮＯ．
３（厚さ１．０ｍｍのＣｕ板）は、反り量が３０±５μ
ｍであり、反りが効果的に抑えられた。The size of each sample used in this test was
It is 88 mm long × 88 mm wide × 800 μm thick. Sample No. Sample No. 1 uses a resin plate as a core material. Sample No. 2 used a 0.4 mm thick Cu plate as a core material. 3 is 1.0 mm thick as a core material
Was used. For each sample, 10
When the amount of warpage was measured for each sample, the sample NO. Sample No. 1 (resin plate) had a warpage of 5000 ± 150 μm. 2 (0.4 mm thick Cu plate)
The amount of warpage was 1000 ± 150 μm, and the amount of warpage was the same as that of Sample No. Reduced to 1/5 of 1. Further, the sample No.
3 (1.0 mm thick Cu plate) has a warpage of 30 ± 5 μm.
m, and the warpage was effectively suppressed.

【００２４】尚、コア材として、Ｃｕ板、ステンレス鋼
板等の金属板を用いれば、反り防止効果と共に放熱効果
も得られる利点があるが、金属板に限定されず、セラミ
ック板、ガラス板、強化樹脂板等を用いても良い。ま
た、ＩＣチップ１１の外周囲の絶縁層をコア材と一体に
形成しても良い。更に、コア材上に複数個のＩＣチップ
を接合するようにしても良い。When a metal plate such as a Cu plate or a stainless steel plate is used as the core material, there is an advantage that a heat dissipation effect can be obtained as well as a warp prevention effect. A resin plate or the like may be used. Further, an insulating layer around the IC chip 11 may be formed integrally with the core material. Further, a plurality of IC chips may be bonded on the core material.

【００２５】[0025]

【発明の効果】以上の説明から明らかなように、本発明
の請求項１のＩＣパッケージの製造方法によれば、ＩＣ
チップ上にビルドアップ多層基板を形成するようにした
ので、ビルドアップ多層基板の積層数が何層になって
も、ＩＣチップとビルドアップ多層基板との接合不良を
防止できると共に、ＩＣチップに半田（Ｐｂ）バンプを
形成しなくても、ＩＣチップとビルドアップ多層基板と
を接続することができて、Ｐｂ不使用（Ｐｂフリー化）
の要求を満たすことができる。As is apparent from the above description, according to the method of manufacturing an IC package of claim 1 of the present invention,
Since the build-up multilayer board is formed on the chip, no matter how many layers of the build-up multilayer board are stacked, it is possible to prevent the bonding failure between the IC chip and the build-up multilayer board and to solder the IC chip. (Pb) Even without forming a bump, an IC chip and a build-up multilayer substrate can be connected, and Pb is not used (Pb free).
Can meet the requirements of

【００２６】更に、請求項２では、コア材上にＩＣチッ
プと同じ厚みの絶縁層を形成するようにしたので、ビル
ドアップ多層基板の面積を拡大できると共に、コア材に
よってビルドアップ多層基板の反りを抑えることがで
き、しかも、ＩＣチップをビルドアップ多層基板、絶縁
層及びコア材によって封止することができる。Further, according to the present invention, since the insulating layer having the same thickness as the IC chip is formed on the core material, the area of the build-up multilayer substrate can be enlarged, and the warpage of the build-up multilayer substrate due to the core material. And the IC chip can be sealed with the build-up multilayer substrate, the insulating layer and the core material.

【００２７】また、請求項３では、ビルドアップ多層基
板の表面に半田バンプを形成したので、ＢＧＡ方式で配
線基板に実装でき、高密度実装化に対応できる。According to the third aspect, since the solder bumps are formed on the surface of the build-up multilayer board, the bumps can be mounted on the wiring board by the BGA method, and it is possible to cope with high-density mounting.

【００２８】また、請求項４では、コア材として金属板
を用いるようにしたので、基板の反り抑制効果と放熱性
を共に高めることができる。Further, in the fourth aspect, since the metal plate is used as the core material, both the effect of suppressing the warpage of the substrate and the heat radiation can be enhanced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施形態におけるＢＧＡパッケージ
の構造を示す縦断面図FIG. 1 is a longitudinal sectional view showing a structure of a BGA package according to an embodiment of the present invention.

【図２】ＢＧＡパッケージを配線基板に実装した状態を
示す縦断面図FIG. 2 is a longitudinal sectional view showing a state in which a BGA package is mounted on a wiring board;

【図３】マルチチップモジュールの製造方法を示す工程
フローチャートFIG. 3 is a process flowchart showing a method for manufacturing a multi-chip module.

【符号の説明】[Explanation of symbols]

１１…ＩＣチップ、１２…パッド、１３…コア材、１４
…接着剤、１５…絶縁層、１６…キャビティ、１７…ビ
ルドアップ多層基板、１８…感光性樹脂層、２０…ビア
導体（配線層）、２１…内層配線パターン（配線層）、
２２…半田バンプ、２３…ソルダーレジスト、２４…Ｂ
ＧＡパッケージ（ＩＣパッケージ）、２５…配線基板、
２６…パッド。11: IC chip, 12: Pad, 13: Core material, 14
... adhesive, 15 ... insulating layer, 16 ... cavity, 17 ... build-up multilayer substrate, 18 ... photosensitive resin layer, 20 ... via conductor (wiring layer), 21 ... inner layer wiring pattern (wiring layer),
22 solder bump, 23 solder resist, 24 B
GA package (IC package), 25 ... wiring board,
26 ... Pad.

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 ＩＣチップのパッド面を上向きにして、
そのパッド面上に感光性樹脂層を形成し、この感光性樹
脂層をフォトエッチングしてビアホールを形成した後、
その上からめっきにて配線層を形成し、以後、前記感光
性樹脂層の形成、ビアホールの形成及び配線層の形成を
順次繰り返して、前記ＩＣチップ上にビルドアップ多層
基板を形成するＩＣパッケージの製造方法。1. An IC chip having a pad surface facing upward,
After forming a photosensitive resin layer on the pad surface and photo-etching the photosensitive resin layer to form a via hole,
After that, a wiring layer is formed by plating, and thereafter, the formation of the photosensitive resin layer, the formation of the via hole, and the formation of the wiring layer are sequentially repeated to form a build-up multilayer substrate on the IC chip. Production method. 【請求項２】 コア材上に、前記ＩＣチップと同じ厚み
の絶縁層を形成すると共に、この絶縁層に前記ＩＣチッ
プを嵌め込むキャビティを形成し、前記ＩＣチップをパ
ッド面を上向きにして前記キャビティ内に嵌め込んで前
記コア材の上面に接合した後、前記ＩＣチップのパッド
面と前記絶縁層の上面とで形成される同一平面上に前記
ビルドアップ多層基板を形成することを特徴とする請求
項１に記載のＩＣパッケージの製造方法。2. An insulating layer having the same thickness as the IC chip is formed on a core material, and a cavity for fitting the IC chip in the insulating layer is formed, and the IC chip is placed with its pad surface facing upward. After being fitted into the cavity and joined to the upper surface of the core material, the build-up multilayer substrate is formed on the same plane formed by the pad surface of the IC chip and the upper surface of the insulating layer. A method for manufacturing an IC package according to claim 1. 【請求項３】 前記ビルドアップ多層基板の表面に半田
バンプを形成し、この半田バンプを用いて配線基板に搭
載することを特徴とする請求項１又は２に記載のＩＣパ
ッケージの製造方法。3. The method of manufacturing an IC package according to claim 1, wherein solder bumps are formed on a surface of the build-up multilayer board, and the solder bumps are mounted on a wiring board using the solder bumps. 【請求項４】 前記コア材として金属板を用いることを
特徴とする請求項２に記載のＩＣパッケージの製造方
法。4. The method according to claim 2, wherein a metal plate is used as the core material.
JP10033130A 1998-02-16 1998-02-16 Manufacture of ic package Pending JPH11233678A (en)

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Publication Number Publication Date
JPH11233678A true JPH11233678A (en) 1999-08-27

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