JP2004095836A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2004095836A
JP2004095836A JP2002254695A JP2002254695A JP2004095836A JP 2004095836 A JP2004095836 A JP 2004095836A JP 2002254695 A JP2002254695 A JP 2002254695A JP 2002254695 A JP2002254695 A JP 2002254695A JP 2004095836 A JP2004095836 A JP 2004095836A
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Japan
Prior art keywords
semiconductor
embedding material
semiconductor device
rewiring
insulating film
Prior art date
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Granted
Application number
JP2002254695A
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Japanese (ja)
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JP3888267B2 (en
Inventor
Hiroyasu Sadabetto
定別当　裕康
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
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Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority to JP2002254695A priority Critical patent/JP3888267B2/en
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to KR1020047005322A priority patent/KR100593049B1/en
Priority to PCT/JP2003/009958 priority patent/WO2004015771A2/en
Priority to EP03784529A priority patent/EP1527480A2/en
Priority to AU2003253425A priority patent/AU2003253425C1/en
Priority to CA2464078A priority patent/CA2464078C/en
Priority to CN038012693A priority patent/CN1568546B/en
Priority to TW092121811A priority patent/TWI231551B/en
Publication of JP2004095836A publication Critical patent/JP2004095836A/en
Priority to US10/826,039 priority patent/US7294922B2/en
Priority to HK05105873.6A priority patent/HK1073389A1/en
Priority to US11/671,318 priority patent/US7547967B2/en
Priority to US11/671,268 priority patent/US7618886B2/en
Application granted granted Critical
Publication of JP3888267B2 publication Critical patent/JP3888267B2/en
Priority to US12/415,782 priority patent/US7737543B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To connect a silicon substrate and solder balls through conductive connection without effecting the bonding process when manufacturing a semiconductor device called as a BGA(ball grid array), for example. <P>SOLUTION: A lattice embedding member 34 is bonded onto a bonding layer above a base board 21 having a size coping with a plurality of semiconductor devices. Next, a semiconductor constituting body 23, provided on the silicon substrate 24 with a rewiring 31, a columnar electrode 32 and a sealing film 33, is bonded onto the bonding layer 22 in the opening of the embedding member 34. Next, a sealing film 36 is formed between the semiconductor constituting body 23 and a square frame embedding member 34 at the outside of the semiconductor constituting body 23. Next, a first upper layer insulating film 37, a first upper layer rewiring 39, a second upper layer insulating film 41, a second upper layer rewiring 43 and a third upper layer insulating film 44 are formed in the form of lamination and subsequently solder balls 46 are formed. Next, when the mutually neighbored semiconductor constituting body 23 is cut along a boundary line between the constituting bodies, a plurality of semiconductor devices equipped with the solder balls 46 are obtained. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
この発明は半導体装置およびその製造方法に関する。
【０００２】
【従来の技術】
例えばＢＧＡ（ｂａｌｌ　ｇｒｉｄ　ａｒｒａｙ）と呼ばれる半導体装置には、ＬＳＩなどからなる半導体チップを該半導体チップのサイズよりもやや大きいサイズの中継基板（インターポーザ）の上面中央部に搭載し、中継基板の下面に半田ボールによる接続端子をマトリクス状に配置したものがある。ここで、中継基板は、半導体チップ上に形成された外部接続電極を他の回路基板にボンディングする際、接続強度および信頼性を得るために、再配線によりそのサイズおよびピッチを充分大きなものとするために用いられる。
【０００３】
図５１は従来のこのような半導体装置の一例の断面図を示したものである。半導体チップ１は、シリコン基板２の下面周辺部に銅などからなる複数のバンプ電極３が設けられた構造となっている。
【０００４】
中継基板４は、サイズが半導体チップ１のシリコン基板２のサイズよりもやや大きいベースフィルム５を備えている。ベースフィルム５の上面には、半導体チップ１のバンプ電極３に接続される再配線６が設けられている。
【０００５】
再配線６は、半導体チップ１のバンプ電極３に対応して設けられた第１の接続パッド７と、マトリクス状に設けられた第２の接続パッド８と、第１と第２の接続パッド７、８を接続する引き回し線９とからなっている。第２の接続パッド８の中央部に対応する部分におけるベースフィルム５には円孔１０が設けられている。
【０００６】
そして、半導体チップ１は中継基板４の上面中央部に異方性導電接着剤１１を介して搭載されている。異方性導電接着剤１１は、熱硬化性樹脂１２中に多数の導電性粒子１３を含有させたものからなっている。
【０００７】
半導体チップ１を中継基板４上に搭載する場合には、まず、中継基板４の上面中央部にシート状の異方性導電接着剤１１を介して半導体チップ１を位置合わせしてただ単に載置する。
【０００８】
次に、熱硬化性樹脂１２が硬化する温度にて所定の圧力を加えてボンディングする。すると、バンプ電極３が熱硬化性樹脂１２を押し退けて第１の接続パッド７の上面に導電性粒子１３を介して導電接続され、且つ、半導体チップ１の下面が中継基板４の上面に熱硬化性樹脂１２を介して接着される。
【０００９】
次に、半導体チップ１を含む中継基板４の上面全体にエポキシ系樹脂からなる樹脂封止膜１４を形成する。次に、円孔１０内およびその下方に半田ボール１５を第２の接続パッド８に接続させて形成する。この場合、第２の接続パッド８はマトリクス状に配置されているため、半田ボール１５もマトリクス状に配置される。
【００１０】
ここで、半田ボール１５のサイズは半導体チップ１のバンプ電極３のサイズより大きく、また、各半田ボール１５相互の接触を避けるため、その配置間隔をバンプ電極３の配置間隔より大きくする必要がある。そこで、半導体チップ１のバンプ電極３の数が増大した場合、各半田ボール１５に必要な配置間隔を得るため、その配置領域を半導体チップ１のサイズより大きくすることが必要となり、そのために、中継基板４のサイズを半導体チップ１のサイズよりもやや大きくしている。したがって、マトリクス状に配置された半田ボール１５のうち、周辺部の半田ボール１５は半導体チップ１の周囲に配置されている。
【００１１】
【発明が解決しようとする課題】
ところで、上記従来の半導体装置では、再配線６が形成された中継基板４を用い、位置合わせした後のボンディングにより、半導体チップ１のバンプ電極３の下面を中継基板４の再配線６の第１の接続パッド７の上面に異方性導電接着剤１１の導電性粒子１３を介して導電接続する構成としているので、半導体チップ１のバンプ電極３の数が増大し、バンプ電極３のサイズおよび配置間隔が小さくなると、位置合わせが極めて大変であるという問題があった。この場合、半導体チップ１のサイズを大きくすれば、バンプ電極３のサイズおよび配置間隔を大きくすることができることは当然であるが、そのようにすると、ウエハ状態からの半導体チップの取り数が激減し、極めて高価なものとなってしまう。また、半導体チップ１を１つずつ中継基板４上にボンディングして搭載しなければならず、製造工程が煩雑であるという問題があった。このようなことは、半導体チップを複数個備えたマルチチップモジュール型の半導体装置の場合も同様である。
【００１２】
そこで、この発明は、ボンディングによることなく外部接続電極の配置間隔を大きくすることができる半導体装置およびその製造方法を提供することを目的とする。
また、この発明は、複数の半導体装置を一括して製造することができる半導体装置の製造方法を提供することを目的とする。
【００１３】
【課題を解決するための手段】
請求項１に記載の発明は、半導体基板上に設けられた複数の再配線および該各再配線の上に設けられた柱状電極を有する半導体構成体と、該半導体構成体の側方に設けられた枠状の埋込材と、前記半導体構成体の柱状電極を除く上面全体に設けられた絶縁膜と、該絶縁膜および前記埋込材上に、前記柱状電極に接続されて設けられ且つ接続パッド部を有する少なくとも一層の上層再配線とを備え、前記上層再配線の中、最上層の上層再配線の少なくとも一部の接続パッド部は前記埋込材上に配置されていることを特徴とするものである。
請求項２に記載の発明は、各々が、半導体基板と、該半導体基板上に設けられた複数の再配線および該各再配線上に設けられた柱状電極を有し、相互に離間して配置された複数の半導体構成体と、前記半導体構成体の間または前記各半導体構成体の側方に設けられた埋込材と、前記各半導体構成体の柱状電極を除く上面全体に設けられた絶縁膜と、該絶縁膜および前記埋込材上に、前記柱状電極に接続されて設けられ且つ接続パッド部を有する少なくとも一層の上層再配線とを備え、前記上層再配線の中、最上層の上層再配線の少なくとも一部の接続パッド部は前記埋込材上に配置されていることを特徴とするものである。
請求項３に記載の発明は、請求項１または２に記載の発明において、前記半導体構成体と前記埋込材との間に別の絶縁膜が設けられていることを特徴とするものである。
請求項４に記載の発明は、請求項１または２に記載の発明において、前記埋込材の下面は前記半導体構成体の下面とほぼ同一の平面上に配置されていることを特徴とするものである。
請求項５に記載の発明は、請求項１または２に記載の発明において、前記埋込材の上面は前記半導体構成体の上面とほぼ同一の平面上に配置されていることを特徴とするものである。
請求項６に記載の発明は、請求項１または２に記載の発明において、前記埋込材の上面は前記半導体構成体の上面と異なる高さ位置に配置されていることを特徴とするものである。
請求項７に記載の発明は、請求項１または２に記載の発明において、前記半導体構成体および前記埋込材はベース板上に設けられていることを特徴とするものである。
請求項８に記載の発明は、請求項１または２に記載の発明において、前記上層再配線はメッキ層を含むことを特徴とするものである。
請求項９に記載の発明は、請求項１または２に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記半導体構成体の柱状電極と前記上層再配線とを接続する層間再配線が設けられていることを特徴とするものである。
請求項１０に記載の発明は、請求項１または２に記載の発明において、前記上層再配線を含む前記絶縁膜の上面に前記上層再配線の接続パッド部の少なくとも一部を除く部分に最上層絶縁膜が設けられていることを特徴とするものである。請求項１１に記載の発明は、請求項１０に記載の発明において、前記上層再配線の接続パッド部上に突起状の接続端子が設けられていることを特徴とするものである。
請求項１２に記載の発明は、請求項１１に記載の発明において、前記突起状の接続端子は半田ボールであることを特徴とするものである。
請求項１３に記載の発明は、請求項１または２に記載の発明において、前記上層再配線の一部の一端部は前記埋込材の端面まで延ばされ、この端面近傍における部分は接続端子となっていることを特徴とするものである。
請求項１４に記載の発明は、ベース板上に、少なくとも一方向に所定間隔で埋込材を配置する工程と、各々が、複数の再配線および該各再配線上に設けられた柱状電極を有する複数の半導体構成体を、前記ベース板上の一方向において、前記埋込材が前記半導体構成体の所定個数毎にその側方に介在されるように配置する工程と、接続パッド部を有し且ついずれかの前記半導体構成体の対応する前記柱状電極に接続される上層再配線を、少なくともいずれかの前記上層再配線の接続パッド部が前記埋込材上に配置されるように形成する工程と、前記半導体構成体間における前記埋込材を切断して少なくともいずれかの前記上層再配線の接続パッド部が前記半導体構成体の側方に介在された前記埋込材上に配置された前記半導体構成体を少なくとも１つ有する半導体装置を複数個得る工程とを有することを特徴とするものである。
請求項１５に記載の発明は、請求項１４に記載の発明において、前記半導体構成体と前記埋込材との間に別の絶縁膜を形成する工程を有することを特徴とするものである。
請求項１６に記載の発明は、請求項１４に記載の発明において、前記埋込材を切断する工程は、前記半導体構成体が複数個含まれるように切断することを特徴とするものである。
請求項１７に記載の発明は、請求項１６に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記各半導体構成体の柱状電極とそれに対応する前記上層再配線とを接続する複数組の層間再配線を形成する工程を有することを特徴とするものである。
請求項１８に記載の発明は、請求項１６に記載の発明において、前記上層再配線を含む前記絶縁膜の上面において前記上層再配線の接続パッド部を除く部分に最上層絶縁膜を形成する工程を有することを特徴とするものである。
請求項１９に記載の発明は、請求項１８に記載の発明において、前記上層再配線の接続パッド部上に突起状の接続端子を形成する工程を有することを特徴とするものである。
請求項２０に記載の発明は、請求項１６に記載の発明において、前記埋込材を切断する工程は前記埋込材を切断するとともに前記ベース板を切断し、前記半導体装置としてベース板を備えたものを得ることを特徴とするものである。
請求項２１に記載の発明は、請求項２０に記載の発明において、切断前の前記ベース板下に別のベース板を配置し、前記ベース板を切断した後に、前記別のベース板を取り除く工程を有することを特徴とするものである。
そして、この発明によれば、半導体基板上に再配線および柱状電極を有する複数または複数組の半導体構成体および埋込材をベース板上に配置し、半導体構成体上の絶縁膜および埋込材上に上層再配線を半導体構成体の柱状電極に接続させて形成し、埋込材を少なくとも切断することにより、半導体構成体を１つまたは１組有するとともに埋込材を有し、且つ、埋込材上に上層再配線の一部が配置されてなる半導体装置を複数個一括して得ることができ、従来のようなボンディング工程がなく、したがってボンディングによることなく外部接続電極の配置間隔を大きくすることができ、また複数または複数組の半導体構成体に対して絶縁膜および上層再配線の形成を一括して行うことができるので、製造工程を簡略化することができる。
【００１４】
【発明の実施の形態】
（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示したものである。この半導体装置は、シリコン、ガラス、セラミックス、樹脂、金属などからなる平面正方形状のベース板２１を備えている。ベース板２１の上面には、接着剤、粘着シート、両面接着テープなどからなる接着層２２が設けられている。
【００１５】
接着層２２の上面中央部には、ベース板２１のサイズよりもやや小さいサイズの平面正方形状の半導体構成体２３の下面が接着されている。この場合、半導体構成体２３は、ＣＳＰ（ｃｈｉｐ　ｓｉｚｅ　ｐａｃｋａｇｅ）と呼ばれるものであり、接着層２２の上面中央部に接着されたシリコン基板（半導体基板）２４を備えている。シリコン基板２４の上面周辺部にはアルミニウムなどからなる複数の接続パッド２５が設けられ、接続パッド２５の中央部を除くシリコン基板２４の上面には酸化シリコンなどからなる絶縁膜２６が設けられている。
【００１６】
シリコン基板２４上に接続パッド２５および絶縁膜２６を設けてなるものは、通常、ウエハ状態の半導体基板をダイシングして個々のチップとなした場合に得られるものである。しかしながら、この発明では、ウエハ状態の半導体基板上に接続パッド２５および絶縁膜２６が形成された状態では、ダイシングを行わず、以下に説明するように、再配線および柱状電極を有する半導体構成体２３が得られる状態でウエハ状態の半導体基板をダイシングする。まず、半導体構成体２３の構成について説明する。
【００１７】
シリコン基板２４上に形成された絶縁膜２６上にはポリイミドなどからなる保護膜２７が設けられている。接続パッド２５の中央部は、絶縁膜２６および保護膜２７に形成された開口部２８を介して露出されている。開口部２８を介して露出された接続パッド２５の上面から保護膜２７の上面の所定の箇所にかけて下地金属層３１ａおよび該下地金属層３１ａ上に設けられた上層金属層３１ｂからなる再配線３１が設けられている。
【００１８】
再配線３１の接続パッド部上面には銅からなる柱状電極３２が設けられている。再配線３１を含む保護膜２７の上面にはエポキシ系樹脂などからなる封止膜（絶縁膜）３３がその上面が柱状電極３２の上面と面一となるように設けられている。このように、半導体構成体２３は、シリコン基板２４、接続パッド２５、絶縁膜２６を含み、さらに、保護膜２７、再配線３１、柱状電極３２、封止膜３３を含んで構成されている。
【００１９】
半導体構成体２３の周囲における接着層２２の上面には方形枠状の埋込材３４が接着されている。この場合、埋込材３４の材料は、ベース板２１と同じであってもよく、また別であってもよい。また、埋込材３４の厚さは、半導体構成体２３の全体の厚さとほぼ同じとなっている。さらに、半導体構成体２３とその外側に配置された方形枠状の埋込材３４との間には比較的狭い隙間３５が形成されている。隙間３５にはエポキシ系樹脂などからなる封止膜（絶縁膜）３６がその上面が封止膜３３および埋込材３４の上面とほぼ面一となるように設けられている。
【００２０】
半導体構成体２３、埋込材３４および封止膜３６の上面全体にはポリイミドなどからなる第１の上層絶縁膜３７が設けられている。第１の上層絶縁膜３７の柱状電極３２の上面中央部に対応する部分には開口部３８が設けられている。開口部３８を介して露出された柱状電極３２の上面から第１の上層絶縁膜３７の上面の所定の箇所にかけて第１の下地金属層３９ａおよび該第１の下地金属層３９ａ上に設けられた第１の上層金属層３９ｂからなる第１の上層再配線３９が設けられている。
【００２１】
第１の上層再配線３９を含む第１の上層絶縁膜３７の上面全体にはポリイミドなどからなる第２の上層絶縁膜４１が設けられている。第２の上層絶縁膜４１の第１の上層再配線３９の接続パッド部に対応する部分には開口部４２が設けられている。開口部４２を介して露出された第１の上層再配線３９の接続パッド部上面から第２の上層絶縁膜４１の上面の所定の箇所にかけて第２の下地金属層４３ａおよび該第２の下地金属層４３ａ上に設けられた第２の上層金属層４３ｂからなる第２の上層再配線４３が設けられている。
【００２２】
第２の上層再配線４３を含む第２の上層絶縁膜４１の上面全体にはポリイミドなどからなる第３の上層絶縁膜４４が設けられている。第３の上層絶縁膜４４の第２の上層再配線４３の接続パッド部に対応する部分には開口部４５が設けられている。開口部４５内およびその上方には半田ボール（突起状の接続端子）４６が第２の上層再配線４３の接続パッド部に接続されて設けられている。複数の半田ボール４６は、第３の上層絶縁膜４４上にマトリクス状に配置されている。
【００２３】
ところで、ベース板２１のサイズを半導体構成体２３のサイズよりもやや大きくしているのは、シリコン基板２４上の接続パッド２５の数の増加に応じて、半田ボール４６の配置領域を半導体構成体２３のサイズよりもやや大きくし、これにより、接続パッド２５のサイズおよび配置間隔を柱状電極３２のサイズおよび配置間隔よりも大きくするためである。
【００２４】
このため、マトリクス状に配置された第２の上層再配線４３の接続パッド部（第３の上層絶縁膜４４の開口部４５内の部分）は、半導体構成体２３に対応する領域のみでなく、半導体構成体２３の周囲に設けられた埋込材３４およびその間の隙間３５に設けられた封止膜３６の領域上にも配置されている。つまり、マトリクス状に配置された半田ボール４６のうち、少なくとも最外周の半田ボール４６は半導体構成体２３よりも外側に位置する周囲に配置されている。
【００２５】
この場合、変形例として、第２の上層再配線４３の接続パッド部を全て半導体構成体２３よりも外側に位置する周囲に配置するようにしてもよい。また、上層の再配線を１層として、つまり第１の上層再配線３９のみとして、少なくとも、最外周の接続パッド部を半導体構成体２３よりも外側に位置する周囲に配置することもできる。
【００２６】
このように、この半導体装置では、シリコン基板２４上に、接続パッド２５、絶縁膜２６を有するのみでなく、保護膜２７、再配線３１、柱状電極３２、封止膜３３などをも形成した半導体構成体２３の周囲に封止膜３６および埋込材３４を設け、その上面に少なくとも第１の上層絶縁膜３７および該第１の上層絶縁膜３７に形成された開口部３８を介して柱状電極３２に接続される第１の上層再配線３９を設ける構成を特徴としている。
【００２７】
この場合、半導体構成体２３とその外側に配置された方形枠状の埋込材３４との間に比較的狭い隙間３５を形成し、この隙間３５内にエポキシ系樹脂などからなる封止膜３６を設けているので、埋込材３４が無い場合と比較して、封止膜３６の量を埋込材３４の体積の分だけ少なくすることができる。この結果、エポキシ系樹脂などからなる封止膜３６の硬化時の収縮による応力を小さくすることができ、ひいてはベース基板２１が反りにくいようにすることができる。
【００２８】
次に、この半導体装置の製造方法の一例について説明するに、まず、半導体構成体２３の製造方法の一例について説明する。この場合、まず、図２に示すように、ウエハ状態のシリコン基板（半導体基板）２４上にアルミニウムからなる接続パッド２５、酸化シリコンからなる絶縁膜２６およびポリイミドからなる保護膜２７が設けられ、接続パッド２５の中央部が絶縁膜２６および保護膜２７に形成された開口部２８を介して露出されたものを用意する。
【００２９】
次に、図３に示すように、開口部２８を介して露出された接続パッド２５の上面を含む保護膜２７の上面全体に下地金属層３１ａを形成する。この場合、下地金属層３１ａは、無電解メッキにより形成された銅層のみからなっているが、スパッタにより形成された銅層のみであってもよく、またスパッタにより形成されたチタンなどの薄膜層上にスパッタにより銅層を形成したものであってもよい。これは、後述する上層下地金属層３９ａ、４３ａの場合も同様である。
【００３０】
次に、下地金属層３１ａの上面にメッキレジスト膜５１をパターン形成する。この場合、再配線３１形成領域に対応する部分におけるメッキレジスト膜５１には開口部５２が形成されている。次に、下地金属層３１ａをメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト膜５１の開口部５２内の下地金属層３１ａの上面に上層金属層３１ｂを形成する。次に、メッキレジスト膜５１を剥離する。
【００３１】
次に、図４に示すように、上層金属層３１ｂを含む下地金属層３１ａの上面にメッキレジスト膜５３をパターン形成する。この場合、柱状電極３２形成領域に対応する部分におけるメッキレジスト膜５３には開口部５４が形成されている。次に、下地金属層３１ａをメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト膜５３の開口部５４内の上層金属層３１ｂの接続パッド部上面に柱状電極３２を形成する。
【００３２】
次に、メッキレジスト膜５３を剥離し、次いで、柱状電極３２および上層金属層３１ｂをマスクとして下地金属層３１ａの不要な部分をエッチングして除去すると、図５に示すように、上層金属層３１ｂ下にのみ下地金属層３１ａが残存され、この残存された下地金属層３１ａおよびその上面全体に形成された上層金属層３１ｂにより再配線３１が形成される。
【００３３】
次に、図６に示すように、柱状電極３２および再配線３１を含む保護膜２７の上面全体にエポキシ系樹脂からなる封止膜３３をその厚さが柱状電極３２の高さよりも厚くなるように形成する。したがって、この状態では、柱状電極３２の上面は封止膜３３によって覆われている。次に、封止膜３３および柱状電極３２の上面側を適宜に研磨し、図７に示すように、柱状電極３２の上面を露出させ、且つ、この露出された柱状電極３２の上面を含む封止膜３３の上面を平坦化する。次に、図８に示すように、ダンシング工程を経ると、図１に示す半導体構成体２３が複数個得られる。
【００３４】
ところで、柱状電極３２の上面側を適宜に研磨するのは、電解メッキにより形成される柱状電極３２の高さにばらつきがあるため、このばらつきを解消して、柱状電極３２の高さを均一にするためである。また、この場合、銅からなる柱状電極３２の上面側を研磨するため、高価で高精度なグラインダーを用いている。
【００３５】
次に、このようにして得られた半導体構成体２３を用いて、図１に示す半導体装置を製造する場合の一例について説明する。まず、図９に示すように、図１に示すベース板２１を複数枚採取することができるベース板２１の上面全体に接着層２２が設けられたものを用意する。
【００３６】
そして、接着層２２の上面の所定の箇所に格子状の埋込材３４の下面を接着する。格子状の埋込材３４は、一例として、シリコン、ガラス、セラミックス、樹脂、金属などからなるシート状の埋込材３４に型抜き加工やエッチングなどにより複数の方形状の開口部３４ａを形成することにより得られる。また、シート状の埋込材３４を接着層２２の上面全体に接着し、座ぐり加工により、格子状の埋込材３４を形成するようにしてもよい。
【００３７】
次に、格子状の埋込材３４の各開口部３４ａ内における接着層２２の上面中央部にそれぞれ半導体構成体２３のシリコン基板２４の下面を接着する。この状態では、埋込材３４の上面と半導体構成体２３の上面とはほぼ同一の平面上に配置されている。また、半導体構成体２３とその外側に配置された方形枠状の埋込材３４との間には比較的狭い隙間３５が形成されている。
【００３８】
次に、図１０に示すように、隙間３５を含む半導体構成体２３および埋込材３４の上面全体にエポキシ系樹脂からなる封止膜３６を印刷などにより塗布する。したがって、この状態では、半導体構成体２３および埋込材３４の上面は封止膜３６によって覆われている。次に、半導体構成体２３および埋込材３４の上面を覆っている未硬化の封止膜３６をバフ研磨により除去することにより、図１１に示すように、半導体構成体２３および埋込材３４の上面を露出させ、且つ、隙間３５内に設けられた封止膜３６の上面を半導体構成体２３および埋込材３４の上面とほぼ面一とし、全体としての上面をほぼ平坦化する。次に、封止膜３６を硬化させる。
【００３９】
ところで、この場合の研磨は、半導体構成体２３の上面側つまり銅からなる柱状電極３２の上面側を研磨するのではなく、半導体構成体２３および埋込材３４の上面を覆っている未硬化の封止膜３６を除去するものであるので、安価で低精度のバフを用いても何ら支障はない。なお、隙間３５内に設けられた未硬化の封止膜３６を研磨し過ぎないためと封止膜３６の硬化収縮を小さくするために、塗布後の封止膜３６を紫外線照射や加熱により仮硬化させるようにしてもよい。また、隙間３５内に設けられた封止膜３６の硬化収縮が大きくて平坦化が不十分な場合には、封止樹脂の塗布および研磨を繰り返すようにしてもよい。
【００４０】
なお、研磨の他の例としては、安価で低精度のエンドレス研磨ベルトの一部をフラット化し、このフラット化した部分で半導体構成体２３および埋込材３４の上面を覆っている未硬化または仮硬化の封止膜３６を半導体構成体２３および埋込材３４の上面を研磨制限面として平滑化研磨するようにしてもよい。
【００４１】
また、半導体構成体２３とその外側に配置された方形枠状の埋込材３４との間に比較的狭い隙間３５を形成し、この隙間３５内にエポキシ系樹脂からなる封止膜３６を設けているので、埋込材３４が無い場合と比較して、封止膜３６の量を埋込材３４の体積の分だけ少なくすることができる。この結果、エポキシ系樹脂からなる封止膜３６の硬化時の収縮による応力を小さくすることができ、ひいてはベース板２１が反りにくいようにすることができる。
【００４２】
さて、図１１に示す研磨工程が終了したら、次に、図１２に示すように、ほぼ面一となった半導体構成体２３、埋込材３４および封止膜３６の上面全体に第１の上層絶縁膜３７を形成する。この第１の上層絶縁膜３７は、感光性ポリイミド、感光性ポリベンザオキサゾール、感光性エポキシ樹脂、感光性ノボラック樹脂、感光性アクリル系カルゾ樹脂などからなり、ドライフィルム化されている。したがって、このドライフィルム化されたものをラミネータによりラミネートすると、第１の上層絶縁膜３７が形成される。なお、後述する第２および第３の上層絶縁膜４１、４４の場合も同様であるが、印刷などの塗布法により形成するようにしてもよい。
【００４３】
次に、第１の上層絶縁膜３７の柱状電極３２の上面中央部に対応する部分に、フォトリソグラフィにより、開口部３８を形成する。次に、図１３に示すように、開口部３８を介して露出された柱状電極３２の上面を含む第１の上層絶縁膜３７の上面全体に第１の下地金属層３９ａを形成する。次に、第１の下地金属層３９ａの上面にメッキレジスト膜５５をパターン形成する。この場合、第１の上層再配線３９形成領域に対応する部分におけるメッキレジスト膜５５には開口部５６が形成されている。次に、第１の下地金属層３９ａをメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト膜５５の開口部５６内の第１の下地金属層３９ａの上面に第１の上層金属層３９ｂを形成する。
【００４４】
次に、メッキレジスト膜５５を剥離し、次いで、第１の上層金属層３９ｂをマスクとして第１の下地金属層３９ａの不要な部分をエッチングして除去すると、図１４に示すように、第１の上層金属層３９ｂ下にのみ第１の下地金属層３９ａが残存され、この残存された第１の下地金属層３９ａおよびその上面全体に形成された第１の上層金属層３９ｂにより第１の上層再配線３９が形成される。
【００４５】
次に、図１５に示すように、第１の上層再配線３９を含む第１の上層絶縁膜３７の上面全体に感光性ポリイミドなどからなる第２の上層絶縁膜４１をパターン形成する。この場合、第２の上層絶縁膜４１の第１の上層再配線３９の接続パッド部に対応する部分には開口部４２が形成されている。次に、開口部４２を介して露出された第１の上層再配線３９の接続パッド部を含む第２の上層絶縁膜４１の上面全体に第２の下地金属層４３ａを無電解メッキにより形成する。
【００４６】
次に、第２の下地金属層４３ａの上面にメッキレジスト膜５７をパターン形成する。この場合、第２の上層再配線４３形成領域に対応する部分におけるメッキレジスト膜５７には開口部５８が形成されている。次に、第２の下地金属層４３ａをメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト膜５７の開口部５８内の第２の下地金属層４３ａの上面に第２の上層金属層４３ｂを形成する。
【００４７】
次に、メッキレジスト膜５７を剥離し、次いで、第２の上層金属層４３ｂをマスクとして第２の下地金属層４３ａの不要な部分をエッチングして除去すると、図１６に示すように、第２の上層金属層４３ｂ下にのみ第２の下地金属層４３ａが残存され、この残存された第２の下地金属層４３ａおよびその上面全体に形成された第２の上層金属層４３ｂにより第２の上層再配線４３が形成される。
【００４８】
次に、図１７に示すように、第２の上層再配線４３を含む第２の上層絶縁膜４１の上面全体に感光性ポリイミドなどからなる第３の上層絶縁膜４４をパターン形成する。この場合、第３の上層絶縁膜４４の第２の上層再配線４３の接続パッド部に対応する部分には開口部４５が形成されている。次に、開口部４５内およびその上方に半田ボール４６を第２の上層再配線４３の接続パッド部に接続させて形成する。
【００４９】
次に、図１８に示すように、互いに隣接する半導体構成体２３間において、３層の絶縁膜４４、４１、３７、埋込材３４、接着層２２およびベース板２１を切断すると、図１に示す半導体装置が複数個得られる。
【００５０】
このようにして得られた半導体装置では、半導体構成体２３の柱状電極３２に接続される第１の下地金属層３９ａおよび第１の上層金属層３９ｂを無電解メッキ（またはスパッタ）および電解メッキにより形成し、第１の上層再配線３９の接続パッド部に接続される第２の下地金属層４３ａおよび第２の上層金属層４３ｂを無電解メッキ（またはスパッタ）および電解メッキにより形成しているので、ボンディングによらないで、半導体構成体２３の柱状電極３２と第１の上層再配線３９との間および第１の上層再配線３９と第２の上層再配線４３との間を導電接続することができる。
【００５１】
また、上記製造方法では、ベース板２１上の接着層２２上に格子状の埋込材３４および複数の半導体構成体２３を接着して配置し、複数の半導体構成体２３に対して封止膜３６、第１〜第３の上層絶縁膜３７、４１、４４、第１、第２の下地金属層３９ａ、４３ａ、第１、第２の上層金属層３９ｂ、４４ｂおよび半田ボール４６の形成を一括して行い、その後に分断して複数個の半導体装置を得ているので、製造工程を簡略化することができる。
【００５２】
また、ベース板２１と共に複数の半導体構成体２３を搬送することができるので、これによっても製造工程を簡略化することができる。さらに、ベース板２１の外形寸法を一定にすると、製造すべき半導体装置の外形寸法に関係なく、搬送系を共有化することができる。
【００５３】
さらに、上記製造方法では、図９に示すように、再配線３１および柱状電極３２を備えたＣＳＰタイプの半導体構成体２３を接着層２２上に接着しているので、例えば、シリコン基板２４上に接続パッド２５および絶縁膜２６を設けてなる通常の半導体チップを接着層２２上に接着して、半導体チップの周囲に設けられた封止膜上などに再配線および柱状電極を形成する場合と比較して、コストを低減することができる。
【００５４】
例えば、切断前のベース板２１がシリコンウエハのように一定のサイズのほぼ円形状である場合、接着層２２上に接着された半導体チップの周囲に設けられた封止膜上などに再配線および柱状電極を形成すると、処理面積が増大する。換言すれば、低密度処理になるため、一回当たりの処理枚数が低減し、スループットが低下するので、コストアップとなる。
【００５５】
これに対し、上記製造方法では、再配線３１および柱状電極３２を備えたＣＳＰタイプの半導体構成体２３を接着層２２上に接着した後に、ビルドアップしているので、プロセス数は増大するが、柱状電極３２を形成するまでは高密度処理のため、効率が良く、プロセス数の増大を考慮しても、全体の価格を低減することができる。
【００５６】
なお、上記実施形態においては、半田ボール４６を、半導体構成体２３上および埋込材３４上の全面に対応してマトリクス状に配列されるよう設けているが、半田ボール４６を半導体構成体２３の周囲の埋込材３４上に対応する領域上にのみ設けるようにしてもよい。その場合、半田ボール４６を半導体構成体２３の全周囲ではなく、半導体構成体２３の４辺の中、１〜３辺の側方のみに設けてもよい。また、このような場合には、埋込材３４を方形枠状のものとする必要はなく、半田ボール４６を設ける辺の側方のみに配置されるようにしてもよい。また、埋込材３４は、印刷、転写、成形などによって形成してもよく、さらに、ベース板２１上に半導体構成体２３を配列した後に形成するようにしてもよい。
【００５７】
次に、図１に示す半導体装置の製造方法の他の例について説明する。まず、図１９に示すように、紫外線透過性の透明樹脂板やガラス板などからなる別のベース板６０の上面全体に紫外線硬化型の粘着シートなどからなる接着層６１を接着し、接着層６１の上面に上述のベース板２１および接着層２２を接着したものを用意する。
【００５８】
そして、図９〜図１７にそれぞれ示す製造工程を経た後に、図２０に示すように、３層の絶縁膜４４、４１、３７、埋込材３４、接着層２２、ベース板２１および接着層６１を切断し、別のベース板６０を切断しない。次に、別のベース板６０の下面側から紫外線を照射し、接着層６１を硬化させる。すると、分断されたベース板２１の下面に対する接着層６１による接着性が低下する。そこで、接着層６１上に存在する個片化されたものを１つずつ剥がしてピックアップすると、図１に示す半導体装置が複数個得られる。
【００５９】
この製造方法では、図２０に示す状態において、接着層６１上に存在する個片化された半導体装置がバラバラとならないので、専用の半導体装置載置用トレーを用いることなく、そのまま、図示しない回路基板上への実装時に１つずつ剥がしてピックアップすることができる。また、別のベース板６０の上面に残存する接着性が低下した接着層６１を剥離すると、別のベース板６０を再利用することができる。さらに、別のベース板６０の外形寸法を一定にすると、製造すべき半導体装置の外形寸法に関係なく、搬送系を共有化することができる。
【００６０】
なおここで、別のベース板６０として、膨張させることにより半導体装置を取り外す、通常のダイシングテープなどを用いることも可能であり、その場合には、接着層は紫外線硬化型でなくてもよい。また、別のベース板６０を研磨やエッチングにより除去するようにしてもよい。
【００６１】
次に、図１に示す半導体装置の製造方法のさらに他の例について説明する。この製造方法では、図１２に示す製造工程後に、図２１に示すように、開口部３８を介して露出された柱状電極３２の上面を含む第１の上層絶縁膜３７の上面全体に銅の無電解メッキにより第１の下地金属層３９ａを形成する。次に、第１の下地金属層３９ａをメッキ電流路として銅の電解メッキを行うことにより、第１の下地金属層３９ａの上面全体に第１の上層金属形成用層３９ｃを形成する。次に、第１の上層金属形成用層３９ｃの上面の第１の上層再配線形成領域に対応する部分にレジスト膜６２をパターン形成する。
【００６２】
次に、レジスト膜６２をマスクとして第１の上層金属形成用層３９ｃおよび第１の下地金属層３９ａの不要な部分をエッチングして除去すると、図２２に示すように、レジスト膜６２下にのみ第１の上層配線層３９が残存される。この後、レジスト膜６２を剥離する。なお、これと同様の形成方法により、第２の上層再配線４３を形成するようにしてもよい。
【００６３】
ところで、図９に示すベース板２１あるいは図１９に示す別のベース板６０をトレイ状とすることもできる。つまり、ベース板を、半導体構成体２３を配列する領域が周囲より陥没した受け皿のような形状とする。そして、このトレイ状のベース板の半導体構成体２３配列領域を囲む周囲の上面にメッキ電流路用金属層を設け、このメッキ電流路用金属層とメッキ電流路用の下地金属層（３９ａ、４３ａ）とを導電部材で接続して、電解メッキを行うようにしてもよい。この場合、トレイの外形サイズを同一としておくことにより、製造する半導体装置のサイズが異なる場合でも、同一の製造装置の使用が可能となり効率的となる。
【００６４】
（第２実施形態）
図９に示す製造工程において、接着層２２を半導体構成体２３のシリコン基板２４の下面および埋込材３４の下面にそれぞれ設け、これらの接着層２２をベース板２１の上面の各所定の箇所に接着した場合には、図２３に示すこの発明の第２実施形態としての半導体装置が得られる。
【００６５】
このようにして得られた半導体装置では、例えば、シリコン基板２４の下面が接着層２２を介してベース板２１の上面に接着されているほかに、シリコン基板２４の側面などが封止膜３６を介してベース板２１の上面に接合されているので、半導体構成体２３および埋込材３４のベース板２１に対する接合強度をある程度強くすることができる。
【００６６】
（第３、第４実施形態）
図２４はこの発明の第３実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、ベース板２１および接着層２２を備えていないことである。
【００６７】
この第３実施形態の半導体装置を製造する場合には、例えば図１７に示すように、半田ボール４６を形成した後に、ベース板２１および接着層２２を研磨やエッチングなどにより除去し、次いで互いに隣接する半導体構成体２３間において、３層の絶縁膜４４、４１、３７および埋込材３４を切断すると、図２４に示す半導体装置が複数個得られる。このようにして得られた半導体装置では、ベース板２１および接着層２２を備えていないので、その分だけ、薄型化することができる。
【００６８】
また、ベース板２１および接着層２２を研磨やエッチングなどにより除去した後に、シリコン基板２４、埋込材３４および封止膜３６の下面側を適宜に研磨し、次いで互いに隣接する半導体構成体２３間において、３層の絶縁膜４４、４１、３７および埋込材３４を切断すると、図２５に示すこの発明の第４実施形態としての半導体装置が複数個得られる。このようにして得られた半導体装置では、さらに薄型化することができる。
【００６９】
なお、半田ボール４６を形成する前に、ベース板２１および接着層２２を研磨やエッチングなどにより除去し（必要に応じてさらにシリコン基板２４、埋込材３４および封止膜３６の下面側を適宜に研磨し）、次いで半田ボール４６を形成し、次いで互いに隣接する半導体構成体２３間において、３層の絶縁膜４４、４１、３７および埋込材３４を切断するようにしてもよい。
【００７０】
（第５実施形態）
図２６はこの発明の第５実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、接着層２２の下面に放熱用の金属層６３が接着されていることである。金属層６３は、厚さ数十μｍの銅箔などからなっている。
【００７１】
この第５実施形態の半導体装置を製造する場合には、例えば図１７に示すように、半田ボール４６を形成した後に、ベース板２１を研磨やエッチングなどにより除去し、次いで接着層２２の下面全体に金属層６３を接着し、次いで互いに隣接する半導体構成体２３間において、３層の絶縁膜４４、４１、３７、埋込材３４、接着層２２および金属層６３を切断すると、図２６に示す半導体装置が複数個得られる。
【００７２】
なお、接着層２２も研磨やエッチングなどにより除去し（必要に応じてさらにシリコン基板２４、埋込材３４および封止膜３６の下面側を適宜に研磨し）、シリコン基板２４、埋込材３４および封止膜３６の下面に新たな接着層を介して金属層６３を接着するようにしてもよい。
【００７３】
（第６実施形態）
図２７はこの発明の第６実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、第１、第２の上層絶縁膜３７、４１の開口部３８、４２のサイズを可及的に小さくし、且つ、これらの開口部３８、４２上における第１、第２の上層再配線３９、４３のランドを可及的に小さくしたことである。
【００７４】
例えば、第１の上層再配線３９は柱状電極３２上にメッキにより直接接合されるものであるため、第１の上層絶縁膜３７の開口部３８は、１０μｍ×１０μｍの方形または同面積の円形の面積を有していれば強度的に十分である。したがって、第１の上層絶縁膜３７の開口部３８のサイズを可及的に小さくすることができ、且つ、この開口部３８上における第１の上層再配線３９のランドを可及的に小さくすることができる。
【００７５】
このように、この第６実施形態によれば、第１、第２の上層絶縁膜３７、４１の開口部３８、４２のサイズを可及的に小さくし、且つ、これらの開口部３８、４２上における第１、第２の上層再配線３９、４３のランドを可及的に小さくすることができるので、第１、第２の上層再配線３９、４３の占有面積を小さくすることができる。この結果、半導体構成体２３のシリコン基板２４上の接続パッド２５（つまり柱状電極３２）の数が増大しても、半導体装置全体としてのサイズを小さいものとすることができる。
【００７６】
（第７実施形態）
図２８はこの発明の第７実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、上層の再配線を１層として、つまり第１の上層再配線３９のみとして、半導体構成体２３の再配線３１の一部をクロス再配線としたことである。
【００７７】
すなわち、半導体構成体２３の保護膜２７上に面積的に余裕がある場合には、保護膜２７上に接続パッド２５と接続されない再配線３１Ａを設け、この再配線３１Ａの両端部上に柱状電極３２Ａを設け、この柱状電極３２Ａと本来の柱状電極３２に第１の上層再配線３９を接続し、再配線３１Ａをクロス再配線としたものである。このようにすれば、上層の再配線の層数を少なくすることができる。
【００７８】
（第８、第９実施形態）
図２９はこの発明の第８実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、第１の上層絶縁膜３７を省略し、封止膜３６を隙間３５の周囲における半導体構成体２３および埋込材３４の各上面にやや盛り上げるように設け、この盛り上げ部、半導体構成体２３および埋込材３４の上面に第１の上層再配線３９を設けたことである。
【００７９】
この場合、封止膜３６は、メタルマスクなどを用いてあるいはスクリーン印刷により形成する。なお、隙間３５の周囲における半導体構成体２３および埋込材３４の各上面にやや盛り上げるように設けられた未硬化または仮硬化の封止膜３６をバフ研磨などにより除去した場合には、図３０に示すこの発明の第９実施形態としての半導体装置が得られる。
【００８０】
（第１０実施形態）
図３１はこの発明の第１０実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、第２の上層配線層４３および第３の上層絶縁膜４４を省略し、第１の上層再配線３７の接続パッド部上に半田ボール４６を設け、埋込材３４の上面に再配線６４を設けたことである。この場合、埋込材３４上の再配線６４の両端部は、その上を覆っている第１の上層絶縁膜３７に形成された開口部３８を介して第１の上層再配線３９に接続されている。
【００８１】
（第１１実施形態）
図３２はこの発明の第１１実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図３１に示す半導体装置と異なる点は、封止膜３６および第１の上層絶縁膜３７をダイコーターなどを用いて感光性ポリイミドなどを塗布して一体的に形成したことである。この場合、第１の上層絶縁膜３７への開口部３８の形成は、フォトリソグラフィであってもよく、またＣＯ２レーザの照射であってもよい。
【００８２】
なお、この場合の塗布材料が熱可塑性樹脂や硬化前に比較的低温加熱で流動状態となる流動化可能な樹脂である場合には、塗布により一体的に形成された絶縁膜３６、３７の平坦化は、加熱加圧処理であってもよい。ここで、図１２に示す第１の上層絶縁膜３７も、このような塗布材料で形成する場合には、その平坦化は加熱加圧処理であってもよい。
【００８３】
（第１２実施形態）
図３３はこの発明の第１２実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図３１に示す半導体装置と異なる点は、第１の上層絶縁膜３７を省略し、半導体構成体２３の上面周辺部、封止膜３６の上面および再配線６４を含む埋込材３４の上面全体に別の第１の上層絶縁膜６５をスクリーン印刷などにより形成したことである。
【００８４】
この場合、埋込材３４上の再配線６４の両端部は、その上を覆っている別の第１の上層絶縁膜６５にＣＯ２レーザの照射などにより形成された開口部６６を介して第１の上層再配線３９に接続されている。また、第１の上層再配線３９は柱状電極３２の上面に絶縁膜の開口部を介することなく直接接続されている。
【００８５】
（第１３、第１４実施形態）
図３４はこの発明の第１３実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図３１に示す半導体装置と大きく異なる点は、再配線６４を含む埋込材３４の高さが半導体構成体２３の高さよりも低くなっていることである。
【００８６】
この場合、再配線６４を含む埋込材３４の上面は封止膜３６で覆われている。また、埋込材３４上の再配線６４の両端部は、その上を覆っている封止膜３６にＣＯ２レーザの照射などにより形成された開口部６７内に必要に応じて充填された導電性樹脂などからなる導電材６８を介して第１の上層再配線３９に接続されている。
【００８７】
なお、図３５に示すこの発明の第１４実施形態のように、再配線６４を含む埋込材３４の高さが半導体構成体２３の高さよりも高くなるようにしてもよい。この場合、半導体構成体２３の上面は封止膜３６で覆われている。また、柱状電極３２は、その上を覆っている封止膜３６にＣＯ２レーザの照射などにより形成された開口部６９内に必要に応じて充填された導電性樹脂などからなる導電材７０を介して第１の上層再配線３９に接続されている。
【００８８】
（第１５実施形態）
図１８に示す場合には、互いに隣接する半導体構成体２３間において切断したが、これに限らず、２個またはそれ以上の半導体構成体２３を１組として切断し、例えば、図３６に示すこの発明の第１５実施形態のように、３個の半導体構成体２３を１組として切断し、マルチチップモジュール型の半導体装置を得るようにしてもよい。この場合、３個で１組の半導体構成体２３は同種、異種のいずれであってもよい。
【００８９】
（第１６実施形態）
図３７はこの発明の第１６実施形態としての半導体装置の断面図を示したものである。この半導体装置では、平面正方形状のベース板７１の上面中央部に第１の接着層７２ａを介して図１に示す場合と同様の第１の半導体構成体７３ａのシリコン基板７４ａの下面が接着されている。
【００９０】
第１の半導体構成体７３ａの周囲におけるベース板７１の上面には方形枠状の第１の埋込材７５ａの下面が接合されている。第１の半導体構成体７３ａと第１の埋込材７５ａとの間には第１の封止膜７６ａが設けられている。第１の半導体構成体７３ａ、第１の埋込材７５ａおよび第１の封止膜７６ａの上面の所定の箇所には第１の上層再配線７７ａが第１の半導体構成体７３ａの柱状電極７８ａに接続されて設けられている。
【００９１】
第１の上層再配線７７ａを含む第１の半導体構成体７３ａの上面には第２の接着層７２ｂを介して図１に示す場合と同様の第２の半導体構成体７３ｂのシリコン基板７４ｂの下面が接着されている。第１の上層再配線７７ａを含む第１の埋込材７５ａの上面には方形枠状の第２の埋込材７５ｂの下面が接合されている。この場合、第２の埋込材７５ｂ内の所定の箇所には上下導通部７９ｂが設けられている。この上下導通部７９ｂの下面は第１の上層再配線７７ａの接続パッドに接続されている。第２の半導体構成体７３ｂと第２の埋込材７５ｂとの間には第２の封止膜７６ｂが設けられている。
【００９２】
第２の半導体構成体７３ｂ、第２の埋込材７５ｂおよび第２の封止膜７６ｂの上面の所定の箇所には第２の上層再配線７７ｂが第２の半導体構成体７３ｂの柱状電極７８ｂおよび第２の埋込材７５ｂ内の上下導通部７９ｂに接続されて設けられている。第２の上層再配線７７ｂを含む第２の半導体構成体７３ｂの上面には第３の接着層７２ｃを介して図１に示す場合と同様の第３の半導体構成体７３ｃのシリコン基板７４ｃの下面が接着されている。
【００９３】
第２の上層再配線７７ｂを含む第２の埋込材７５ｂの上面には方形枠状の第３の埋込材７５ｃの下面が接合されている。この場合、第３の埋込材７５ｃ内の所定の箇所には上下導通部７９ｃが設けられている。この上下導通部７９ｃの下面は第２の上層再配線７７ｂの接続パッドに接続されている。第３の半導体構成体７３ｃと第３の埋込材７５ｃとの間には第３の封止膜７６ｃが設けられている。
【００９４】
第３の半導体構成体７３ｃ、第３の埋込材７５ｃおよび第３の封止膜７６ｃの上面の所定の箇所には第３の上層再配線７７ｃが第３の半導体構成体７３ｃの柱状電極７８ｃおよび第３の埋込材７５ｃ内の上下導通部７９ｃに接続されて設けられている。第３の上層再配線７７ｃを含む第３の半導体構成体７３ｃ、第３の埋込材７５ｃおよび第３の封止膜７６ｃの上面全体には上層絶縁膜８０が設けられている。上層絶縁膜８０上の所定の箇所には半田ボール８１が第３の上層再配線７７ｃの接続パッドに接続されて設けられている。
【００９５】
次に、この半導体装置の製造方法の一例について説明する。まず、図３８に示すように、図３７に示すベース板７１を複数枚採取することができるベース板７１の上面の所定の箇所に格子状の第１の埋込材７５ａを配置する。この場合、ベース板７１、第１の埋込材７５ａおよび後述する第２、第３の埋込材７５ｂ、７５ｃは熱可塑性樹脂からなっている。そして、加熱加圧により、第１の埋込材７５ａをベース板７１の上面の所定の箇所に接合する。
【００９６】
次に、図３９に示すように、格子状の第１の埋込材７５ａの各開口部内におけるベース板７１の上面中央部にそれぞれ第１の半導体構成体７３ａのシリコン基板７４ａの下面を該下面に予め接着された第１の接着層７２ａを介して接着する。この状態では、第１の埋込材７５ａの上面と第１の半導体構成体７３ａの上面とはほぼ同一の平面上に配置されている。また、第１の半導体構成体７３ａとその外側に配置された方形枠状の第１の埋込材７５ａとの間には比較的狭い第１の隙間８２ａが形成されている。
【００９７】
次に、図４０に示すように、第１の隙間８２ａ内に第１の封止膜７６ａを形成する。次に、第１の半導体構成体７３ａ、第１の埋込材７５ａおよび第１の封止膜７６ａの上面の所定の箇所に第１の上層再配線７７ａを第１の半導体構成体７３ａの柱状電極７８ａに接続させて形成する。
【００９８】
次に、図４１に示すように、第１の上層再配線７７ａを含む格子状の第１の埋込材７５ａの上面に格子状の第２の埋込材７５ｂを熱圧着する。この場合、第２の埋込材７５ｂ内の所定の箇所には上下導通材７９ｂが予め形成されている。そして、熱圧着により、第１の上層再配線７７ａによる段差は解消され、第２の埋込材７５ｂ内の上下導通材７９ｂの下面は第１の上層再配線７７ａの接続パッドに接続される。
【００９９】
次に、図４２に示すように、格子状の第２の埋込材７５ｂの開口部内における第１の上層再配線７７ａを含む第１の半導体構成体７３ａの上面に第２の半導体構成体７３ｂのシリコン基板７４ｂの下面を該下面に予め接着された第２の接着層７２ｂを介して接着する。
【０１００】
次に、第２の半導体構成体７３ｂとその外側に配置された方形枠状の第２の埋込材７５ｂとの間に形成された比較的狭い第２の隙間内に第２の封止膜７６ｂを形成する。次に、第１の半導体構成体７３ａ、第１の埋込材７５ａおよび第１の封止膜７６ａの上面の所定の箇所に第２の上層再配線７７ｂを第２の半導体構成体７３ｂの柱状電極７８ｂおよび第２の埋込材７５ｂ内の上下導通材７９ｂに接続させて形成する。
【０１０１】
次に、図４３に示すように、第２の上層再配線７７ｂを含む格子状の第２の埋込材７５ｂの上面に格子状の第３の埋込材７５ｃを熱圧着する。この場合、第３の埋込材７５ｃ内の所定の箇所には上下導通材７９ｃが予め形成されている。そして、熱圧着により、第２の上層再配線７７ｂによる段差は解消され、第３の埋込材７５ｃ内の上下導通材７９ｃの下面は第２の上層再配線７７ｂの接続パッドに接続される。
【０１０２】
次に、格子状の第３の埋込材７５ｃの開口部内における第２の上層再配線７７ｂを含む第２の半導体構成体７３ｂの上面に第３の半導体構成体７３ｃのシリコン基板７４ｃの下面を該下面に予め接着された第３の接着層７２ｃを介して接着する。
【０１０３】
次に、第３の半導体構成体７３ｃとその外側に配置された方形枠状の第３の埋込材７５ｃとの間に形成された比較的狭い第３の隙間内に第３の封止膜７６ｃを形成する。次に、第３の半導体構成体７３ｃ、第３の埋込材７５ｃおよび第３の封止膜７６ｃの上面の所定の箇所に第３の上層再配線７７ｃを第３の半導体構成体７３ｃの柱状電極７８ｃおよび第３の埋込材７５ｃ内の上下導通材７９ｃに接続させて形成する。
【０１０４】
次に、第３の上層再配線７７ｃを含む第３の半導体構成体７３ｃ、第３の埋込材７５ｃおよび第３の封止膜７６ｃの上面に上層絶縁膜８０をパターン形成する。次に、上層絶縁膜８０上の所定の箇所に半田ボール８１を第３の上層再配線７７ｃの接続パッド部に接続させて形成する。次に、図４４に示すように、所定のダイシング工程を経ると、図３７に示す半導体装置が複数個得られる。
【０１０５】
（第１７実施形態）
図４５はこの発明の第１７実施形態としての半導体装置の断面図を示したものである。この半導体装置では、まず、図１に示すものとほぼ同じものを用意する。以下、この用意したものを第１の半導体ブロック８１という。ただし、第１の半導体ブロック８１の半田ボール４６は、全て半導体構成体２３よりも外側に位置する周囲にのみ配置され、図１に示す場合よりも径がやや小さくなっている。
【０１０６】
また、図２４に示すものとほぼ同じであるが、埋込材３４内に上下導通材８２が設けられたものを用意する。以下、この用意したものを第２の半導体ブロック８３という。そして、第２の半導体ブロック８３は第１の半導体ブロック８１上に、第２の半導体ブロック８３の埋込材３４内の上下導通材８２の下面を第１の半導体ブロック８１の半田ボール４６に接続されて、搭載されている。
【０１０７】
（第１８、第１９実施形態）
図４６はこの発明の第１８実施形態としての半導体装置の断面図を示したものである。この半導体装置では、まず、図２４に示すものとほぼ同じであるが、埋込材３４内に上下導通材８４が設けられたものを用意する。以下、この用意したものを半導体ブロック８５という。
【０１０８】
ただし、この半導体ブロック８５では、半導体構成体２３、埋込材３４および封止膜３６の上面に第１の絶縁膜８６がパターン形成され、第１の絶縁膜８６の上面に配線８７が上下導通材８４の上面に接続されて形成され、配線８７を含む第１の絶縁膜８６の上面に第２の絶縁膜８８がパターン形成され、第２の絶縁膜８８で覆われずに露出された配線８７の接続パッド部上に小径の半田ボール８９が形成されている。
【０１０９】
そして、半導体ブロック８５上には、図１に示す場合とほぼ同じ構造の複数の半導体構成体２３が、その柱状電極３２を半導体ブロック８５の半田ボール８９に接続されて、搭載されている。
【０１１０】
なお、図４７に示すこの発明の第１９実施形態のように、半導体ブロック８５上にＬＳＩなどからなる第１および第２の半導体チップ９１、９２を搭載するようにしてもよい。この場合、半導体ブロック８５の第２の絶縁膜８８で覆われずに露出された配線８７の接続パッド部は、全て半導体構成体２３よりも外側に位置する周囲にのみ配置されている。
【０１１１】
第１および第２の半導体チップ９１、９２は、チップ本体９１ａ、９２ａの上周辺部に複数の接続パッド９１ｂ、９２ｂが設けられた構造となっている。第１の半導体チップ９１の平面サイズは半導体構成体２３の平面サイズとほぼ同じであり、第２の半導体チップ９２の平面サイズは半導体チップ９１の平面サイズよりもある程度小さくなっている。
【０１１２】
そして、第１の半導体チップ９１は半導体ブロック８５の絶縁膜８８の上面中央部に接着層９３を介して搭載され、その接続パッド９１ｂはワイヤ９４を介して半導体ブロック８５の第２の絶縁膜８８で覆われずに露出された配線８７の接続パッド部に接続されている。第２の半導体チップ９２は第１の半導体チップ９１の上面中央部に接着層９５を介して搭載され、その接続パッド９２ｂはワイヤ９６を介して半導体ブロック８５の第２の絶縁膜８８で覆われずに露出された配線８７の接続パッド部に接続されている。第１、第２の半導体チップ９１、９２およびワイヤ９４、９６を含む絶縁膜８８の上面全体にはエポキシ系樹脂などからなる封止膜９７が設けられている。
【０１１３】
（第２０、第２１実施形態）
図４８はこの発明の第２０実施形態としての半導体装置の断面図を示したものである。この半導体装置では、まず、図１に示すものとほぼ同じであるが、第２の上層再配線４３、第３の上層絶縁膜４４および半田ボール４６を備えていないものを用意する。ただし、この場合、埋込材３４の一辺部３４ａは平面的にある程度幅広となっている。
【０１１４】
そして、第１の上層再配線３９の一部の一端部は埋込材３４の一辺部３４ａの端面まで延ばされ、この端面近傍における部分は接続端子３９Ａとなっている。また、接続端子３９Ａを含む接続部分を除いて、第１の上層再配線３９を含む第２の上層絶縁膜４１の上面には接着層１０１を介してシールド用の金属層１０２が設けられている。金属層１０２は、厚さ数十μｍの同箔などからなっている。
【０１１５】
この半導体装置の具体的な応用例としては、端子数が少なく、シリコン基板２４（チップ部分）とモジュール間の接続の温度サイクル信頼性が要求されるＤＲＡＭなどのメモリーモジュールが考えられる。この場合、図４９に示すこの発明の第２１実施形態のように、図４８に示すものにおいてベース板２１を除去してなるものを２つ接着層２２を介して接着するようにしてもよい。
【０１１６】
ところで、図４８に示す半導体装置において、半導体構成体２３が不良品である場合、リペアー法として、金属層１０２を接着層１０１を介して接着せずに、第１の上層再配線３９の一部をレーザの照射によりカットして、不良品である半導体構成体２３を使用不能とし、次いで、図５０に示すように、別の良品の半導体構成体２３Ａを搭載するようにしてもよい。この場合、第１の上層絶縁膜４１の所定の箇所にＣＯ２レーザの照射により開口部を形成し、この開口部内に導電性樹脂などからなる導電材１０３を埋め込み、別の良品の半導体構成体２３Ａの柱状電極３２をこの導電材１０３に半田（図示せず）を介して接続するようにしてもよい。
【０１１７】
（その他の実施形態）
例えば、図９に示す状態において、半導体構成体２３として封止膜３３を備えていないものを用意する。つまり、図５に示すように、接続パッド２５および絶縁膜２６が形成されたウエハ状態のシリコン基板２４上に保護膜２７、再配線３１および柱状電極３２を形成した後、封止膜３３を形成することなく、これをダイシングする。
【０１１８】
そして、例えば、図１０に示す製造工程において、封止膜３３、３６を形成すべき領域に同一の封止材料によって同時に封止膜３３、３６を形成し、該封止膜３３、３６（ただし、封止膜は一体化されており境界はない）の上面側を研磨して、図１１に示す状態とするようにしてもよい。
【０１１９】
【発明の効果】
以上説明したように、この発明によれば、半導体基板上に再配線および柱状電極を有する複数または複数組の半導体構成体および埋込材をベース板上に配置し、半導体構成体上の絶縁膜および埋込材上に上層再配線を半導体構成体の柱状電極に接続させて形成し、埋込材を少なくとも切断することにより、半導体構成体を１つまたは１組有するとともに埋込材を有し、且つ、埋込材上に上層再配線の一部が配置されてなる半導体装置を複数個一括して得ることができ、従来のようなボンディング工程がなく、したがってボンディングによることなく外部接続電極の配置間隔を大きくすることができ、また複数または複数組の半導体構成体に対して絶縁膜および上層再配線の形成を一括して行うことができるので、製造工程を簡略化することができる。
【図面の簡単な説明】
【図１】この発明の第１実施形態としての半導体装置の断面図。
【図２】図１に示す半導体装置の製造方法の一例において、当初用意したものの断面図。
【図３】図２に続く製造工程の断面図。
【図４】図３に続く製造工程の断面図。
【図５】図４に続く製造工程の断面図。
【図６】図５に続く製造工程の断面図。
【図７】図６に続く製造工程の断面図。
【図８】図７に続く製造工程の断面図。
【図９】図８に続く製造工程の断面図。
【図１０】図９に続く製造工程の断面図。
【図１１】図１０に続く製造工程の断面図。
【図１２】図１１に続く製造工程の断面図。
【図１３】図１２に続く製造工程の断面図。
【図１４】図１３に続く製造工程の断面図。
【図１５】図１４に続く製造工程の断面図。
【図１６】図１５に続く製造工程の断面図。
【図１７】図１６に続く製造工程の断面図。
【図１８】図１７に続く製造工程の断面図。
【図１９】図１に示す半導体装置の製造方法の他の例において、当初用意したものの断面図。
【図２０】同他の例において、所定の製造工程の断面図。
【図２１】図１に示す半導体装置の製造方法のさらに他の例において、所定の製造工程の断面図。
【図２２】図２１に続く製造工程の断面図。
【図２３】この発明の第２実施形態としての半導体装置の断面図。
【図２４】この発明の第３実施形態としての半導体装置の断面図。
【図２５】この発明の第４実施形態としての半導体装置の断面図。
【図２６】この発明の第５実施形態としての半導体装置の断面図。
【図２７】この発明の第６実施形態としての半導体装置の断面図。
【図２８】この発明の第７実施形態としての半導体装置の断面図。
【図２９】この発明の第８実施形態としての半導体装置の断面図。
【図３０】この発明の第９実施形態としての半導体装置の断面図。
【図３１】この発明の第１０実施形態としての半導体装置の断面図。
【図３２】この発明の第１１実施形態としての半導体装置の断面図。
【図３３】この発明の第１２実施形態としての半導体装置の断面図。
【図３４】この発明の第１３実施形態としての半導体装置の断面図。
【図３５】この発明の第１４実施形態としての半導体装置の断面図。
【図３６】この発明の第１５実施形態としての半導体装置の断面図。
【図３７】この発明の第１６実施形態としての半導体装置の断面図。
【図３８】図３７に示す半導体装置の製造方法の一例において、当初の製造工程の断面図。
【図３９】図３８に続く製造工程の断面図。
【図４０】図３９に続く製造工程の断面図。
【図４１】図４０に続く製造工程の断面図。
【図４２】図４１に続く製造工程の断面図。
【図４３】図４２に続く製造工程の断面図。
【図４４】図４３に続く製造工程の断面図。
【図４５】この発明の第１７実施形態としての半導体装置の断面図。
【図４６】この発明の第１８実施形態としての半導体装置の断面図。
【図４７】この発明の第１９実施形態としての半導体装置の断面図。
【図４８】この発明の第２０実施形態としての半導体装置の断面図。
【図４９】この発明の第２１実施形態としての半導体装置の断面図。
【図５０】図４８に示す半導体装置においてリペアーを行う場合を説明するために示す断面図。
【図５１】従来の半導体装置の一例の断面図。
【符号の説明】
２１　ベース板
２２　接着層
２３　半導体構成体
２４　シリコン基板
２５　接続パッド
３１　再配線
３２　柱状電極
３３　封止膜
３４　埋込材
３６　封止膜
３７　第１の上層絶縁膜
３９　第１の上層再配線
４１　第２の上層絶縁膜
４３　第２の上層再配線
４４　第３の上層絶縁膜
４６　半田ボール[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
For example, in a semiconductor device called a BGA (ball grid array), a semiconductor chip composed of an LSI or the like is mounted on the center of the upper surface of a relay substrate (interposer) slightly larger than the size of the semiconductor chip, and is mounted on the lower surface of the relay substrate. There is one in which connection terminals using solder balls are arranged in a matrix. Here, when bonding the external connection electrodes formed on the semiconductor chip to another circuit board, the relay board has a sufficiently large size and pitch by rewiring in order to obtain connection strength and reliability. Used for
[0003]
FIG. 51 is a sectional view showing an example of such a conventional semiconductor device. The semiconductor chip 1 has a structure in which a plurality of bump electrodes 3 made of copper or the like are provided around the lower surface of a silicon substrate 2.
[0004]
The relay substrate 4 includes a base film 5 whose size is slightly larger than the size of the silicon substrate 2 of the semiconductor chip 1. On the upper surface of the base film 5, a rewiring 6 connected to the bump electrode 3 of the semiconductor chip 1 is provided.
[0005]
The rewiring 6 includes a first connection pad 7 provided corresponding to the bump electrode 3 of the semiconductor chip 1, a second connection pad 8 provided in a matrix, and first and second connection pads 7. , 8 are connected. A circular hole 10 is provided in the base film 5 at a portion corresponding to the center of the second connection pad 8.
[0006]
The semiconductor chip 1 is mounted on the center of the upper surface of the relay board 4 via the anisotropic conductive adhesive 11. The anisotropic conductive adhesive 11 is made of a thermosetting resin 12 containing a large number of conductive particles 13.
[0007]
When the semiconductor chip 1 is mounted on the relay substrate 4, first, the semiconductor chip 1 is positioned at the center of the upper surface of the relay substrate 4 via the sheet-like anisotropic conductive adhesive 11 and simply placed. I do.
[0008]
Next, bonding is performed by applying a predetermined pressure at a temperature at which the thermosetting resin 12 is cured. Then, the bump electrode 3 pushes away the thermosetting resin 12 and is conductively connected to the upper surface of the first connection pad 7 through the conductive particles 13, and the lower surface of the semiconductor chip 1 is thermoset to the upper surface of the relay substrate 4. It is bonded via the conductive resin 12.
[0009]
Next, a resin sealing film 14 made of an epoxy resin is formed on the entire upper surface of the relay substrate 4 including the semiconductor chip 1. Next, a solder ball 15 is formed in and below the circular hole 10 so as to be connected to the second connection pad 8. In this case, since the second connection pads 8 are arranged in a matrix, the solder balls 15 are also arranged in a matrix.
[0010]
Here, the size of the solder balls 15 is larger than the size of the bump electrodes 3 of the semiconductor chip 1, and the interval between the solder balls 15 needs to be larger than the interval between the bump electrodes 3 to avoid contact between the solder balls 15. . Therefore, when the number of the bump electrodes 3 of the semiconductor chip 1 increases, it is necessary to make the arrangement area larger than the size of the semiconductor chip 1 in order to obtain a necessary arrangement interval between the solder balls 15. The size of the substrate 4 is slightly larger than the size of the semiconductor chip 1. Therefore, among the solder balls 15 arranged in a matrix, the peripheral solder balls 15 are arranged around the semiconductor chip 1.
[0011]
[Problems to be solved by the invention]
By the way, in the above-mentioned conventional semiconductor device, the lower surface of the bump electrode 3 of the semiconductor chip 1 is bonded to the first wiring of the relay substrate 4 by bonding after the alignment using the relay substrate 4 on which the redistribution 6 is formed. Is electrically connected to the upper surface of the connection pad 7 via the conductive particles 13 of the anisotropic conductive adhesive 11, the number of the bump electrodes 3 of the semiconductor chip 1 increases, and the size and arrangement of the bump electrodes 3 are increased. When the interval is small, there is a problem that alignment is extremely difficult. In this case, if the size of the semiconductor chip 1 is increased, it is natural that the size and the arrangement interval of the bump electrodes 3 can be increased. However, in this case, the number of semiconductor chips to be removed from the wafer state is drastically reduced. Would be extremely expensive. In addition, the semiconductor chips 1 must be bonded and mounted one by one on the relay substrate 4, and there is a problem that the manufacturing process is complicated. The same applies to a multi-chip module type semiconductor device including a plurality of semiconductor chips.
[0012]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of manufacturing the semiconductor device, which can increase the interval between external connection electrodes without using bonding.
Another object of the present invention is to provide a method of manufacturing a semiconductor device, which can manufacture a plurality of semiconductor devices collectively.
[0013]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a semiconductor structure having a plurality of rewirings provided on a semiconductor substrate and a columnar electrode provided on each of the rewirings, and a semiconductor structure provided on a side of the semiconductor structure. Frame-shaped embedding material, an insulating film provided on the entire upper surface of the semiconductor structure excluding the columnar electrode, and provided on the insulating film and the embedding material so as to be connected to the columnar electrode and connected. And at least one upper layer rewiring having a pad portion, wherein at least a part of the connection pad portion of the uppermost layer upper rewiring in the upper layer rewiring is arranged on the embedding material. Is what you do.
The invention according to claim 2 has a semiconductor substrate, a plurality of rewirings provided on the semiconductor substrate, and a columnar electrode provided on each of the rewirings, which are arranged apart from each other. A plurality of semiconductor structures, an embedding material provided between the semiconductor structures or on a side of each semiconductor structure, and an insulating material provided on the entire upper surface of each of the semiconductor structures except for the columnar electrodes. A film, and at least one upper layer rewiring provided on the insulating film and the burying material and connected to the columnar electrode and having a connection pad portion. At least a part of the connection pad portion of the rewiring is arranged on the embedding material.
According to a third aspect of the present invention, in the first or second aspect of the present invention, another insulating film is provided between the semiconductor structure and the embedding material. .
According to a fourth aspect of the present invention, in the first or second aspect of the present invention, the lower surface of the embedding material is disposed on substantially the same plane as the lower surface of the semiconductor structure. It is.
According to a fifth aspect of the present invention, in the first or second aspect of the present invention, an upper surface of the embedding material is disposed on substantially the same plane as an upper surface of the semiconductor structure. It is.
According to a sixth aspect of the present invention, in the first or second aspect of the present invention, an upper surface of the embedding material is arranged at a different height from an upper surface of the semiconductor structure. is there.
According to a seventh aspect of the present invention, in the first or second aspect, the semiconductor structure and the embedding material are provided on a base plate.
According to an eighth aspect of the present invention, in the first or second aspect, the upper layer rewiring includes a plating layer.
According to a ninth aspect of the present invention, in the first or second aspect of the invention, the insulating film has a plurality of layers, and an interlayer connecting the columnar electrode of the semiconductor structure and the upper layer rewiring is provided between the layers. A rewiring is provided.
According to a tenth aspect of the present invention, in the invention according to the first or second aspect, an uppermost layer is formed on an upper surface of the insulating film including the upper layer rewiring except for at least a part of a connection pad portion of the upper layer rewiring. An insulating film is provided. According to an eleventh aspect of the present invention, in the invention of the tenth aspect, a protruding connection terminal is provided on the connection pad portion of the upper layer rewiring.
According to a twelfth aspect of the present invention, in the eleventh aspect of the present invention, the projecting connection terminals are solder balls.
According to a thirteenth aspect of the present invention, in the first or second aspect, one end of a part of the upper layer rewiring is extended to an end face of the embedding material, and a portion near the end face is a connection terminal. It is characterized by having become.
According to a fourteenth aspect of the present invention, the step of arranging the embedding material at predetermined intervals in at least one direction on the base plate, and each of the step includes a plurality of rewirings and a columnar electrode provided on each of the rewirings. Arranging a plurality of semiconductor structures having a plurality of semiconductor structures in one direction on the base plate such that the embedding material is interposed at a predetermined number of the semiconductor structures on a side thereof; and a connection pad portion. And forming an upper layer rewiring connected to the corresponding columnar electrode of any of the semiconductor structures such that at least a connection pad portion of the upper layer rewiring is arranged on the embedding material. A step of cutting the burying material between the semiconductor structures and disposing at least one of the connection pad portions of the upper layer rewiring on the burying material interposed on the side of the semiconductor structure Reduce the semiconductor structure It is characterized in that a step of obtaining a plurality of semiconductor devices also have one.
According to a fifteenth aspect, in the fourteenth aspect, a step of forming another insulating film between the semiconductor structure and the burying material is provided.
According to a sixteenth aspect of the present invention, in the invention according to the fourteenth aspect, the step of cutting the embedding material is performed so as to include a plurality of the semiconductor structures.
According to a seventeenth aspect, in the invention according to the sixteenth aspect, the insulating film has a plurality of layers, and a columnar electrode of each of the semiconductor structures and the corresponding upper layer rewiring are connected between the layers. A step of forming a plurality of sets of interlayer rewirings.
According to an eighteenth aspect of the present invention, in the invention according to the sixteenth aspect, a step of forming an uppermost-layer insulating film on a portion of the upper surface of the insulating film including the upper-layer rewiring except for a connection pad portion of the upper-layer rewiring. Which is characterized by having
A nineteenth aspect of the present invention is characterized in that, in the invention of the eighteenth aspect, a step of forming a projecting connection terminal on the connection pad portion of the upper layer rewiring is provided.
In the invention according to claim 20, in the invention according to claim 16, the step of cutting the embedding material includes cutting the embedding material and cutting the base plate, and comprising a base plate as the semiconductor device. It is characterized in that it is obtained.
According to a twenty-first aspect of the present invention, in the invention of the twentieth aspect, a step of disposing another base plate below the base plate before cutting, and removing the another base plate after cutting the base plate. Which is characterized by having
According to the present invention, a plurality of or a plurality of sets of the semiconductor structure and the embedding material having the rewiring and the columnar electrode on the semiconductor substrate are arranged on the base plate, and the insulating film and the embedding material on the semiconductor structure are An upper layer rewiring is formed thereon by connecting it to the columnar electrode of the semiconductor structure, and at least the burying material is cut to have one or one set of the semiconductor structure and the burying material. It is possible to collectively obtain a plurality of semiconductor devices in which a part of the upper layer redistribution is arranged on the embedded material, and there is no bonding process as in the related art, so that the arrangement interval of the external connection electrodes can be increased without bonding. In addition, the insulating film and the upper layer rewiring can be collectively formed on a plurality of or a plurality of sets of the semiconductor structures, so that the manufacturing process can be simplified.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. This semiconductor device includes a square base plate 21 made of silicon, glass, ceramics, resin, metal, or the like. An adhesive layer 22 made of an adhesive, a pressure-sensitive adhesive sheet, a double-sided adhesive tape, or the like is provided on the upper surface of the base plate 21.
[0015]
At the center of the upper surface of the adhesive layer 22, the lower surface of a planar square semiconductor structure 23 slightly smaller than the size of the base plate 21 is bonded. In this case, the semiconductor structure 23 is called a CSP (chip size package), and includes a silicon substrate (semiconductor substrate) 24 bonded to the center of the upper surface of the bonding layer 22. A plurality of connection pads 25 made of aluminum or the like are provided around the upper surface of the silicon substrate 24, and an insulating film 26 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 24 except for the center of the connection pad 25. .
[0016]
The one in which the connection pads 25 and the insulating film 26 are provided on the silicon substrate 24 is usually obtained when a semiconductor substrate in a wafer state is diced into individual chips. However, according to the present invention, in a state where the connection pads 25 and the insulating film 26 are formed on the semiconductor substrate in a wafer state, dicing is not performed, and as described below, the semiconductor structure 23 having a rewiring and a columnar electrode is formed. The semiconductor substrate in a wafer state is diced in a state where the above is obtained. First, the configuration of the semiconductor component 23 will be described.
[0017]
On the insulating film 26 formed on the silicon substrate 24, a protective film 27 made of polyimide or the like is provided. The central portion of the connection pad 25 is exposed through an opening 28 formed in the insulating film 26 and the protective film 27. From the upper surface of the connection pad 25 exposed through the opening 28 to a predetermined portion of the upper surface of the protective film 27, a redistribution wiring 31 composed of a base metal layer 31a and an upper metal layer 31b provided on the base metal layer 31a is formed. Is provided.
[0018]
A columnar electrode 32 made of copper is provided on the upper surface of the connection pad portion of the rewiring 31. A sealing film (insulating film) 33 made of an epoxy resin or the like is provided on the upper surface of the protective film 27 including the rewiring 31 so that the upper surface thereof is flush with the upper surface of the columnar electrode 32. As described above, the semiconductor structure 23 includes the silicon substrate 24, the connection pad 25, and the insulating film 26, and further includes the protective film 27, the rewiring 31, the columnar electrode 32, and the sealing film 33.
[0019]
A rectangular frame-shaped embedding material 34 is adhered to the upper surface of the adhesive layer 22 around the semiconductor structure 23. In this case, the material of the embedding material 34 may be the same as the base plate 21 or may be different. The thickness of the embedding material 34 is substantially the same as the entire thickness of the semiconductor structure 23. Further, a relatively narrow gap 35 is formed between the semiconductor structure 23 and the rectangular frame-shaped embedding material 34 disposed outside the semiconductor structure 23. A sealing film (insulating film) 36 made of an epoxy resin or the like is provided in the gap 35 so that the upper surface thereof is substantially flush with the upper surfaces of the sealing film 33 and the embedding material 34.
[0020]
A first upper insulating film 37 made of polyimide or the like is provided on the entire upper surfaces of the semiconductor structure 23, the embedding material 34, and the sealing film 36. An opening 38 is provided in a portion of the first upper insulating film 37 corresponding to the center of the upper surface of the columnar electrode 32. The first base metal layer 39a and the first base metal layer 39a are provided on the first base metal layer 39a from the upper surface of the columnar electrode 32 exposed through the opening 38 to a predetermined portion of the upper surface of the first upper insulating film 37. A first upper layer redistribution line 39 made of a first upper layer metal layer 39b is provided.
[0021]
A second upper insulating film 41 made of polyimide or the like is provided on the entire upper surface of the first upper insulating film 37 including the first upper wiring 39. An opening 42 is provided in a portion of the second upper insulating film 41 corresponding to the connection pad of the first upper rewiring 39. The second base metal layer 43a and the second base metal from the upper surface of the connection pad portion of the first upper layer redistribution wiring 39 exposed through the opening 42 to a predetermined portion of the upper surface of the second upper layer insulating film 41. A second upper layer redistribution wiring 43 composed of a second upper layer metal layer 43b provided on the layer 43a is provided.
[0022]
A third upper insulating film 44 made of polyimide or the like is provided on the entire upper surface of the second upper insulating film 41 including the second upper wiring 43. An opening 45 is provided in a portion of the third upper insulating film 44 corresponding to the connection pad portion of the second upper rewiring 43. Inside and above the opening 45, a solder ball (protruding connection terminal) 46 is provided so as to be connected to the connection pad portion of the second upper layer rewiring 43. The plurality of solder balls 46 are arranged in a matrix on the third upper insulating film 44.
[0023]
By the way, the reason why the size of the base plate 21 is made slightly larger than the size of the semiconductor component 23 is that the arrangement area of the solder balls 46 is changed according to the increase in the number of connection pads 25 on the silicon substrate 24. This is because the size and the arrangement interval of the connection pads 25 are made slightly larger than the size and the arrangement interval of the columnar electrodes 32.
[0024]
For this reason, the connection pad portions of the second upper layer redistribution wirings 43 (portions in the openings 45 of the third upper layer insulating film 44) arranged in a matrix form are not limited to the region corresponding to the semiconductor structure 23, An embedding material 34 provided around the semiconductor structure 23 and a sealing film 36 provided in a gap 35 therebetween are also arranged. In other words, of the solder balls 46 arranged in a matrix, at least the outermost solder balls 46 are arranged around the outside of the semiconductor structure 23.
[0025]
In this case, as a modification, all the connection pad portions of the second upper layer redistribution wiring 43 may be arranged around the semiconductor element 23. Further, the upper layer redistribution may be formed as one layer, that is, only the first upper layer redistribution 39, and at least the outermost connection pad portion may be arranged around the outer side of the semiconductor structure 23.
[0026]
As described above, in this semiconductor device, a semiconductor in which not only the connection pad 25 and the insulating film 26 are formed on the silicon substrate 24 but also the protective film 27, the rewiring 31, the columnar electrode 32, the sealing film 33, and the like are formed. A sealing film 36 and an embedding material 34 are provided around the structure 23, and the columnar electrode is formed on the upper surface thereof through at least a first upper insulating film 37 and an opening 38 formed in the first upper insulating film 37. The second embodiment is characterized in that a first upper layer redistribution line 39 connected to the second upper layer wiring 32 is provided.
[0027]
In this case, a relatively narrow gap 35 is formed between the semiconductor structure 23 and the rectangular frame-shaped embedding material 34 disposed outside the semiconductor structure 23, and a sealing film 36 made of an epoxy resin or the like is formed in the gap 35. Is provided, the amount of the sealing film 36 can be reduced by the volume of the embedding material 34 as compared with the case where the embedding material 34 is not provided. As a result, stress due to shrinkage of the sealing film 36 made of an epoxy resin or the like at the time of curing can be reduced, and the base substrate 21 can be less likely to warp.
[0028]
Next, an example of a method of manufacturing the semiconductor device will be described. First, an example of a method of manufacturing the semiconductor structure 23 will be described. In this case, first, as shown in FIG. 2, a connection pad 25 made of aluminum, an insulating film 26 made of silicon oxide, and a protective film 27 made of polyimide are provided on a silicon substrate (semiconductor substrate) 24 in a wafer state. A pad whose central portion is exposed through an opening 28 formed in the insulating film 26 and the protective film 27 is prepared.
[0029]
Next, as shown in FIG. 3, a base metal layer 31a is formed on the entire upper surface of the protective film 27 including the upper surface of the connection pad 25 exposed through the opening 28. In this case, the base metal layer 31a is composed of only a copper layer formed by electroless plating, but may be only a copper layer formed by sputtering, or a thin film layer of titanium or the like formed by sputtering. A copper layer may be formed thereon by sputtering. This is the same in the case of the upper base metal layers 39a and 43a to be described later.
[0030]
Next, a plating resist film 51 is pattern-formed on the upper surface of the base metal layer 31a. In this case, an opening 52 is formed in the plating resist film 51 in a portion corresponding to the rewiring 31 forming region. Next, an upper metal layer 31b is formed on the upper surface of the base metal layer 31a in the opening 52 of the plating resist film 51 by performing copper electrolytic plating using the base metal layer 31a as a plating current path. Next, the plating resist film 51 is peeled off.
[0031]
Next, as shown in FIG. 4, a plating resist film 53 is pattern-formed on the upper surface of the base metal layer 31a including the upper metal layer 31b. In this case, an opening 54 is formed in the plating resist film 53 at a portion corresponding to the region where the columnar electrode 32 is formed. Next, the columnar electrode 32 is formed on the upper surface of the connection pad portion of the upper metal layer 31b in the opening 54 of the plating resist film 53 by performing copper electrolytic plating using the base metal layer 31a as a plating current path.
[0032]
Next, the plating resist film 53 is peeled off, and then unnecessary portions of the base metal layer 31a are removed by etching using the columnar electrodes 32 and the upper metal layer 31b as a mask. As shown in FIG. The underlying metal layer 31a is left only below, and the rewiring 31 is formed by the remaining underlying metal layer 31a and the upper metal layer 31b formed on the entire upper surface thereof.
[0033]
Next, as shown in FIG. 6, a sealing film 33 made of an epoxy resin is formed on the entire upper surface of the protective film 27 including the columnar electrode 32 and the rewiring 31 so that the thickness thereof is larger than the height of the columnar electrode 32. Formed. Therefore, in this state, the upper surface of the columnar electrode 32 is covered with the sealing film 33. Next, the sealing film 33 and the upper surface of the columnar electrode 32 are appropriately polished to expose the upper surface of the columnar electrode 32 and seal the upper surface of the columnar electrode 32 including the exposed upper surface, as shown in FIG. The upper surface of the stop film 33 is flattened. Next, as shown in FIG. 8, through a dancing step, a plurality of semiconductor components 23 shown in FIG. 1 are obtained.
[0034]
By the way, when the upper surface of the columnar electrode 32 is appropriately polished, the height of the columnar electrode 32 formed by the electrolytic plating has a variation. To do that. In this case, an expensive and high-precision grinder is used to polish the upper surface side of the columnar electrode 32 made of copper.
[0035]
Next, an example in which the semiconductor device shown in FIG. 1 is manufactured using the semiconductor component 23 obtained in this manner will be described. First, as shown in FIG. 9, a base plate 21 from which a plurality of base plates 21 shown in FIG. 1 can be obtained is provided with an adhesive layer 22 provided on the entire upper surface thereof.
[0036]
Then, the lower surface of the lattice-shaped embedding material 34 is bonded to a predetermined location on the upper surface of the adhesive layer 22. As an example, the lattice-shaped embedding material 34 forms a plurality of square openings 34a in a sheet-shaped embedding material 34 made of silicon, glass, ceramics, resin, metal, or the like by stamping or etching. It can be obtained by: Alternatively, the sheet-shaped embedding material 34 may be adhered to the entire upper surface of the adhesive layer 22 and the lattice-shaped embedding material 34 may be formed by spot facing.
[0037]
Next, the lower surface of the silicon substrate 24 of the semiconductor structure 23 is bonded to the center of the upper surface of the adhesive layer 22 in each opening 34a of the lattice-shaped embedding material 34, respectively. In this state, the upper surface of the embedding material 34 and the upper surface of the semiconductor structure 23 are arranged on substantially the same plane. A relatively narrow gap 35 is formed between the semiconductor structure 23 and the rectangular frame-shaped embedding material 34 disposed outside the semiconductor structure 23.
[0038]
Next, as shown in FIG. 10, a sealing film 36 made of an epoxy-based resin is applied to the entire upper surfaces of the semiconductor structure 23 including the gap 35 and the embedding material 34 by printing or the like. Therefore, in this state, the upper surfaces of the semiconductor structure 23 and the embedding material 34 are covered with the sealing film 36. Next, the uncured sealing film 36 covering the upper surfaces of the semiconductor structure 23 and the embedding material 34 is removed by buffing, so that the semiconductor structure 23 and the embedding material 34 are removed as shown in FIG. Is exposed, and the upper surface of the sealing film 36 provided in the gap 35 is substantially flush with the upper surfaces of the semiconductor structure 23 and the embedding material 34, and the entire upper surface is substantially flattened. Next, the sealing film 36 is cured.
[0039]
By the way, in this case, the polishing is not performed on the upper surface side of the semiconductor structure 23, that is, on the upper surface side of the columnar electrode 32 made of copper, but the uncured uncured material covering the upper surfaces of the semiconductor structure 23 and the embedding material 34. Since the sealing film 36 is removed, there is no problem even if an inexpensive and low-precision buff is used. In order to prevent the uncured sealing film 36 provided in the gap 35 from being polished excessively and to reduce the curing shrinkage of the sealing film 36, the applied sealing film 36 is temporarily irradiated with ultraviolet light or heated. You may make it harden. When the curing shrinkage of the sealing film 36 provided in the gap 35 is large and the flattening is insufficient, the application and polishing of the sealing resin may be repeated.
[0040]
As another example of polishing, a part of an inexpensive and low-precision endless polishing belt is flattened, and the flattened portion covers the upper surfaces of the semiconductor structure 23 and the embedding material 34. The hardened sealing film 36 may be smoothed and polished by using the upper surfaces of the semiconductor structure 23 and the embedding material 34 as polishing restriction surfaces.
[0041]
Further, a relatively narrow gap 35 is formed between the semiconductor structure 23 and the rectangular frame-shaped embedding material 34 disposed outside the semiconductor structure 23, and a sealing film 36 made of an epoxy resin is provided in the gap 35. Therefore, the amount of the sealing film 36 can be reduced by the volume of the embedding material 34 as compared with the case where the embedding material 34 is not provided. As a result, stress due to shrinkage of the sealing film 36 made of an epoxy resin during curing can be reduced, and the base plate 21 can be made less likely to warp.
[0042]
When the polishing step shown in FIG. 11 is completed, next, as shown in FIG. 12, a first upper layer is formed on the entire upper surfaces of the semiconductor structure 23, the embedding material 34, and the sealing film 36 which are substantially flush. An insulating film 37 is formed. The first upper insulating film 37 is made of a photosensitive polyimide, a photosensitive polybenzoxazole, a photosensitive epoxy resin, a photosensitive novolak resin, a photosensitive acrylic calzo resin, or the like, and is formed into a dry film. Therefore, when this dry film is laminated by a laminator, the first upper insulating film 37 is formed. The same applies to the second and third upper insulating films 41 and 44 described later, but they may be formed by a coating method such as printing.
[0043]
Next, an opening 38 is formed by photolithography in a portion of the first upper insulating film 37 corresponding to the center of the upper surface of the columnar electrode 32. Next, as shown in FIG. 13, a first base metal layer 39a is formed on the entire upper surface of the first upper insulating film 37 including the upper surface of the columnar electrode 32 exposed through the opening 38. Next, a plating resist film 55 is pattern-formed on the upper surface of the first base metal layer 39a. In this case, an opening 56 is formed in the plating resist film 55 in a portion corresponding to the first upper layer rewiring 39 formation region. Next, copper electrolytic plating is performed using the first base metal layer 39a as a plating current path, so that the first upper metal layer 39a is formed on the upper surface of the first base metal layer 39a in the opening 56 of the plating resist film 55. 39b is formed.
[0044]
Next, the plating resist film 55 is peeled off, and then unnecessary portions of the first base metal layer 39a are removed by etching using the first upper metal layer 39b as a mask. As shown in FIG. The first base metal layer 39a remains only under the upper metal layer 39b, and the remaining first base metal layer 39a and the first upper metal layer 39b formed over the entire upper surface thereof form a first upper layer. The rewiring 39 is formed.
[0045]
Next, as shown in FIG. 15, a second upper insulating film 41 made of photosensitive polyimide or the like is pattern-formed on the entire upper surface of the first upper insulating film 37 including the first upper wiring 39. In this case, an opening 42 is formed in a portion of the second upper insulating film 41 corresponding to the connection pad of the first upper wiring 39. Next, a second base metal layer 43a is formed by electroless plating over the entire upper surface of the second upper insulating film 41 including the connection pad portion of the first upper wiring layer 39 exposed through the opening. .
[0046]
Next, a plating resist film 57 is pattern-formed on the upper surface of the second base metal layer 43a. In this case, an opening 58 is formed in the plating resist film 57 at a portion corresponding to the second upper layer rewiring 43 forming region. Next, copper electrolytic plating is performed using the second base metal layer 43a as a plating current path, so that a second upper metal layer is formed on the upper surface of the second base metal layer 43a in the opening 58 of the plating resist film 57. 43b is formed.
[0047]
Next, the plating resist film 57 is peeled off, and then unnecessary portions of the second base metal layer 43a are removed by etching using the second upper metal layer 43b as a mask. As shown in FIG. The second base metal layer 43a remains only under the upper metal layer 43b, and the remaining second base metal layer 43a and the second upper metal layer 43b formed over the entire upper surface thereof form a second upper layer. The rewiring 43 is formed.
[0048]
Next, as shown in FIG. 17, a third upper insulating film 44 made of photosensitive polyimide or the like is patterned on the entire upper surface of the second upper insulating film 41 including the second upper wiring 43. In this case, an opening 45 is formed in a portion of the third upper insulating film 44 corresponding to the connection pad of the second upper rewiring 43. Next, a solder ball 46 is formed in and above the opening 45 so as to be connected to the connection pad portion of the second upper layer rewiring 43.
[0049]
Next, as shown in FIG. 18, the three insulating films 44, 41, 37, the embedding material 34, the adhesive layer 22, and the base plate 21 are cut between the semiconductor structures 23 adjacent to each other. A plurality of the semiconductor devices shown are obtained.
[0050]
In the semiconductor device thus obtained, the first base metal layer 39a and the first upper metal layer 39b connected to the columnar electrodes 32 of the semiconductor structure 23 are formed by electroless plating (or sputtering) and electrolytic plating. Since the second base metal layer 43a and the second upper metal layer 43b connected to the connection pad portion of the first upper layer rewiring 39 are formed by electroless plating (or sputtering) and electrolytic plating. Conductive connection between the columnar electrode 32 of the semiconductor structure 23 and the first upper layer redistribution line 39 and between the first upper layer redistribution line 39 and the second upper layer redistribution line 43 without using bonding. Can be.
[0051]
In the above-described manufacturing method, the lattice-shaped embedding material 34 and the plurality of semiconductor components 23 are bonded and arranged on the adhesive layer 22 on the base plate 21, and the sealing film is applied to the plurality of semiconductor components 23. 36, the formation of the first to third upper insulating films 37, 41, 44, the first and second base metal layers 39a, 43a, the first and second upper metal layers 39b, 44b, and the solder balls 46 are collectively performed. After that, a plurality of semiconductor devices are obtained by dividing the semiconductor device, so that the manufacturing process can be simplified.
[0052]
In addition, since the plurality of semiconductor components 23 can be transported together with the base plate 21, the manufacturing process can be simplified. Furthermore, if the outer dimensions of the base plate 21 are made constant, the transport system can be shared regardless of the outer dimensions of the semiconductor device to be manufactured.
[0053]
Further, in the above-described manufacturing method, as shown in FIG. 9, the CSP type semiconductor structure 23 including the rewiring 31 and the columnar electrode 32 is bonded on the bonding layer 22. Compared with the case where a normal semiconductor chip provided with the connection pads 25 and the insulating film 26 is adhered on the adhesive layer 22 to form a rewiring and a columnar electrode on a sealing film provided around the semiconductor chip. Thus, costs can be reduced.
[0054]
For example, when the base plate 21 before cutting has a substantially circular shape with a certain size like a silicon wafer, rewiring and re-wiring are performed on a sealing film provided around a semiconductor chip bonded on the bonding layer 22. When the columnar electrodes are formed, the processing area increases. In other words, low-density processing results in a reduction in the number of processed sheets at one time and a decrease in throughput, resulting in an increase in cost.
[0055]
On the other hand, in the above-described manufacturing method, since the CSP type semiconductor structure 23 having the rewiring 31 and the columnar electrode 32 is adhered on the adhesive layer 22 and then built up, the number of processes increases. Since the high-density processing is performed until the columnar electrodes 32 are formed, the efficiency is high, and the overall cost can be reduced even if the number of processes is increased.
[0056]
In the above embodiment, the solder balls 46 are provided so as to be arranged in a matrix corresponding to the entire surface of the semiconductor structure 23 and the embedding material 34. May be provided only on a region corresponding to the surrounding embedding material 34. In this case, the solder balls 46 may be provided not on the entire periphery of the semiconductor structure 23 but only on the sides of the first to third sides of the four sides of the semiconductor structure 23. In such a case, the embedding material 34 need not be formed in a rectangular frame shape, and may be arranged only on the side of the side where the solder ball 46 is provided. The embedding material 34 may be formed by printing, transfer, molding, or the like, or may be formed after the semiconductor components 23 are arranged on the base plate 21.
[0057]
Next, another example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. First, as shown in FIG. 19, an adhesive layer 61 made of an ultraviolet-curable pressure-sensitive adhesive sheet or the like is adhered to the entire upper surface of another base plate 60 made of a transparent resin plate or a glass plate that is transparent to ultraviolet light. The base plate 21 and the adhesive layer 22 described above are bonded to the upper surface of the substrate.
[0058]
Then, after passing through the manufacturing steps shown in FIGS. 9 to 17, respectively, as shown in FIG. 20, the three insulating films 44, 41, and 37, the embedding material 34, the adhesive layer 22, the base plate 21, and the adhesive layer 61 are formed. Is cut, and another base plate 60 is not cut. Next, ultraviolet rays are irradiated from the lower surface side of another base plate 60 to cure the adhesive layer 61. Then, the adhesiveness of the adhesive layer 61 to the separated lower surface of the base plate 21 is reduced. Then, when the individual pieces existing on the adhesive layer 61 are peeled off one by one and picked up, a plurality of semiconductor devices shown in FIG. 1 are obtained.
[0059]
In this manufacturing method, in the state shown in FIG. 20, the individualized semiconductor devices existing on the adhesive layer 61 do not fall apart, so that a circuit (not shown) is used without using a dedicated semiconductor device mounting tray. At the time of mounting on a substrate, it can be peeled off and picked up one by one. Further, when the adhesive layer 61 remaining on the upper surface of another base plate 60 and having reduced adhesiveness is peeled off, another base plate 60 can be reused. Furthermore, if the external dimensions of another base plate 60 are constant, the transport system can be shared regardless of the external dimensions of the semiconductor device to be manufactured.
[0060]
Here, as another base plate 60, it is also possible to use a normal dicing tape or the like, from which the semiconductor device is removed by expanding, and in this case, the adhesive layer does not need to be of the ultraviolet curing type. Further, another base plate 60 may be removed by polishing or etching.
[0061]
Next, still another example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. In this manufacturing method, after the manufacturing process shown in FIG. 12, as shown in FIG. 21, the entire upper surface of the first upper insulating film 37 including the upper surface of the columnar electrode 32 exposed through the opening 38 is free of copper. A first base metal layer 39a is formed by electrolytic plating. Next, a first upper metal forming layer 39c is formed on the entire upper surface of the first base metal layer 39a by performing copper electrolytic plating using the first base metal layer 39a as a plating current path. Next, a resist film 62 is pattern-formed on a portion of the upper surface of the first upper metal formation layer 39c corresponding to the first upper layer rewiring formation region.
[0062]
Next, unnecessary portions of the first upper metal forming layer 39c and the first base metal layer 39a are removed by etching using the resist film 62 as a mask, and as shown in FIG. The first upper wiring layer 39 remains. After that, the resist film 62 is peeled off. Note that the second upper layer redistribution wiring 43 may be formed by the same forming method.
[0063]
By the way, the base plate 21 shown in FIG. 9 or another base plate 60 shown in FIG. 19 may be formed in a tray shape. That is, the base plate is shaped like a saucer in which the region where the semiconductor components 23 are arranged is depressed from the surroundings. Then, a plating current path metal layer is provided on the upper surface of the tray base plate surrounding the semiconductor structure 23 arrangement region, and the plating current path metal layer and the plating current path base metal layer (39a, 43a) are provided. ) May be connected by a conductive member to perform electrolytic plating. In this case, by setting the outer dimensions of the trays to be the same, the same manufacturing apparatus can be used even when the sizes of the semiconductor devices to be manufactured are different, so that the efficiency is improved.
[0064]
(2nd Embodiment)
In the manufacturing process shown in FIG. 9, the adhesive layers 22 are provided on the lower surface of the silicon substrate 24 of the semiconductor structure 23 and the lower surface of the embedding material 34, respectively, and these adhesive layers 22 are provided at predetermined positions on the upper surface of the base plate 21. In the case of bonding, a semiconductor device as a second embodiment of the present invention shown in FIG. 23 is obtained.
[0065]
In the semiconductor device obtained in this manner, for example, in addition to the lower surface of the silicon substrate 24 being bonded to the upper surface of the base plate 21 via the adhesive layer 22, the side surface of the silicon substrate 24 is provided with a sealing film 36. Since the semiconductor structure 23 and the embedding material 34 are joined to the base plate 21 to some extent, the joining strength can be increased to some extent.
[0066]
(Third and fourth embodiments)
FIG. 24 is a sectional view of a semiconductor device according to a third embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 1 in that it does not include a base plate 21 and an adhesive layer 22.
[0067]
In the case of manufacturing the semiconductor device of the third embodiment, for example, as shown in FIG. 17, after the solder balls 46 are formed, the base plate 21 and the adhesive layer 22 are removed by polishing or etching, and then adjacent to each other. When the three insulating films 44, 41, and 37 and the burying material 34 are cut between the semiconductor structures 23 to be formed, a plurality of semiconductor devices shown in FIG. 24 are obtained. Since the semiconductor device thus obtained does not include the base plate 21 and the adhesive layer 22, the thickness can be reduced accordingly.
[0068]
After the base plate 21 and the adhesive layer 22 are removed by polishing or etching, the lower surfaces of the silicon substrate 24, the embedding material 34, and the sealing film 36 are appropriately polished, and then, between the semiconductor structures 23 adjacent to each other. In this case, when the three insulating films 44, 41, 37 and the burying material 34 are cut, a plurality of semiconductor devices according to the fourth embodiment of the present invention shown in FIG. 25 are obtained. The semiconductor device thus obtained can be further reduced in thickness.
[0069]
Before forming the solder balls 46, the base plate 21 and the adhesive layer 22 are removed by polishing, etching, or the like (if necessary, the lower surfaces of the silicon substrate 24, the embedding material 34, and the sealing film 36 may be appropriately removed). Then, a solder ball 46 is formed, and then the three-layered insulating films 44, 41, 37 and the embedding material 34 may be cut between the semiconductor structures 23 adjacent to each other.
[0070]
(Fifth embodiment)
FIG. 26 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 1 in that a metal layer 63 for heat dissipation is adhered to the lower surface of the adhesive layer 22. The metal layer 63 is made of a copper foil having a thickness of several tens μm or the like.
[0071]
In the case of manufacturing the semiconductor device of the fifth embodiment, for example, as shown in FIG. 17, after the solder balls 46 are formed, the base plate 21 is removed by polishing or etching, and then the entire lower surface of the adhesive layer 22 is formed. FIG. 26 shows a state in which the metal layers 63 are bonded to each other, and then the three insulating films 44, 41, and 37, the embedding material 34, the adhesive layer 22, and the metal layers 63 are cut between the semiconductor structures 23 adjacent to each other. A plurality of semiconductor devices are obtained.
[0072]
The adhesive layer 22 is also removed by polishing, etching, or the like (the silicon substrate 24, the embedding material 34, and the lower surface of the sealing film 36 are appropriately polished as necessary), and the silicon substrate 24, the embedding material 34 are removed. Alternatively, the metal layer 63 may be bonded to the lower surface of the sealing film 36 via a new bonding layer.
[0073]
(Sixth embodiment)
FIG. 27 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that the sizes of the openings 38 and 42 of the first and second upper insulating films 37 and 41 are made as small as possible, and That is, the lands of the first and second upper layer rewirings 39 and 43 on 38 and 42 are made as small as possible.
[0074]
For example, since the first upper layer redistribution line 39 is directly bonded to the columnar electrode 32 by plating, the opening 38 of the first upper layer insulating film 37 has a square shape of 10 μm × 10 μm or a circular shape having the same area. If it has an area, the strength is sufficient. Therefore, the size of the opening 38 of the first upper insulating film 37 can be made as small as possible, and the land of the first upper wiring 39 on this opening 38 is made as small as possible. be able to.
[0075]
Thus, according to the sixth embodiment, the sizes of the openings 38, 42 of the first and second upper insulating films 37, 41 are made as small as possible, and the openings 38, 42 Since the lands of the first and second upper layer redistribution lines 39 and 43 can be made as small as possible, the area occupied by the first and second upper layer redistribution lines 39 and 43 can be reduced. As a result, even if the number of connection pads 25 (that is, the columnar electrodes 32) on the silicon substrate 24 of the semiconductor structure 23 increases, the size of the entire semiconductor device can be reduced.
[0076]
(Seventh embodiment)
FIG. 28 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that the upper layer rewiring is a single layer, that is, only the first upper layer rewiring 39 is used, and a part of the rewiring 31 of the semiconductor structure 23 is cross-reconnected. That is to say, wiring.
[0077]
That is, when there is room in area on the protective film 27 of the semiconductor structure 23, a rewiring 31A not connected to the connection pad 25 is provided on the protective film 27, and columnar electrodes are provided on both ends of the rewiring 31A. 32A, a first upper layer rewiring 39 is connected to the columnar electrode 32A and the original columnar electrode 32, and the rewiring 31A is a cross rewiring. By doing so, the number of layers of the rewiring in the upper layer can be reduced.
[0078]
(Eighth and ninth embodiments)
FIG. 29 is a sectional view of a semiconductor device according to an eighth embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that the first upper insulating film 37 is omitted and the sealing film 36 is formed on the upper surfaces of the semiconductor structure 23 and the embedding material 34 around the gap 35. That is, the first upper layer rewiring 39 is provided on the upper surface of the raised portion, the semiconductor structure 23 and the embedding material 34.
[0079]
In this case, the sealing film 36 is formed using a metal mask or the like or by screen printing. In the case where the uncured or temporarily cured sealing film 36 provided so as to be slightly raised on the upper surfaces of the semiconductor structure 23 and the embedding material 34 around the gap 35 is removed by buff polishing or the like, FIG. The semiconductor device according to the ninth embodiment of the present invention shown in FIG.
[0080]
(Tenth embodiment)
FIG. 31 is a sectional view of a semiconductor device according to a tenth embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that the second upper wiring layer 43 and the third upper insulating film 44 are omitted, and solder balls are provided on the connection pad portions of the first upper redistribution wiring 37. 46 and the rewiring 64 is provided on the upper surface of the embedding material 34. In this case, both ends of the rewiring 64 on the embedding material 34 are connected to the first upper rewiring 39 via the opening 38 formed in the first upper insulating film 37 covering the rewiring 64. ing.
[0081]
(Eleventh embodiment)
FIG. 32 is a sectional view of a semiconductor device according to an eleventh embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 31 in that the sealing film 36 and the first upper insulating film 37 are integrally formed by applying photosensitive polyimide or the like using a die coater or the like. is there. In this case, the opening 38 in the first upper insulating film 37 may be formed by photolithography or irradiation of a CO2 laser.
[0082]
In this case, when the coating material is a thermoplastic resin or a fluidizable resin which becomes a fluidized state by heating at a relatively low temperature before curing, the insulating films 36 and 37 formed integrally by coating are flattened. The formation may be a heating and pressing treatment. Here, when the first upper insulating film 37 shown in FIG. 12 is also formed of such a coating material, the flattening may be performed by heating and pressing.
[0083]
(Twelfth embodiment)
FIG. 33 is a sectional view of a semiconductor device according to a twelfth embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 31 in that the first upper insulating film 37 is omitted, and the embedded portion including the peripheral portion of the upper surface of the semiconductor structure 23, the upper surface of the sealing film 36, and the rewiring 64 is provided. Another upper insulating film 65 is formed on the entire upper surface of the material 34 by screen printing or the like.
[0084]
In this case, both ends of the rewiring 64 on the embedding material 34 are connected to the first upper insulating film 65 covering the other via an opening 66 formed by irradiation of a CO2 laser or the like. Is connected to the upper layer rewiring 39. Further, the first upper layer rewiring 39 is directly connected to the upper surface of the columnar electrode 32 without passing through the opening of the insulating film.
[0085]
(Thirteenth and fourteenth embodiments)
FIG. 34 is a sectional view of a semiconductor device according to a thirteenth embodiment of the present invention. This semiconductor device is significantly different from the semiconductor device shown in FIG. 31 in that the height of the embedding material 34 including the rewiring 64 is lower than the height of the semiconductor structure 23.
[0086]
In this case, the upper surface of the embedding material 34 including the rewiring 64 is covered with the sealing film 36. Both ends of the rewiring 64 on the embedding material 34 are filled with a conductive film filled as necessary in an opening 67 formed by irradiating a CO2 laser on the sealing film 36 covering the rewiring 64. It is connected to the first upper layer rewiring 39 via a conductive material 68 made of resin or the like.
[0087]
Note that, as in the fourteenth embodiment of the present invention shown in FIG. 35, the height of the embedding material 34 including the rewiring 64 may be higher than the height of the semiconductor structure 23. In this case, the upper surface of the semiconductor structure 23 is covered with the sealing film 36. In addition, the columnar electrode 32 is provided with a conductive material 70 made of a conductive resin or the like filled as necessary in an opening 69 formed by irradiating the sealing film 36 with a CO2 laser or the like on the sealing film 36. Connected to the first upper layer rewiring 39.
[0088]
(Fifteenth embodiment)
In the case shown in FIG. 18, the cutting is performed between the semiconductor components 23 adjacent to each other. However, the cutting is not limited to this, and two or more semiconductor components 23 are cut as one set. As in the fifteenth embodiment of the present invention, the three semiconductor components 23 may be cut into one set to obtain a multi-chip module type semiconductor device. In this case, the set of three semiconductor components 23 may be the same or different.
[0089]
(Sixteenth embodiment)
FIG. 37 is a sectional view of a semiconductor device according to a sixteenth embodiment of the present invention. In this semiconductor device, the lower surface of a silicon substrate 74a of a first semiconductor component 73a similar to the case shown in FIG. 1 is bonded to the center of the upper surface of a base plate 71 having a planar square shape via a first adhesive layer 72a. ing.
[0090]
The lower surface of a first embedding material 75a having a rectangular frame shape is joined to the upper surface of the base plate 71 around the first semiconductor structure 73a. A first sealing film 76a is provided between the first semiconductor structure 73a and the first embedding material 75a. The first upper layer rewiring 77a is provided at a predetermined position on the upper surface of the first semiconductor structure 73a, the first burying material 75a, and the first sealing film 76a with the columnar electrode 78a of the first semiconductor structure 73a. Is provided to be connected to.
[0091]
The lower surface of the silicon substrate 74b of the second semiconductor component 73b similar to that shown in FIG. 1 is provided on the upper surface of the first semiconductor component 73a including the first upper layer rewiring 77a via the second adhesive layer 72b. Is glued. The lower surface of a second embedding material 75b having a rectangular frame shape is joined to the upper surface of the first embedding material 75a including the first upper layer rewiring 77a. In this case, a vertical conduction portion 79b is provided at a predetermined position in the second embedding material 75b. The lower surface of the upper / lower conducting portion 79b is connected to the connection pad of the first upper layer rewiring 77a. A second sealing film 76b is provided between the second semiconductor component 73b and the second embedding material 75b.
[0092]
A second upper layer rewiring 77b is provided at a predetermined position on the upper surface of the second semiconductor component 73b, the second burying material 75b, and the second sealing film 76b by the columnar electrode 78b of the second semiconductor component 73b. And it is provided so as to be connected to the upper and lower conductive portions 79b in the second embedding material 75b. The lower surface of the silicon substrate 74c of the third semiconductor component 73c similar to that shown in FIG. 1 is provided on the upper surface of the second semiconductor component 73b including the second upper layer rewiring 77b via the third adhesive layer 72c. Is glued.
[0093]
The lower surface of a rectangular frame-shaped third embedding material 75c is joined to the upper surface of the second embedding material 75b including the second upper layer rewiring 77b. In this case, a vertical conduction portion 79c is provided at a predetermined location in the third embedding material 75c. The lower surface of the upper / lower conducting portion 79c is connected to the connection pad of the second upper layer rewiring 77b. A third sealing film 76c is provided between the third semiconductor component 73c and the third embedding material 75c.
[0094]
A third upper layer rewiring 77c is provided at a predetermined location on the upper surface of the third semiconductor component 73c, the third burying material 75c, and the third sealing film 76c by the columnar electrode 78c of the third semiconductor component 73c. And, it is connected to the upper and lower conductive portions 79c in the third embedding material 75c. An upper insulating film 80 is provided on the entire upper surfaces of the third semiconductor structure 73c including the third upper layer rewiring 77c, the third burying material 75c, and the third sealing film 76c. At predetermined positions on the upper insulating film 80, solder balls 81 are provided so as to be connected to connection pads of the third upper rewiring 77c.
[0095]
Next, an example of a method for manufacturing the semiconductor device will be described. First, as shown in FIG. 38, a grid-like first embedding material 75a is arranged at a predetermined position on the upper surface of the base plate 71 from which a plurality of base plates 71 shown in FIG. 37 can be sampled. In this case, the base plate 71, the first embedding material 75a, and second and third embedding materials 75b and 75c described later are made of a thermoplastic resin. Then, the first embedding material 75a is joined to a predetermined location on the upper surface of the base plate 71 by heating and pressing.
[0096]
Next, as shown in FIG. 39, the lower surface of the silicon substrate 74a of the first semiconductor structure 73a is placed at the center of the upper surface of the base plate 71 in each opening of the first embedding material 75a in a lattice shape. Is bonded via a first bonding layer 72a which has been bonded beforehand. In this state, the upper surface of the first embedding material 75a and the upper surface of the first semiconductor structure 73a are arranged on substantially the same plane. Further, a relatively narrow first gap 82a is formed between the first semiconductor component 73a and the first embedding material 75a having a rectangular frame shape disposed outside the first semiconductor component 73a.
[0097]
Next, as shown in FIG. 40, a first sealing film 76a is formed in the first gap 82a. Next, a first upper layer rewiring 77a is formed at a predetermined location on the upper surface of the first semiconductor structure 73a, the first burying material 75a, and the first sealing film 76a in a columnar shape of the first semiconductor structure 73a. It is formed so as to be connected to the electrode 78a.
[0098]
Next, as shown in FIG. 41, a lattice-shaped second embedding material 75b is thermocompression-bonded to the upper surface of the lattice-shaped first embedding material 75a including the first upper layer rewiring 77a. In this case, a vertical conductive material 79b is formed in advance at a predetermined location in the second embedding material 75b. Then, the step caused by the first upper layer rewiring 77a is eliminated by thermocompression bonding, and the lower surface of the upper and lower conductive material 79b in the second embedding material 75b is connected to the connection pad of the first upper layer rewiring 77a.
[0099]
Next, as shown in FIG. 42, the second semiconductor component 73b is formed on the upper surface of the first semiconductor component 73a including the first upper layer rewiring 77a in the opening of the grid-like second embedding material 75b. The lower surface of the silicon substrate 74b is bonded to the lower surface of the silicon substrate 74b via a second bonding layer 72b previously bonded to the lower surface.
[0100]
Next, the second sealing film is inserted into a relatively narrow second gap formed between the second semiconductor component 73b and the second embedding material 75b having a rectangular frame shape disposed outside the second semiconductor component 73b. 76b is formed. Next, a second upper layer rewiring 77b is formed at a predetermined position on the upper surface of the first semiconductor structure 73a, the first burying material 75a, and the first sealing film 76a by forming a columnar shape of the second semiconductor structure 73b. It is formed so as to be connected to the electrode 78b and the vertical conducting material 79b in the second embedding material 75b.
[0101]
Next, as shown in FIG. 43, a grid-like third embedding material 75c is thermocompression-bonded to the upper surface of the grid-like second embedding material 75b including the second upper layer rewiring 77b. In this case, a vertical conductive material 79c is formed in advance at a predetermined location in the third embedding material 75c. Then, the step due to the second upper layer rewiring 77b is eliminated by the thermocompression bonding, and the lower surface of the upper and lower conductive material 79c in the third embedding material 75c is connected to the connection pad of the second upper layer rewiring 77b.
[0102]
Next, the lower surface of the silicon substrate 74c of the third semiconductor component 73c is placed on the upper surface of the second semiconductor component 73b including the second upper layer rewiring 77b in the opening of the third embedding material 75c having a lattice shape. It is bonded to the lower surface via a third bonding layer 72c which has been bonded in advance.
[0103]
Next, a third sealing film is formed in a relatively narrow third gap formed between the third semiconductor component 73c and the third embedding material 75c having a rectangular frame shape disposed outside the third semiconductor component 73c. 76c is formed. Next, a third upper layer rewiring 77c is formed at a predetermined position on the upper surface of the third semiconductor component 73c, the third embedding material 75c, and the third sealing film 76c in a columnar shape of the third semiconductor component 73c. It is formed so as to be connected to the electrode 78c and the vertical conductive material 79c in the third embedding material 75c.
[0104]
Next, the upper insulating film 80 is patterned on the upper surfaces of the third semiconductor component 73c including the third upper layer rewiring 77c, the third burying material 75c, and the third sealing film 76c. Next, a solder ball 81 is formed at a predetermined location on the upper insulating film 80 so as to be connected to the connection pad portion of the third upper layer rewiring 77c. Next, as shown in FIG. 44, after a predetermined dicing step, a plurality of semiconductor devices shown in FIG. 37 are obtained.
[0105]
(Seventeenth embodiment)
FIG. 45 is a sectional view of a semiconductor device according to a seventeenth embodiment of the present invention. In this semiconductor device, first, a device substantially the same as that shown in FIG. 1 is prepared. Hereinafter, the prepared one is referred to as a first semiconductor block 81. However, the solder balls 46 of the first semiconductor block 81 are all disposed only on the periphery located outside the semiconductor structure 23, and have a slightly smaller diameter than that shown in FIG.
[0106]
Also, a material which is substantially the same as that shown in FIG. 24 but in which the vertical conductive material 82 is provided in the embedded material 34 is prepared. Hereinafter, the prepared one is referred to as a second semiconductor block 83. Then, the second semiconductor block 83 connects the lower surface of the vertical conductive material 82 in the embedded material 34 of the second semiconductor block 83 to the solder ball 46 of the first semiconductor block 81 on the first semiconductor block 81. It has been installed.
[0107]
(Eighteenth and nineteenth embodiments)
FIG. 46 is a sectional view showing a semiconductor device according to the eighteenth embodiment of the present invention. First, in this semiconductor device, a device which is substantially the same as that shown in FIG. 24 but in which a vertical conductive material 84 is provided in an embedded material 34 is prepared. Hereinafter, the prepared one is referred to as a semiconductor block 85.
[0108]
However, in this semiconductor block 85, a first insulating film 86 is pattern-formed on the upper surfaces of the semiconductor structure 23, the embedding material 34, and the sealing film 36, and the wiring 87 is vertically connected to the upper surface of the first insulating film 86. The wiring is formed by being connected to the upper surface of the material 84 and the second insulating film 88 is pattern-formed on the upper surface of the first insulating film 86 including the wiring 87, and is exposed without being covered by the second insulating film 88. Small solder balls 89 are formed on the connection pad portions 87.
[0109]
A plurality of semiconductor components 23 having substantially the same structure as that shown in FIG. 1 are mounted on the semiconductor block 85 by connecting the columnar electrodes 32 to the solder balls 89 of the semiconductor block 85.
[0110]
Incidentally, as in the nineteenth embodiment of the present invention shown in FIG. 47, the first and second semiconductor chips 91 and 92 made of LSI or the like may be mounted on the semiconductor block 85. In this case, the connection pad portions of the wiring 87 that are exposed without being covered with the second insulating film 88 of the semiconductor block 85 are all disposed only on the periphery located outside the semiconductor structure 23.
[0111]
The first and second semiconductor chips 91 and 92 have a structure in which a plurality of connection pads 91b and 92b are provided on the upper peripheral portion of the chip bodies 91a and 92a. The plane size of the first semiconductor chip 91 is substantially the same as the plane size of the semiconductor structure 23, and the plane size of the second semiconductor chip 92 is somewhat smaller than the plane size of the semiconductor chip 91.
[0112]
The first semiconductor chip 91 is mounted on the central portion of the upper surface of the insulating film 88 of the semiconductor block 85 via an adhesive layer 93, and its connection pad 91 b is connected via a wire 94 to the second insulating film 88 of the semiconductor block 85. It is connected to the connection pad portion of the wiring 87 which is not covered with and exposed. The second semiconductor chip 92 is mounted on the center of the upper surface of the first semiconductor chip 91 via an adhesive layer 95, and its connection pad 92 b is covered by a second insulating film 88 of the semiconductor block 85 via a wire 96. Without being connected to the exposed connection pad portion of the wiring 87. A sealing film 97 made of an epoxy resin or the like is provided on the entire upper surface of the insulating film 88 including the first and second semiconductor chips 91 and 92 and the wires 94 and 96.
[0113]
(Twentieth and twenty-first embodiments)
FIG. 48 is a sectional view of a semiconductor device according to a twentieth embodiment of the present invention. In this semiconductor device, first, a device which is substantially the same as that shown in FIG. 1 but does not include the second upper layer redistribution wiring 43, the third upper layer insulating film 44 and the solder balls 46 is prepared. However, in this case, one side portion 34a of the embedding material 34 is somewhat wide in plan view.
[0114]
One end of a part of the first upper layer redistribution wiring 39 extends to the end surface of one side 34a of the embedding material 34, and a portion near this end surface is a connection terminal 39A. Except for the connection portion including the connection terminal 39A, a shielding metal layer 102 is provided on the upper surface of the second upper insulating film 41 including the first upper redistribution wiring 39 via an adhesive layer 101. . The metal layer 102 is made of the same foil having a thickness of several tens of μm.
[0115]
As a specific application example of this semiconductor device, a memory module such as a DRAM, which requires a small number of terminals and requires a temperature cycle reliability of connection between the silicon substrate 24 (chip portion) and the module, can be considered. In this case, as shown in the twenty-first embodiment of the present invention shown in FIG. 49, two components obtained by removing the base plate 21 from the components shown in FIG.
[0116]
Incidentally, in the semiconductor device shown in FIG. 48, when the semiconductor structure 23 is defective, a part of the first upper layer rewiring 39 without bonding the metal layer 102 via the adhesive layer 101 is used as a repair method. May be cut by laser irradiation to make the defective semiconductor component 23 unusable, and then another non-defective semiconductor component 23A may be mounted as shown in FIG. In this case, an opening is formed in a predetermined portion of the first upper insulating film 41 by irradiating a CO2 laser, a conductive material 103 made of a conductive resin or the like is embedded in the opening, and another non-defective semiconductor structure 23A is formed. May be connected to this conductive material 103 via solder (not shown).
[0117]
(Other embodiments)
For example, in the state shown in FIG. 9, a semiconductor component 23 that does not include the sealing film 33 is prepared. That is, as shown in FIG. 5, after forming the protective film 27, the rewiring 31, and the columnar electrode 32 on the silicon substrate 24 in a wafer state on which the connection pads 25 and the insulating film 26 are formed, the sealing film 33 is formed. Dicing this without doing.
[0118]
Then, for example, in the manufacturing process shown in FIG. 10, the sealing films 33 and 36 are simultaneously formed with the same sealing material in the regions where the sealing films 33 and 36 are to be formed, and the sealing films 33 and 36 (however, (The sealing film is integrated and has no boundary) and the upper surface side may be polished to obtain the state shown in FIG.
[0119]
【The invention's effect】
As described above, according to the present invention, a plurality of or a plurality of sets of a semiconductor structure having rewiring and columnar electrodes on a semiconductor substrate and an embedding material are arranged on a base plate, and an insulating film on the semiconductor structure is provided. And forming an upper layer rewiring on the embedding material by connecting to the columnar electrode of the semiconductor structure, and cutting at least the embedding material, thereby having one or one set of semiconductor components and having the embedding material. In addition, a plurality of semiconductor devices in which a part of the upper layer rewiring is arranged on the embedding material can be obtained in a lump, and there is no conventional bonding step, and thus the external connection electrode can be formed without bonding. The arrangement interval can be increased, and the insulating film and the upper-layer rewiring can be collectively formed on a plurality or a plurality of sets of semiconductor structures, so that the manufacturing process can be simplified. Kill.
[Brief description of the drawings]
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a cross-sectional view of an example of a method for manufacturing the semiconductor device shown in FIG. 1 which is initially prepared.
FIG. 3 is a sectional view of the manufacturing process following FIG. 2;
FIG. 4 is a sectional view of the manufacturing process following FIG. 3;
FIG. 5 is a sectional view of the manufacturing process following FIG. 4;
FIG. 6 is a sectional view of the manufacturing process following FIG. 5;
FIG. 7 is a sectional view of the manufacturing process following FIG. 6;
FIG. 8 is a sectional view of the manufacturing process following FIG. 7;
FIG. 9 is a sectional view of the manufacturing process following FIG. 8;
FIG. 10 is a sectional view of the manufacturing process following FIG. 9;
FIG. 11 is a sectional view of the manufacturing process continued from FIG. 10;
FIG. 12 is a sectional view of the manufacturing process following FIG. 11;
FIG. 13 is a sectional view of the manufacturing process following FIG. 12;
FIG. 14 is a sectional view of the manufacturing process following FIG. 13;
FIG. 15 is a sectional view of the manufacturing process continued from FIG. 14;
FIG. 16 is a sectional view of the manufacturing process continued from FIG. 15;
FIG. 17 is a sectional view of the manufacturing process continued from FIG. 16;
FIG. 18 is a sectional view of the manufacturing process following FIG. 17;
FIG. 19 is a sectional view of another example of the method of manufacturing the semiconductor device shown in FIG. 1 which is initially prepared.
FIG. 20 is a sectional view of a predetermined manufacturing process in the other example.
FIG. 21 is a sectional view of a predetermined manufacturing step in still another example of the method of manufacturing the semiconductor device shown in FIG. 1;
FIG. 22 is a sectional view of the manufacturing process continued from FIG. 21;
FIG. 23 is a sectional view of a semiconductor device as a second embodiment of the present invention.
FIG. 24 is a sectional view of a semiconductor device according to a third embodiment of the present invention;
FIG. 25 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention;
FIG. 26 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention;
FIG. 27 is a sectional view of a semiconductor device as a sixth embodiment of the present invention.
FIG. 28 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention;
FIG. 29 is a sectional view of a semiconductor device as an eighth embodiment of the present invention;
FIG. 30 is a sectional view of a semiconductor device according to a ninth embodiment of the present invention;
FIG. 31 is a sectional view of a semiconductor device as a tenth embodiment of the present invention;
FIG. 32 is a sectional view of a semiconductor device according to an eleventh embodiment of the present invention;
FIG. 33 is a sectional view of a semiconductor device according to a twelfth embodiment of the present invention;
FIG. 34 is a sectional view of a semiconductor device according to a thirteenth embodiment of the present invention;
FIG. 35 is a sectional view of a semiconductor device as a fourteenth embodiment of the present invention;
FIG. 36 is a sectional view of a semiconductor device according to a fifteenth embodiment of the present invention;
FIG. 37 is a sectional view of a semiconductor device according to a sixteenth embodiment of the present invention;
38 is a cross-sectional view of an example of a manufacturing method of the semiconductor device shown in FIG. 37, which is an initial manufacturing process;
FIG. 39 is a sectional view of the manufacturing process following FIG. 38;
FIG. 40 is a sectional view of the manufacturing process continued from FIG. 39;
FIG. 41 is a sectional view of the manufacturing process continued from FIG. 40;
FIG. 42 is a sectional view of the manufacturing process continued from FIG. 41;
FIG. 43 is a sectional view of the manufacturing process continued from FIG. 42;
FIG. 44 is a sectional view of the manufacturing process following FIG. 43;
FIG. 45 is a sectional view of a semiconductor device as a seventeenth embodiment of the present invention;
FIG. 46 is a sectional view of a semiconductor device according to an eighteenth embodiment of the present invention;
FIG. 47 is a sectional view of a semiconductor device as a nineteenth embodiment of the present invention;
FIG. 48 is a sectional view of a semiconductor device according to a twentieth embodiment of the present invention;
FIG. 49 is a sectional view of a semiconductor device as a twenty-first embodiment of the present invention;
50 is a cross-sectional view for explaining a case where repair is performed in the semiconductor device shown in FIG. 48;
FIG. 51 is a cross-sectional view of an example of a conventional semiconductor device.
[Explanation of symbols]
21 Base plate
22 Adhesive layer
23 Semiconductor Structure
24 Silicon substrate
25 connection pads
31 Rewiring
32 pillar electrode
33 sealing film
34 embedded material
36 sealing film
37 First Upper Insulating Film
39 1st upper layer rewiring
41 Second upper insulating film
43 Second Upper Layer Rewiring
44 Third upper insulating film
46 Solder Ball

Claims (21)

半導体基板上に設けられた複数の再配線および該各再配線の上に設けられた柱状電極を有する半導体構成体と、該半導体構成体の側方に設けられた枠状の埋込材と、前記半導体構成体の柱状電極を除く上面全体に設けられた絶縁膜と、該絶縁膜および前記埋込材上に、前記柱状電極に接続されて設けられ且つ接続パッド部を有する少なくとも一層の上層再配線とを備え、前記上層再配線の中、最上層の上層再配線の少なくとも一部の接続パッド部は前記埋込材上に配置されていることを特徴とする半導体装置。A semiconductor structure having a plurality of rewirings provided on a semiconductor substrate and columnar electrodes provided on each of the rewirings, and a frame-shaped embedding material provided on a side of the semiconductor structure, An insulating film provided on the entire upper surface of the semiconductor structure excluding the columnar electrodes, and at least one upper layer having a connection pad portion provided on the insulating film and the embedding material and connected to the columnar electrodes. And a connection pad portion of at least a part of the upper layer rewiring in the upper layer rewiring is disposed on the embedding material. 各々が、半導体基板と、該半導体基板上に設けられた複数の再配線および該各再配線上に設けられた柱状電極を有し、相互に離間して配置された複数の半導体構成体と、前記半導体構成体の間または前記各半導体構成体の側方に設けられた埋込材と、前記各半導体構成体の柱状電極を除く上面全体に設けられた絶縁膜と、該絶縁膜および前記埋込材上に、前記柱状電極に接続されて設けられ且つ接続パッド部を有する少なくとも一層の上層再配線とを備え、前記上層再配線の中、最上層の上層再配線の少なくとも一部の接続パッド部は前記埋込材上に配置されていることを特徴とする半導体装置。Each having a semiconductor substrate, a plurality of rewiring provided on the semiconductor substrate and a plurality of columnar electrodes provided on each of the rewiring, a plurality of semiconductor structures disposed apart from each other, An embedding material provided between the semiconductor structures or on the side of each of the semiconductor structures; an insulating film provided on the entire upper surface of each of the semiconductor structures except for the columnar electrodes; At least one upper layer rewiring connected to the columnar electrode and having a connection pad portion, on at least one of the upper layer rewirings in the upper layer rewiring. A semiconductor device, wherein a portion is disposed on the embedding material. 請求項１または２に記載の発明において、前記半導体構成体と前記埋込材との間に別の絶縁膜が設けられていることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein another insulating film is provided between the semiconductor structure and the embedding material. 請求項１または２に記載の発明において、前記埋込材の下面は前記半導体構成体の下面とほぼ同一の平面上に配置されていることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein a lower surface of the embedding material is disposed on a substantially same plane as a lower surface of the semiconductor structure. 請求項１または２に記載の発明において、前記埋込材の上面は前記半導体構成体の上面とほぼ同一の平面上に配置されていることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein an upper surface of the embedding material is arranged on substantially the same plane as an upper surface of the semiconductor structure. 4. 請求項１または２に記載の発明において、前記埋込材の上面は前記半導体構成体の上面と異なる高さ位置に配置されていることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein an upper surface of the embedding material is arranged at a height different from an upper surface of the semiconductor structure. 4. 請求項１または２に記載の発明において、前記半導体構成体および前記埋込材はベース板上に設けられていることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the semiconductor structure and the embedding material are provided on a base plate. 請求項１または２に記載の発明において、前記上層再配線はメッキ層を含むことを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the upper rewiring includes a plating layer. 請求項１または２に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記半導体構成体の柱状電極と前記上層再配線とを接続する層間再配線が設けられていることを特徴とする半導体装置。3. The invention according to claim 1, wherein the insulating film has a plurality of layers, and an interlayer rewiring for connecting the columnar electrode of the semiconductor structure and the upper layer rewiring is provided between the layers. Characteristic semiconductor device. 請求項１または２に記載の発明において、前記上層再配線を含む前記絶縁膜の上面に前記上層再配線の接続パッド部の少なくとも一部を除く部分に最上層絶縁膜が設けられていることを特徴とする半導体装置。3. The method according to claim 1, wherein an uppermost insulating film is provided on a portion of the upper surface of the insulating film including the upper redistribution wiring except at least a part of a connection pad portion of the upper redistribution wiring. Characteristic semiconductor device. 請求項１０に記載の発明において、前記上層再配線の接続パッド部上に突起状の接続端子が設けられていることを特徴とする半導体装置。11. The semiconductor device according to claim 10, wherein a protruding connection terminal is provided on the connection pad portion of the upper layer rewiring. 請求項１１に記載の発明において、前記突起状の接続端子は半田ボールであることを特徴とする半導体装置。12. The semiconductor device according to claim 11, wherein the projecting connection terminals are solder balls. 請求項１または２に記載の発明において、前記上層再配線の一部の一端部は前記埋込材の端面まで延ばされ、この端面近傍における部分は接続端子となっていることを特徴とする半導体装置。3. The invention according to claim 1, wherein one end of a part of the upper layer rewiring is extended to an end face of the embedding material, and a portion near the end face is a connection terminal. Semiconductor device. ベース板上に、少なくとも一方向に所定間隔で埋込材を配置する工程と、
各々が、複数の再配線および該各再配線上に設けられた柱状電極を有する複数の半導体構成体を、前記ベース板上の一方向において、前記埋込材が前記半導体構成体の所定個数毎にその側方に介在されるように配置する工程と、
接続パッド部を有し且ついずれかの前記半導体構成体の対応する前記柱状電極に接続される上層再配線を、少なくともいずれかの前記上層再配線の接続パッド部が前記埋込材上に配置されるように形成する工程と、
前記半導体構成体間における前記埋込材を切断して少なくともいずれかの前記上層再配線の接続パッド部が前記半導体構成体の側方に介在された前記埋込材上に配置された前記半導体構成体を少なくとも１つ有する半導体装置を複数個得る工程とを有することを特徴とする半導体装置の製造方法。On the base plate, a step of arranging the embedding material at predetermined intervals in at least one direction,
A plurality of semiconductor structures each having a plurality of rewirings and columnar electrodes provided on each of the rewirings, in one direction on the base plate, the embedding material is provided for every predetermined number of the semiconductor structures. Arranging it so as to be interposed on its side,
An upper layer rewiring having a connection pad portion and connected to a corresponding one of the columnar electrodes of any of the semiconductor structures, a connection pad portion of at least one of the upper layer rewirings is disposed on the embedding material. Forming a so that
The semiconductor structure in which the embedding material between the semiconductor structures is cut and at least one of the connection pad portions of the upper layer rewiring is disposed on the embedding material interposed on a side of the semiconductor structure. Obtaining a plurality of semiconductor devices having at least one body. 請求項１４に記載の発明において、前記半導体構成体と前記埋込材との間に別の絶縁膜を形成する工程を有することを特徴とする半導体装置の製造方法。15. The method of manufacturing a semiconductor device according to claim 14, further comprising a step of forming another insulating film between the semiconductor structure and the embedding material. 請求項１４に記載の発明において、前記埋込材を切断する工程は、前記半導体構成体が複数個含まれるように切断することを特徴とする半導体装置の製造方法。15. The method of manufacturing a semiconductor device according to claim 14, wherein in the step of cutting the embedding material, cutting is performed so that a plurality of the semiconductor components are included. 請求項１６に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記各半導体構成体の柱状電極とそれに対応する前記上層再配線とを接続する複数組の層間再配線を形成する工程を有することを特徴とする半導体装置の製造方法。17. The invention according to claim 16, wherein the insulating film has a plurality of layers, and between the layers, a plurality of sets of interlayer rewirings for connecting the columnar electrodes of the respective semiconductor structures and the corresponding upper layer rewirings are formed. A method for manufacturing a semiconductor device, comprising: 請求項１６に記載の発明において、前記上層再配線を含む前記絶縁膜の上面において前記上層再配線の接続パッド部を除く部分に最上層絶縁膜を形成する工程を有することを特徴とする半導体装置の製造方法。17. The semiconductor device according to claim 16, further comprising a step of forming an uppermost insulating film on a portion of the upper surface of the insulating film including the upper layer redistribution except for a connection pad portion of the upper layer redistribution. Manufacturing method. 請求項１８に記載の発明において、前記上層再配線の接続パッド部上に突起状の接続端子を形成する工程を有することを特徴とする半導体装置の製造方法。19. The method of manufacturing a semiconductor device according to claim 18, further comprising a step of forming a protruding connection terminal on the connection pad portion of the upper layer rewiring. 請求項１６に記載の発明において、前記埋込材を切断する工程は前記埋込材を切断するとともに前記ベース板を切断し、前記半導体装置としてベース板を備えたものを得ることを特徴とする半導体装置の製造方法。In the invention according to claim 16, the step of cutting the embedding material cuts the embedding material and cuts the base plate, and obtains a semiconductor device having a base plate. A method for manufacturing a semiconductor device. 請求項２０に記載の発明において、切断前の前記ベース板下に別のベース板を配置し、前記ベース板を切断した後に、前記別のベース板を取り除く工程を有することを特徴とする半導体装置の製造方法。21. The semiconductor device according to claim 20, further comprising a step of disposing another base plate below the base plate before cutting, and removing the another base plate after cutting the base plate. Manufacturing method.
JP2002254695A 2002-08-09 2002-08-30 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3888267B2 (en)

Priority Applications (13)

Application Number Priority Date Filing Date Title
JP2002254695A JP3888267B2 (en) 2002-08-30 2002-08-30 Semiconductor device and manufacturing method thereof
CN038012693A CN1568546B (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
PCT/JP2003/009958 WO2004015771A2 (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
EP03784529A EP1527480A2 (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
AU2003253425A AU2003253425C1 (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
CA2464078A CA2464078C (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
KR1020047005322A KR100593049B1 (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
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