JP2006148161A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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JP2006148161A
JP2006148161A JP2006037375A JP2006037375A JP2006148161A JP 2006148161 A JP2006148161 A JP 2006148161A JP 2006037375 A JP2006037375 A JP 2006037375A JP 2006037375 A JP2006037375 A JP 2006037375A JP 2006148161 A JP2006148161 A JP 2006148161A
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protruding electrode
semiconductor device
rewiring
insulating film
semiconductor chip
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JP4349376B2 (en
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Takeshi Wakabayashi
猛 若林
Ichiro Mihara
一郎 三原
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To directly and surely conductively connect a semiconductor chip and a rewiring to a circuit board without using a relay substrate, and to directly conductively connect to the circuit boards arranged above and below. <P>SOLUTION: This device comprises a semiconductor chip 21, having a connection pad 23, a first rewiring 32 and a second rewiring 36 which are provided on the top surface of an insulating film 26, while being connected to the connection pad 23 of the semiconductor chip 21 and have a pad part arranged on the outside of a peripheral side surface of the semiconductor chip 21; a first protruding electrode 33 connected to the pad part of the first rewiring 32 via an opening part formed in the insulating film 26, and a second protruding electrode 37 connected to the pad part of the second rewiring 36. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

例えばＢＧＡ(ball grid array)と呼ばれる半導体装置には、ＬＳＩ等からなる半導体チップを該半導体チップのサイズよりもやや大きいサイズの中継基板(インターポーザ)の上面中央部に搭載し、中継基板の下面に半田ボールによる接続端子をマトリクス状に配置したものがある。     For example, in a semiconductor device called a BGA (ball grid array), a semiconductor chip made of LSI or the like is mounted on the center of the upper surface of a relay substrate (interposer) that is slightly larger than the size of the semiconductor chip, and is mounted on the lower surface of the relay substrate. There is one in which connection terminals by solder balls are arranged in a matrix.

図１８は従来のこのような半導体装置の一例の断面図を示したものである。半導体チップ１は、半導体基板２の上面周辺部に複数のバンプ電極３が設けられた構造となっている。   FIG. 18 shows a sectional view of an example of such a conventional semiconductor device. The semiconductor chip 1 has a structure in which a plurality of bump electrodes 3 are provided around the upper surface of a semiconductor substrate 2.

中継基板４は、サイズが半導体チップ１の半導体基板２のサイズよりもやや大きいベースフィルム５を備えている。ベースフィルム５の上面には、半導体チップ１のバンプ電極３に接続される再配線６が設けられている。   The relay substrate 4 includes a base film 5 whose size is slightly larger than the size of the semiconductor substrate 2 of the semiconductor chip 1. A rewiring 6 connected to the bump electrode 3 of the semiconductor chip 1 is provided on the upper surface of the base film 5.

再配線６は、半導体チップ１のバンプ電極３に対応して設けられた第１の接続パッド７と、マトリクス状に設けられた第２の接続パッド８と、第１と第２の接続パッド７、８を接続する引き回し線９とからなっている。第２の接続パッド８の中央部に対応する部分におけるベースフィルム５には円孔１０が設けられている。   The rewiring 6 includes a first connection pad 7 provided corresponding to the bump electrode 3 of the semiconductor chip 1, a second connection pad 8 provided in a matrix, and the first and second connection pads 7. , 8 and a lead-out line 9 connecting them. A circular hole 10 is provided in the base film 5 in a portion corresponding to the central portion of the second connection pad 8.

そして、半導体チップ１は中継基板４の上面中央部に異方性導電接着剤１１を介して搭載されている。異方性導電接着剤１１は、熱硬化性樹脂１２中に多数の導電性粒子１３を含有させたものからなっている。   The semiconductor chip 1 is mounted on the center of the upper surface of the relay substrate 4 via an anisotropic conductive adhesive 11. The anisotropic conductive adhesive 11 is made of a thermosetting resin 12 containing a large number of conductive particles 13.

半導体チップ１を中継基板４上に搭載する場合には、まず、中継基板４の上面中央部にシート状の異方性導電接着剤１１を介して半導体チップ１を位置合わせしてただ単に載置する。   When the semiconductor chip 1 is mounted on the relay substrate 4, first, the semiconductor chip 1 is simply placed on the center of the upper surface of the relay substrate 4 with the sheet-like anisotropic conductive adhesive 11 being positioned. To do.

次に、熱硬化性樹脂１２が硬化する温度にて所定の圧力を加えてボンディングする。すると、バンプ電極３が熱硬化性樹脂１２を押し退けて第１の接続パッド７の上面に導電性粒子１３を介して導電接続され、且つ、半導体チップ１の下面が中継基板４の上面に熱硬化性樹脂１２を介して接着される。   Next, bonding is performed by applying a predetermined pressure at a temperature at which the thermosetting resin 12 is cured. Then, the bump electrode 3 pushes away the thermosetting resin 12 and is conductively connected to the upper surface of the first connection pad 7 via the conductive particles 13, and the lower surface of the semiconductor chip 1 is thermoset to the upper surface of the relay substrate 4. It adheres via the adhesive resin 12.

次に、半導体チップ１を含む中継基板４の上面全体にエポキシ系樹脂からなる樹脂封止膜１４を形成する。次に、円孔１０内およびその下方に半田ボール１５を第２の接続パッド８に接続させて形成する。この場合、第２の接続パッド８はマトリクス状に配置されているため、半田ボール１５もマトリクス状に配置される。   Next, a resin sealing film 14 made of an epoxy resin is formed on the entire top surface of the relay substrate 4 including the semiconductor chip 1. Next, solder balls 15 are formed in the circular hole 10 and below the circular holes 10 by being connected to the second connection pads 8. In this case, since the second connection pads 8 are arranged in a matrix, the solder balls 15 are also arranged in a matrix.

ここで、半田ボール１５のサイズは半導体チップ１のバンプ電極３のサイズより大きく、また、各半田ボール１５相互の接触を避けるため、その配置間隔をバンプ電極３の配置間隔より大きくする必要がある。そこで、半導体チップ１のバンプ電極３の数が増大した場合、各半田ボール１５に必要な配置間隔を得るため、配置領域を半導体チップ１のサイズより大きくすることが必要となり、そのために、中継基板４のサイズを半導体チップ１のサイズよりもやや大きくしている。したがって、マトリクス状に配置された半田ボール１５のうち、周辺部の半田ボール１５は半導体チップ１の周囲に配置されている。   Here, the size of the solder balls 15 is larger than the size of the bump electrodes 3 of the semiconductor chip 1, and it is necessary to make the arrangement interval larger than the arrangement interval of the bump electrodes 3 in order to avoid contact between the solder balls 15. . Therefore, when the number of bump electrodes 3 of the semiconductor chip 1 is increased, it is necessary to make the arrangement region larger than the size of the semiconductor chip 1 in order to obtain a necessary arrangement interval for each solder ball 15, and for this reason, The size of 4 is slightly larger than the size of the semiconductor chip 1. Therefore, among the solder balls 15 arranged in a matrix, the peripheral solder balls 15 are arranged around the semiconductor chip 1.

ところで、上記のように半田ボール１５による接続端子を半導体チップ１の周囲にも備える従来の半導体装置では、再配線６が形成された中継基板４を用い、ボンディングにより、半導体チップ１のバンプ電極３の下面を中継基板４の再配線６の第１の接続電極７の上面に異方性導電接着剤１１の導電性粒子１３を介して導電接続する構成としているので、ボンディング状態により接続不良が発生する可能性があるという問題があった。また、回路基板を半導体チップ１の上下に分離して配置する構造の場合、上下の回路基板を接続するためのコネクタが別途必要となるため、工数や価格に問題があった。   By the way, in the conventional semiconductor device having the connection terminals by the solder balls 15 also around the semiconductor chip 1 as described above, the bump electrode 3 of the semiconductor chip 1 is bonded by using the relay substrate 4 on which the rewiring 6 is formed. Is connected to the upper surface of the first connection electrode 7 of the rewiring 6 of the relay substrate 4 through the conductive particles 13 of the anisotropic conductive adhesive 11, so that connection failure occurs depending on the bonding state. There was a problem that could be. Further, in the case of the structure in which the circuit boards are arranged separately on the upper and lower sides of the semiconductor chip 1, a connector for connecting the upper and lower circuit boards is required separately, which causes problems in man-hours and prices.

そこで、この発明は、接続端子を半導体チップの周囲にも備える半導体装置において、中継基板を用いることなく、直接、回路基板に半導体チップと再配線とを確実に導電接続することができる、半導体装置およびその製造方法を提供することを目的とする。
また、この発明は、上下に配置された回路基板に、直接、導電接続することができる半導体装置の製造方法を提供することを目的とする。 Accordingly, the present invention provides a semiconductor device having a connection terminal also provided around a semiconductor chip, in which the semiconductor chip and the rewiring can be reliably conductively connected directly to the circuit board without using a relay substrate. And it aims at providing the manufacturing method.
It is another object of the present invention to provide a method for manufacturing a semiconductor device that can be directly conductively connected to circuit boards disposed above and below.

請求項１に記載の発明に係る半導体装置は、一面上に接続パッドを有する半導体チップと、該半導体チップの一面および周側面を覆うように設けられた絶縁膜と、該絶縁膜の上面に前記半導体チップの接続パッドに接続されて設けられ、前記半導体チップの周側面より外側に配置されたパッド部を有する第１および第２の再配線と、前記第１の再配線のパッド部に前記絶縁膜に形成された開口部を介して接続された第１の突起電極と、前記第２の再配線のパッド部に接続されて設けられた第２の突起電極とを備えていることを特徴とするものである。
請求項２に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記第１の再配線のパッド部上には第２の突起電極が設けられていることを特徴とするものである。
請求項３に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記第２の再配線のパッド部上には第１の突起電極が設けられていることを特徴とするものである。
請求項４に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記絶縁膜上に前記第２の突起電極の周囲を覆う第２の絶縁膜が形成されていることを特徴とするものである。
請求項５に記載の発明に係る半導体装置は、請求項１に記載の発明において、さらに、前記接続パッドに接続されない突起電極を有することを特徴とするものである。
請求項６に記載の発明に係る半導体装置は、請求項１〜５のいずれかに記載の半導体装置上に同種または異種の半導体装置が１つ以上搭載されていることを特徴とするものである。
請求項７に記載の発明に係る半導体装置の製造方法は、一面上に接続パッドを有する複数の半導体チップをベース板に固着する工程と、前記複数の半導体チップを含む前記ベース板上に絶縁膜を形成する工程と、前記各半導体チップの周側面より外側における前記絶縁膜に開口部を形成する工程と、前記絶縁膜の上面に、前記各半導体チップの接続パッドに接続されて設けられ、前記絶縁膜の開口部に対応するパッド部に第１の突起電極が接続された第１の再配線、および前記各半導体チップの接続パッドに接続されて設けられ、且つ、前記各半導体チップの周側面より外側にパッド部を有する第２の再配線を形成する工程と、前記第２の再配線のパッド部上に第２の突起電極を形成する工程と、前記各組の半導体チップ間における前記両絶縁膜を切断して前記各半導体チップの周囲に前記第１および第２の突起電極が形成された半導体装置を複数個得る工程とを有することを特徴とするものである。
請求項８に記載の発明に係る半導体装置の製造方法は、請求項７に記載の発明において、前記第１の突起電極を前記再配線と同一工程で形成することを特徴とするものである。
請求項９に記載の発明に係る半導体装置の製造方法は、請求項７に記載の発明において、前記第１の突起電極を前記再配線の後工程で形成することを特徴とするものである。
請求項１０に記載の発明に係る半導体装置の製造方法は、請求項に記載の発明において、さらに、前記絶縁膜上に前記突起電極の周囲を覆う第２の絶縁膜を形成する工程を有することを特徴とするものである。 According to a first aspect of the present invention, there is provided a semiconductor device including a semiconductor chip having a connection pad on one surface, an insulating film provided so as to cover one surface and a peripheral side surface of the semiconductor chip, and an upper surface of the insulating film on the upper surface. First and second rewirings having pad portions provided to be connected to connection pads of the semiconductor chip and disposed outside the peripheral side surface of the semiconductor chip, and the insulation on the pad portions of the first rewiring A first protruding electrode connected through an opening formed in the film; and a second protruding electrode connected to the pad portion of the second rewiring. To do.
A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein a second protruding electrode is provided on the pad portion of the first rewiring. It is.
A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, wherein a first protruding electrode is provided on a pad portion of the second rewiring. It is.
A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the first aspect, wherein a second insulating film that covers the periphery of the second protruding electrode is formed on the insulating film. It is what.
A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to the first aspect, further comprising a protruding electrode that is not connected to the connection pad.
A semiconductor device according to a sixth aspect of the invention is characterized in that one or more semiconductor devices of the same kind or different kinds are mounted on the semiconductor device according to any one of the first to fifth aspects. .
According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: fixing a plurality of semiconductor chips having connection pads on one surface to a base plate; and insulating films on the base plate including the plurality of semiconductor chips. A step of forming an opening in the insulating film outside the peripheral side surface of each semiconductor chip, and an upper surface of the insulating film provided to be connected to a connection pad of each semiconductor chip, A first rewiring in which a first protruding electrode is connected to a pad portion corresponding to an opening of the insulating film, and a peripheral side surface of each semiconductor chip provided to be connected to a connection pad of each semiconductor chip A step of forming a second rewiring having a pad portion on the outer side, a step of forming a second protruding electrode on the pad portion of the second rewiring, and the both of the two pairs of semiconductor chips. Absolute It is characterized in that a step of cutting the film to obtain a plurality of semiconductor device wherein the first and second protruding electrode are formed around the respective semiconductor chips.
According to an eighth aspect of the present invention, in the semiconductor device manufacturing method according to the seventh aspect of the present invention, the first protruding electrode is formed in the same process as the rewiring.
According to a ninth aspect of the present invention, in the semiconductor device manufacturing method according to the seventh aspect of the present invention, the first protruding electrode is formed after the rewiring.
According to a tenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the tenth aspect of the present invention, further comprising forming a second insulating film covering the periphery of the protruding electrode on the insulating film. It is characterized by.

そして、この発明によれば、半導体チップの周側面より外側に配置されたパッド部を有する第１および第２の再配線と、第１の再配線のパッド部に絶縁膜に形成された開口部を介して接続された第１の突起電極と、第２の再配線のパッド部に接続されて設けられた第２の突起電極とを備えているため中継基板を用いることなく、直接、回路基板に半導体チップと再配線とを確実に導電接続することができる。また、第１の突起電極および第２の突起電極は、それぞれ、上下面に配置されているので、上下に配置された回路基板に、直接、導電接続することができる。   And according to this invention, the 1st and 2nd rewiring which has a pad part arrange | positioned outside the surrounding side surface of a semiconductor chip, and the opening part formed in the insulating film in the pad part of the 1st rewiring Circuit board without using a relay board, since the first protrusion electrode connected via the first protrusion electrode and the second protrusion electrode connected to the pad portion of the second rewiring are provided. In addition, the semiconductor chip and the rewiring can be reliably conductively connected. Further, since the first protruding electrode and the second protruding electrode are arranged on the upper and lower surfaces, respectively, they can be conductively connected directly to the circuit boards arranged on the upper and lower sides.

図１（Ａ）〜（Ｃ）はこの発明の一実施形態としての半導体装置を示すものであり、図１（Ａ）は同半導体装置の拡大平面図、図１（Ｂ）は同半導体装置の裏面側の配線状態を説明するためのもので、図１（Ａ）のＩB −ＩB に沿う拡大断面図、図１（Ｃ）は同半導体装置の表面側の配線状態を説明するためのもので、図１（Ａ）のＩC −ＩC に沿う拡大断面図である。 1A to 1C show a semiconductor device as an embodiment of the present invention. FIG. 1A is an enlarged plan view of the semiconductor device, and FIG. It intended to illustrate the interconnection state of the back side, enlarged cross-sectional view taken along the I B -I B of FIG. 1 (a), FIG. 1 (C) is for explaining a wiring state of the surface side of the semiconductor device FIG. 2 is an enlarged cross-sectional view taken along I C -I C in FIG.

この半導体装置は、ＬＳＩ等からなる半導体チップ２１を備えている。半導体チップ２１は、シリコン等からなる半導体基板２２の上面周辺部に複数の接続パッド２３が設けられ、接続パッド２３の中央部を除く半導体基板２２の上面に酸化シリコン等からなる絶縁膜２４が設けられ、接続パッド２３の中央部が絶縁膜２４に設けられた開口部２５を介して露出された構造となっている。   This semiconductor device includes a semiconductor chip 21 made of LSI or the like. The semiconductor chip 21 is provided with a plurality of connection pads 23 on the periphery of the upper surface of a semiconductor substrate 22 made of silicon or the like, and an insulating film 24 made of silicon oxide or the like is provided on the upper surface of the semiconductor substrate 22 excluding the central portion of the connection pads 23. Thus, the central portion of the connection pad 23 is exposed through an opening 25 provided in the insulating film 24.

半導体チップ２１には、その下面を除いて、上面および周側面にポリイミド系樹脂、エポキシ系樹脂、ＰＢＯ（ポリベンザオキシドール）系樹脂等からなる絶縁膜２６が被着されている。絶縁膜２６は、その上面を平坦とされ、且つ、その下面が半導体基板２２の下面と面一となるように設けられている。この場合、絶縁膜２６の半導体チップ２１の開口部２５に対応する部分には開口部２７が設けられている。また、半導体チップ２１の周側面より外側における絶縁膜２６の所定の複数箇所にはスルーホール（開口部）２８が設けられている。   The semiconductor chip 21 is covered with an insulating film 26 made of polyimide resin, epoxy resin, PBO (polybenzoxide) resin or the like on the upper surface and the peripheral side surface except for the lower surface. The insulating film 26 is provided such that its upper surface is flat and its lower surface is flush with the lower surface of the semiconductor substrate 22. In this case, an opening 27 is provided in a portion of the insulating film 26 corresponding to the opening 25 of the semiconductor chip 21. In addition, through holes (openings) 28 are provided at predetermined plural positions of the insulating film 26 outside the peripheral side surface of the semiconductor chip 21.

図１（Ａ）、（Ｂ）に示すように、半導体チップ２１の相対向する一対の辺側に配列され、両開口部２５、２７を介して露出された接続パッド２３の上面から絶縁膜２６の上面およびスルーホール２８の内壁面と内底部に亘り第１の下地金属層３１が設けられている。この場合、スルーホール２８の内底部に設けられた第１の下地金属層３１の下面は絶縁膜２６の下面と面一となっている。第１の下地金属層３１の上面には第１の再配線３２が設けられている。   As shown in FIGS. 1A and 1B, the insulating film 26 is arranged from the upper surface of the connection pad 23 that is arranged on a pair of opposite sides of the semiconductor chip 21 and exposed through both openings 25 and 27. A first base metal layer 31 is provided across the top surface of the through hole 28 and the inner wall surface and inner bottom portion of the through hole 28. In this case, the lower surface of the first base metal layer 31 provided on the inner bottom portion of the through hole 28 is flush with the lower surface of the insulating film 26. A first rewiring 32 is provided on the upper surface of the first base metal layer 31.

ここで、スルーホール２８内に設けられた第１の下地金属層３１および第１の再配線３２は、後述する如く、外部回路に接続される接続端子部の機能を有する第１の突起電極３３を構成している。したがって、第１の再配線３２は、半導体チップ２１の接続パッド２３に接続された部分からなるパッド部と、スルーホール２８上に配置されて第１の突起電極３３に一体的に接続された部分からなるパッド部と、両パッド部を接続する引き回し線とからなっている。そして、スルーホール２８の内底部に設けられた第１の下地金属層３１の下面、すなわち、第１の突起電極３３の下面には第１の半田ボール３４が設けられている。   Here, the first base metal layer 31 and the first rewiring 32 provided in the through hole 28 are, as will be described later, a first protruding electrode 33 having a function of a connection terminal portion connected to an external circuit. Is configured. Accordingly, the first rewiring 32 includes a pad portion formed of a portion connected to the connection pad 23 of the semiconductor chip 21 and a portion disposed on the through hole 28 and integrally connected to the first protruding electrode 33. And a lead line connecting the two pad portions. A first solder ball 34 is provided on the lower surface of the first base metal layer 31 provided at the inner bottom of the through hole 28, that is, on the lower surface of the first protruding electrode 33.

図１（Ａ）、（Ｃ）に示すように、半導体チップ２１の相対向する他の一対の辺側に配列され、両開口部２５、２７を介して露出された接続パッド２３の上面から絶縁膜２６の上面の他の箇所にかけて第２の下地金属層３５が設けられている。第２の下地金属層３５の上面には第２の再配線３６が設けられている。第２の再配線３６の先端部上には柱状の第２の突起電極３７が設けられている。ここで、第２の再配線３６は、半導体チップ２１の接続パッド２３に接続された部分からなるパッド部と、第２の突起電極３７に接続された部分からなるパッド部と、両パッド部を接続する引き回し線とからなっている。後述する如く、第２の下地金属層３５および第２の再配線３６は、それぞれ、第１の下地金属層３１および第１の再配線３２と同一工程で形成されるもので、材料、膜厚は、それぞれ、同一である。   As shown in FIGS. 1A and 1C, the semiconductor chip 21 is insulated from the upper surface of the connection pad 23 arranged on the other pair of sides facing each other and exposed through the openings 25 and 27. A second base metal layer 35 is provided over another portion of the upper surface of the film 26. A second rewiring 36 is provided on the upper surface of the second base metal layer 35. A columnar second protruding electrode 37 is provided on the tip of the second rewiring 36. Here, the second rewiring 36 includes a pad portion formed of a portion connected to the connection pad 23 of the semiconductor chip 21, a pad portion formed of a portion connected to the second protruding electrode 37, and both pad portions. It consists of a lead wire to connect. As will be described later, the second base metal layer 35 and the second rewiring 36 are formed in the same process as the first base metal layer 31 and the first rewiring 32, respectively. Are the same.

第２の突起電極３７の上面には第２の半田ボール３８が設けられている。第２の突起電極３７を除いて両再配線３２、３６を含む絶縁膜２６の上面にはポリイミド系樹脂、エポキシ系樹脂、ＰＢＯ系樹脂等からなる絶縁膜（封止膜）３９がその上面が第２の突起電極３７の上面と面一となるように設けられている。   A second solder ball 38 is provided on the upper surface of the second protruding electrode 37. An insulating film (sealing film) 39 made of polyimide resin, epoxy resin, PBO resin or the like is formed on the upper surface of the insulating film 26 including both the rewirings 32 and 36 except for the second protruding electrode 37. The second protrusion electrode 37 is provided so as to be flush with the upper surface.

このように、この半導体装置では、上・下面側に第１および第２の突起電極３３、３７が形成され、各第１および第２の突起電極３３、３７に接合された第１および第２の半田ボール３４、３８を備えているので、該半導体装置の一面側の第１の半田ボール３４を回路基板または他の電子部品に接合し、他面側の第２の半田ボール３８を他の回路基板または電子部品に直接接合することが可能になり、生産効率およびコスト面で有利となるばかりでなく、実装密度を向上することが可能となる。   As described above, in this semiconductor device, the first and second protruding electrodes 33 and 37 are formed on the upper and lower surfaces, and the first and second protruding electrodes 33 and 37 joined to the first and second protruding electrodes 33 and 37, respectively. Therefore, the first solder ball 34 on the one surface side of the semiconductor device is joined to the circuit board or other electronic component, and the second solder ball 38 on the other surface side is connected to the other solder balls 34, 38. It becomes possible to directly bond to a circuit board or an electronic component, which is advantageous not only in terms of production efficiency and cost but also in improving the mounting density.

また、上記実施形態では、上・下面の第１および第２の半田ボール３４、３８を半導体チップ２１の外周部に配置しているので、第１および第２の半田ボール３４、３８間のピッチを大きくすることが可能となるので、半導体チップ２１の接続パッド２３のピッチが小さい場合でも、接続部間の短絡を防止することができる。   In the above embodiment, since the first and second solder balls 34 and 38 on the upper and lower surfaces are arranged on the outer periphery of the semiconductor chip 21, the pitch between the first and second solder balls 34 and 38 is set. Therefore, even when the pitch of the connection pads 23 of the semiconductor chip 21 is small, a short circuit between the connection portions can be prevented.

なお、上記実施形態においては、半導体装置の上・下面に配列される第１および第２の半田ボール３４、３８を半導体チップ２１の外周部に１列だけ配列したものとしているが、複数列配列することもできる。また、半導体装置の上面側に配列する第２の半田ボール３８は、半導体チップ２１の外周部のみでなく、半導体チップ２１に対応する領域上にも、例えば、マトリクス状等の配列にして形成することができる。   In the above embodiment, the first and second solder balls 34 and 38 arranged on the upper and lower surfaces of the semiconductor device are arranged in one row on the outer peripheral portion of the semiconductor chip 21. You can also Further, the second solder balls 38 arranged on the upper surface side of the semiconductor device are formed not only on the outer peripheral portion of the semiconductor chip 21 but also on an area corresponding to the semiconductor chip 21 in an array such as a matrix. be able to.

次に、この半導体装置の製造方法の一例について説明する。まず、図２に示すように、紫外線透過性のガラス板、透明金属板、透明樹脂板等からなるベース板４１の上面に紫外線の照射により接着力が低下する接着層４２が設けられたものを用意する。そして、接着層４２の上面の所定の複数箇所にそれぞれ半導体チップ２１を構成する半導体基板２２の下面を接着する。半導体チップ２１の厚さは２０〜５０μｍ程度である。この場合、ベース板４１にダイシングにより分離された個々の半導体チップ２１を搭載する方法に替えて、ベース板４１に半導体ウエハを接着し、ブレード等により各半導体チップ２１が分離されるように半導体ウエハを切除するようにしてもよい。なお、以下の製造方法を説明する各図においては、中央部の半導体チップ２１の領域は、図１（Ａ）のＩB −ＩB 線に沿う断面を、また、その両側の半導体チップ２１の領域は図１（Ａ）のＩC −ＩC 線に沿う断面を示している。 Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 2, a base plate 41 made of an ultraviolet transmissive glass plate, a transparent metal plate, a transparent resin plate, or the like is provided with an adhesive layer 42 whose adhesive strength is reduced by irradiation of ultraviolet rays. prepare. Then, the lower surface of the semiconductor substrate 22 constituting the semiconductor chip 21 is bonded to a plurality of predetermined locations on the upper surface of the adhesive layer 42. The thickness of the semiconductor chip 21 is about 20 to 50 μm. In this case, instead of the method of mounting the individual semiconductor chips 21 separated by dicing on the base plate 41, the semiconductor wafer is bonded to the base plate 41 and the semiconductor chips 21 are separated by a blade or the like. May be excised. In the drawings for explaining the following manufacturing method, the region of the semiconductor chip 21 of the center portion, the cross section along the I B -I B line in FIG. 1 (A), also on both sides of the semiconductor chip 21 The region shows a cross section taken along the line I C -I C in FIG.

次に、複数の半導体チップ２１を含む接着層４２の上面にポリイミド系樹脂、エポキシ系樹脂、ＰＢＯ系樹脂等からなる絶縁膜２６をスピンコート法や印刷法等により塗布し、これを乾燥した後に、フォトレジストを塗布し、フォトリソグラフィー法により絶縁膜２６を図３に示すようにパターニングする。この場合、絶縁膜２６の上面は平坦であり、その半導体チップ２１の開口部２５に対応する部分には開口部２７が形成され、また中央部の半導体チップ２１の周囲における絶縁膜２６の所定の複数箇所にはスルーホール２８が形成されている。絶縁膜２６をパターニングした後、フォトレジストを剥離する。   Next, an insulating film 26 made of polyimide resin, epoxy resin, PBO resin, or the like is applied to the upper surface of the adhesive layer 42 including the plurality of semiconductor chips 21 by spin coating or printing, and dried. Then, a photoresist is applied, and the insulating film 26 is patterned as shown in FIG. 3 by photolithography. In this case, the upper surface of the insulating film 26 is flat, an opening 27 is formed in a portion corresponding to the opening 25 of the semiconductor chip 21, and a predetermined portion of the insulating film 26 around the semiconductor chip 21 in the central portion is formed. Through holes 28 are formed at a plurality of locations. After patterning the insulating film 26, the photoresist is peeled off.

次に、図４に示すように、スルーホール２８内および両開口部２５、２７を介して露出された接続パッド２３の上面を含む絶縁膜２６の上面に下地金属層４３を形成する。下地金属層４３は、例えば、スパッタにより形成された銅層のみであってもよく、またスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。   Next, as shown in FIG. 4, a base metal layer 43 is formed on the upper surface of the insulating film 26 including the upper surfaces of the connection pads 23 exposed in the through holes 28 and through the openings 25 and 27. The underlying metal layer 43 may be, for example, only a copper layer formed by sputtering, or may be a copper layer formed by sputtering on a thin film layer such as titanium formed by sputtering.

次に、下地金属層４３の上面にメッキレジスト膜４４をパターン形成する。この場合、第１および第２の再配線３２、３６形成領域に対応する部分におけるメッキレジスト膜４４には開口部４５が形成されている。次に、下地金属層４３をメッキ電流路として銅等の電解メッキを行うことにより、メッキレジスト膜４４の開口部４５内の下地金属層４３の上面に第１および第２の再配線３２、３６を形成する。   Next, a plating resist film 44 is patterned on the upper surface of the base metal layer 43. In this case, an opening 45 is formed in the plating resist film 44 in a portion corresponding to the region where the first and second rewirings 32 and 36 are formed. Next, the first and second rewirings 32 and 36 are formed on the upper surface of the base metal layer 43 in the opening 45 of the plating resist film 44 by performing electrolytic plating of copper or the like using the base metal layer 43 as a plating current path. Form.

これにより、第１の再配線３２は、半導体チップ２１の接続パッド２３に接続された部分からなるパッド部と、スルーホール２８上に配置されて第１の突起電極３３に一体的に接続された部分からなるパッド部と、両パッド部を接続する引き回し線とから構成され、第２の再配線３６は、半導体チップ２１の接続パッド２３に接続された部分からなるパッド部と、後述する第２の突起電極３７に接続される部分からなるパッド部と、両パッド部を接続する引き回し線とから構成される。次に、メッキレジスト膜４４を剥離する。   As a result, the first rewiring 32 is integrally connected to the first protruding electrode 33 disposed on the through hole 28 and the pad portion formed of the portion connected to the connection pad 23 of the semiconductor chip 21. The second rewiring 36 is composed of a pad portion formed of a portion connected to the connection pad 23 of the semiconductor chip 21 and a second portion to be described later. The pad portion is composed of a portion connected to the protruding electrode 37, and a lead line connecting the two pad portions. Next, the plating resist film 44 is peeled off.

第１の再配線３２の形成において、絶縁膜２６の開口部２７に対応するパッド部は、第１の突起電極３３に一体的に設けられるので、生産が、大変効率的である。しかし、第１の突起電極３３を構成する第１の再配線３２のパッド部の上部側は、メッキ時に窪んで形成される。もし、第１の突起電極３３の上部側を引き回し線と平坦になるように形成することを望むならば、図３において、絶縁膜２６にスルーホール２８を形成せず、半導体チップ２１の開口部２５に対応する部分には開口部２７のみを形成し、下地金属層４３を形成し、メッキレジスト膜４４をパターン形成し、下地金属層４３をメッキ電流路として銅等の電解メッキを行うことにより、第１および第２の再配線３２、３６を形成してから、絶縁膜２６にスルーホール２８を形成し（ベース板４１を剥がして行う）、メッキ等によりスルーホール２８内の第１の再配線３２のパッド部上に第１の突起電極３３を形成するようにしてもよい。   In the formation of the first rewiring 32, the pad portion corresponding to the opening 27 of the insulating film 26 is provided integrally with the first protruding electrode 33, so that the production is very efficient. However, the upper side of the pad portion of the first rewiring 32 constituting the first protruding electrode 33 is formed to be depressed during plating. If it is desired to form the upper side of the first protruding electrode 33 so as to be flat with the lead line, the through hole 28 is not formed in the insulating film 26 in FIG. In the portion corresponding to 25, only the opening 27 is formed, the base metal layer 43 is formed, the plating resist film 44 is patterned, and electrolytic plating such as copper is performed using the base metal layer 43 as a plating current path. After the first and second rewirings 32 and 36 are formed, the through hole 28 is formed in the insulating film 26 (performed by removing the base plate 41), and the first re-wiring in the through hole 28 is formed by plating or the like. The first protruding electrode 33 may be formed on the pad portion of the wiring 32.

次に、図５に示すように、第１および第２の再配線３２、３６を含む下地金属層４３の上面にメッキレジスト膜４６をパターン形成する。この場合、第２の再配線３６のパッド部に対応する部分におけるメッキレジスト膜４６には開口部４７が形成されている。次に、下地金属層４３をメッキ電流路として銅等の電解メッキを行うことにより、メッキレジスト膜４６の開口部４７内の第２の再配線３６のパッド部の上面に第２の突起電極３７を高さ１００〜１５０μｍ程度に形成する。次に、メッキレジスト膜４６を剥離する。   Next, as shown in FIG. 5, a plating resist film 46 is patterned on the upper surface of the base metal layer 43 including the first and second rewirings 32 and 36. In this case, an opening 47 is formed in the plating resist film 46 in a portion corresponding to the pad portion of the second rewiring 36. Next, the second protruding electrode 37 is formed on the upper surface of the pad portion of the second rewiring 36 in the opening 47 of the plating resist film 46 by performing electrolytic plating of copper or the like using the base metal layer 43 as a plating current path. Is formed to a height of about 100 to 150 μm. Next, the plating resist film 46 is peeled off.

次に、第１および第２の再配線３２、３６をマスクとして下地金属層４３の不要な部分をエッチングして除去する（この場合、マスクとなる第１および第２の再配線３２、３６も同時にエッチングされるが、下地金属層４３に比し厚さが厚いので、下地金属層４３がエッチングされた時点でエッチングをやめればよい）と、図６に示すように、第１および第２の再配線３２、３６下にのみ第１および第２の下地金属層３１、３５が残存される。   Next, unnecessary portions of the base metal layer 43 are removed by etching using the first and second rewirings 32 and 36 as a mask (in this case, the first and second rewirings 32 and 36 serving as masks are also removed). Etching is performed at the same time, but since the thickness is larger than that of the base metal layer 43, the etching should be stopped when the base metal layer 43 is etched). As shown in FIG. The first and second base metal layers 31 and 35 remain only under the rewirings 32 and 36.

ここで、スルーホール２８内に形成された第１の下地金属層３１および第１の再配線３２からなる第１の突起電極３３の高さは、半導体チップ２１の厚さ（２０〜５０μｍ程度）と絶縁膜２６の厚さ（例えば半導体チップ２１上で１０μｍ程度）との合計厚さ（３０〜６０μｍ程度）であり、第２の突起電極３７の高さ（１００〜１５０μｍ程度）よりも低くなっている。   Here, the height of the first protruding electrode 33 formed of the first base metal layer 31 and the first rewiring 32 formed in the through hole 28 is the thickness of the semiconductor chip 21 (about 20 to 50 μm). And the thickness of the insulating film 26 (for example, about 10 μm on the semiconductor chip 21), which is lower than the height of the second protruding electrode 37 (about 100 to 150 μm). ing.

次に、図７に示すように、第２の突起電極３７、第１および第２の再配線３２、３６を含む絶縁膜２６の上面にポリイミド系樹脂、エポキシ系樹脂、ＰＢＯ系樹脂等からなる絶縁膜３９をディスペンサ法、印刷法、トランスファモールド法等によりその厚さが第２の突起電極３７の高さよりもやや厚くなるように形成する。したがって、この状態では、第２の突起電極３７の上面は絶縁膜３９によって覆われている。   Next, as shown in FIG. 7, the upper surface of the insulating film 26 including the second protruding electrode 37 and the first and second rewirings 32 and 36 is made of polyimide resin, epoxy resin, PBO resin, or the like. The insulating film 39 is formed by a dispenser method, a printing method, a transfer mold method or the like so that its thickness is slightly larger than the height of the second protruding electrode 37. Therefore, in this state, the upper surface of the second protruding electrode 37 is covered with the insulating film 39.

次に、絶縁膜３９の上面側を適宜に研磨することにより、図８に示すように、第２の突起電極３７の上面を露出させる。次に、図９に示すように、第２の突起電極３７の上面に第２の半田ボール３８を形成する。第２の半田ボール３８の形成は、第２の半田ボール３８を吸着具で吸着して第２の突起電極３７上に載置し、リフローを行う方法、印刷等により第２の突起電極３７の上面に半田層を被着し、リフローにより第２の半田ボール３８を形成する方法等による。   Next, the upper surface side of the insulating film 39 is appropriately polished to expose the upper surface of the second protruding electrode 37 as shown in FIG. Next, as shown in FIG. 9, the second solder ball 38 is formed on the upper surface of the second protruding electrode 37. The second solder ball 38 is formed by adsorbing the second solder ball 38 with an adsorbing tool and placing the second solder ball 38 on the second protruding electrode 37, performing reflow, printing, or the like. For example, a solder layer is deposited on the upper surface and the second solder balls 38 are formed by reflow.

次に、ベース板４１の下面側から紫外線を照射し、接着層４２の接着力を低下させ、ベース板４１および接着層４２を剥がすと、図１０に示すようになる。この状態では、絶縁膜２６の下面および第１の突起電極３３の下面は半導体基板２２の下面と面一となっている。ここで、第１の突起電極３３の下面に、接着剤や異物等が付着している場合には、プラズマエッチング等を行って除去する。   Next, when ultraviolet rays are irradiated from the lower surface side of the base plate 41 to reduce the adhesive force of the adhesive layer 42 and the base plate 41 and the adhesive layer 42 are peeled off, the result is as shown in FIG. In this state, the lower surface of the insulating film 26 and the lower surface of the first protruding electrode 33 are flush with the lower surface of the semiconductor substrate 22. Here, when an adhesive or a foreign substance adheres to the lower surface of the first protruding electrode 33, it is removed by plasma etching or the like.

次に、図１１に示すように、第１の突起電極３３下に第１の半田ボール３４を形成する。次に、図１２に示すように、互いに隣接する半導体チップ２１、２１間において絶縁膜２６および絶縁膜３９を切断すると、図１（Ａ）、（Ｂ）、（Ｃ）に示す半導体装置が複数個得られる。   Next, as shown in FIG. 11, a first solder ball 34 is formed under the first protruding electrode 33. Next, as shown in FIG. 12, when the insulating film 26 and the insulating film 39 are cut between the adjacent semiconductor chips 21, 21, a plurality of semiconductor devices shown in FIGS. 1A, 1B, 1C are obtained. Can be obtained.

このようにして得られた半導体装置では、半導体チップ２１の接続パッド２３に接続される第１、第２の下地金属層３１、３５および第１、第２の再配線３２、３６をスパッタおよび電解メッキにより形成しているので、半導体チップ２１の接続パッド２３と第１および第２の再配線３２、３６との間の導電接続を確実とすることができる。   In the semiconductor device thus obtained, the first and second base metal layers 31 and 35 and the first and second rewirings 32 and 36 connected to the connection pads 23 of the semiconductor chip 21 are sputtered and electrolyzed. Since it is formed by plating, the conductive connection between the connection pad 23 of the semiconductor chip 21 and the first and second rewirings 32 and 36 can be ensured.

また、本実施形態の製造方法では、ベース板４１上の接着層４２上の所定の複数箇所にそれぞれ半導体チップ２１を接着して配置し、複数の半導体チップ２１に対して絶縁膜１６、３９、第１、第２の下地金属層３１、３５、第１、第２の再配線３２、３６、第１、第２の突起電極３３、３７および第１、第２の半田ボール３４、３８の形成を一括して行い、その後に分断して複数個の半導体装置を得ているので、製造工程を簡略化することができる。   Further, in the manufacturing method of the present embodiment, the semiconductor chip 21 is adhered and arranged at a plurality of predetermined positions on the adhesive layer 42 on the base plate 41, and the insulating films 16, 39, Formation of first and second base metal layers 31 and 35, first and second rewirings 32 and 36, first and second protruding electrodes 33 and 37, and first and second solder balls 34 and 38 Are performed in a lump and then divided into a plurality of semiconductor devices, so that the manufacturing process can be simplified.

また、ベース板４１と共に複数の半導体チップ２１を搬送することができるので、これによっても製造工程を簡略化することができる。さらに、ベース板４１の外形寸法を一定にすると、製造すべき半導体装置の外形寸法に関係なく、搬送系を共有化することができる。   Moreover, since the several semiconductor chip 21 can be conveyed with the base plate 41, a manufacturing process can also be simplified by this. Furthermore, if the outer dimensions of the base plate 41 are made constant, the transport system can be shared regardless of the outer dimensions of the semiconductor device to be manufactured.

なお、上記実施形態では、例えば図９に示すように、ベース板４１の上面全体に接着層４２を設けた場合について説明したが、これに限らず、例えば図１３に示す他の製造方法のように、半導体チップ２１の半導体基板２２の下面のみを接着層４２を介してベース板４１上に接着するようにしてもよい。ただし、この場合、ベース板４１および接着層４２を剥がすと、絶縁膜２６の下面および第１の突起電極３３の下面が半導体基板２２の下面から突出するので、実装時の必要性に応じてこれらの突出部を研磨して除去してもよい。また、接着層４２の代わりに、ダイシングテープのように引き延ばして半導体基板２２等から剥離するものを用いてもよい。   In the above-described embodiment, the case where the adhesive layer 42 is provided on the entire upper surface of the base plate 41 as shown in FIG. 9 is described. However, the present invention is not limited to this, and other manufacturing methods shown in FIG. In addition, only the lower surface of the semiconductor substrate 22 of the semiconductor chip 21 may be bonded onto the base plate 41 via the adhesive layer 42. However, in this case, when the base plate 41 and the adhesive layer 42 are peeled off, the lower surface of the insulating film 26 and the lower surface of the first protruding electrode 33 protrude from the lower surface of the semiconductor substrate 22. You may grind | polish and remove the protrusion part. Further, instead of the adhesive layer 42, a material that is stretched like a dicing tape and peeled from the semiconductor substrate 22 or the like may be used.

また、上記実施形態では、図１（Ａ）、（Ｂ）、（Ｃ）に示すように、第１の再配線３２のパッド部下に第１の突起電極３３を形成し、第２の再配線３６のパッド部上に第２の突起電極３７を形成した場合について説明したが、これに限定されるものではない。例えば、図１４に示すこの発明の他の実施形態のように、第１の再配線３２のパッド部上に第２の突起電極３７を形成するようにしてもよい。この場合、第１の突起電極３３と第２の突起電極３７は同じ位置に形成されるので、図１５に図示するように、半田ボール３４を半導体装置の一面側、例えば、第１の突起電極３３側上のみに形成しておけば、他面側の第２の突起電極３７上に第２の半田ボール３８を形成せずとも、この上に同様な半導体装置を積層することもできる。   Moreover, in the said embodiment, as shown to FIG. 1 (A), (B), (C), the 1st protruding electrode 33 is formed under the pad part of the 1st rewiring 32, and 2nd rewiring is carried out. Although the case where the second protruding electrode 37 is formed on the pad portion 36 has been described, the present invention is not limited to this. For example, the second protruding electrode 37 may be formed on the pad portion of the first rewiring 32 as in another embodiment of the present invention shown in FIG. In this case, since the first protruding electrode 33 and the second protruding electrode 37 are formed at the same position, as shown in FIG. 15, the solder ball 34 is placed on one side of the semiconductor device, for example, the first protruding electrode. If it is formed only on the 33 side, a similar semiconductor device can be laminated on the second protruding electrode 37 on the other side without forming the second solder ball 38.

さらに、図示していないが、第１の突起電極３３下に半田ボールを形成せずに、第２の突起電極３７上にのみ半田ボールを形成するようにしてもよい。また、図１４および図１５に図示された構造の変形例として、全ての再配線に第１、第２の突起電極３３、３７を形成するのではなく、一部は、図１（Ｃ）に示すような、第２の再配線３６を形成し、そのパッド部上に第２の突起電極３７を有するものとしたり、また、第１の再配線３２を形成し、図１（Ｂ）に示すような、第１の突起電極３３のみを有するようにもよい。   Further, although not shown, a solder ball may be formed only on the second protruding electrode 37 without forming a solder ball under the first protruding electrode 33. Further, as a modification of the structure shown in FIGS. 14 and 15, the first and second protruding electrodes 33 and 37 are not formed on all the rewirings, but a part thereof is shown in FIG. As shown in FIG. 1B, a second rewiring 36 is formed and a second protruding electrode 37 is formed on the pad portion, or a first rewiring 32 is formed. Only the first protruding electrode 33 may be provided.

次に、図１６は複数の例えば３個の半導体装置を回路基板上に積層して実装した場合の一例の断面図を示したものである。この例では、第１番目の半導体装置５１は、その半田ボール３４が回路基板５４上の接続端子５５に接合されていることにより、回路基板５４上に搭載されている。第２番目の半導体装置５２は、その半田ボール３４が第１番目の半導体装置５１の突起電極３７上に接合されていることにより、第１番目の半導体装置５１上に搭載されている。第３番目の半導体装置５３は、その半田ボール３４が第２番目の半導体装置５２の突起電極３７上に接合されていることにより、第２番目の半導体装置５２上に搭載されている。   Next, FIG. 16 shows a cross-sectional view of an example when a plurality of, for example, three semiconductor devices are stacked and mounted on a circuit board. In this example, the first semiconductor device 51 is mounted on the circuit board 54 by the solder balls 34 being bonded to the connection terminals 55 on the circuit board 54. The second semiconductor device 52 is mounted on the first semiconductor device 51 by bonding the solder balls 34 onto the protruding electrodes 37 of the first semiconductor device 51. The third semiconductor device 53 is mounted on the second semiconductor device 52 by the solder ball 34 being bonded onto the protruding electrode 37 of the second semiconductor device 52.

この場合、一番上の第３番目の半導体装置５３は、例えば、図１（Ｂ）に示すような第１の再配線３２および第１の突起電極３３のみを有し、第２の再配線３６および第２の突起電極３７を備えていないものからなっている。なお、回路基板５４上に４個以上の半導体装置を積層して実装する場合には、当然のことながら、第３番目の半導体装置５３は第２の突起電極３７を備えている。   In this case, the uppermost third semiconductor device 53 has only the first rewiring 32 and the first protruding electrode 33 as shown in FIG. 1B, for example, and the second rewiring. 36 and the second protruding electrode 37 are not provided. In the case where four or more semiconductor devices are stacked and mounted on the circuit board 54, the third semiconductor device 53 is provided with the second protruding electrode 37 as a matter of course.

また、第１番目と第２番目の半導体装置５１、５２は、第３番目の半導体装置５３への中継端子の機能のみを有する突起電極を数本有する。すなわち、図１６において左側に示すように、第１の突起電極３３と第２の突起電極３７とは、当該半導体装置に内蔵された半導体チップ２１のいずれの接続パッド２３にも接続されていないフローティング状態の下地金属層５６および中継パッド部５７を介して接続された構造となっている。この場合、図１６において、このような中継端子の機能を有する突起電極に接続される回路基板５４の接続端子５５（図１６における左側）には、第３番目の半導体装置５３のセレクト信号、リセット信号等の制御信号や、場合により駆動電圧が供給される。   In addition, the first and second semiconductor devices 51 and 52 have several protruding electrodes having only a function of a relay terminal to the third semiconductor device 53. That is, as shown on the left side in FIG. 16, the first protruding electrode 33 and the second protruding electrode 37 are not connected to any connection pad 23 of the semiconductor chip 21 incorporated in the semiconductor device. The structure is connected via the underlying metal layer 56 and the relay pad portion 57 in the state. In this case, in FIG. 16, the select signal and reset of the third semiconductor device 53 are connected to the connection terminal 55 (the left side in FIG. 16) of the circuit board 54 connected to the protruding electrode having the function of the relay terminal. A control signal such as a signal, and in some cases a drive voltage is supplied.

また、図１７に示す他の例のように、回路基板５４の左側の接続端子５５がＧＮＤ端子である場合には、第１番目と第２番目の半導体装置５１、５２において、左側の第１の再配線３２のパッド部上に第２の突起電極３７を設けるようにしてもよい。ただし、この場合、第３番目の半導体装置５３は、例えば、図１（Ｃ）に示すような第２の再配線３６および第２の突起電極３７のみを有し、第１の再配線３２および第１の突起電極３３を備えていないものからなっている。この場合、第２番目の半導体装置５２の突起電極２７と第３番目の突起電極２７とを接続するための半田ボール３４は、第２番目の半導体装置５２の突起電極２７上または第３番目の半導体装置５３の突起電極２７下に予め形成しておく。   Further, as in the other example shown in FIG. 17, when the left connection terminal 55 of the circuit board 54 is a GND terminal, the first and second semiconductor devices 51 and 52 have the left first A second protruding electrode 37 may be provided on the pad portion of the rewiring 32. However, in this case, the third semiconductor device 53 has only the second rewiring 36 and the second protruding electrode 37 as shown in FIG. 1C, for example, and the first rewiring 32 and The first protrusion electrode 33 is not provided. In this case, the solder ball 34 for connecting the protruding electrode 27 of the second semiconductor device 52 and the third protruding electrode 27 is on the protruding electrode 27 of the second semiconductor device 52 or the third one. It is formed in advance under the bump electrode 27 of the semiconductor device 53.

さらに、例えば、図１７において、第１番目の半導体装置５１の第１の突起電極３３下および第２の突起電極３７上にそれぞれ半田ボール３４を予め形成しておくようにしてもよい。この場合、実装形態等に応じて、回路基板５４の接続端子５５に接合される半田ボール３４の高さをやや高くし、第２番目の半導体装置５２の第１の突起電極３３に接合される半田ボール３４の高さをやや低くするようにしてもよい。   Further, for example, in FIG. 17, solder balls 34 may be formed in advance under the first protruding electrode 33 and the second protruding electrode 37 of the first semiconductor device 51, respectively. In this case, the height of the solder ball 34 bonded to the connection terminal 55 of the circuit board 54 is slightly increased according to the mounting form and the like, and is bonded to the first protruding electrode 33 of the second semiconductor device 52. The height of the solder ball 34 may be slightly lowered.

なお、図１（Ａ）において、第１の突起電極３３を半導体チップ２１の相対向する一対の辺に配列し、第２の突起電極３７を半導体チップ２１の相対向する他の一対の辺に配列したものとしているが、第１の突起電極３３および第２の突起電極３７を半導体チップ２１の隣接する辺に配列したり、全ての辺に配列することも可能である。   In FIG. 1A, the first protruding electrodes 33 are arranged on a pair of opposite sides of the semiconductor chip 21, and the second protruding electrodes 37 are arranged on the other pair of opposite sides of the semiconductor chip 21. Although the arrangement is such that the first protruding electrode 33 and the second protruding electrode 37 are arranged on adjacent sides of the semiconductor chip 21 or arranged on all sides.

また、機器への実装の都合で、半導体装置を細長状にするために、第１の突起電極３３および第２の突起電極３７を一対の辺にのみ配列し、他の辺には配列しないようにしたり、あるいはボンディング時に各突起電極にかかる荷重を均一にするため、各半導体装置に内蔵される半導体チップ２１のいずれの接続パッド２３にも接続されない、あるいは他の突起電極と共通の接続パッドに接続されるダミーの突起電極を形成してもよい。   Further, for the convenience of mounting on equipment, in order to make the semiconductor device elongated, the first protruding electrode 33 and the second protruding electrode 37 are arranged only on a pair of sides and not on the other sides. In order to make the load applied to each protruding electrode uniform during bonding, it is not connected to any connection pad 23 of the semiconductor chip 21 incorporated in each semiconductor device, or is connected to a common connection pad with other protruding electrodes A dummy protruding electrode to be connected may be formed.

さらに、各半導体装置に内蔵される半導体チップ２１はその底面が露出された状態で第１の突起電極３３に第１の半田ボール３４を接合したが、第１の半田ボール３４を接合する前に半導体チップ２１の底面を絶縁膜（封止材）で被覆し、該絶縁膜の各第１の突起電極３３と対応する領域にスルーホールを形成し、必要に応じ、該スルーホール内にメッキをした上、第１の半田ボール３４を接合してもよく、本発明の趣旨を逸脱しない範囲内で適宜変形することが可能である。   Further, the first solder ball 34 is bonded to the first protruding electrode 33 with the bottom surface of the semiconductor chip 21 incorporated in each semiconductor device exposed, but before the first solder ball 34 is bonded. The bottom surface of the semiconductor chip 21 is covered with an insulating film (sealing material), a through hole is formed in a region corresponding to each first protruding electrode 33 of the insulating film, and plating is performed in the through hole as necessary. In addition, the first solder balls 34 may be joined and can be appropriately modified without departing from the spirit of the present invention.

（Ａ）はこの発明の一実施形態としての半導体装置の拡大平面図、（Ｂ）はそのＩB −ＩB に沿う拡大断面図、（Ｃ）はそのＩC −ＩC に沿う拡大断面図。(A) is an enlarged plan view of a semiconductor device as an embodiment of the present invention, (B) is an enlarged sectional view taken along the I B -I B, (C) is an enlarged sectional view taken along the I C -I C . 図１に示す半導体装置の製造方法の一例において、当初の製造工程の断面図。Sectional drawing of the initial manufacturing process in an example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図３に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図４に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図５に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図６に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図７に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図８に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図９に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１０に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１１に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１に示す半導体装置の製造方法の他の例を説明するために示す断面図。Sectional drawing shown in order to demonstrate the other example of the manufacturing method of the semiconductor device shown in FIG. この発明の他の実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as other Embodiment of this invention. この発明のさらに他の実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as further another embodiment of this invention. 複数の半導体装置を回路基板上に積層して実装した場合の一例の断面図。Sectional drawing of an example at the time of laminating | stacking and mounting a some semiconductor device on a circuit board. 複数の半導体装置を回路基板上に積層して実装した場合の他の例の断面図。Sectional drawing of the other example at the time of laminating | stacking and mounting a several semiconductor device on a circuit board. 従来の半導体装置の一例の断面図。Sectional drawing of an example of the conventional semiconductor device.

符号の説明Explanation of symbols

２１ 半導体チップ
２２ 半導体基板
２３ 接続パッド
２４ 絶縁膜
２６ 絶縁膜
２８ スルーホール
３１ 第１の下地金属層
３２ 第１の再配線
３３ 突起電極
３４ 第１の半田ボール
３５ 第２の下地金属層
３６ 第２の再配線
３７ 第２の突起電極
３８ 第２の半田ボール
３９ 絶縁膜
４１ ベース板
４２ 接着層 DESCRIPTION OF SYMBOLS 21 Semiconductor chip 22 Semiconductor substrate 23 Connection pad 24 Insulating film 26 Insulating film 28 Through hole 31 1st base metal layer 32 1st rewiring 33 Projection electrode 34 1st solder ball 35 2nd base metal layer 36 2nd Redistribution of wiring 37 Second protruding electrode 38 Second solder ball 39 Insulating film 41 Base plate 42 Adhesive layer

Claims (10)

一面上に接続パッドを有する半導体チップと、該半導体チップの一面および周側面を覆うように設けられた絶縁膜と、該絶縁膜の上面に前記半導体チップの接続パッドに接続されて設けられ、前記半導体チップの周側面より外側に配置されたパッド部を有する第１および第２の再配線と、前記第１の再配線のパッド部に前記絶縁膜に形成された開口部を介して接続された第１の突起電極と、前記第２の再配線のパッド部に接続されて設けられた第２の突起電極とを備えていることを特徴とする半導体装置。   A semiconductor chip having a connection pad on one surface; an insulating film provided so as to cover one surface and a peripheral side surface of the semiconductor chip; and an upper surface of the insulating film provided to be connected to the connection pad of the semiconductor chip, The first and second rewirings having pad portions arranged outside the peripheral side surface of the semiconductor chip are connected to the pad portions of the first rewiring through openings formed in the insulating film. A semiconductor device comprising: a first protruding electrode; and a second protruding electrode connected to the pad portion of the second rewiring. 請求項１に記載の発明において、前記第１の再配線のパッド部上には第２の突起電極が設けられていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein a second protruding electrode is provided on the pad portion of the first rewiring. 請求項１に記載の発明において、前記第２の再配線のパッド部上には第１の突起電極が設けられていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein a first protruding electrode is provided on a pad portion of the second rewiring. 請求項１に記載の発明において、前記絶縁膜上に前記第２の突起電極の周囲を覆う第２の絶縁膜が形成されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein a second insulating film that covers the periphery of the second protruding electrode is formed on the insulating film. 請求項１に記載の発明において、さらに、前記接続パッドに接続されない突起電極を有することを特徴とする半導体装置。   2. The semiconductor device according to claim 1, further comprising a protruding electrode that is not connected to the connection pad. 請求項１〜５のいずれかに記載の半導体装置上に同種または異種の半導体装置が１つ以上搭載されていることを特徴とする半導体装置。   6. A semiconductor device comprising one or more semiconductor devices of the same type or different types mounted on the semiconductor device according to claim 1. 一面上に接続パッドを有する複数の半導体チップをベース板に固着する工程と、
前記複数の半導体チップを含む前記ベース板上に絶縁膜を形成する工程と、
前記各半導体チップの周側面より外側における前記絶縁膜に開口部を形成する工程と、
前記絶縁膜の上面に、前記各半導体チップの接続パッドに接続されて設けられ、前記絶縁膜の開口部に対応するパッド部に第１の突起電極が接続された第１の再配線、および前記各半導体チップの接続パッドに接続されて設けられ、且つ、前記各半導体チップの周側面より外側にパッド部を有する第２の再配線を形成する工程と、
前記第２の再配線のパッド部上に第２の突起電極を形成する工程と、
前記各組の半導体チップ間における前記両絶縁膜を切断して前記各半導体チップの周囲に前記第１および第２の突起電極が形成された半導体装置を複数個得る工程とを有することを特徴とする半導体装置の製造方法。 Fixing a plurality of semiconductor chips having connection pads on one surface to a base plate;
Forming an insulating film on the base plate including the plurality of semiconductor chips;
Forming an opening in the insulating film outside the peripheral side surface of each semiconductor chip;
A first rewiring provided on the upper surface of the insulating film, connected to a connection pad of each semiconductor chip, and having a first protruding electrode connected to a pad portion corresponding to an opening of the insulating film; and Forming a second rewiring provided to be connected to a connection pad of each semiconductor chip and having a pad portion outside the peripheral side surface of each semiconductor chip;
Forming a second protruding electrode on the pad portion of the second rewiring;
Cutting the both insulating films between the semiconductor chips of each set to obtain a plurality of semiconductor devices in which the first and second protruding electrodes are formed around the semiconductor chips. A method for manufacturing a semiconductor device. 請求項７に記載の発明において、前記第１の突起電極を前記再配線と同一工程で形成することを特徴とする半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, wherein the first protruding electrode is formed in the same step as the rewiring. 請求項７に記載の発明において、前記第１の突起電極を前記再配線の後工程で形成することを特徴とする半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, wherein the first protruding electrode is formed in a subsequent process of the rewiring. 請求項７に記載の発明において、さらに、前記絶縁膜上に前記突起電極の周囲を覆う第２の絶縁膜を形成する工程を有することを特徴とする半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming a second insulating film covering the periphery of the protruding electrode on the insulating film.
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JP2012084841A (en) * 2010-10-12 2012-04-26 Headway Technologies Inc Stacked chip package and method of manufacturing the same
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JP2008311599A (en) * 2007-06-18 2008-12-25 Hynix Semiconductor Inc Molded reconfigured wafer, stack package using the same, and method for manufacturing the stack package
JP2012253392A (en) * 2007-06-18 2012-12-20 Sk Hynix Inc Stack package manufactured using molded reconfigured wafer, and method for manufacturing the same
JP2012256951A (en) * 2007-07-27 2012-12-27 Sk Hynix Inc Semiconductor package, laminated wafer level package having the same and laminated wafer level package manufacturing method
US8541887B2 (en) 2010-09-03 2013-09-24 Headway Technologies, Inc. Layered chip package and method of manufacturing same
JP2012080067A (en) * 2010-10-01 2012-04-19 Headway Technologies Inc Method of manufacturing stacked chip package
US8441112B2 (en) 2010-10-01 2013-05-14 Headway Technologies, Inc. Method of manufacturing layered chip package
JP2012084841A (en) * 2010-10-12 2012-04-26 Headway Technologies Inc Stacked chip package and method of manufacturing the same
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8652877B2 (en) 2010-12-06 2014-02-18 Headway Technologies, Inc. Method of manufacturing layered chip package
US9397057B2 (en) 2014-06-02 2016-07-19 Kabushiki Kaisha Toshiba Plurality of semiconductor devices in resin with a via

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