JP2007035989A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2007035989A
JP2007035989A JP2005218290A JP2005218290A JP2007035989A JP 2007035989 A JP2007035989 A JP 2007035989A JP 2005218290 A JP2005218290 A JP 2005218290A JP 2005218290 A JP2005218290 A JP 2005218290A JP 2007035989 A JP2007035989 A JP 2007035989A
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layer
semiconductor
semiconductor device
insulating
semiconductor structure
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JP4913372B2 (en
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Osamu Okada
修 岡田
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Casio Computer Co Ltd
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

<P>PROBLEM TO BE SOLVED: To set the bottom surface of an SOI substrate to a grounding potential in a semiconductor device wherein a semiconductor configuration having the SOI substrate is provided on a base plate. <P>SOLUTION: The bottom surface of a silicon substrate 7 of an SOI substrate 6 of a semiconductor configuration 3 is connected via protruding electrodes 5 with a grounding layer 2 provided on the top surface of a base plate 1. The grounding layer 2 is connected with an upper-layer wiring 25 for grounding, via a continuity portion 32 interposed between the upper and lower sides of the semiconductor configuration 3 which is provided in a through-hole 31 provided in an upper-layer insulating film 22, an insulating layer 21, the grounding layer 2, and the base plate 1. Consequently, the bottom surface of the silicon substrate 7 of the SOI substrate 6 of the semiconductor configuration 3 is set to the grounding potential. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は半導体装置に関する。   The present invention relates to a semiconductor device.

従来の半導体装置には、半導体基板のサイズ外にも接続端子としての半田ボールを備えるため、上面に複数の接続パッドを有する半導体基板の下面をベース板の上面に絶縁性接着層を介して接着し、半導体基板の上面およびその周囲におけるベース板の上面に絶縁層を設け、絶縁層の上面に上層配線を半導体基板の接続パッドに接続させて設け、上層配線の接続パッド部を除く部分をオーバーコート膜で覆い、上層配線の接続パッド部上に半田ボールを設けたものがある（例えば、特許文献１参照）。   Since conventional semiconductor devices include solder balls as connection terminals in addition to the size of the semiconductor substrate, the lower surface of the semiconductor substrate having a plurality of connection pads on the upper surface is bonded to the upper surface of the base plate via an insulating adhesive layer. Then, an insulating layer is provided on the upper surface of the semiconductor substrate and the upper surface of the base plate around the semiconductor substrate, and the upper layer wiring is provided on the upper surface of the insulating layer so as to be connected to the connection pads of the semiconductor substrate. There is one in which a solder ball is provided on a connection pad portion of an upper wiring (see, for example, Patent Document 1).

特開２００４−７２０３２号公報JP 2004-72032 A

ところで、上記のような半導体装置において、上面に複数の接続パッドを有する半導体基板の代わりに、ＳＯＩ(silicon on insulator)と呼ばれるもので、半導体基板上に絶縁膜を設け、絶縁膜上に薄膜トランジスタを形成してなるＳＯＩ集積回路部を設けた構造のＳＯＩ基板を用いることが考えられる。この場合、半導体基板の電位の安定化を図るために、半導体基板の下面はグランド電位とする必要がある。   By the way, in the semiconductor device as described above, instead of a semiconductor substrate having a plurality of connection pads on the upper surface, it is called SOI (silicon on insulator), an insulating film is provided on the semiconductor substrate, and a thin film transistor is provided on the insulating film. It is conceivable to use an SOI substrate having a structure in which a formed SOI integrated circuit portion is provided. In this case, in order to stabilize the potential of the semiconductor substrate, the lower surface of the semiconductor substrate needs to be a ground potential.

しかしながら、上記のような半導体装置では、半導体基板の下面をベース板の上面に絶縁性接着層を介して接着しているだけであるので、ＳＯＩ基板を用いる場合には、その半導体基板の下面をグランド電位とするための技術を開発する必要がある。   However, in the semiconductor device as described above, since the lower surface of the semiconductor substrate is merely bonded to the upper surface of the base plate via an insulating adhesive layer, when the SOI substrate is used, the lower surface of the semiconductor substrate is It is necessary to develop a technology for achieving the ground potential.

そこで、この発明は、ＳＯＩ基板のようにグランド電位にする必要がある半導体基板を確実にグランド電位に接続することができる半導体装置を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can reliably connect a semiconductor substrate that needs to be at a ground potential, such as an SOI substrate, to the ground potential.

この発明は、上記目的を達成するため、少なくとも表面にグランド接続用導電層を有するベース部材に、一面に集積回路が形成された半導体構成体の他面を接着層により接着すると共に、前記グランド接続用導電層と前記半導体構成体の他面との間に両者を電気的に接続する上下導通部材を介在したことを特徴とするものである。   In order to achieve the above-described object, the present invention provides a base member having a ground connection conductive layer on at least a surface thereof, wherein the other surface of the semiconductor structure having an integrated circuit formed thereon is adhered by an adhesive layer, and the ground connection is performed. A vertical conductive member for electrically connecting the conductive layer and the other surface of the semiconductor structure is interposed.

この発明によれば、一面に集積回路が形成された半導体構成体の他面とベース部材のグランド接続用導電層との間に両者を電気的に接続する上下導通部材を介在させているので、半導体構成体のＳＯＩ基板のようにグランド電位にする必要がある半導体基板を確実にグランド電位に接続することができる。   According to this invention, since the vertical conduction member that electrically connects both is interposed between the other surface of the semiconductor structure in which the integrated circuit is formed on one surface and the ground connection conductive layer of the base member, A semiconductor substrate that needs to be at a ground potential, such as an SOI substrate of a semiconductor structure, can be reliably connected to the ground potential.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示す。この半導体装置は平面方形状のベース板１を備えている。ベース板１は、例えば、通常、プリント基板用として用いられる材料であればよく、一例を挙げれば、ガラス布、ガラス繊維等からなる基材にエポキシ系樹脂やポリイミド系樹脂等の熱硬化性樹脂を含浸させたものからなっている。ベース板１の上面には銅箔からなるべたパターンのグランド層（グランド接続用導電層）２が設けられている。 (First embodiment)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. This semiconductor device includes a base plate 1 having a planar square shape. The base plate 1 may be, for example, a material that is usually used for a printed circuit board. For example, a thermosetting resin such as an epoxy resin or a polyimide resin is used for a base material made of glass cloth, glass fiber, or the like. It is made of impregnated. A ground layer (ground connection conductive layer) 2 made of a copper foil is provided on the upper surface of the base plate 1.

グランド層２の上面には、ベース板１のサイズよりもある程度小さいサイズの平面方形状の半導体構成体３の下面がダイボンド材からなる絶縁性接着層４を介して接着されている。この場合、半導体構成体３の下側におけるグランド層２の上面の所定の複数箇所には金属ペーストや銅等からなる突起電極〔上下導通部材）５が設けられている。突起電極５は、絶縁性接着層４を貫通して半導体構成体３の下面に当接されている。   On the upper surface of the ground layer 2, the lower surface of the planar rectangular semiconductor structure 3 having a size somewhat smaller than the size of the base plate 1 is bonded via an insulating adhesive layer 4 made of a die bond material. In this case, projecting electrodes (vertical conducting members) 5 made of a metal paste, copper, or the like are provided at predetermined plural positions on the upper surface of the ground layer 2 below the semiconductor structure 3. The protruding electrode 5 penetrates the insulating adhesive layer 4 and is in contact with the lower surface of the semiconductor structure 3.

半導体構成体３は、一般的にはＣＳＰ(chip size package)と呼ばれるものであり、ＳＯＩ基板６を備えている。ＳＯＩ基板６は、平面方形状のシリコン基板（半導体基板）７の上面に酸化シリコン等からなる絶縁膜８が設けられ、絶縁膜８の上面に薄膜トランジスタを形成してなるＳＯＩ集積回路部９が設けられた構造となっている。この場合、ＳＯＩ集積回路部９の薄膜トランジスタのソース領域またはドレイン領域の一方は、絶縁膜８に設けられた導通部（図示せず）を介してシリコン基板７に接続されている。また、シリコン基板７の下面は、絶縁性接着層４を介してグランド層２の上面に接着され、且つ、突起電極（上下導通部材）５を介してグランド層２の上面に電気的に接続されている。   The semiconductor structure 3 is generally called a CSP (chip size package) and includes an SOI substrate 6. The SOI substrate 6 is provided with an insulating film 8 made of silicon oxide or the like on the upper surface of a planar rectangular silicon substrate (semiconductor substrate) 7, and an SOI integrated circuit portion 9 formed by forming a thin film transistor on the upper surface of the insulating film 8. It has a structured. In this case, one of the source region and the drain region of the thin film transistor of the SOI integrated circuit portion 9 is connected to the silicon substrate 7 via a conduction portion (not shown) provided in the insulating film 8. Further, the lower surface of the silicon substrate 7 is bonded to the upper surface of the ground layer 2 through the insulating adhesive layer 4 and is electrically connected to the upper surface of the ground layer 2 through the protruding electrodes (vertical conducting members) 5. ing.

ＳＯＩ集積回路部９の上面周辺部にはアルミニウム系金属等からなる複数の接続パッド１０がＳＯＩ集積回路部９に接続されて設けられている。接続パッド１０の上面中央部を除くＳＯＩ集積回路部９の上面には酸化シリコン等からなる絶縁膜１１が設けられ、接続パッド１０の上面中央部は絶縁膜１１に設けられた開口部１２を介して露出されている。   A plurality of connection pads 10 made of an aluminum-based metal or the like are provided on the periphery of the upper surface of the SOI integrated circuit portion 9 so as to connect to the SOI integrated circuit portion 9. An insulating film 11 made of silicon oxide or the like is provided on the upper surface of the SOI integrated circuit portion 9 excluding the central portion of the upper surface of the connection pad 10, and the central portion of the upper surface of the connection pad 10 is provided through an opening 12 provided in the insulating film 11. Is exposed.

絶縁膜１１の上面にはポリイミド系樹脂等からなる保護膜１３が設けられている。この場合、絶縁膜１１の開口部１２に対応する部分における保護膜１３には開口部１４が設けられている。保護膜１３の上面には銅等からなる下地金属層１５が設けられている。下地金属層１５の上面全体には銅からなる配線１６が設けられている。下地金属層１５を含む配線１６の一端部は、保護膜１３および絶縁膜１１の開口部１４、１２を介して接続パッド１０に接続されている。   A protective film 13 made of polyimide resin or the like is provided on the upper surface of the insulating film 11. In this case, an opening 14 is provided in the protective film 13 in a portion corresponding to the opening 12 of the insulating film 11. A base metal layer 15 made of copper or the like is provided on the upper surface of the protective film 13. A wiring 16 made of copper is provided on the entire upper surface of the base metal layer 15. One end of the wiring 16 including the base metal layer 15 is connected to the connection pad 10 via the protective film 13 and the openings 14 and 12 of the insulating film 11.

配線１６の接続パッド部上面には銅からなる柱状電極（外部接続用電極）１７が設けられている。配線１６を含む保護膜１３の上面にはエポキシ系樹脂等からなる封止膜１８がその上面が柱状電極１７の上面と面一となるように設けられている。   A columnar electrode (external connection electrode) 17 made of copper is provided on the upper surface of the connection pad portion of the wiring 16. A sealing film 18 made of an epoxy resin or the like is provided on the upper surface of the protective film 13 including the wiring 16 so that the upper surface is flush with the upper surface of the columnar electrode 17.

半導体構成体３の周囲におけるグランド層２の上面には方形枠状の絶縁層２１が設けられている。絶縁層２１は、例えば、ポリイミド系樹脂、ポリベンゾオキサゾール（ＰＢＯ）、ベンゾシクロブテン（ＢＣＢ）、エポキシ系樹脂等の熱硬化性樹脂中にシリカフィラー等の無機材料からなる補強材を分散させたものからなっている。   A rectangular frame-like insulating layer 21 is provided on the upper surface of the ground layer 2 around the semiconductor structure 3. For the insulating layer 21, for example, a reinforcing material made of an inorganic material such as silica filler is dispersed in a thermosetting resin such as polyimide resin, polybenzoxazole (PBO), benzocyclobutene (BCB), or epoxy resin. It consists of things.

半導体構成体３および絶縁層２１の上面には上層絶縁膜２２がその上面を平坦とされて設けられている。上層絶縁膜２２は、例えば、ガラス布、ガラス繊維、フッ素ポリマー等の３次元ポリマー等からなる基材にエポキシ系樹脂やポリイミド系樹脂等の熱硬化性樹脂を含浸させたもの、あるいは、エポキシ系樹脂等の熱硬化性樹脂のみからなっている。半導体構成体３の柱状電極１７の上面中央部に対応する部分における上層絶縁膜２２には開口部２３が設けられている。   An upper insulating film 22 is provided on the upper surfaces of the semiconductor structure 3 and the insulating layer 21 with the upper surface being flat. The upper insulating film 22 is, for example, a material in which a base material made of glass cloth, glass fiber, a three-dimensional polymer such as a fluoropolymer is impregnated with a thermosetting resin such as an epoxy resin or a polyimide resin, or an epoxy resin It consists only of thermosetting resin such as resin. An opening 23 is provided in the upper insulating film 22 in a portion corresponding to the center of the upper surface of the columnar electrode 17 of the semiconductor structure 3.

上層絶縁膜２２の上面には銅等からなる上層下地金属層２４が設けられている。上層下地金属層２４の上面全体には銅からなる上層配線２５が設けられている。上層下地金属層２４を含む上層配線２５の一端部は、上層絶縁膜２２の開口部２３を介して半導体構成体３の柱状電極１７の上面に接続されている。   An upper base metal layer 24 made of copper or the like is provided on the upper surface of the upper insulating film 22. An upper layer wiring 25 made of copper is provided on the entire upper surface of the upper base metal layer 24. One end of the upper wiring 25 including the upper base metal layer 24 is connected to the upper surface of the columnar electrode 17 of the semiconductor structure 3 through the opening 23 of the upper insulating film 22.

上層配線２５を含む上層絶縁膜２２の上面にはソルダーレジスト等からなる上層オーバーコート膜２６が設けられている。上層配線２５の接続パッド部に対応する部分における上層オーバーコート膜２６には開口部２７が設けられている。開口部２７内およびその上方には半田ボール２８が上層配線２５の接続パッド部に接続されて設けられている。複数の半田ボール２８は、上層オーバーコート膜２６上にマトリクス状に配置されている。   An upper overcoat film 26 made of solder resist or the like is provided on the upper surface of the upper insulating film 22 including the upper wiring 25. An opening 27 is provided in the upper overcoat film 26 in a portion corresponding to the connection pad portion of the upper wiring 25. Solder balls 28 are provided in the opening 27 and above the opening 27 so as to be connected to the connection pad portion of the upper layer wiring 25. The plurality of solder balls 28 are arranged in a matrix on the upper overcoat film 26.

上層絶縁膜２２、絶縁層２１、グランド層２およびベース板１の所定の箇所には貫通孔３１が設けられている。貫通孔３１の内壁面には銅等からなる下地金属層３２ａと銅層３２ｂとからなる上下導通部３２がグランド層２に接続されて設けられている。この場合、上下導通部３２の上部はグランド用の上層下地金属層２４および上層配線２４に接続されている。   Through holes 31 are provided at predetermined locations of the upper insulating film 22, the insulating layer 21, the ground layer 2, and the base plate 1. On the inner wall surface of the through hole 31, a vertical conduction part 32 made of a base metal layer 32 a made of copper or the like and a copper layer 32 b is provided connected to the ground layer 2. In this case, the upper part of the vertical conduction part 32 is connected to the upper base metal layer 24 and the upper wiring 24 for ground.

上下導通部３２の下部は、貫通孔３１の周囲におけるベース板１の下面に島状に設けられた下層下地金属層３３および下層配線３４に接続されている。この場合、下層下地金属層３３を含む下層配線３４は、島状であるため、上下導通部３２以外はどことも電気的に接続されていない。上下導通部３２内にはソルダーレジスト等からなる充填材３５が充填されている。下層配線３４を含むベース板１の下面にはソルダーレジスト等からなる下層オーバーコート膜３６が設けられている。   The lower part of the vertical conduction part 32 is connected to a lower base metal layer 33 and a lower layer wiring 34 provided in an island shape on the lower surface of the base plate 1 around the through hole 31. In this case, the lower layer wiring 34 including the lower layer base metal layer 33 has an island shape, and is not electrically connected anywhere except the vertical conduction portion 32. The vertical conduction part 32 is filled with a filler 35 made of solder resist or the like. A lower overcoat film 36 made of a solder resist or the like is provided on the lower surface of the base plate 1 including the lower wiring 34.

以上のように、この半導体装置では、半導体構成体３のＳＯＩ基板６のシリコン基板７の下面を、突起電極５を介して、ベース板１の上面に設けられたグランド層２に接続し、上層絶縁膜２２、絶縁層２１、グランド層２およびベース板１に設けられた貫通孔３１内に設けられた上下導通部３２を介して、グランド層２をグランド用の上層配線２５に接続しているので、半導体構成体３のＳＯＩ基板６のシリコン基板７の下面をグランド電位とすることができる。   As described above, in this semiconductor device, the lower surface of the silicon substrate 7 of the SOI substrate 6 of the semiconductor structure 3 is connected to the ground layer 2 provided on the upper surface of the base plate 1 via the protruding electrode 5, and the upper layer The ground layer 2 is connected to the ground upper layer wiring 25 via the insulating film 22, the insulating layer 21, the ground layer 2, and the vertical conduction portion 32 provided in the through hole 31 provided in the base plate 1. Therefore, the lower surface of the silicon substrate 7 of the SOI substrate 6 of the semiconductor structure 3 can be set to the ground potential.

次に、この半導体装置の製造方法の一例について説明する。まず、図２に示すように、図１に示す完成された半導体装置を複数個形成することが可能な面積を有するベース板１を用意する。ベース板１は、限定する意味ではないが、例えば、平面方形状である。ベース板１は、ガラス布等からなる基材にエポキシ系樹脂等の熱硬化性樹脂を含浸させ、熱硬化性樹脂を硬化させてシート状となしたものである。   Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 2, a base plate 1 having an area capable of forming a plurality of completed semiconductor devices shown in FIG. 1 is prepared. Although the base plate 1 is not limited, for example, the base plate 1 has a planar rectangular shape. The base plate 1 is a sheet formed by impregnating a base material made of glass cloth or the like with a thermosetting resin such as an epoxy resin and curing the thermosetting resin.

この場合、ベース板１の上面には銅箔からなるべたパターンのグランド層２が設けられている。グランド層２の上面の所定の箇所には複数の突起電極５が分散して設けられている。突起電極５は、金属ペーストをスクリーン印刷等により塗布して硬化させることにより形成するようにしてもよく、また銅の無電解メッキあるいは電解メッキにより形成するようにしてもよく、また真空法によりナノ金属粒子をジェットプリントすることにより形成するようにしてもよい。   In this case, a ground layer 2 having a solid pattern made of copper foil is provided on the upper surface of the base plate 1. A plurality of protruding electrodes 5 are provided in a dispersed manner at predetermined locations on the upper surface of the ground layer 2. The protruding electrode 5 may be formed by applying a metal paste by screen printing or the like and curing it, or may be formed by electroless plating or electrolytic plating of copper, or by a vacuum method. The metal particles may be formed by jet printing.

ここで、一例として、スクリーン印刷により形成すると、突起電極５の形状をほぼ円錐形状とすることができる。すなわち、グランド層２の上面にスクリーン印刷により金属ペーストを塗布した後に、スクリーン版をグランド層２の上面から離間すると、このスクリーン版の離間に伴って、スクリーン版の円形状の開口部内に充填された金属ペーストが持ち上げられ、その粘性によりほぼ円錐形状となり、この状態で硬化させると、ほぼ円錐形状の突起電極が形成される。   Here, as an example, when formed by screen printing, the shape of the protruding electrode 5 can be made substantially conical. That is, after the metal paste is applied to the upper surface of the ground layer 2 by screen printing, when the screen plate is separated from the upper surface of the ground layer 2, the circular opening of the screen plate is filled with the separation of the screen plate. The metal paste is lifted and becomes substantially conical due to its viscosity. When cured in this state, a substantially conical protruding electrode is formed.

また、半導体構成体３のシリコン基板７の下面に絶縁性接着層４が設けられたものを用意する。この場合、絶縁性接着層４を有する半導体構成体３は、ウエハ状態のシリコン基板７上に絶縁膜８、ＳＯＩ集積回路部９、接続パッド１０、絶縁膜１１、保護膜１３、下地金属層１５、配線１６、柱状電極１７および封止膜１８を形成した後、ウエハ状態のシリコン基板７の下面に、ダイアタッチメントフィルムとして市販されているエポキシ系樹脂やポリイミド系樹脂等のダイボンド材からなる絶縁性接着層４を加熱加圧により半硬化させた状態で固着し、ダイシングにより個片化することにより得られる。ここで、ベース板１の上面に設けられた複数の突起電極５は、いずれも絶縁性接着層４の領域内に配置されるようにする。   Also, a semiconductor structure 3 having an insulating adhesive layer 4 provided on the lower surface of the silicon substrate 7 is prepared. In this case, the semiconductor structure 3 having the insulating adhesive layer 4 includes the insulating film 8, the SOI integrated circuit portion 9, the connection pad 10, the insulating film 11, the protective film 13, and the base metal layer 15 on the silicon substrate 7 in a wafer state. After forming the wiring 16, the columnar electrode 17 and the sealing film 18, an insulating property made of a die bond material such as epoxy resin or polyimide resin commercially available as a die attachment film is formed on the lower surface of the silicon substrate 7 in a wafer state. It is obtained by fixing the adhesive layer 4 in a state where it is semi-cured by heating and pressing, and separating it by dicing. Here, the plurality of protruding electrodes 5 provided on the upper surface of the base plate 1 are all arranged in the region of the insulating adhesive layer 4.

次に、グランド層２の上面の所定の複数箇所に複数の半導体構成体３のシリコン基板７の下面に固着された絶縁性接着層４を相互に離間させて接着する。ここでの接着は、加熱加圧により、絶縁性接着層４を本硬化させる。この場合、加圧により、グランド層２の上面に設けられた突起電極５が半硬化状態の絶縁性接着層４に相対的に食い込み、シリコン基板７の下面に当接される。このように、突起電極５を半硬化状態の絶縁性接着層４に食い込ませるため、突起電極５の形状としてはほぼ円錐形状である方が好ましい。   Next, the insulating adhesive layers 4 fixed to the lower surfaces of the silicon substrates 7 of the plurality of semiconductor structures 3 are adhered to the predetermined plural positions on the upper surface of the ground layer 2 while being separated from each other. In this bonding, the insulating adhesive layer 4 is fully cured by heating and pressing. In this case, due to the pressurization, the protruding electrode 5 provided on the upper surface of the ground layer 2 bites into the semi-cured insulating adhesive layer 4 and comes into contact with the lower surface of the silicon substrate 7. Thus, in order to cause the protruding electrode 5 to bite into the semi-cured insulating adhesive layer 4, it is preferable that the protruding electrode 5 has a substantially conical shape.

次に、図４に示すように、半導体構成体３の周囲におけるグランド層２の上面に格子状の絶縁層形成用シート２１ａをピン等で位置決めしながら配置する。格子状の絶縁層形成用シート２１ａは、熱硬化性樹脂中に補強材を分散させ、熱硬化性樹脂を半硬化状態にしてシート状となしたものである。次に、半導体構成体３および絶縁層形成用層２１ａの上面に上層絶縁膜形成用シート２２ａを配置する。上層絶縁膜形成用シート２２ａは、ガラス布等にエポキシ系樹脂等の熱硬化性樹脂を含浸させ、熱硬化性樹脂を半硬化状態にしてシート状となしたものである。   Next, as shown in FIG. 4, a lattice-shaped insulating layer forming sheet 21 a is arranged on the upper surface of the ground layer 2 around the semiconductor structure 3 while being positioned with pins or the like. The lattice-shaped insulating layer forming sheet 21a is a sheet in which a reinforcing material is dispersed in a thermosetting resin and the thermosetting resin is semi-cured. Next, the upper insulating film forming sheet 22a is disposed on the upper surfaces of the semiconductor structure 3 and the insulating layer forming layer 21a. The upper insulating film forming sheet 22a is formed by impregnating a glass cloth or the like with a thermosetting resin such as an epoxy resin to make the thermosetting resin into a semi-cured state into a sheet shape.

次に、一対の加熱加圧板４１、４２を用いて上下から絶縁層形成用層２１ａおよび上層絶縁膜形成用シート２２ａを加熱加圧する。そして、その後の冷却により、半導体構成体３の周囲におけるグランド層２の上面に絶縁層２１が形成され、また、半導体構成体３および絶縁層２１の上面に上層絶縁膜２２が形成される。この場合、上層絶縁膜２２の上面は、上側の加熱加圧板４１の下面によって押さえ付けられるため、平坦面となる。したがって、上層絶縁膜２２の上面を平坦化するための研磨工程は不要である。   Next, the insulating layer forming layer 21a and the upper insulating film forming sheet 22a are heated and pressed from above and below using a pair of heating and pressing plates 41,. Then, by subsequent cooling, an insulating layer 21 is formed on the upper surface of the ground layer 2 around the semiconductor structure 3, and an upper insulating film 22 is formed on the upper surfaces of the semiconductor structure 3 and the insulating layer 21. In this case, since the upper surface of the upper insulating film 22 is pressed by the lower surface of the upper heating and pressing plate 41, it becomes a flat surface. Therefore, a polishing step for flattening the upper surface of the upper insulating film 22 is not necessary.

次に、図５に示すように、レーザビームを照射するレーザ加工により、半導体構成体３の柱状電極１７の上面中央部に対応する部分における上層絶縁膜２２に開口部２３を形成する。また、メカニカルドリルを用いて、上層絶縁膜２２、絶縁層２１、グランド層２およびベース板１の所定の箇所に貫通孔３１を形成する。次に、必要に応じて、開口部２３内および貫通孔３１内等に発生したエポキシスミア等をデスミア処理により除去する。   Next, as shown in FIG. 5, an opening 23 is formed in the upper insulating film 22 in a portion corresponding to the center of the upper surface of the columnar electrode 17 of the semiconductor structure 3 by laser processing with laser beam irradiation. Moreover, the through-hole 31 is formed in the predetermined location of the upper-layer insulating film 22, the insulating layer 21, the ground layer 2, and the base board 1 using a mechanical drill. Next, the epoxy smear etc. which generate | occur | produced in the opening part 23, the through-hole 31, etc. are removed by a desmear process as needed.

次に、図６に示すように、開口部２３を介して露出された柱状電極１７の上面を含む上層絶縁膜２２の上面全体、ベース板１の下面全体および貫通孔３１の内壁面に、銅の無電解メッキにより、上層下地金属層２４、下層下地金属層３３、下地金属層３２ａを形成する。次に、上層下地金属層２４の上面に上層メッキレジスト膜４３をパターン形成し、また、下層下地金属層３３の下面に下層メッキレジスト膜４４をパターン形成する。この場合、貫通孔３１を含む上層配線２５形成領域に対応する部分における上層メッキレジスト膜４３には開口部４５が形成されている。また、貫通孔３１を含む下層配線３４形成領域に対応する部分における下層メッキレジスト膜４４には開口部４６が形成されている。   Next, as shown in FIG. 6, copper is applied to the entire upper surface of the upper insulating film 22 including the upper surface of the columnar electrode 17 exposed through the opening 23, the entire lower surface of the base plate 1, and the inner wall surface of the through hole 31. The upper base metal layer 24, the lower base metal layer 33, and the base metal layer 32a are formed by electroless plating. Next, the upper plating resist film 43 is patterned on the upper surface of the upper lower metal layer 24, and the lower plating resist film 44 is patterned on the lower surface of the lower base metal layer 33. In this case, an opening 45 is formed in the upper plating resist film 43 in a portion corresponding to the upper layer wiring 25 forming region including the through hole 31. Further, an opening 46 is formed in the lower plating resist film 44 in a portion corresponding to the lower wiring 34 forming region including the through hole 31.

次に、下地金属層２４、３３、３２ａをメッキ電流路として銅の電解メッキを行なうことにより、上層メッキレジスト膜４３の開口部４５内の上層下地金属層２４の上面に上層配線２５を形成し、また、下層メッキレジスト膜４４の開口部４６内の下層下地金属層３３の下面に下層配線３４を形成し、さらに、貫通孔３１内の下地金属層３２ａの表面に銅層３２ｂを形成する。   Next, the upper layer wiring 25 is formed on the upper surface of the upper layer metal layer 24 in the opening 45 of the upper layer plating resist film 43 by performing copper electroplating using the base metal layers 24, 33 and 32 a as a plating current path. In addition, the lower layer wiring 34 is formed on the lower surface of the lower base metal layer 33 in the opening 46 of the lower plating resist film 44, and the copper layer 32 b is formed on the surface of the base metal layer 32 a in the through hole 31.

次に、両メッキレジスト膜４３、４４を剥離し、次いで、上層配線２５および下層配線３４をマスクとして下地金属層２４、３３の不要な部分をエッチングして除去すると、図７に示すように、上層配線２５下にのみ上層下地金属層２４が残存され、また、下層配線３４上にのみ下層下地金属層３３が残存される。この状態では、貫通孔３１の内壁面には下地金属層３２ａと銅層３２ｂとからなる上下導通部３２がグランド層２に接続されて形成されている。   Next, both plating resist films 43 and 44 are peeled off, and then unnecessary portions of the base metal layers 24 and 33 are removed by etching using the upper layer wiring 25 and the lower layer wiring 34 as a mask, as shown in FIG. The upper base metal layer 24 remains only under the upper layer wiring 25, and the lower base metal layer 33 remains only on the lower layer wiring 34. In this state, a vertical conduction portion 32 composed of a base metal layer 32 a and a copper layer 32 b is formed on the inner wall surface of the through hole 31 so as to be connected to the ground layer 2.

次に、図８に示すように、スクリーン印刷法やスピンコーティング法等により、上層配線２５を含む上層絶縁膜２２の上面にソルダーレジスト等からなる上層オーバーコート膜２６を形成し、また、下層配線３４を含むベース板１の下面にソルダーレジスト等からなる下層オーバーコート膜３６を形成し、同時に、上下導通部３２内にソルダーレジスト等からなる充填材３５を充填する。この場合、上層配線２５の接続パッド部に対応する部分における上層オーバーコート膜２６には開口部２７が形成されている。   Next, as shown in FIG. 8, an upper overcoat film 26 made of a solder resist or the like is formed on the upper surface of the upper insulating film 22 including the upper wiring 25 by a screen printing method, a spin coating method, or the like. A lower overcoat film 36 made of solder resist or the like is formed on the lower surface of the base plate 1 including 34, and at the same time, a filling material 35 made of solder resist or the like is filled into the vertical conduction part 32. In this case, an opening 27 is formed in the upper overcoat film 26 in a portion corresponding to the connection pad portion of the upper layer wiring 25.

次に、開口部２７内およびその上方に半田ボール２８を上層配線２５の接続パッド部に接続させて形成する。次に、互いに隣接する半導体構成体３間において、上層オーバーコート膜２６、上層絶縁膜２２、絶縁層２１、グランド層２、ベース板１および下層オーバーコート膜３６を切断すると、図１に示す半導体装置が複数個得られる。   Next, a solder ball 28 is formed in the opening 27 and above it by connecting to the connection pad portion of the upper wiring 25. Next, when the upper overcoat film 26, the upper insulating film 22, the insulating layer 21, the ground layer 2, the base plate 1, and the lower overcoat film 36 are cut between the adjacent semiconductor structures 3, the semiconductor shown in FIG. Multiple devices are obtained.

（第２実施形態）
図９はこの発明の第２実施形態としての半導体装置の断面図を示す。この半導体装置において、図１に示す半導体装置と異なる点は、半導体構成体３のシリコン基板７の下面を異方性導電接着剤５１を介してグランド層２の上面に接着するとともに電気的に接続した点である。すなわち、異方性導電接着剤５１は、詳細には図示していないが、エポキシ系樹脂等の熱硬化性樹脂からなる絶縁性接着剤中に導電性粒子を分散させたものであり、このうちの絶縁性接着剤により、シリコン基板７の下面がグランド層２の上面に接着され、導電性粒子により、シリコン基板７の下面がグランド層２の上面に電気的に接続される。従って、この実施形態では、異方性導電接着剤５１に分散して配置された導電性粒子がグランド層２と半導体構成体３の裏面とを電気的に接続する上下導通部材となる。 (Second Embodiment)
FIG. 9 shows a sectional view of a semiconductor device as a second embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 1 in that the lower surface of the silicon substrate 7 of the semiconductor structure 3 is bonded to the upper surface of the ground layer 2 via an anisotropic conductive adhesive 51 and electrically connected. This is the point. That is, although not shown in detail, the anisotropic conductive adhesive 51 is obtained by dispersing conductive particles in an insulating adhesive made of a thermosetting resin such as an epoxy resin. The lower surface of the silicon substrate 7 is bonded to the upper surface of the ground layer 2 by the insulating adhesive, and the lower surface of the silicon substrate 7 is electrically connected to the upper surface of the ground layer 2 by the conductive particles. Therefore, in this embodiment, the conductive particles dispersed and arranged in the anisotropic conductive adhesive 51 serve as a vertical conduction member that electrically connects the ground layer 2 and the back surface of the semiconductor structure 3.

（第３実施形態）
図１０はこの発明の第３実施形態としての半導体装置の断面図を示す。この半導体装置において、図１に示す半導体装置と大きく異なる点は、上層絶縁膜および上層配線を２層とした点である。すなわち、第１の上層配線２５Ａを含む第１の上層絶縁膜２２Ａの上面には、第１の上層絶縁膜２２Ａと同じ材料からなる第２の上層絶縁膜２２Ｂが設けられている。第２の上層絶縁膜２２Ｂの上面には第２の上層下地金属層２４Ｂを含む第２の上層配線２５Ｂが設けられている。 (Third embodiment)
FIG. 10 is a sectional view of a semiconductor device as a third embodiment of the present invention. This semiconductor device differs greatly from the semiconductor device shown in FIG. 1 in that the upper insulating film and the upper wiring have two layers. That is, the second upper layer insulating film 22B made of the same material as the first upper layer insulating film 22A is provided on the upper surface of the first upper layer insulating film 22A including the first upper layer wiring 25A. A second upper layer wiring 25B including a second upper layer base metal layer 24B is provided on the upper surface of the second upper layer insulating film 22B.

第１の上層下地金属層２４Ａを含む第２の上層配線２５Ａの一端部は、第１の上層絶縁膜２２Ａの開口部２３Ａを介して半導体構成体３の柱状電極１７の上面に接続されている。第２の上層下地金属層２４Ｂを含む第２の上層配線２５Ｂの一端部は、第２の上層絶縁膜２２Ｂの開口部２３Ｂを介して第１の上層配線２５Ａの接続パッド部上面に接続されている。半田ボール２８は、上層オーバーコート膜２６の開口部２７を介して第２の上層配線２５Ｂの接続パッド部上面に接続されている。   One end of the second upper wiring 25A including the first upper base metal layer 24A is connected to the upper surface of the columnar electrode 17 of the semiconductor structure 3 through the opening 23A of the first upper insulating film 22A. . One end of the second upper layer wiring 25B including the second upper layer underlying metal layer 24B is connected to the upper surface of the connection pad portion of the first upper layer wiring 25A through the opening 23B of the second upper layer insulating film 22B. Yes. The solder ball 28 is connected to the upper surface of the connection pad portion of the second upper layer wiring 25B through the opening 27 of the upper layer overcoat film 26.

（その他の実施形態）
上記第１実施形態には、互いに隣接する半導体構成体３間において切断したが、これに限らず、２個またはそれ以上の半導体構成体３を１組として切断し、マルチチップモジュール型の半導体装置を得るようにしてもよい。この場合、２個で１組の半導体構成体３は同種、異種のいずれであってもよい。 (Other embodiments)
In the first embodiment, the semiconductor structures 3 that are adjacent to each other are cut. However, the present invention is not limited to this, and two or more semiconductor structures 3 are cut as a set to obtain a multichip module type semiconductor device. May be obtained. In this case, two sets of semiconductor structures 3 may be the same type or different types.

また、ベース板１は、銅、アルミニウム、ニッケル、クロム等からなる導電性金属板であってもよい。ベース板１をこのような導電性金属板によって形成した場合には、ベース板１自体にグランド層としての機能を持たせることができるので、上述の銅箔からなるグランド層２は省略してもよい。また、ベース板１をステンレス鋼によって形成し、その上面に銅箔からなるグランド層２を設けるようにしてもよい。   The base plate 1 may be a conductive metal plate made of copper, aluminum, nickel, chromium, or the like. When the base plate 1 is formed of such a conductive metal plate, the base plate 1 itself can have a function as a ground layer. Therefore, the ground layer 2 made of the copper foil can be omitted. Good. Alternatively, the base plate 1 may be formed of stainless steel, and a ground layer 2 made of copper foil may be provided on the upper surface thereof.

さらに、上記各実施形態では、半導体構成体３として、封止膜１８を有し、且つ、外部接続用電極としての柱状電極１７を有する場合について説明したが、これに限らず、例えば、封止膜１８および柱状電極１７を有せず、外部接続用電極としての接続パッド部を有する配線１６を有するものとしてもよい。この場合、配線１６の接続パッド部以外を覆うオーバーコート膜を有するものとしてもよい。   Furthermore, although each said embodiment demonstrated the case where it had the sealing film 18 as the semiconductor structure 3, and it has the columnar electrode 17 as an electrode for external connection, it is not restricted to this, For example, sealing The film 18 and the columnar electrode 17 may be omitted, and the wiring 16 having a connection pad portion as an external connection electrode may be included. In this case, an overcoat film that covers the wiring 16 other than the connection pad portion may be provided.

この発明の第１実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as a first embodiment of the present invention. 図１に示す半導体装置の製造方法の一例において、当初用意したものの断面図。Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く工程の断面図。Sectional drawing of the process following FIG. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. この発明の第２実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 2nd Embodiment of this invention. この発明の第３実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 3rd Embodiment of this invention.

符号の説明Explanation of symbols

１ ベース板
２ グランド層
３ 半導体構成体
４ 絶縁性接着層
５ 突起電極
６ ＳＯＩ基板
７ シリコン基板
８ 酸化シリコン膜
９ ＳＯＩ集積回路部
１０ 接続パッド
１１ 絶縁膜
１３ 保護膜
１６ 配線
１７ 柱状電極
１８ 封止膜
２１ 絶縁層
２２ 上層絶縁膜
２５ 上層配線
２６ 上層オーバーコート膜
２８ 半田ボール
３１ 貫通孔
３２ 上下導通部
３４ 下層配線
３６ 下層オーバーコート膜 DESCRIPTION OF SYMBOLS 1 Base board 2 Ground layer 3 Semiconductor structure 4 Insulating adhesive layer 5 Protruding electrode 6 SOI substrate 7 Silicon substrate 8 Silicon oxide film 9 SOI integrated circuit part 10 Connection pad 11 Insulating film 13 Protective film 16 Wiring 17 Columnar electrode 18 Sealing Film 21 Insulating layer 22 Upper layer insulating film 25 Upper layer wiring 26 Upper layer overcoat film 28 Solder ball 31 Through hole 32 Vertical conduction part 34 Lower layer wiring 36 Lower layer overcoat film

Claims (9)

少なくとも表面にグランド接続用導電層を有するベース部材に、一面に集積回路が形成された半導体構成体の他面を接着層により接着すると共に、前記グランド接続用導電層と前記半導体構成体の他面との間に両者を電気的に接続する上下導通部材を介在したことを特徴とする半導体装置。   At least the surface of the base member having the ground connection conductive layer is bonded to the other surface of the semiconductor structure having the integrated circuit formed on one surface thereof by an adhesive layer, and the ground connection conductive layer and the other surface of the semiconductor structure are bonded. And a vertical conduction member for electrically connecting the two. 請求項１に記載の発明において、前記ベース部材上に突起電極が設けられ、該突起電極は前記半導体構成体の半導体基板の下面に接続されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein a protruding electrode is provided on the base member, and the protruding electrode is connected to a lower surface of a semiconductor substrate of the semiconductor structure. 請求項１に記載の発明において、前記上下導通部材は複数個介在されており、これら複数個の前記上下導通部材は、前記接着層の領域内に分散して配置されていることを特徴とする半導体装置。   The invention according to claim 1 is characterized in that a plurality of the vertical conduction members are interposed, and the plurality of the vertical conduction members are arranged in a distributed manner in the region of the adhesive layer. Semiconductor device. 請求項１に記載の発明において、前記半導体構成体の半導体基板の下面は前記ベース部材上に異方性導電接着剤を介して接着されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein a lower surface of the semiconductor substrate of the semiconductor structure is bonded to the base member via an anisotropic conductive adhesive. 請求項１に記載の発明において、前記ベース部材は、絶縁性のベース板と、前記ベース板の上面に設けられたグランド層とからなることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the base member includes an insulating base plate and a ground layer provided on an upper surface of the base plate. 請求項１に記載の発明において、前記ベース部材はグランド層を兼ねた金属板からなることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the base member is made of a metal plate also serving as a ground layer. 請求項１に記載の発明において、前記ベース板上に前記半導体構成体の周囲を外部から封止する絶縁層が設けられ、前記半導体構成体および前記絶縁層上に上層配線が設けられていることを特徴とする半導体装置。   The invention according to claim 1, wherein an insulating layer for sealing the periphery of the semiconductor structure from the outside is provided on the base plate, and an upper layer wiring is provided on the semiconductor structure and the insulating layer. A semiconductor device characterized by the above. 請求項７に記載の発明において、前記上層配線の少なくとも一部は、前記絶縁層に設けられた開口部を介して前記グランド接続用導電層に接続されていることを特徴とする半導体装置。   8. The semiconductor device according to claim 7, wherein at least part of the upper wiring is connected to the ground connection conductive layer through an opening provided in the insulating layer. 請求項１に記載の発明において、前記半導体構成体は、半導体基板、該半導体基板上に設けられた絶縁膜、該絶縁膜上に設けられたＳＯＩ集積回路部および外部接続用電極を含むことを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the semiconductor structure includes a semiconductor substrate, an insulating film provided on the semiconductor substrate, an SOI integrated circuit portion provided on the insulating film, and an external connection electrode. A featured semiconductor device.
JP2005218290A 2005-07-28 2005-07-28 Semiconductor device Expired - Fee Related JP4913372B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008288481A (en) * 2007-05-21 2008-11-27 Casio Comput Co Ltd Semiconductor device and method for manufacturing the same
WO2010041630A1 (en) * 2008-10-10 2010-04-15 日本電気株式会社 Semiconductor device and method for manufacturing same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005142466A (en) * 2003-11-10 2005-06-02 Casio Comput Co Ltd Semiconductor device, and manufacturing method thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005142466A (en) * 2003-11-10 2005-06-02 Casio Comput Co Ltd Semiconductor device, and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008288481A (en) * 2007-05-21 2008-11-27 Casio Comput Co Ltd Semiconductor device and method for manufacturing the same
WO2010041630A1 (en) * 2008-10-10 2010-04-15 日本電気株式会社 Semiconductor device and method for manufacturing same
JPWO2010041630A1 (en) * 2008-10-10 2012-03-08 日本電気株式会社 Semiconductor device and manufacturing method thereof
US8569892B2 (en) 2008-10-10 2013-10-29 Nec Corporation Semiconductor device and manufacturing method thereof

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