JP2006073844A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the number of columnar electrodes in a semiconductor device called a CSP provided with the columnar electrodes. <P>SOLUTION: The plurality of columnar electrodes 4 are respectively arranged on four virtual circulating lines in a flat rectangular frame shape in different sizes on a silicon substrate 4. In this case, the interval of the columnar electrodes 12 arranged on the second virtual circulating line from the inner side is such an interval that one of upper layer wiring 18 pulled out from the columnar electrodes 12 arranged on the first virtual circulating line from the inner side can be put around. The interval of the columnar electrodes 12 arranged on the third virtual circulating line from the inner side is such an interval that two of the upper layer wiring 18 pulled out from the columnar electrodes 12 arranged on the first and second virtual circulating lines from the inner side can be put around. The interval of the columnar electrodes 12 arranged on the fourth virtual circulating line from the inner side is such an interval that three of the upper layer wiring 18 pulled out from the columnar electrodes 12 arranged on the first, second and third virtual circulating lines from the inner side can be put around. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device.

  A conventional semiconductor device is called a CSP (chip size package), and a wiring is connected to the connection pad via an insulating film on a semiconductor substrate having a plurality of connection pads on the upper surface. A columnar electrode is provided on the part, and a sealing film is provided over the insulating film including the wiring so that the upper surface thereof is flush with the upper surface of the columnar electrode (for example, see Patent Document 1).

  In addition, since other conventional semiconductor devices include solder balls as external connection terminals in addition to the size of the semiconductor substrate, a semiconductor substrate having a plurality of connection pads on the upper surface is provided on the upper surface of the base plate. An insulating layer is provided on the upper surface of the base plate around the substrate, an upper insulating film is provided on the upper surface of the semiconductor substrate and the insulating layer, and an upper layer wiring is provided on the upper surface of the upper insulating film through an opening provided in the upper insulating film. Some are provided by being connected to the connection pads of the substrate, the portions other than the connection pad portions of the upper layer wiring are covered with an overcoat film, and solder balls are provided on the connection pad portions of the upper layer wiring (for example, see Patent Document 2). .

Japanese Patent Laid-Open No. 2000-22052 (FIG. 8) JP 2003-298005 A

  By the way, in the thing of patent document 2, it is thought that the semiconductor device (henceforth a semiconductor structure for convenience) provided with the columnar electrode of patent document 1 is provided on the upper surface of the base plate instead of the semiconductor substrate. It has been. That is, a semiconductor structure having columnar electrodes is provided on the upper surface of the base plate, an insulating layer is provided on the upper surface of the base plate around the semiconductor structure, and an upper insulating film is provided on the upper surfaces of the semiconductor structure and the insulating layer. The upper layer wiring is provided on the upper surface of the film by being connected to the columnar electrode of the semiconductor structure through the opening provided in the upper layer insulating film, and the portion other than the connection pad portion of the upper layer wiring is covered with the overcoat film, It is considered to provide solder balls on the connection pad portions.

  Here, in the current processing technique, when the diameter of the columnar electrodes is about 120 μm, the limit of the arrangement pitch of the columnar electrodes is about 200 μm, and the limit of the wiring pitch of the upper layer wiring is about 70 μm (wiring width of about 35 μm, wiring The interval is about 35 μm). If the diameter of the opening formed in the upper insulating film on the columnar electrode having a diameter of 120 μm is 95 μm, the interval between the openings on the columnar electrodes arranged at an arrangement pitch of 200 μm is 105 μm. The number of upper layer wirings that can be routed to the upper surface of the upper insulating film is 35 μm and the wiring interval is 35 μm.

  Under these conditions, when the columnar electrodes are maximally arranged on the periphery of the 5 mm × 5 mm semiconductor substrate, the result is as shown in FIG. That is, since the length of one side of the semiconductor substrate 41 is 5 mm, when the columnar electrodes 42 having a diameter of 120 μm are arranged on this one side with an arrangement pitch of 200 μm, the number is (5000 ÷ 200) −1 = 24, There are a total of 92 pieces on the four sides.

  Further, as shown in FIG. 21, one upper layer wiring 44 can be routed to the upper surface of the upper insulating film 43 between each of the 92 columnar electrodes 42 arranged on the four sides, as shown in FIG. In addition, the same number of 92 columnar electrodes 42 can be arranged inside the 92 columnar electrodes 42 arranged on the four sides. In this case, 84 columnar electrodes 42 are arranged as the second row inside the 92 columnar electrodes 42 arranged on the four sides, and eight columnar electrodes 42 are arranged as the third row inside thereof. .

  As described above, in the semiconductor device having the columnar electrode arrangement structure, the same number of 92 columnar electrodes 42 can be arranged inside the 92 columnar electrodes 42 arranged on the four sides. However, this is a limitation, and a larger number of columnar electrodes 42 cannot be disposed.

  Accordingly, an object of the present invention is to provide a semiconductor device in which external connection electrodes including a larger number of columnar electrodes and the like can be arranged.

  According to the present invention, external connection electrodes composed of a plurality of columnar electrodes and the like are arranged on three or more planar rectangular frame-shaped virtual circuits each having a different size, and the n (two or more) virtual circuits from the inside. The interval between the external connection electrodes arranged on the line is set to an interval that allows (n-1) or more upper-layer wirings drawn from the external connection electrode arranged on the inner side to be routed. It is characterized by.

  According to the present invention, the external connection electrodes composed of a plurality of columnar electrodes and the like are respectively arranged on three or more planar rectangular frame-shaped virtual peripheral lines having different sizes, and the n (two or more) th from the inside. An interval between at least a part of the external connection electrodes arranged on the virtual peripheral line is an interval at which (n-1) or more upper layer wirings drawn from the connection electrode arranged on the inner side can be routed. Then, for example, as compared with the case shown in FIG. 21, it is possible to arrange external connection electrodes including a larger number of columnar electrodes.

(First embodiment)
FIG. 1 is a plan view of a main part of a semiconductor device as a first embodiment of the present invention, FIG. 2 is a plan view of a semiconductor structure in the semiconductor device shown in FIG. 1, and FIG. 3 is a semiconductor shown in FIG. Figure 2 shows a longitudinal section of a suitable part of the device. In this case, for convenience of illustration, the dimensions of the respective parts in FIGS. 1, 2, and 3 do not match. First, referring to FIG. 3, this semiconductor device includes a planar square base plate 1 made of glass cloth base epoxy resin or the like.

  The bottom surface of the planar square semiconductor structure 2 having a size somewhat smaller than the size of the base plate 1 is bonded to the central portion of the upper surface of the base plate 1 via an adhesive layer 3 made of a die bond material. In this case, the semiconductor structure 2 has a wiring 11, a columnar electrode 12, and a sealing film 13, which will be described later, and is generally called CSP. In particular, as described later, the wiring is formed on the silicon wafer. 11, after the columnar electrode 12 and the sealing film 13 are formed, a method for obtaining individual semiconductor structures 2 by dicing is adopted, and therefore, it is also called a wafer level CSP (W-CSP). Below, the structure of the semiconductor structure 2 is demonstrated.

  The semiconductor structure 2 includes a silicon substrate (semiconductor substrate) 4. The lower surface of the silicon substrate 4 is bonded to the upper surface of the base plate 1 via the adhesive layer 3. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 4, and a plurality of connection pads 5 made of aluminum-based metal or the like are provided on the periphery of the upper surface so as to be connected to the integrated circuit. An insulating film 6 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 4 excluding the central portion of the connection pad 5, and the central portion of the connection pad 5 is exposed through an opening 7 provided in the insulating film 6. Yes.

  A protective film (insulating film) 8 made of an epoxy resin, a polyimide resin, or the like is provided on the upper surface of the insulating film 6. In this case, an opening 9 is provided in the protective film 8 at a portion corresponding to the opening 7 of the insulating film 6. A base metal layer 10 made of copper or the like is provided on the upper surface of the protective film 8. A wiring 11 made of copper is provided on the entire upper surface of the base metal layer 10. One end of the wiring 11 including the base metal layer 10 is connected to the connection pad 5 through both openings 7 and 9.

  A columnar electrode (external connection electrode) 12 made of copper is provided on the upper surface of the connection pad portion of the wiring 11. A sealing film 13 made of epoxy resin, polyimide resin, or the like is provided on the upper surface of the protective film 8 including the wiring 11 so that the upper surface is flush with the upper surface of the columnar electrode 12. Thus, the semiconductor structure 2 called W-CSP includes the silicon substrate 4, the connection pad 5, and the insulating film 6, and further includes the protective film 8, the wiring 11, the columnar electrode 12, and the sealing film 13. Has been.

  A planar rectangular frame-like insulating layer 14 is provided on the upper surface of the base plate 1 around the semiconductor structure 2 so that the upper surface is substantially flush with the upper surface of the semiconductor structure 2. The insulating layer 14 is made of, for example, a thermosetting resin such as an epoxy resin, or a reinforcing material made of silica filler or the like mixed in such a thermosetting resin.

  An upper insulating film 15 is provided on the upper surfaces of the semiconductor structure 2 and the insulating layer 14 with the upper surfaces thereof being flat. The upper insulating film 15 is generally used as a build-up material used for a build-up substrate. For example, the upper insulating film 15 is formed by mixing a reinforcing material made of silica filler or the like in a thermosetting resin such as an epoxy resin. It has become.

  A via hole 16 is provided in the upper insulating film 15 in a portion corresponding to the center of the upper surface of the columnar electrode 12. An upper base metal layer 17 made of copper or the like is provided on the upper surface of the upper insulating film 15. An upper wiring 18 made of copper is provided on the entire upper surface of the upper base metal layer 17. One end portion of the upper wiring 18 including the upper base metal layer 17 is connected to the upper surface of the columnar electrode 12 through the via hole 16 of the upper insulating film 15.

  An overcoat film 19 made of a solder resist or the like is provided on the upper surface of the upper insulating film 15 including the upper wiring 18. An opening 20 is provided in the overcoat film 19 in a portion corresponding to the connection pad portion of the upper wiring 18. Solder balls 21 are provided in the opening 20 and above it so as to be connected to the connection pads of the upper wiring 18.

  Here, in the current processing technique, when the diameter of the columnar electrodes 12 is about 120 μm, the limit of the arrangement pitch of the columnar electrodes 12 is about 200 μm, and the limit of the wiring pitch of the upper layer wiring 18 is about 70 μm (wiring width 35 μm). The wiring interval is about 35 μm). When the diameter of the via hole 16 formed in the upper insulating film 15 on the columnar electrode 12 having a diameter of 120 μm is 95 μm, the interval between the via holes 16 on the columnar electrodes 12 arranged at an arrangement pitch of 200 μm is 105 μm. The number of the upper layer wirings 18 that can be routed to the upper surface of the upper insulating film 15 corresponding to the spacing is 35 μm and the wiring spacing is 35 μm is one.

  By the way, in this embodiment, as shown in FIG. 2, the plurality of columnar electrodes 12 are respectively arranged on four planar rectangular frame-shaped virtual peripheral lines having different sizes on the silicon substrate 4. In this case, the columnar electrodes 12 are arranged at a constant arrangement pitch (200 μm) on the first and second virtual peripheral lines from the inside. The columnar electrodes 12 are arranged at a constant arrangement pitch (270 μm) on the third virtual peripheral line from the inside. The columnar electrodes 12 are arranged at a constant arrangement pitch (340 μm) on the fourth virtual peripheral line from the inside.

  That is, the arrangement pitch of the columnar electrodes 12 arranged on the first virtual peripheral line from the inside is as small as possible, and is set to 200 μm, which is the processing limit. As shown in FIG. 1, the arrangement pitch of the columnar electrodes 12 arranged on the second virtual circumference line from the inside is determined by the upper layer wiring 18 drawn from the columnar electrodes 12 arranged on the first virtual circumference line from the inside. In order to draw one wire, (minimum wiring width) + (minimum wiring interval) × 2 + (diameter of via hole 16) = 200 μm.

  As shown in FIG. 1, the arrangement pitch of the columnar electrodes 12 arranged on the third virtual circumference line from the inside is the upper layer drawn from the columnar electrodes 12 arranged on the first and second virtual circumference lines from the inside. In order to route two wirings 18, (minimum wiring width) × 2 + (minimum wiring interval) × 3 + (diameter of via hole 16) = 270 μm.

  As shown in FIG. 1, the arrangement pitch of the columnar electrodes 12 arranged on the fourth virtual circumferential line from the inside is drawn from the columnar electrodes 12 arranged on the first, second and third virtual circumferential lines from the inside. In order to route the three upper layer wirings 18, (minimum wiring width) × 3 + (minimum wiring interval) × 4 + (diameter of via hole 16) = 340 μm.

  In other words, the interval between the columnar electrodes 12 arranged on the nth (two or more) virtual peripheral line from the inside is (n−1) upper layer wirings 18 drawn from the columnar electrodes 12 arranged on the inside. It is set as an interval that can be routed.

  Under the above conditions, when the columnar electrodes 12 are arranged on four planar rectangular frame-like virtual peripheral lines having different sizes on the 5 mm × 5 mm silicon substrate 4, the result is as shown in FIG. 2. That is, 52 columnar electrodes 12 are arranged on the first virtual circumference line from the inside, 60 columnar electrodes 12 are arranged on the second virtual circumference line from the inside, and on the third virtual circumference line from the inside. 52 columnar electrodes 12 are arranged, and 52 columnar electrodes 12 are arranged on the fourth virtual peripheral line from the inside.

  Then, the total number of columnar electrodes 12 is 216. However, as shown in FIG. 1, the upper layer wiring 18 cannot be drawn from the 12 columnar electrodes 12 arranged on the first virtual peripheral line from the inside. The number of columnar electrodes 12 that can be used is 204. However, even in this case, a larger number (204−184 = 20) of columnar electrodes 12 can be arranged as compared with the case shown in FIG.

  By the way, the size of the base plate 1 is made somewhat larger than the size of the semiconductor structure 2 because the area where the solder balls 21 are arranged is increased as the number of connection pads 5 on the silicon substrate 4 increases. This is because the size and pitch of the connection pad portion (portion in the opening 20 of the overcoat film 19) of the upper layer wiring 18 is made larger than the size and pitch of the columnar electrode 14 due to this. is there.

  In this case, as shown in FIG. 1, the upper layer wiring 18 is drawn from the region corresponding to the semiconductor structure 2 toward the outside thereof, so that the solder balls 21 are connected to the semiconductor structure 2 as shown in FIG. 3. Is disposed only on the region corresponding to the insulating layer 14 provided on the upper surface of the base plate 1 in the periphery.

  Next, an example of a method for manufacturing the semiconductor device 2 will be described. In this case, first, as shown in FIG. 4, on a silicon substrate (semiconductor substrate) 4 in a wafer state, a connection pad 5 made of an aluminum-based metal, an insulating film 6 made of silicon oxide, and an epoxy-based resin or a polyimide-based resin. A protective film 8 made of the like is provided, and a central portion of the connection pad 5 is exposed through openings 7 and 9 formed in the insulating film 6 and the protective film 8. In the above, on the silicon substrate 4 in the wafer state, an integrated circuit having a predetermined function is formed in a region where each semiconductor structure is formed, and the connection pad 5 is electrically connected to the integrated circuit formed in the corresponding region. Connected.

  Next, as shown in FIG. 5, a base metal layer 10 is formed on the entire upper surface of the protective film 8 including the upper surface of the connection pad 5 exposed through the openings 7 and 9. In this case, the base metal layer 10 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

  Next, a plating resist film 31 is pattern-formed on the upper surface of the base metal layer 10. In this case, an opening 32 is formed in the plating resist film 31 in a portion corresponding to the wiring 11 formation region. Next, by performing electrolytic plating of copper using the base metal layer 10 as a plating current path, the wiring 11 is formed on the upper surface of the base metal layer 10 in the opening 32 of the plating resist film 31. Next, the plating resist film 31 is peeled off.

  Next, as shown in FIG. 6, a plating resist film 33 is patterned on the upper surface of the base metal layer 10 including the wiring 11. In this case, an opening 34 is formed in the plating resist film 33 in a portion corresponding to the columnar electrode 12 formation region. Next, the columnar electrode 12 is formed on the upper surface of the connection pad portion of the wiring 11 in the opening 34 of the plating resist film 33 by performing electrolytic plating of copper using the base metal layer 10 as a plating current path. Next, when the plating resist film 33 is peeled off, and then unnecessary portions of the base metal layer 10 are removed by etching using the wiring 11 as a mask, the base metal layer 10 is formed only under the wiring 11 as shown in FIG. Remain.

  Next, as shown in FIG. 8, the entire upper surface of the protective film 8 including the columnar electrode 12 and the wiring 11 is sealed with an epoxy resin, a polyimide resin, or the like by screen printing, spin coating, die coating, or the like. The film 13 is formed so that its thickness is greater than the height of the columnar electrode 12. Therefore, in this state, the upper surface of the columnar electrode 12 is covered with the sealing film 13.

  Next, the upper surface side of the sealing film 13 and the columnar electrode 12 is appropriately polished to expose the upper surface of the columnar electrode 12 and to include the exposed upper surface of the columnar electrode 12 as shown in FIG. The upper surface of the stop film 13 is flattened. Here, the reason why the upper surface side of the columnar electrode 12 is appropriately polished is that there is a variation in the height of the columnar electrode 12 formed by electrolytic plating, so this variation is eliminated and the height of the columnar electrode 12 is made uniform. It is to make it.

  Next, as shown in FIG. 10, the adhesive layer 3 is bonded to the entire lower surface of the silicon substrate 4. The adhesive layer 3 is made of a die bond material such as an epoxy resin or a polyimide resin, and is fixed to the silicon substrate 4 in a semi-cured state by heating and pressing. Next, the adhesive layer 3 fixed to the silicon substrate 4 is affixed to a dicing tape (not shown), passed through the dicing process shown in FIG. 11, and then peeled off from the dicing tape. As shown in FIG. A plurality of semiconductor structures 2 having the adhesive layer 3 on the lower surface of 4 are obtained.

  Since the semiconductor structure 2 obtained in this way has the adhesive layer 3 on the lower surface of the silicon substrate 4, it is extremely troublesome to provide an adhesive layer on the lower surface of the silicon substrate 4 of each semiconductor structure 2 after the dicing process. Work becomes unnecessary. In addition, the operation | work which peels from a dicing tape after a dicing process is very simple compared with the operation | work which each provides an adhesive layer on the lower surface of the silicon substrate 4 of each semiconductor structure 2 after a dicing process.

  Next, an example of manufacturing the semiconductor device shown in FIG. 3 using the semiconductor structure 2 obtained in this manner will be described. First, as shown in FIG. 12, a base plate 1 having an area capable of forming a plurality of completed semiconductor devices shown in FIG. 3 is prepared. Although the base plate 1 is not limited, for example, the base plate 1 has a planar rectangular shape. Next, the adhesive layer 3 bonded to the lower surface of the silicon substrate 4 of the semiconductor structure 2 is bonded to a plurality of predetermined locations on the upper surface of the base plate 1. In this bonding, the adhesive layer 3 is fully cured by heating and pressing.

  Next, as shown in FIG. 13, an insulating layer forming layer 14 a is formed on the upper surface of the base plate 1 around the semiconductor structure 2 by, for example, a screen printing method or a spin coating method. The insulating layer forming layer 14a is, for example, a thermosetting resin such as an epoxy resin, or a reinforcing material made of silica filler or the like mixed in such a thermosetting resin.

  Next, the upper insulating film forming sheet 15a is disposed on the upper surfaces of the semiconductor structure 2 and the insulating layer forming layer 14a. The upper insulating film forming sheet 15a is not limited, but is preferably a sheet-like buildup material. As this buildup material, a silica filler is mixed in a thermosetting resin such as an epoxy resin, There is a curable resin in a semi-cured state. As the upper insulating film forming sheet 15a, a prepreg material in which a glass fiber is impregnated with a thermosetting resin such as an epoxy resin and the thermosetting resin is in a semi-cured state, or a silica filler is used. You may make it use the sheet-like thing which consists only of a thermosetting resin which is not mixed.

  Next, as shown in FIG. 14, the insulating layer forming layer 14 a and the upper insulating film forming sheet 15 a are heated and pressed from above and below using a pair of heating and pressing plates 35 and 36. Then, the insulating layer 14 is formed on the upper surface of the base plate 1 around the semiconductor structure 2, and the upper insulating film 15 is formed on the upper surfaces of the semiconductor structure 2 and the insulating layer 14. In this case, since the upper surface of the upper insulating film 15 is pressed by the lower surface of the upper heating / pressing plate 35, it becomes a flat surface. Therefore, a polishing process for flattening the upper surface of the upper insulating film 15 is unnecessary.

  Next, as shown in FIG. 15, a via hole 16 is formed in the upper insulating film 15 in a portion corresponding to the central portion of the upper surface of the columnar electrode 12 by laser processing with laser beam irradiation. Next, if necessary, epoxy smear or the like generated in the via hole 16 or the like is removed by a desmear process. Next, as shown in FIG. 16, an upper base metal layer 17 is formed by electroless plating of copper over the entire upper surface of the upper insulating film 15 including the upper surface of the columnar electrode 12 exposed through the via holes 16. Next, a plating resist film 37 is patterned on the upper surface of the upper base metal layer 17. In this case, an opening 38 is formed in the plating resist film 37 in a portion corresponding to the upper layer wiring 18 formation region.

  Next, the upper wiring 18 is formed on the upper surface of the upper base metal layer 17 in the opening 38 of the plating resist film 37 by performing electrolytic plating of copper using the upper base metal layer 18 as a plating current path. Next, the plating resist film 37 is peeled off, and then an unnecessary portion of the upper base metal layer 17 is removed by etching using the upper layer wiring 18 as a mask. As shown in FIG. The metal layer 17 remains.

  Next, as shown in FIG. 18, an overcoat film 19 made of a solder resist or the like is formed on the entire upper surface of the upper insulating film 15 including the upper wiring 18 by a screen printing method or the like. In this case, an opening 20 is formed in the overcoat film 19 in a portion corresponding to the connection pad portion of the upper layer wiring 18. Next, a solder ball 21 is formed in the opening 20 and above it by connecting it to the connection pad portion of the upper wiring 18. Next, when the overcoat film 19, the upper insulating film 15, the insulating layer 14, and the base plate 1 are cut between adjacent semiconductor structures 2, a plurality of semiconductor devices shown in FIG. 3 are obtained.

  As described above, in the manufacturing method described above, a plurality of semiconductor structures 2 are arranged on the base plate 1, and the upper layer wiring 18 and the solder balls 21 are collectively formed on the plurality of semiconductor structures 2. Thereafter, the semiconductor device is divided to obtain a plurality of semiconductor devices, so that the manufacturing process can be simplified. Further, after the manufacturing process shown in FIG. 14, a plurality of semiconductor structures 2 can be transported together with the base plate 1, so that the manufacturing process can be simplified.

  Incidentally, in the above embodiment, as shown in FIG. 1, the total number of columnar electrodes 12 is 216, but the upper wiring 18 is drawn from the 12 columnar electrodes 12 arranged on the first virtual peripheral line from the inside. Therefore, the number of usable columnar electrodes 12 is 204. Therefore, next, an embodiment in which all the columnar electrodes 12 arranged on the first virtual peripheral line from the inside can be used will be described.

(Second Embodiment)
FIG. 19 shows a plan view of a main part of a semiconductor device as a second embodiment of the present invention, and FIG. 20 shows a plan view of a semiconductor structure in the semiconductor device shown in FIG. In this semiconductor device, the arrangement pitch of the columnar electrodes 12 arranged on the first and second virtual circumferential lines from the inside is constant, but the columnar electrodes 12 arranged on the third and fourth virtual circumferential lines from the inside. The arrangement pitch is different.

  That is, the arrangement pitch of the columnar electrodes 12 arranged on the first virtual peripheral line from the inside is as small as possible, and is set to 200 μm, which is the processing limit. The arrangement pitch of the columnar electrodes 12 arranged on the second virtual circumference line from the inside is 200 μm in order to route one upper layer wiring 18 drawn from the columnar electrode 12 arranged on the first virtual circumference line from the inside. It is said.

  The arrangement pitch of the columnar electrodes 12 arranged on the third virtual circumferential line from the inside is such that one upper layer wiring 18 drawn from the columnar electrodes 12 arranged on the first and second virtual circumferential lines from the inside is one, two. In order to route six or six books, three types of 200 μm, 270 μm, and 550 μm are provided.

  The arrangement pitch of the columnar electrodes 12 arranged on the fourth virtual circumferential line from the inside is 1 for the upper layer wiring 18 drawn from the columnar electrodes 12 arranged on the first, second and third virtual circumferential lines from the inside. There are four types of 200 μm, 270 μm, 340 μm, and 1040 μm in order to route 2, 3, 3, and 13 wires.

  In other words, the interval between at least a part of the columnar electrodes 12 arranged on the nth (two or more) virtual peripheral line from the inner side is determined by (n) the upper-layer wiring 18 drawn from the columnar electrode 12 arranged on the inner side. -1) It is set as the space | interval which can be routed more than this.

  Under the above conditions, when the columnar electrodes 12 are arranged on four planar rectangular frame-shaped virtual peripheral lines having different sizes on the 5 mm × 5 mm silicon substrate 4, the result is as shown in FIG. That is, 52 columnar electrodes 12 are arranged on the first virtual circumference line from the inside, 60 columnar electrodes 12 are arranged on the second virtual circumference line from the inside, and on the third virtual circumference line from the inside. Forty-eight columnar electrodes 12 are arranged, and 52 columnar electrodes 12 are arranged on the fourth virtual peripheral line from the inside.

  Then, the total number of columnar electrodes 12 is 212, and as shown in FIG. 19, the upper-layer wiring 18 can be drawn out from all the columnar electrodes 12 arranged on the first virtual peripheral line from the inside. In this case, the number of columnar electrodes 12 that can be substantially used is larger than that in the case shown in FIG. 1 (212−204 = 8).

(Other embodiments)
In the above embodiment, the semiconductor structure 2 has the columnar electrode 12 as the external connection electrode. However, the present invention is not limited to this, and the columnar electrode 12 and the sealing film 13 are not provided. An overcoat film made of a solder resist or the like covering other than the portion is provided, and an upper layer connection pad including a base metal layer as an external connection electrode is provided on the connection pad portion of the wiring 11 and on the overcoat film in the vicinity thereof. It may be a thing. Further, the silicon substrate 4 and the base plate 1 of the semiconductor structure 2 may be rectangular.

The top view of the principal part of the semiconductor device as 1st Embodiment of this invention. FIG. 2 is a plan view of a semiconductor structure in the semiconductor device shown in FIG. 1. FIG. 2 is a longitudinal sectional view of an appropriate portion of the semiconductor device shown in FIG. 1. Sectional drawing of what was initially prepared in the case of manufacture of the semiconductor structure shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 16 is a cross-sectional view of the process following FIG. 15. FIG. 17 is a cross-sectional view of the process following FIG. 16. FIG. 18 is a cross-sectional view of the process following FIG. 17. The top view of the principal part of the semiconductor device as 2nd Embodiment of this invention. FIG. 20 is a plan view of a semiconductor structure in the semiconductor device shown in FIG. 19. The top view similar to FIG. 2 for demonstrating background art. The top view similar to FIG. 1 for demonstrating background art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Base board 2 Semiconductor structure 3 Adhesion layer 4 Silicon substrate 5 Connection pad 6 Insulating film 8 Protective film 11 Wiring 12 Columnar electrode 13 Sealing film 14 Insulating layer 15 Upper layer insulating film 18 Upper layer wiring 19 Overcoat film 21 Solder ball

Claims (17)

  A planar rectangular semiconductor substrate provided with a plurality of connection pads on the upper surface, an insulating film provided on a portion of the semiconductor substrate excluding the connection pads, and provided on the insulating film connected to the connection pads In the semiconductor device comprising a plurality of external connection electrodes, the external connection electrodes are respectively disposed on three or more planar rectangular frame-shaped virtual peripheral lines having different sizes on the semiconductor substrate, and , At least a part of the space between the external connection electrodes arranged on the nth (two or more) virtual peripheral line from the inside is defined by an upper layer wiring drawn from the external connection electrode arranged on the inside (n -1) A semiconductor device characterized in that the interval is one or more.   In the first aspect of the invention, the interval between the external connection electrodes arranged on the second virtual peripheral line from the inside is one upper layer wiring drawn from the external connection electrode arranged on the inside. A semiconductor device characterized in that it can be routed.   In the invention according to claim 2, the interval between the external connection electrodes arranged on the first virtual circumference line from the inside is between the external connection electrodes arranged on the second virtual circumference line from the inside. A semiconductor device having the same spacing.   In the invention according to claim 1, the interval between the external connection electrodes arranged on the third and subsequent virtual peripheral lines from the inside is such that the external connection electrode located at the corner and the external connection electrode A semiconductor device, which is constant except for an interval between adjacent external connection electrodes, and has an interval capable of routing the same number of upper layer wirings.   In the invention according to claim 1, the number of external connection electrodes arranged on the third and subsequent virtual peripheral lines from the inside is different from an interval in which (n-1) upper layer wirings can be routed. A semiconductor device, characterized in that the upper layer wirings are arranged at intervals that can be routed.   2. The semiconductor device according to claim 1, wherein the semiconductor substrate has a planar square shape.   The invention according to claim 1, wherein the external connection electrode is a columnar electrode provided on a connection pad portion of a wiring provided on the insulating film and connected to the connection pad. Semiconductor device.   The invention according to claim 1, wherein the external connection electrode is an upper layer connection pad provided on a connection pad portion of a wiring provided on the insulating film and connected to the connection pad. Semiconductor device.   A base plate, a semiconductor structure provided on the base board and having a planar rectangular semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate, and the semiconductor structure around the semiconductor structure A semiconductor device comprising: an insulating layer provided on a base plate; and the semiconductor structure and an upper layer wiring connected to an external connection electrode of the semiconductor structure on the insulating layer through a via hole. The external connection electrodes of the structure are respectively arranged on three or more planar rectangular frame-shaped virtual peripheral lines having different sizes on the semiconductor substrate, and the upper layer wiring is n (2 or more) from the inside. At least part of the external connection electrodes arranged on the virtual peripheral line, (n−1) upper layer wirings drawn from the external connection electrodes arranged on the inner side thereof Wherein a being routed above.   The invention according to claim 9, wherein the upper layer wiring is routed by one in the interval between the external connection electrodes arranged on the second virtual peripheral line from the inside of the semiconductor structure. A featured semiconductor device.   The space between the external connection electrodes arranged on the first virtual circumference line from the inside of the semiconductor structure is the second virtual circumference line from the inside of the semiconductor structure. A semiconductor device having the same interval between the arranged external connection electrodes.   In the invention according to claim 9, an interval between the external connection electrodes arranged on the third and subsequent virtual peripheral lines from the inside of the semiconductor structure is set between the external connection electrodes located at corners and the external connection electrodes. A semiconductor device, which is constant except for an interval with an external connection electrode located adjacent to the external connection electrode, and the same number of the upper layer wirings are routed.   In the invention according to claim 9, between the external connection electrodes arranged on the third and subsequent virtual peripheral lines from the inside of the semiconductor structure, the upper layer wiring (n -1) A semiconductor device characterized in that a number different from the number is routed.   10. The semiconductor device according to claim 9, wherein the base plate and the semiconductor substrate have a planar square shape.   10. The semiconductor device according to claim 9, further comprising an overcoat film that covers a portion other than the connection pad portion of the upper wiring.   16. The semiconductor device according to claim 15, wherein a solder ball is provided on a connection pad portion of the upper layer wiring.   17. The semiconductor device according to claim 16, wherein the solder ball is disposed only on a region corresponding to the insulating layer.

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