JP4442181B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4442181B2
JP4442181B2 JP2003347797A JP2003347797A JP4442181B2 JP 4442181 B2 JP4442181 B2 JP 4442181B2 JP 2003347797 A JP2003347797 A JP 2003347797A JP 2003347797 A JP2003347797 A JP 2003347797A JP 4442181 B2 JP4442181 B2 JP 4442181B2
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rewiring
layer
connection
thin film
circuit element
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JP2005116714A (en
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伸治 脇坂
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Casio Computer Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

Description

この発明は半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

従来の半導体装置には、集積回路が形成されて接続パッドを有する半導体基板が配線基板に埋め込まれ、接続パッドに接続される外部接続用の端子が配線基板上に形成されるようにしたものがある。また、このような半導体装置において、半導体基板上に設けられた絶縁膜上に２つの端子部を有する薄膜回路素子が設けられ、薄膜回路素子の両端子部が絶縁膜上に設けられた接続配線を介して接続パッドに接続されるように構成されたものがある。そして、薄膜回路素子として薄膜コイル素子（誘導素子）を設けるようにしたものがある。（例えば、特許文献１参照）   In a conventional semiconductor device, an integrated circuit is formed, a semiconductor substrate having connection pads is embedded in the wiring substrate, and terminals for external connection connected to the connection pads are formed on the wiring substrate. is there. Further, in such a semiconductor device, a thin film circuit element having two terminal portions is provided on an insulating film provided on a semiconductor substrate, and both terminal portions of the thin film circuit element are provided on the insulating film. Some are configured to be connected to the connection pad via the connector. Some thin film coil elements (inductive elements) are provided as thin film circuit elements. (For example, see Patent Document 1)

特開平９−１８１２６４号公報JP-A-9-181264

しかしながら、上記従来の半導体装置では、半導体基板上に薄膜回路素子として薄膜コイル素子を設けるようにした場合、薄膜コイル素子は渦巻き状の形状を有するため、２つの端子部のうちの一方の内端部は渦巻き状の形状の中央部に形成され、該内端部を接続パッドに接続するためにはそれ専用の接続配線を絶縁膜下に形成し、この接続配線に薄膜コイル素子の内端部を接続させるためのそれ専用のコンタクトホールを絶縁膜に形成しなければならず、製造工程数が増加するという問題がある。   However, in the above-described conventional semiconductor device, when a thin film coil element is provided as a thin film circuit element on a semiconductor substrate, the thin film coil element has a spiral shape, so one inner end of two terminal portions. The part is formed at the center of the spiral shape, and in order to connect the inner end to the connection pad, a dedicated connection wiring is formed under the insulating film, and the inner end of the thin film coil element is formed on the connection wiring. There is a problem in that the number of manufacturing steps increases because a dedicated contact hole for connecting the two must be formed in the insulating film.

そこで、この発明は、製造工程数を増加することなく、薄膜回路素子を形成することができる半導体装置およびその製造方法を提供することを目的とする。   In view of the above, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can form a thin film circuit element without increasing the number of manufacturing steps.

請求項１に記載の発明は、ベース板と、前記ベース板上に設けられ、且つ、複数の接続パッドを有する半導体基板および該半導体基板上に前記接続パッドに電気的に接続されて設けられた再配線を有する半導体構成体と、前記半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、前記半導体構成体および前記絶縁層上に設けられた少なくとも１層の上層絶縁膜と、前記上層絶縁膜の何れかの層上に前記半導体構成体の再配線の接続パッド部に電気的に接続されて設けられ、外部接続用の接続パッド部を備える少なくとも１層の上層再配線と、２つの端部を有し、前記再配線と前記上層再配線の何れかの層の一方と同一の平面上に設けられ、一端部が前記接続パッドに電気的に接続された薄膜回路素子と、前記再配線と前記上層再配線の何れかの層の他方と同一の平面上に設けられ、前記薄膜回路素子の他端部および前記接続パッドに電気的に接続された接続配線と、を備えていることを特徴とするものである。
請求項２に記載の発明は、請求項１に記載の発明において、前記薄膜回路素子は前記再配線と同一の平面上に設けられ、前記接続配線は前記上層再配線と同一の平面上に設けられていることを特徴とするものである。
請求項３に記載の発明は、請求項１に記載の発明において、前記薄膜回路素子は前記上層再配線と同一の平面上に設けられ、前記接続配線は前記再配線と同一の平面上に設けられていることを特徴とするものである。
請求項４に記載の発明は、請求項１に記載の発明において、前記薄膜回路素子は、渦巻き状の形状を備える誘導素子であることを特徴とするものである。
請求項５に記載の発明は、請求項１に記載の発明において、前記上層絶縁膜上に、前記上層再配線の前記外部接続用の接続パッド部を除く部分を覆う最上層絶縁膜を有することを特徴とするものである。
請求項６に記載の発明は、請求項５に記載の発明において、前記上層再配線の接続パッド部上に半田ボールが設けられていることを特徴とするものである。
請求項７に記載の発明は、ベース板と、前記ベース板上に設けられ、且つ、複数の接続パッドを有する半導体基板および該半導体基板上に前記接続パッドに電気的に接続されて設けられた再配線を有する半導体構成体と、前記半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、前記半導体構成体および前記絶縁層上に設けられた複数層の上層絶縁膜と、前記各上層絶縁膜上に層間で互いに接続され、且つ、前記半導体構成体の再配線の接続パッド部に接続されて設けられ、外部接続用の接続パッド部を備える複数層の上層再配線と、２つの端部を有し、前記複数層の上層再配線のうちの１層と同一の平面上に設けられ、一端部が前記接続パッドに電気的に接続された薄膜回路素子と、前記複数層の上層再配線のうちの他の１層と同一の平面上に設けられ、前記薄膜回路素子の他端部および前記接続パッドに電気的に接続された接続配線とを備えていることを特徴とする半導体装置。
請求項８に記載の発明は、請求項７に記載の発明において、前記接続配線は、前記複数層の上層絶縁膜における前記薄膜回路素子が設けられた層より上層の絶縁膜上に設けられていることを特徴とするものである。
請求項９に記載の発明は、請求項７に記載の発明において、前記接続配線は、前記複数層の上層絶縁膜における前記薄膜回路素子が設けられた層より下層の絶縁膜上に設けられていることを特徴とするものである。
請求項１０に記載の発明は、請求項７に記載の発明において、前記薄膜回路素子は、渦巻き状の形状を備える誘導素子であることを特徴とするものである。
請求項１１に記載の発明は、請求項７に記載の発明において、前記上層絶縁膜上に、前記上層再配線の前記外部接続用の接続パッド部を除く部分を覆う最上層絶縁膜を有することを特徴とするものである。
請求項１２に記載の発明は、請求項５または１１に記載の発明において、前記上層再配線の前記外部接続用の接続パッド部上に半田ボールが設けられていることを特徴とするものである。
請求項１３に記載の発明は、請求項１または７に記載の発明において、前記半導体構成体は、前記再配線に接続された柱状電極と、前記柱状電極の上端面を除き、少なくとも前記半導体基板の上面を覆う封止膜と、を有するものであることを特徴とするものである。
請求項１４に記載の発明は、ベース板と、前記ベース板上に設けられ、且つ、複数の接続パッドを有する半導体基板および該半導体基板上に前記接続パッドに電気的に接続されて設けられた再配線を有する半導体構成体と、前記半導体構成体の周囲における前記ベース板上に設けられた少なくとも１層の絶縁層と、前記半導体構成体および前記絶縁層上に設けられた上層絶縁膜と、前記上層絶縁膜の何れかの層上に前記半導体構成体の再配線の接続パッド部に電気的に接続されて設けられ、外部接続用の接続パッド部を備える少なくとも１層の上層再配線と、２つの端部を有し、前記再配線と前記上層再配線の何れかの層とのうちの一方と同一の平面上に設けられ、一端部が前記接続パッドに電気的に接続された薄膜回路素子と、前記再配線と前記上層再配線の何れかの層の他方と同一の平面上に設けられ、前記薄膜回路素子の他端部および前記接続パッドに電気的に接続された接続配線とを備えた半導体装置の製造方法において、前記再配線と前記上層再配線の何れかの層の一方と前記薄膜回路素子とを同一の材料によって同時に形成し、前記再配線と前記上層再配線の何れかの層の他方と前記接続配線とを同一の材料によって同時に形成することを特徴とするものである。
請求項１５に記載の発明は、請求項１４に記載の発明において、前記再配線と前記薄膜回路素子とを同一の平面上に形成し、前記上層再配線と前記接続配線とを同一の平面上に形成することを特徴とするものである。
請求項１６に記載の発明は、請求項１４に記載の発明において、前記上層再配線と前記薄膜回路素子とを同一の平面上に形成し、前記再配線と前記接続配線とを同一の平面上に形成することを特徴とするものである。
請求項１７に記載の発明は、ベース板と、前記ベース板上に設けられ、且つ、複数の接続パッドを有する半導体基板および該半導体基板上に前記接続パッドに電気的に接続されて設けられた再配線を有する半導体構成体と、前記半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、前記半導体構成体および前記絶縁層上に設けられた複数層の上層絶縁膜と、前記各上層絶縁膜上に層間で互いに接続され、且つ、前記半導体構成体の再配線の接続パッド部に接続されて設けられ、外部接続用の接続パッド部を備える複数層の上層再配線と、２つの端部を有し、前記複数層の上層再配線のうちの１層と同一の平面上に設けられ、一端部が前記接続パッドに電気的に接続された薄膜回路素子と、前記複数層の上層再配線のうちの他の１層と同一の平面上に設けられ、前記薄膜回路素子の他端部および前記接続パッドに電気的に接続された接続配線とを備えた半導体装置の製造方法において、前記複数層の上層再配線のうちの１層と前記薄膜回路素子とを同一の材料によって同時に形成し、前記複数層の上層再配線のうちの他の１層と前記接続配線とを同一の材料によって同時に形成することを特徴とするものである。
請求項１８に記載の発明は、請求項１７に記載の発明において、前記接続配線を、前記複数層の上層絶縁膜における前記薄膜回路素子が設けられた層より上層の絶縁膜上に形成することを特徴とするものである。
請求項１９に記載の発明は、請求項１７に記載の発明において、前記接続配線を、前記複数層の上層絶縁膜における前記薄膜回路素子が設けられた層より下層の絶縁膜上に形成することを特徴とするものである。 The invention described in claim 1 is provided with a base plate, a semiconductor substrate provided on the base plate and having a plurality of connection pads, and electrically connected to the connection pads on the semiconductor substrate. A semiconductor structure having rewiring; an insulating layer provided on the base plate around the semiconductor structure; and at least one upper insulating film provided on the semiconductor structure and the insulating layer; At least one upper layer redistribution provided with a connection pad portion for external connection, provided on any layer of the upper insulating film and electrically connected to a connection pad portion for rewiring of the semiconductor structure; A thin film circuit element having two ends, provided on the same plane as one of the layers of the rewiring and the upper layer rewiring, and having one end electrically connected to the connection pad; The rewiring and the upper layer A wiring that is provided on the same plane as the other of the layers of the wiring and that is electrically connected to the other end of the thin film circuit element and the connection pad; It is.
The invention according to claim 2 is the invention according to claim 1, wherein the thin film circuit element is provided on the same plane as the rewiring, and the connection wiring is provided on the same plane as the upper layer rewiring. It is characterized by being.
According to a third aspect of the present invention, in the first aspect of the present invention, the thin film circuit element is provided on the same plane as the upper layer rewiring, and the connection wiring is provided on the same plane as the rewiring. It is characterized by being.
According to a fourth aspect of the present invention, in the first aspect of the present invention, the thin film circuit element is an inductive element having a spiral shape.
According to a fifth aspect of the present invention, in the first aspect of the invention, the upper layer insulating film has an uppermost layer insulating film covering a portion of the upper layer rewiring except for the connection pad portion for external connection on the upper layer insulating film. It is characterized by.
According to a sixth aspect of the invention, in the fifth aspect of the invention, a solder ball is provided on the connection pad portion of the upper layer rewiring.
The invention according to claim 7 is provided with a base plate, a semiconductor substrate provided on the base plate and having a plurality of connection pads, and electrically connected to the connection pads on the semiconductor substrate. A semiconductor structure having rewiring; an insulating layer provided on the base plate around the semiconductor structure; a plurality of upper insulating films provided on the semiconductor structure and the insulating layer; A plurality of upper layer rewirings connected to each other on each upper insulating film and connected to a connection pad portion for rewiring of the semiconductor structure, and provided with a connection pad portion for external connection; A thin film circuit element having one end, provided on the same plane as one layer of the plurality of upper layer rewirings, and having one end electrically connected to the connection pad; and The other one of the upper layer rewiring The semiconductor device characterized by being provided on the same plane, and an electrically connected connection wiring to the other end and the connection pad of the thin-film circuit elements and.
The invention according to an eighth aspect is the invention according to the seventh aspect, wherein the connection wiring is provided on an insulating film in a layer above the layer in which the thin film circuit element is provided in the upper insulating film in the plurality of layers. It is characterized by being.
The invention according to claim 9 is the invention according to claim 7, wherein the connection wiring is provided on an insulating film below the layer in which the thin film circuit element is provided in the upper insulating film of the plurality of layers. It is characterized by being.
The invention according to claim 10 is the invention according to claim 7, wherein the thin film circuit element is an inductive element having a spiral shape.
According to an eleventh aspect of the present invention, in the seventh aspect of the present invention, the upper layer insulating film is provided on the upper layer insulating film so as to cover a portion of the upper layer rewiring except the connection pad portion for external connection. It is characterized by.
The invention described in claim 12 is characterized in that, in the invention described in claim 5 or 11, a solder ball is provided on the connection pad portion for external connection of the upper layer rewiring. .
The invention according to claim 13 is the invention according to claim 1 or 7, wherein the semiconductor structure includes at least the semiconductor substrate except for a columnar electrode connected to the rewiring and an upper end surface of the columnar electrode. And a sealing film covering the upper surface of the substrate.
The invention described in claim 14 is provided with a base plate, a semiconductor substrate provided on the base plate and having a plurality of connection pads, and electrically connected to the connection pads on the semiconductor substrate. A semiconductor structure having rewiring; an at least one insulating layer provided on the base plate around the semiconductor structure; an upper insulating film provided on the semiconductor structure and the insulating layer; At least one upper layer redistribution provided with a connection pad portion for external connection, provided on any layer of the upper insulating film and electrically connected to a connection pad portion for rewiring of the semiconductor structure; A thin film circuit having two ends, provided on the same plane as one of the rewiring and any one of the upper layer rewirings, and having one end electrically connected to the connection pad Element and said rewiring A method of manufacturing a semiconductor device comprising a connection wiring provided on the same plane as the other of any one of the upper layer rewirings and electrically connected to the other end of the thin film circuit element and the connection pad In this case, one of the layers of the rewiring and the upper layer rewiring and the thin film circuit element are simultaneously formed of the same material, and the other of the layers of the rewiring and the upper layer rewiring and the connection The wiring is formed of the same material at the same time.
The invention according to claim 15 is the invention according to claim 14, wherein the rewiring and the thin film circuit element are formed on the same plane, and the upper layer rewiring and the connection wiring are on the same plane. It is characterized by forming.
The invention according to claim 16 is the invention according to claim 14, wherein the upper layer rewiring and the thin film circuit element are formed on the same plane, and the rewiring and the connection wiring are on the same plane. It is characterized by forming.
The invention described in claim 17 is provided with a base plate, a semiconductor substrate provided on the base plate and having a plurality of connection pads, and electrically connected to the connection pads on the semiconductor substrate. A semiconductor structure having rewiring; an insulating layer provided on the base plate around the semiconductor structure; a plurality of upper insulating films provided on the semiconductor structure and the insulating layer; A plurality of upper layer rewirings connected to each other on each upper insulating film and connected to a connection pad portion for rewiring of the semiconductor structure, and provided with a connection pad portion for external connection; A thin film circuit element having one end, provided on the same plane as one layer of the plurality of upper layer rewirings, and having one end electrically connected to the connection pad; and Other of the upper layer rewiring In the method of manufacturing a semiconductor device, comprising a connection wiring provided on the same plane as the layer and electrically connected to the other end of the thin film circuit element and the connection pad, One of the layers and the thin film circuit element are simultaneously formed of the same material, and the other one of the plurality of upper layer rewirings and the connection wiring are simultaneously formed of the same material. To do.
According to an eighteenth aspect of the present invention, in the invention of the seventeenth aspect, the connection wiring is formed on an insulating film above the layer in which the thin film circuit element is provided in the upper insulating film of the plurality of layers. It is characterized by.
According to a nineteenth aspect of the present invention, in the invention according to the seventeenth aspect, the connection wiring is formed on an insulating film below the layer in which the thin film circuit element is provided in the upper insulating film of the plurality of layers. It is characterized by.

この発明によれば、接続パッドと接続パッドに接続される再配線を有する半導体基板が埋め込まれ、再配線に接続されて形成される上層再配線を介して外部接続用の端子が形成される半導体装置およびその製造方法において、例えば、再配線と上層再配線の一方と同一の平面上に薄膜回路素子を設け、再配線と上層再配線の他方と同一の平面上に接続配線を薄膜回路素子の一端部に接続されて設けているので、再配線と上層再配線の一方と薄膜回路素子とを同一の材料によって同時に形成し、再配線と上層再配線の他方と接続配線とを同一の材料によって同時に形成することができ、したがって製造工程数を増加することなく、薄膜回路素子を形成することができる。   According to this invention, a semiconductor substrate having a connection pad and a rewiring connected to the connection pad is embedded, and a terminal for external connection is formed via an upper layer rewiring formed by being connected to the rewiring In the apparatus and the manufacturing method thereof, for example, the thin film circuit element is provided on the same plane as one of the rewiring and the upper layer rewiring, and the connection wiring is provided on the same plane as the other of the rewiring and the upper layer rewiring. Since it is connected to one end, one of the rewiring and upper layer rewiring and the thin film circuit element are simultaneously formed of the same material, and the other of the rewiring and upper layer rewiring and the connection wiring are formed of the same material. Thus, the thin film circuit elements can be formed without increasing the number of manufacturing steps.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の一部の平面図を示し、図２は図１のII−II線に沿う断面図を示し、図３は図１のIII−III線に沿う断面図を示す。この半導体装置は平面方形状のベース板１を備えている。ベース板１は、ガラス繊維、アラミド繊維、液晶繊維等にエポキシ系樹脂、ポリイミド系樹脂、ＢＴ（ビスマレイミド・トリアジン）樹脂、ＰＰＥ（ポリフェニレンエーテル）等を含浸させたもの、シリコン、ガラス、セラミックス、樹脂単体等の絶縁材料、あるいは、銅やアルミニウム等の金属材料からなっている。 (First embodiment)
1 is a plan view of a part of a semiconductor device as a first embodiment of the present invention, FIG. 2 is a sectional view taken along line II-II in FIG. 1, and FIG. 3 is a line III-III in FIG. FIG. This semiconductor device includes a base plate 1 having a planar square shape. The base plate 1 is made of glass fiber, aramid fiber, liquid crystal fiber or the like impregnated with epoxy resin, polyimide resin, BT (bismaleimide / triazine) resin, PPE (polyphenylene ether), silicon, glass, ceramics, It is made of an insulating material such as a single resin, or a metal material such as copper or aluminum.

ベース板１の上面には、ベース板１のサイズよりもある程度小さいサイズの平面方形状の半導体構成体２の下面がダイボンド材からなる接着層３を介して接着されている。この場合、半導体構成体２は、後述する再配線、柱状電極、封止膜を有しており、一般的にはＣＳＰ(chip size package)と呼ばれるものであり、特に、後述の如く、シリコンウエハ上に再配線、柱状電極、封止膜を形成した後、ダイシングにより個々の半導体構成体２を得る方法を採用しているため、特に、ウエハレベルＣＳＰ（Ｗ−ＣＳＰ）とも言われている。ただし、この場合、半導体構成体２は、後述する渦巻き状の薄膜コイル素子を形成する構成の一部を有する。以下に、半導体構成体２の構成について説明する。   On the upper surface of the base plate 1, the lower surface of the planar rectangular semiconductor structure 2 having a size somewhat smaller than the size of the base plate 1 is bonded via an adhesive layer 3 made of a die bond material. In this case, the semiconductor structure 2 has a rewiring, a columnar electrode, and a sealing film, which will be described later, and is generally called a CSP (chip size package). Since a method of obtaining individual semiconductor structures 2 by dicing after forming rewiring, columnar electrodes, and a sealing film thereon is employed, it is also called wafer level CSP (W-CSP). However, in this case, the semiconductor structure 2 has a part of a structure for forming a spiral thin film coil element to be described later. Below, the structure of the semiconductor structure 2 is demonstrated.

半導体構成体２は平面方形状のシリコン基板（半導体基板）４を備えている。シリコン基板４は接着層３を介してベース板１に接着されている。シリコン基板４の上面には所定の機能の集積回路（図示せず）が設けられ、上面周辺部にはアルミニウム系金属等からなる複数の接続パッド５、６が集積回路に接続されて設けられている。この場合、符号６で示す接続パッドは、後述する渦巻き状の薄膜コイル素子の両端部に接続されるものであり、シリコン基板４上に少なくとも２つ設けられている。   The semiconductor structure 2 includes a planar rectangular silicon substrate (semiconductor substrate) 4. The silicon substrate 4 is bonded to the base plate 1 via the adhesive layer 3. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 4, and a plurality of connection pads 5 and 6 made of aluminum metal or the like are provided on the periphery of the upper surface so as to be connected to the integrated circuit. Yes. In this case, connection pads indicated by reference numeral 6 are connected to both ends of a spiral thin film coil element described later, and are provided on the silicon substrate 4 at least two.

接続パッド５、６の中央部を除くシリコン基板４の上面には酸化シリコン等からなる絶縁膜７が設けられ、接続パッド５、６の中央部は絶縁膜７に設けられた開口部８を介して露出されている。絶縁膜７の上面にはエポキシ系樹脂やポリイミド系樹脂等からなる保護膜（絶縁膜）９が設けられている。この場合、絶縁膜７の開口部８に対応する部分における保護膜９には開口部１０が設けられている。   An insulating film 7 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 4 except for the central part of the connection pads 5 and 6, and the central part of the connection pads 5 and 6 is provided through an opening 8 provided in the insulating film 7. Is exposed. A protective film (insulating film) 9 made of an epoxy resin, a polyimide resin, or the like is provided on the upper surface of the insulating film 7. In this case, an opening 10 is provided in the protective film 9 in a portion corresponding to the opening 8 of the insulating film 7.

両開口部８、１０を介して露出された接続パッド５、６の上面から保護膜９の上面の所定の箇所にかけて、銅等からなる下地金属層１１、１２、１３が設けられている。下地金属層１１、１２、１３の上面全体には銅からなる再配線１４および第１、第２の接続配線１５、１６が設けられている。   Underlying metal layers 11, 12, 13 made of copper or the like are provided from the upper surfaces of the connection pads 5, 6 exposed through the openings 8, 10 to predetermined positions on the upper surface of the protective film 9. A rewiring 14 made of copper and first and second connection wirings 15 and 16 are provided on the entire upper surface of the base metal layers 11, 12 and 13.

保護膜９の上面には銅等からなる薄膜コイル素子用下地金属層１７が渦巻き状に設けられている。薄膜コイル素子用下地金属層１７の上面全体には銅からなる薄膜コイル素子（薄膜回路素子）１８が設けられている。薄膜コイル素子１８の内端部は正方形状の接続パッド部１９となっている。薄膜コイル素子１８の外端部を含む下地金属層１７は、第１の接続配線１５を含む下地金属層１２を介して一方の薄膜コイル素子用の接続パッド６に接続されている。   A base metal layer 17 for a thin film coil element made of copper or the like is provided on the upper surface of the protective film 9 in a spiral shape. A thin film coil element (thin film circuit element) 18 made of copper is provided on the entire upper surface of the base metal layer 17 for the thin film coil element. The inner end portion of the thin film coil element 18 is a square connection pad portion 19. The base metal layer 17 including the outer end portion of the thin film coil element 18 is connected to the connection pad 6 for one thin film coil element through the base metal layer 12 including the first connection wiring 15.

再配線１４の接続パッド部上面には銅からなる柱状電極２０が設けられている。薄膜コイル素子１８の接続パッド部１９上面には柱状電極２１が設けられている。第２の接続配線１６の接続パッド部上面には銅からなる柱状電極２２が設けられている。再配線１４、第１、第２の接続配線１５、１６および薄膜コイル素子１８を含む保護膜９の上面にはエポキシ系樹脂やポリイミド系樹脂等からなる封止膜（絶縁膜）２３がその上面が柱状電極２０、２１、２２の上面と面一となるように設けられている。   A columnar electrode 20 made of copper is provided on the upper surface of the connection pad portion of the rewiring 14. A columnar electrode 21 is provided on the upper surface of the connection pad portion 19 of the thin film coil element 18. A columnar electrode 22 made of copper is provided on the upper surface of the connection pad portion of the second connection wiring 16. On the upper surface of the protective film 9 including the rewiring 14, the first and second connection wirings 15 and 16, and the thin film coil element 18, a sealing film (insulating film) 23 made of epoxy resin, polyimide resin, or the like is the upper surface. Is provided so as to be flush with the upper surfaces of the columnar electrodes 20, 21, 22.

このように、Ｗ−ＣＳＰと呼ばれる半導体構成体２は、シリコン基板４、接続パッド５、絶縁膜７を含み、さらに、保護膜９、再配線１４、第１、第２の接続配線１５、１６、薄膜コイル素子１８、柱状電極２０、２１、２２、封止膜２３を含んで構成されている。   Thus, the semiconductor structure 2 called W-CSP includes the silicon substrate 4, the connection pad 5, and the insulating film 7, and further includes the protective film 9, the rewiring 14, and the first and second connection wirings 15 and 16. The thin film coil element 18, the columnar electrodes 20, 21 and 22, and the sealing film 23 are configured.

半導体構成体２の周囲におけるベース板１の上面には方形枠状の絶縁層２４がその上面が半導体構成体２の上面とほぼ面一となるように設けられている。絶縁層２４は、例えば、熱可塑性樹脂中にガラス繊維やシリカフィラー等の補強材を分散させたものである。   A rectangular frame-shaped insulating layer 24 is provided on the upper surface of the base plate 1 around the semiconductor structure 2 so that the upper surface is substantially flush with the upper surface of the semiconductor structure 2. The insulating layer 24 is made of, for example, a reinforcing material such as glass fiber or silica filler dispersed in a thermoplastic resin.

半導体構成体２および絶縁層２４の上面には上層絶縁膜２５がその上面を平坦とされて設けられている。上層絶縁膜２５は、ビルドアップ基板に用いられる、通常、ビルドアップ材と言われるもので、例えば、エポキシ系樹脂やＢＴ樹脂等の熱硬化性樹脂中に繊維やフィラー等の補強材を含有させたものである。この場合、繊維は、ガラス繊維やアラミド繊維等である。フィラーは、シリカフィラーやセラミックス系フィラー等である。   An upper insulating film 25 is provided on the upper surfaces of the semiconductor structure 2 and the insulating layer 24 so that the upper surface is flat. The upper insulating film 25 is generally used as a build-up material used for a build-up substrate. For example, a reinforcing material such as a fiber or a filler is contained in a thermosetting resin such as an epoxy resin or a BT resin. It is a thing. In this case, the fiber is glass fiber, aramid fiber, or the like. The filler is a silica filler or a ceramic filler.

上層絶縁膜２５の上面には銅等からなる上層下地金属層２６、２７が設けられている。上層下地金属層２６、２７の上面全体には銅からなる上層再配線２８および第３の接続配線２９が設けられている。上層再配線２８を含む上層下地金属層２６は、柱状電極２０の上面中央部に対応する部分における上層絶縁膜２５に設けられた開口部３０を介して柱状電極２０の上面に接続されている。   On the upper surface of the upper insulating film 25, upper base metal layers 26 and 27 made of copper or the like are provided. An upper layer rewiring 28 and a third connection wiring 29 made of copper are provided on the entire upper surface of the upper base metal layers 26 and 27. The upper base metal layer 26 including the upper layer rewiring 28 is connected to the upper surface of the columnar electrode 20 through an opening 30 provided in the upper insulating film 25 in a portion corresponding to the central portion of the upper surface of the columnar electrode 20.

第３の接続配線２９の一端部を含む上層下地金属層２７は、柱状電極２１の上面中央部に対応する部分における上層絶縁膜２５に設けられた開口部３１を介して柱状電極２１の上面に接続されている。第３の接続配線２９の他端部を含む上層下地金属層２７は、柱状電極２２の上面中央部に対応する部分における上層絶縁膜２５に設けられた開口部３２を介して柱状電極２２の上面に接続されている。したがって、薄膜コイル素子１８の接続パッド部１９は、柱状電極２１、第３の接続配線２９を含む上層下地金属層２７、柱状電極２２、第２の接続配線１６を含む下地金属層１３を介して他方の薄膜コイル素子用の接続パッド６に接続されている。   The upper base metal layer 27 including one end portion of the third connection wiring 29 is formed on the upper surface of the columnar electrode 21 via the opening 31 provided in the upper insulating film 25 in a portion corresponding to the central portion of the upper surface of the columnar electrode 21. It is connected. The upper base metal layer 27 including the other end portion of the third connection wiring 29 is formed on the upper surface of the columnar electrode 22 through the opening 32 provided in the upper insulating film 25 in a portion corresponding to the center of the upper surface of the columnar electrode 22. It is connected to the. Therefore, the connection pad portion 19 of the thin film coil element 18 is interposed via the columnar electrode 21, the upper base metal layer 27 including the third connection wiring 29, the columnar electrode 22, and the base metal layer 13 including the second connection wiring 16. It is connected to the connection pad 6 for the other thin film coil element.

上層再配線２８を含む上層絶縁膜２５の上面にはソルダーレジスト等からなるオーバーコート膜（最上層絶縁膜）３３が設けられている。上層再配線２８の接続パッド部に対応する部分におけるオーバーコート膜３３には開口部３４が設けられている。開口部３４内およびその上方には半田ボール３５が上層再配線２８の接続パッド部に接続されて設けられている。複数の半田ボール３５は、図１では、オーバーコート膜３３の上面外周部のみに図示しているが、実際には、オーバーコート膜３３の上面にマトリクス状に配置されている。   An overcoat film (uppermost layer insulating film) 33 made of a solder resist or the like is provided on the upper surface of the upper layer insulating film 25 including the upper layer rewiring 28. An opening 34 is provided in the overcoat film 33 in a portion corresponding to the connection pad portion of the upper layer rewiring 28. Solder balls 35 are provided in and above the opening 34 so as to be connected to the connection pad portion of the upper layer rewiring 28. In FIG. 1, the plurality of solder balls 35 are illustrated only on the outer peripheral portion of the upper surface of the overcoat film 33, but actually, are arranged in a matrix on the upper surface of the overcoat film 33.

ところで、ベース板１のサイズを半導体構成体２のサイズよりもある程度大きくしているのは、シリコン基板４上の接続パッド５の数の増加に応じて、半田ボール３５の配置領域を半導体構成体２のサイズよりもある程度大きくし、これにより、上層再配線２８の接続パッド部（オーバーコート膜３３の開口部３４内の部分）のサイズおよびピッチを柱状電極２０のサイズおよびピッチよりも大きくするためである。   By the way, the size of the base plate 1 is made somewhat larger than the size of the semiconductor structure 2 because the area where the solder balls 35 are arranged is increased as the number of connection pads 5 on the silicon substrate 4 increases. In order to make the size and pitch of the connection pad portion (portion in the opening 34 of the overcoat film 33) of the upper layer rewiring 28 larger than that of the columnar electrode 20. It is.

このため、マトリクス状に配置された上層再配線２８の接続パッド部は、半導体構成体２に対応する領域のみでなく、半導体構成体２の側面の外側に設けられた絶縁層２４に対応する領域上にも配置されている。つまり、マトリクス状に配置された半田ボール３５のうち、少なくとも最外周の半田ボール３５は半導体構成体２よりも外側に位置する周囲に配置されている。   Therefore, the connection pad portion of the upper layer rewiring 28 arranged in a matrix form not only the region corresponding to the semiconductor structure 2 but also the region corresponding to the insulating layer 24 provided outside the side surface of the semiconductor structure 2. It is also arranged on the top. That is, among the solder balls 35 arranged in a matrix, at least the outermost solder balls 35 are arranged around the semiconductor structure 2.

次に、この半導体装置の製造方法の一例について説明する。ただし、この場合、図示の都合上、図２に示す半導体装置の製造方法について説明し、図３に示す第２の接続配線１６および柱状電極２２等についてはその説明を省略する。まず、半導体構成体２の製造方法について説明する。   Next, an example of a method for manufacturing this semiconductor device will be described. However, in this case, for the sake of illustration, the method for manufacturing the semiconductor device shown in FIG. 2 will be described, and the description of the second connection wiring 16 and the columnar electrode 22 shown in FIG. 3 will be omitted. First, a method for manufacturing the semiconductor structure 2 will be described.

図４に示すように、ウエハ状態のシリコン基板４上にアルミニウム系金属等からなる接続パッド５、６、酸化シリコン等からなる絶縁膜７およびエポキシ系樹脂やポリイミド系樹脂等からなる保護膜９が設けられ、接続パッド５、６の中央部が絶縁膜７および保護膜９に形成された開口部８、１０を介して露出されたものを用意する。上記において、ウエハ状態のシリコン基板４には、各半導体構成体が形成される領域に所定の機能の集積回路が形成され、接続パッド５、６は、それぞれ、対応する領域に形成された集積回路に電気的に接続されている。   As shown in FIG. 4, on the silicon substrate 4 in a wafer state, connection pads 5 and 6 made of aluminum-based metal, an insulating film 7 made of silicon oxide or the like, and a protective film 9 made of epoxy-based resin or polyimide-based resin are formed. Provided are those in which the central portions of the connection pads 5 and 6 are exposed through the openings 8 and 10 formed in the insulating film 7 and the protective film 9. In the above, on the silicon substrate 4 in the wafer state, an integrated circuit having a predetermined function is formed in a region where each semiconductor structure is formed, and the connection pads 5 and 6 are integrated circuits formed in the corresponding regions, respectively. Is electrically connected.

次に、図５に示すように、両開口部８、１０を介して露出された接続パッド５、６の上面を含む保護膜９の上面全体に下地金属層４１を形成する。この場合、下地金属層４１は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。これは、後述する上層下地金属層５５の場合も同様である。   Next, as shown in FIG. 5, a base metal layer 41 is formed on the entire upper surface of the protective film 9 including the upper surfaces of the connection pads 5 and 6 exposed through the openings 8 and 10. In this case, the base metal layer 41 may be only a copper layer formed by electroless plating, may be only a copper layer formed by sputtering, or a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering. The same applies to the case of the upper base metal layer 55 described later.

次に、下地金属層４１の上面にメッキレジスト膜４２をパターン形成する。この場合、再配線１４形成領域、第１の接続配線１５形成領域および薄膜コイル素子１８形成領域に対応する部分におけるメッキレジスト膜４２には開口部４３、４４、４５が形成されている。次に、下地金属層４１をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜４２の開口部４３、４４、４５内の下地金属層４１の上面に再配線１４、第１の接続配線１５および薄膜コイル素子１８を形成する。次に、メッキレジスト膜４２を剥離する。   Next, a plating resist film 42 is patterned on the upper surface of the base metal layer 41. In this case, openings 43, 44, 45 are formed in the plating resist film 42 in portions corresponding to the rewiring 14 formation region, the first connection wiring 15 formation region, and the thin film coil element 18 formation region. Next, by performing electrolytic plating of copper using the base metal layer 41 as a plating current path, the rewiring 14 and the first connection are formed on the upper surface of the base metal layer 41 in the openings 43, 44, 45 of the plating resist film 42. The wiring 15 and the thin film coil element 18 are formed. Next, the plating resist film 42 is peeled off.

次に、図６に示すように、再配線１４、第１の接続配線１５および薄膜コイル素子１８を含む下地金属層４１の上面にメッキレジスト膜４６をパターン形成する。この場合、柱状電極２０形成領域および柱状電極２１形成領域に対応する部分におけるメッキレジスト膜４６には開口部４７、４８が形成されている。次に、下地金属層４１をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜４６の開口部４７、４８内の再配線１４の接続パッド部上面および薄膜コイル素子１８の接続パッド部１９上面に柱状電極２０、２１を形成する。   Next, as shown in FIG. 6, a plating resist film 46 is formed on the upper surface of the base metal layer 41 including the rewiring 14, the first connection wiring 15, and the thin film coil element 18. In this case, openings 47 and 48 are formed in the plating resist film 46 in portions corresponding to the columnar electrode 20 formation region and the columnar electrode 21 formation region. Next, by performing electrolytic plating of copper using the base metal layer 41 as a plating current path, the upper surface of the connection pad portion of the rewiring 14 in the openings 47 and 48 of the plating resist film 46 and the connection pad portion of the thin film coil element 18 are formed. 19 Columnar electrodes 20 and 21 are formed on the upper surface.

次に、メッキレジスト膜４６を剥離し、次いで、柱状電極２０、２１、再配線１４、第１の接続配線１５および薄膜コイル素子１８をマスクとして下地金属層４１の不要な部分をエッチングして除去すると、図７に示すように、再配線１４下、第１の接続配線１５下および薄膜コイル素子１８下にのみ下地金属層１１、１２、１７が残存される。   Next, the plating resist film 46 is peeled off, and then unnecessary portions of the base metal layer 41 are removed by etching using the columnar electrodes 20 and 21, the rewiring 14, the first connection wiring 15 and the thin film coil element 18 as a mask. Then, as shown in FIG. 7, the base metal layers 11, 12, and 17 remain only under the rewiring 14, the first connection wiring 15, and the thin film coil element 18.

次に、図８に示すように、スクリーン印刷法、スピンコーティング法、ダイコート法等により、柱状電極２０、２１、再配線１４、第１の接続配線１５および薄膜コイル素子１８を含む保護膜９の上面全体にエポキシ系樹脂やポリイミド系樹脂等からなる封止膜２３をその厚さが柱状電極２０、２１の高さよりも厚くなるように形成する。したがって、この状態では、柱状電極２０、２１の上面は封止膜２３によって覆われている。   Next, as shown in FIG. 8, the protective film 9 including the columnar electrodes 20, 21, the rewiring 14, the first connection wiring 15, and the thin film coil element 18 is formed by screen printing, spin coating, die coating, or the like. A sealing film 23 made of an epoxy resin, a polyimide resin, or the like is formed on the entire upper surface so that its thickness is greater than the height of the columnar electrodes 20, 21. Therefore, in this state, the upper surfaces of the columnar electrodes 20 and 21 are covered with the sealing film 23.

次に、封止膜２３および柱状電極２０、２１の上面側を適宜に研磨し、図９に示すように、柱状電極２０、２１の上面を露出させ、且つ、この露出された柱状電極２０、２１の上面を含む封止膜２３の上面を平坦化する。ここで、柱状電極２０およびコイル素子用柱状電極１７の上面側を適宜に研磨するのは、電解メッキにより形成される柱状電極２０、２１の高さにばらつきがあるため、このばらつきを解消して、柱状電極２０、２１の高さを均一にするためである。   Next, the upper surface side of the sealing film 23 and the columnar electrodes 20 and 21 is appropriately polished to expose the upper surfaces of the columnar electrodes 20 and 21 and to expose the exposed columnar electrodes 20 and 21 as shown in FIG. The upper surface of the sealing film 23 including the upper surface of 21 is planarized. Here, the reason why the upper surfaces of the columnar electrode 20 and the coil element columnar electrode 17 are appropriately polished is that there is variation in the height of the columnar electrodes 20 and 21 formed by electrolytic plating. This is because the height of the columnar electrodes 20 and 21 is made uniform.

次に、図１０に示すように、シリコン基板４の下面全体に接着層３を接着する。接着層３は、エポキシ系樹脂、ポリイミド系樹脂等のダイボンド材からなるものであり、加熱加圧により、半硬化した状態でシリコン基板４に固着する。次に、シリコン基板４に固着された接着層３をダイシングテープ（図示せず）に貼り付け、図１１に示すダイシング工程を経た後に、ダイシングテープから剥がすと、図２に示すように、シリコン基板４の下面に接着層３を有する半導体構成体２が複数個得られる。   Next, as shown in FIG. 10, the adhesive layer 3 is bonded to the entire lower surface of the silicon substrate 4. The adhesive layer 3 is made of a die bond material such as an epoxy resin or a polyimide resin, and is fixed to the silicon substrate 4 in a semi-cured state by heating and pressing. Next, the adhesive layer 3 fixed to the silicon substrate 4 is affixed to a dicing tape (not shown), passed through the dicing process shown in FIG. 11, and then peeled off from the dicing tape, as shown in FIG. A plurality of semiconductor structures 2 having the adhesive layer 3 on the lower surface of 4 are obtained.

このようにして得られた半導体構成体２では、シリコン基板４の下面に接着層３を有するため、ダイシング工程後に各半導体構成体２のシリコン基板４の下面にそれぞれ接着層を設けるといった極めて面倒な作業が不要となる。なお、ダイシング工程後にダイシングテープから剥がす作業は、ダイシング工程後に各半導体構成体２のシリコン基板４の下面にそれぞれ接着層を設ける作業に比べれば、極めて簡単である。   Since the semiconductor structure 2 obtained in this way has the adhesive layer 3 on the lower surface of the silicon substrate 4, it is extremely troublesome to provide an adhesive layer on the lower surface of the silicon substrate 4 of each semiconductor structure 2 after the dicing process. Work becomes unnecessary. In addition, the operation | work which peels from a dicing tape after a dicing process is very simple compared with the operation | work which each provides an adhesive layer on the lower surface of the silicon substrate 4 of each semiconductor structure 2 after a dicing process.

次に、このようにして得られた半導体構成体２を用いて、図２に示す半導体装置を製造する場合の一例について説明する。まず、図１２に示すように、図２に示すベース板１を複数枚採取することができる大きさで、限定する意味ではないが、平面形状が方形状のベース板１を用意する。次に、ベース板１の上面の所定の複数箇所にそれぞれ半導体構成体２のシリコン基板４の下面に接着された接着層３を接着する。ここでの接着は、加熱加圧により、接着層３を本硬化させる。   Next, an example of manufacturing the semiconductor device shown in FIG. 2 using the semiconductor structure 2 obtained in this manner will be described. First, as shown in FIG. 12, the base plate 1 is prepared in such a size that a plurality of the base plates 1 shown in FIG. Next, the adhesive layer 3 bonded to the lower surface of the silicon substrate 4 of the semiconductor structure 2 is bonded to a plurality of predetermined locations on the upper surface of the base plate 1. In this bonding, the adhesive layer 3 is fully cured by heating and pressing.

次に、半導体構成体２間および最外周に配置された半導体構成体２の外側におけるベース板１の上面に、例えばスクリーン印刷法やスピンコーティング法等により、第１の絶縁材料２４ａを形成し、さらにその上面にシート状の第２の絶縁材料２５ａを配置する。第１の絶縁材料２４ａは、例えば、熱硬化性樹脂や、熱硬化性樹脂中にガラス繊維やシリカフィラー等の補強材を分散させたものからなる。   Next, the first insulating material 24a is formed on the upper surface of the base plate 1 between the semiconductor structural bodies 2 and outside the semiconductor structural bodies 2 arranged on the outermost periphery by, for example, a screen printing method or a spin coating method. Further, a sheet-like second insulating material 25a is disposed on the upper surface. The first insulating material 24a is made of, for example, a thermosetting resin or a material in which a reinforcing material such as glass fiber or silica filler is dispersed in the thermosetting resin.

シート状の第２の絶縁材料２５ａは、限定する意味ではないが、ビルドアップ材が好ましく、このビルドアップ材としては、エポキシ系樹脂やＢＴ樹脂等の熱硬化性樹脂中にシリカフィラーを混入させ、熱硬化性樹脂を半硬化状態にしたものがある。しかしながら、第２の絶縁材料２５ａとして、ガラス繊維にエポキシ系樹脂等の熱硬化性樹脂を含浸させ、熱硬化性樹脂を半硬化状態にしてシート状となしたプリプレグ材、またはフィラーが混入されない、熱硬化性樹脂のみからなる材料を用いるようにしてもよい。   The sheet-like second insulating material 25a is not limited, but is preferably a build-up material. As this build-up material, a silica filler is mixed in a thermosetting resin such as an epoxy resin or a BT resin. Some thermosetting resins are in a semi-cured state. However, as the second insulating material 25a, a glass fiber impregnated with a thermosetting resin such as an epoxy-based resin, and a prepreg material that is in a sheet shape with the thermosetting resin being semi-cured, or a filler is not mixed, You may make it use the material which consists only of thermosetting resins.

次に、図１３に示す一対の加熱加圧板５３、５４を用いて、第１および第２の絶縁材料２４ａ、２５ａを加熱加圧する。かくして、図１３に示すように、半導体構成体２間および最外周に配置された半導体構成体２の外側におけるベース板１の上面に絶縁層２４が形成され、半導体構成体２および絶縁層２４の上面に上層絶縁膜２５が形成される。   Next, the first and second insulating materials 24a and 25a are heated and pressurized using a pair of heating and pressing plates 53 and 54 shown in FIG. Thus, as shown in FIG. 13, the insulating layer 24 is formed on the upper surface of the base plate 1 between the semiconductor structural bodies 2 and outside the semiconductor structural bodies 2 arranged at the outermost periphery, and the semiconductor structural body 2 and the insulating layer 24 An upper insulating film 25 is formed on the upper surface.

この場合、上層絶縁膜２５の上面は、上側の加熱加圧板５３の下面によって押さえ付けられるため、平坦面となる。したがって、上層絶縁膜２５の上面を平坦化するための研磨工程は不要である。このため、ベース板１のサイズが例えば５００×５００ｍｍ程度と比較的大きくても、その上に配置された複数の半導体構成体２に対して上層絶縁膜２５の上面の平坦化を一括して簡単に行なうことができる。   In this case, since the upper surface of the upper insulating film 25 is pressed by the lower surface of the upper heating / pressing plate 53, it becomes a flat surface. Therefore, a polishing step for flattening the upper surface of the upper insulating film 25 is unnecessary. For this reason, even if the size of the base plate 1 is relatively large, for example, about 500 × 500 mm, the flattening of the upper surface of the upper insulating film 25 can be easily performed for a plurality of semiconductor structures 2 arranged thereon. Can be done.

次に、図１４に示すように、レーザビームを照射するレーザ加工あるいはフォトリソグラフィ法により、柱状電極２０、２１の上面中央部に対応する部分における上層絶縁膜２５に開口部３０、３１を形成する。次に、必要に応じて、開口部３０、３１内等に発生したエポキシスミア等をデスミア処理により除去する。   Next, as shown in FIG. 14, openings 30 and 31 are formed in the upper insulating film 25 at portions corresponding to the central portions of the upper surfaces of the columnar electrodes 20 and 21 by laser processing or photolithography with laser beam irradiation. . Next, the epoxy smear etc. which generate | occur | produced in the opening parts 30 and 31 etc. are removed by a desmear process as needed.

次に、図１５に示すように、開口部３０、３１を介して露出された柱状電極２０、２１の上面を含む上層絶縁膜２５の上面全体に上層下地金属層５５を形成する。次に、上層下地金属層５５の上面にメッキレジスト膜５６をパターン形成する。この場合、上層再配線２８形成領域および第３の接続配線２９形成領域に対応する部分におけるメッキレジスト膜５６には開口部５７、５８が形成されている。   Next, as shown in FIG. 15, an upper base metal layer 55 is formed on the entire upper surface of the upper insulating film 25 including the upper surfaces of the columnar electrodes 20 and 21 exposed through the openings 30 and 31. Next, a plating resist film 56 is patterned on the upper surface of the upper base metal layer 55. In this case, openings 57 and 58 are formed in the plating resist film 56 in portions corresponding to the upper layer rewiring 28 formation region and the third connection wiring 29 formation region.

次に、上層下地金属層５５をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜５６の開口部５７、５８内の上層下地金属層５５の上面に上層再配線２８および第３の接続配線２９を形成する。次に、メッキレジスト膜５６を剥離し、次いで、上層再配線２８および第３の接続配線２９をマスクとして上層下地金属層５５の不要な部分をエッチングして除去すると、図１６に示すように、上層再配線２８および第３の接続配線２９下にのみ上層下地金属層２６、２７が残存される。   Next, by performing electrolytic plating of copper using the upper base metal layer 55 as a plating current path, the upper layer rewiring 28 and the third layer are formed on the upper surface of the upper base metal layer 55 in the openings 57 and 58 of the plating resist film 56. Connection wiring 29 is formed. Next, the plating resist film 56 is peeled off, and then unnecessary portions of the upper base metal layer 55 are removed by etching using the upper layer rewiring 28 and the third connection wiring 29 as a mask, as shown in FIG. Upper base metal layers 26 and 27 remain only under upper layer rewiring 28 and third connection wiring 29.

次に、図１７に示すように、スクリーン印刷法やスピンコーティング法等により、上層再配線２８および第３の接続配線２９を含む上層絶縁膜２５の上面にソルダーレジスト等からなるオーバーコート膜３３を形成する。この場合、上層再配線２８の接続パッド部に対応する部分におけるオーバーコート膜３３には開口部３４が形成されている。   Next, as shown in FIG. 17, an overcoat film 33 made of a solder resist or the like is formed on the upper surface of the upper insulating film 25 including the upper rewiring 28 and the third connection wiring 29 by screen printing, spin coating, or the like. Form. In this case, an opening 34 is formed in the overcoat film 33 in a portion corresponding to the connection pad portion of the upper layer rewiring 28.

次に、開口部３４内およびその上方に半田ボール３５を上層再配線２８の接続パッド部に接続させて形成する。次に、互いに隣接する半導体構成体２間において、オーバーコート膜３３、上層絶縁膜２５、絶縁層２４およびベース板１を切断すると、図２に示す半導体装置が複数個得られる。   Next, a solder ball 35 is formed in the opening 34 and above it by connecting it to the connection pad portion of the upper layer rewiring 28. Next, when the overcoat film 33, the upper insulating film 25, the insulating layer 24, and the base plate 1 are cut between the adjacent semiconductor structures 2, a plurality of semiconductor devices shown in FIG. 2 are obtained.

以上のように、上記製造方法では、図５に示す工程において、下地金属層４１の上面に再配線１４、第１の接続配線１５および薄膜コイル素子１８を同一の材料によって同時に形成し、図６に示す工程において、再配線１４の接続パッド部上面および薄膜コイル素子１８の接続パッド１９上面に柱状電極２０、２１を同一の材料によって同時に形成し、図１５に示す工程において、上層下地金属層５５の上面に上層再配線２８および第３の接続配線２９を同一の材料によって同時に形成しているので、製造工程数を増加することなく、渦巻き状の薄膜コイル素子１８を形成することができる。   As described above, in the above manufacturing method, in the step shown in FIG. 5, the rewiring 14, the first connection wiring 15 and the thin film coil element 18 are simultaneously formed on the upper surface of the base metal layer 41 with the same material. In the step shown in FIG. 15, columnar electrodes 20 and 21 are simultaneously formed of the same material on the upper surface of the connection pad portion of the rewiring 14 and the upper surface of the connection pad 19 of the thin film coil element 18, and in the step shown in FIG. Since the upper layer rewiring 28 and the third connection wiring 29 are simultaneously formed of the same material on the upper surface, the spiral thin film coil element 18 can be formed without increasing the number of manufacturing steps.

また、上記製造方法では、ベース板１上に複数の半導体構成体２を接着層３を介して配置し、複数の半導体構成体２に対して、特に、上層再配線２８、第３の接続配線２９および半田ボール３５の形成を一括して行い、その後に分断して複数個の半導体装置を得ているので、製造工程を簡略化することができる。また、図１３に示す工程以降では、ベース板１と共に複数の半導体構成体２を搬送することができるので、これによっても製造工程を簡略化することができる。   In the above manufacturing method, a plurality of semiconductor structures 2 are arranged on the base plate 1 via the adhesive layer 3, and the upper layer rewiring 28, the third connection wiring, in particular, with respect to the plurality of semiconductor structures 2. 29 and the solder balls 35 are formed in a lump and then divided to obtain a plurality of semiconductor devices, so that the manufacturing process can be simplified. Further, after the step shown in FIG. 13, a plurality of semiconductor structures 2 can be transferred together with the base plate 1, so that the manufacturing process can be simplified.

（第２実施形態）
図１８はこの発明の第２実施形態としての半導体装置の図２同様の断面図を示し、図１９は同半導体装置の図３同様の断面図を示す。この半導体装置において、図２および図３に示す場合と大きく異なる点は、上層絶縁膜２５の上面に薄膜コイル素子１８を設けた点である。 (Second Embodiment)
18 is a cross-sectional view similar to FIG. 2 of the semiconductor device as the second embodiment of the present invention, and FIG. 19 is a cross-sectional view similar to FIG. 3 of the semiconductor device. In this semiconductor device, a significant difference from the cases shown in FIGS. 2 and 3 is that a thin film coil element 18 is provided on the upper surface of the upper insulating film 25.

この場合、半導体構成体２の保護膜７の上面には第１の接続配線１５および第２の接続配線１６が各接続パッド６、６に接続されて設けられている。第１、第２の接続配線１５、１６の接続パッド部上面には柱状電極２１、２２が設けられている。薄膜コイル素子１８の外端部は、上層絶縁膜２５の上面に設けられた第３の接続配線２９および上層絶縁膜２５に設けられた開口部３１を介して柱状電極２１の上面に接続されている。薄膜コイル素子１８の内端部は、上層絶縁膜２５に設けられた開口部３２を介して柱状電極２２の上面に接続されている。   In this case, a first connection wiring 15 and a second connection wiring 16 are provided on the upper surface of the protective film 7 of the semiconductor structure 2 so as to be connected to the connection pads 6 and 6. Columnar electrodes 21 and 22 are provided on the upper surfaces of the connection pad portions of the first and second connection wirings 15 and 16. The outer end portion of the thin film coil element 18 is connected to the upper surface of the columnar electrode 21 via the third connection wiring 29 provided on the upper surface of the upper insulating film 25 and the opening 31 provided in the upper insulating film 25. Yes. The inner end of the thin film coil element 18 is connected to the upper surface of the columnar electrode 22 through an opening 32 provided in the upper insulating film 25.

そして、この半導体装置では、保護膜７の上面に再配線１４および第１、第２の接続配線１５、１６が同一の材料によって同時に形成され、再配線１４の接続パッド部上面および第１、第２の接続配線１５、１６の接続パッド上面に柱状電極２０、２１、２２が同一の材料によって同時に形成され、上層絶縁膜２５の上面に上層再配線２８、薄膜コイル素子１８および第３の接続配線２９が同一の材料によって同時に形成されている。したがって、この場合も、製造工程数を増加することなく、渦巻き状の薄膜コイル素子１８を形成することができる。   In this semiconductor device, the rewiring 14 and the first and second connection wirings 15 and 16 are simultaneously formed of the same material on the upper surface of the protective film 7. The columnar electrodes 20, 21, 22 are simultaneously formed of the same material on the upper surface of the connection pads of the second connection wires 15, 16, and the upper layer rewiring 28, the thin film coil element 18, and the third connection wiring are formed on the upper surface of the upper layer insulating film 25. 29 are simultaneously formed of the same material. Therefore, also in this case, the spiral thin film coil element 18 can be formed without increasing the number of manufacturing steps.

（第３実施形態）
上記第１実施形態では、図２および図３に示すように、上層絶縁膜２５上に上層再配線２８を１層だけ形成した場合について説明したが、これに限らず、２層以上としてもよく、例えば、図２０および図２１に示すこの発明の第３実施形態のように、２層としてもよい。この場合、図２０は図２同様の断面図を示し、図２１は図３同様の断面図を示す。 (Third embodiment)
In the first embodiment, as shown in FIGS. 2 and 3, the case where only one upper layer rewiring 28 is formed on the upper insulating film 25 has been described. However, the present invention is not limited to this, and two or more layers may be used. For example, two layers may be used as in the third embodiment of the present invention shown in FIGS. In this case, FIG. 20 shows a sectional view similar to FIG. 2, and FIG. 21 shows a sectional view similar to FIG.

この半導体装置では、半導体構成体２および絶縁層２４の上面にビルドアップ材等からなる第１の上層絶縁膜６１が設けられている。第１の上層絶縁膜６１の上面のほぼ中央部を除く領域には上層下地金属層６２を含む第１の上層再配線６３が第１の上層絶縁膜６１に設けられた開口部６４を介して半導体構成体２の柱状電極２０の上面に接続されて設けられている。   In this semiconductor device, a first upper insulating film 61 made of a buildup material or the like is provided on the upper surfaces of the semiconductor structure 2 and the insulating layer 24. A first upper layer rewiring 63 including an upper base metal layer 62 is provided through an opening 64 provided in the first upper layer insulating film 61 in a region excluding the substantially central portion of the upper surface of the first upper layer insulating film 61. It is connected to the upper surface of the columnar electrode 20 of the semiconductor structure 2.

第１の上層絶縁膜６１の上面には上層下地金属層６５を含む薄膜コイル素子６６が設けられている。薄膜コイル素子６６の外端部は、第１の上層絶縁膜６１の上面に設けられた上層下地金属層６７を含む第３の接続配線６８および第１の上層絶縁膜６１に設けられた開口部６９を介して半導体構成体２の柱状電極２１の上面に接続されて設けられている。   A thin film coil element 66 including an upper base metal layer 65 is provided on the upper surface of the first upper insulating film 61. The outer end portion of the thin-film coil element 66 has an opening provided in the third connection wiring 68 including the upper base metal layer 67 provided on the upper surface of the first upper insulating film 61 and the first upper insulating film 61. 69 and connected to the upper surface of the columnar electrode 21 of the semiconductor structure 2.

第１の上層再配線６３、薄膜コイル素子６６および第３の接続配線６８を含む第１の上層絶縁膜６１の上面にはビルドアップ材等からなる第２の上層絶縁膜７０が設けられている。第２の上層絶縁膜７０の上面のほぼ中央部を除く領域には上層下地金属層７１を含む第２の上層再配線７２が第２の上層絶縁膜７０に形成された開口部７３を介して第１の上層再配線６３の接続パッド部に接続されて設けられている。   A second upper insulating film 70 made of a build-up material or the like is provided on the upper surface of the first upper insulating film 61 including the first upper rewiring 63, the thin film coil element 66, and the third connection wiring 68. . A second upper layer rewiring 72 including the upper base metal layer 71 is provided through an opening 73 formed in the second upper layer insulating film 70 in a region excluding the substantially central portion of the upper surface of the second upper layer insulating film 70. The first upper layer rewiring 63 is provided connected to the connection pad portion.

第２の上層絶縁膜７０の上面には上層下地金属層７４を含む第４の接続配線７５が設けられている。第４の接続配線７５の一端部は、第２の上層絶縁膜７０に設けられた開口部７６を介して薄膜コイル素子６６の内端部に接続されている。第４の接続配線７５の他端部は、第２の上層絶縁膜７０に設けられた開口部７６を介して、第１の上層絶縁膜６１の上面に設けられた上層下地金属層７８を含む中継接続パッド７９に接続されている。上層下地金属層７８を含む中継接続パッド７９は、第１の上層絶縁膜６１に設けられた開口部８０を介して半導体構成体２の柱状電極２２の上面に接続されている。   A fourth connection wiring 75 including an upper base metal layer 74 is provided on the upper surface of the second upper insulating film 70. One end portion of the fourth connection wiring 75 is connected to the inner end portion of the thin-film coil element 66 through the opening 76 provided in the second upper insulating film 70. The other end of the fourth connection wiring 75 includes an upper base metal layer 78 provided on the upper surface of the first upper insulating film 61 through an opening 76 provided in the second upper insulating film 70. It is connected to the relay connection pad 79. The relay connection pad 79 including the upper base metal layer 78 is connected to the upper surface of the columnar electrode 22 of the semiconductor structure 2 through the opening 80 provided in the first upper layer insulating film 61.

第２の上層再配線７２および第４の接続配線７５を含む第２の上層絶縁膜７０の上面にはソルダーレジスト等からなるオーバーコート膜８１が設けられている。第２の上層再配線７２の接続パッド部に対応する部分におけるオーバーコート膜８１には開口部８２が設けられている。開口部８２内およびその上方には半田ボール８３が第２の上層再配線７２の接続パッド部に接続されて設けられている。   An overcoat film 81 made of a solder resist or the like is provided on the upper surface of the second upper layer insulating film 70 including the second upper layer rewiring 72 and the fourth connection wiring 75. An opening 82 is provided in the overcoat film 81 in a portion corresponding to the connection pad portion of the second upper layer rewiring 72. Solder balls 83 are provided in the opening portion 82 and above the opening portion 82 so as to be connected to the connection pad portion of the second upper layer rewiring 72.

そして、この半導体装置では、第１の上層絶縁膜６１の上面に第１の上層再配線６３、薄膜コイル素子６６、第３の接続配線６８および中継接続パッド７９が同一の材料によって同時に形成され、第２の上層絶縁膜７０の上面に第２の上層再配線７２および第４の接続配線７５が同一の材料によって同時に形成されている。したがって、この場合も、製造工程数を増加することなく、渦巻き状の薄膜コイル素子６６を形成することができる。   In this semiconductor device, the first upper layer rewiring 63, the thin film coil element 66, the third connection wiring 68 and the relay connection pad 79 are simultaneously formed on the upper surface of the first upper insulating film 61 with the same material, A second upper layer rewiring 72 and a fourth connection wiring 75 are simultaneously formed of the same material on the upper surface of the second upper layer insulating film 70. Therefore, also in this case, the spiral thin film coil element 66 can be formed without increasing the number of manufacturing steps.

（第４実施形態）
図２２はこの発明の第４実施形態としての半導体装置の図２０同様の断面図を示し、図２３は同半導体装置の図２１同様の断面図を示す。この半導体装置において、図２０および図２１に示す場合と大きく異なる点は、第２の上層絶縁膜７０の上面に薄膜コイル素子６６を設けた点である。 (Fourth embodiment)
22 shows a cross-sectional view similar to FIG. 20 of the semiconductor device as the fourth embodiment of the present invention, and FIG. 23 shows a cross-sectional view similar to FIG. 21 of the semiconductor device. In this semiconductor device, a significant difference from the case shown in FIGS. 20 and 21 is that a thin film coil element 66 is provided on the upper surface of the second upper insulating film 70.

この場合、薄膜コイル素子６６の外端部は、第２の上層絶縁膜７０の上面に設けられた第４の接続配線７５および中継接続パッド７９を介して半導体構成体２の柱状電極２１の上面に接続されている。薄膜コイル素子６６の内端部は、第１の上層絶縁膜６１の上面に設けられた第３の接続配線６８を介して半導体構成体２の柱状電極２２の上面に接続されている。   In this case, the outer end portion of the thin film coil element 66 is connected to the upper surface of the columnar electrode 21 of the semiconductor structure 2 via the fourth connection wiring 75 and the relay connection pad 79 provided on the upper surface of the second upper layer insulating film 70. It is connected to the. The inner end of the thin film coil element 66 is connected to the upper surface of the columnar electrode 22 of the semiconductor structure 2 via a third connection wiring 68 provided on the upper surface of the first upper insulating film 61.

そして、この半導体装置では、第１の上層絶縁膜６１の上面に第１の上層再配線６３、第３の接続配線６８および中継接続パッド７９が同一の材料によって同時に形成され、第２の上層絶縁膜７０の上面に第２の上層再配線７２、薄膜コイル素子６６および第４の接続配線７５が同一の材料によって同時に形成されている。したがって、この場合も、製造工程数を増加することなく、渦巻き状の薄膜コイル素子６６を形成することができる。   In this semiconductor device, the first upper layer rewiring 63, the third connection wiring 68, and the relay connection pad 79 are simultaneously formed of the same material on the upper surface of the first upper layer insulating film 61, and the second upper layer insulation is formed. The second upper layer rewiring 72, the thin film coil element 66, and the fourth connection wiring 75 are simultaneously formed of the same material on the upper surface of the film 70. Therefore, also in this case, the spiral thin film coil element 66 can be formed without increasing the number of manufacturing steps.

（その他の実施形態）
なお、上記各実施形態において、半導体構成体２は、外部接続用電極として、再配線１４の接続パッド部上に設けられた柱状電極２０を有するものとしたが、これに限定されるものではない。例えば、半導体構成体２は、外部接続用電極としての接続パッド部を有する再配線１４のみを有するものであってもよい。また、ベース板１は、１枚の部材に限らず、絶縁膜および配線が交互に積層された多層印刷回路板としてもよい。 (Other embodiments)
In each of the above embodiments, the semiconductor structure 2 has the columnar electrode 20 provided on the connection pad portion of the rewiring 14 as the external connection electrode. However, the present invention is not limited to this. . For example, the semiconductor structure 2 may have only the rewiring 14 having a connection pad portion as an external connection electrode. The base plate 1 is not limited to a single member, and may be a multilayer printed circuit board in which insulating films and wirings are alternately stacked.

この発明の第１実施形態としての半導体装置の一部の平面図。1 is a plan view of a part of a semiconductor device as a first embodiment of the present invention; 図１のII−II線に沿う断面図。Sectional drawing which follows the II-II line | wire of FIG. 図１のIII−III線に沿う断面図。Sectional drawing which follows the III-III line of FIG. 図２に示す半導体装置の製造方法の一例において、当初用意したものの断面図。Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図９に続く工程の断面図。Sectional drawing of the process following FIG. 図１０に続く工程の断面図。Sectional drawing of the process following FIG. 図１１に続く工程の断面図。Sectional drawing of the process following FIG. 図１２に続く工程の断面図。Sectional drawing of the process following FIG. 図１３に続く工程の断面図。Sectional drawing of the process following FIG. 図１４に続く工程の断面図。FIG. 15 is a sectional view of a step following FIG. 14. 図１５に続く工程の断面図。FIG. 16 is a cross-sectional view of the process following FIG. 15. 図１６に続く工程の断面図。FIG. 17 is a cross-sectional view of the process following FIG. 16. この発明の第２実施形態としての半導体装置の図２同様の断面図。Sectional drawing similar to FIG. 2 of the semiconductor device as 2nd Embodiment of this invention. 第２実施形態としての半導体装置の図３同様の断面図。Sectional drawing similar to FIG. 3 of the semiconductor device as 2nd Embodiment. この発明の第３実施形態としての半導体装置の図２同様の断面図。Sectional drawing similar to FIG. 2 of the semiconductor device as 3rd Embodiment of this invention. 第３実施形態としての半導体装置の図３同様の断面図。Sectional drawing similar to FIG. 3 of the semiconductor device as 3rd Embodiment. この発明の第４実施形態としての半導体装置の図２０同様の断面図。Sectional drawing similar to FIG. 20 of the semiconductor device as 4th Embodiment of this invention. 第４実施形態としての半導体装置の図２１同様の断面図。Sectional drawing similar to FIG. 21 of the semiconductor device as 4th Embodiment.

符号の説明Explanation of symbols

１ ベース板
２ 半導体構成体
３ 接着層
４ シリコン基板
５、６ 接続パッド
７ 絶縁膜
９ 保護膜
１４ 再配線
１５ 第１の接続配線
１６ 第２の接続配線
１８ 薄膜コイル素子
２０、２１、２２ 柱状電極
２３ 封止膜
２４ 絶縁層
２５ 上層絶縁膜
２８ 上層再配線
２９ 第３の接続配線
３３ オーバーコート膜
３５ 半田ボール DESCRIPTION OF SYMBOLS 1 Base board 2 Semiconductor structure 3 Adhesion layer 4 Silicon substrate 5, 6 Connection pad 7 Insulating film 9 Protective film 14 Rewiring 15 1st connection wiring 16 2nd connection wiring 18 Thin film coil element 20, 21, 22 Columnar electrode 23 Sealing film 24 Insulating layer 25 Upper layer insulating film 28 Upper layer rewiring 29 Third connection wiring 33 Overcoat film 35 Solder ball

Claims (19)

ベース板と、
前記ベース板上に設けられ、且つ、複数の接続パッドを有する半導体基板および該半導体基板上に前記接続パッドに電気的に接続されて設けられた再配線を有する半導体構成体と、
前記半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、
前記半導体構成体および前記絶縁層上に設けられた少なくとも１層の上層絶縁膜と、
前記上層絶縁膜の何れかの層上に前記半導体構成体の再配線の接続パッド部に電気的に接続されて設けられ、外部接続用の接続パッド部を備える少なくとも１層の上層再配線と、
２つの端部を有し、前記再配線と前記上層再配線の何れかの層の一方と同一の平面上に設けられ、一端部が前記接続パッドに電気的に接続された薄膜回路素子と、
前記再配線と前記上層再配線の何れかの層の他方と同一の平面上に設けられ、前記薄膜回路素子の他端部および前記接続パッドに電気的に接続された接続配線と、
を備えていることを特徴とする半導体装置。 A base plate,
A semiconductor structure having a semiconductor substrate provided on the base plate and having a plurality of connection pads, and a rewiring provided on the semiconductor substrate and electrically connected to the connection pads;
An insulating layer provided on the base plate around the semiconductor structure;
At least one upper insulating film provided on the semiconductor structure and the insulating layer;
At least one upper layer redistribution provided with a connection pad portion for external connection, provided on any layer of the upper insulating film and electrically connected to a connection pad portion for rewiring of the semiconductor structure;
A thin film circuit element having two ends, provided on the same plane as one of the layers of the rewiring and the upper layer rewiring, and having one end electrically connected to the connection pad;
A connection wiring provided on the same plane as the other of the layers of the rewiring and the upper layer rewiring, and electrically connected to the other end of the thin film circuit element and the connection pad;
A semiconductor device comprising: 請求項１に記載の発明において、前記薄膜回路素子は前記再配線と同一の平面上に設けられ、前記接続配線は前記上層再配線と同一の平面上に設けられていることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein the thin film circuit element is provided on the same plane as the rewiring, and the connection wiring is provided on the same plane as the upper layer rewiring. apparatus. 請求項１に記載の発明において、前記薄膜回路素子は前記上層再配線と同一の平面上に設けられ、前記接続配線は前記再配線と同一の平面上に設けられていることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein the thin film circuit element is provided on the same plane as the upper layer rewiring, and the connection wiring is provided on the same plane as the rewiring. apparatus. 請求項１に記載の発明において、前記薄膜回路素子は、渦巻き状の形状を備える誘導素子であることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein the thin film circuit element is an inductive element having a spiral shape. 請求項１に記載の発明において、前記上層絶縁膜上に、前記上層再配線の前記外部接続用の接続パッド部を除く部分を覆う最上層絶縁膜を有することを特徴とする半導体装置。 2. The semiconductor device according to claim 1, further comprising an uppermost insulating film that covers a portion of the upper-layer rewiring except for the connection pad portion for external connection on the upper-layer insulating film. 請求項５に記載の発明において、前記外部接続用の接続パッド部上に半田ボールが設けられていることを特徴とする半導体装置。 6. The semiconductor device according to claim 5, wherein a solder ball is provided on the connection pad portion for external connection. ベース板と、
前記ベース板上に設けられ、且つ、複数の接続パッドを有する半導体基板および該半導体基板上に前記接続パッドに電気的に接続されて設けられた再配線を有する半導体構成体と、
前記半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、
前記半導体構成体および前記絶縁層上に設けられた複数層の上層絶縁膜と、
前記各上層絶縁膜上に層間で互いに接続され、且つ、前記半導体構成体の再配線の接続パッド部に接続されて設けられ、外部接続用の接続パッド部を備える複数層の上層再配線と、
２つの端部を有し、前記複数層の上層再配線のうちの１層と同一の平面上に設けられ、一端部が前記接続パッドに電気的に接続された薄膜回路素子と、
前記複数層の上層再配線のうちの他の１層と同一の平面上に設けられ、前記薄膜回路素子の他端部および前記接続パッドに電気的に接続された接続配線と、
を備えていることを特徴とする半導体装置。 A base plate,
A semiconductor structure having a semiconductor substrate provided on the base plate and having a plurality of connection pads, and a rewiring provided on the semiconductor substrate and electrically connected to the connection pads;
An insulating layer provided on the base plate around the semiconductor structure;
A plurality of upper insulating films provided on the semiconductor structure and the insulating layer;
A plurality of upper layer rewirings that are connected to each other between the layers on each upper insulating film and connected to the connection pad portion of the rewiring of the semiconductor structure, and provided with a connection pad portion for external connection;
A thin film circuit element having two ends, provided on the same plane as one of the upper layer rewirings of the plurality of layers, and having one end electrically connected to the connection pad;
A connection wiring provided on the same plane as the other one layer of the plurality of upper layer rewirings, and electrically connected to the other end of the thin film circuit element and the connection pad;
A semiconductor device comprising: 請求項７に記載の発明において、前記接続配線は、前記複数層の上層絶縁膜における前記薄膜回路素子が設けられた層より上層の絶縁膜上に設けられていることを特徴とする半導体装置。 8. The semiconductor device according to claim 7, wherein the connection wiring is provided on an insulating film above the layer in which the thin film circuit element is provided in the upper insulating film of the plurality of layers. 請求項７に記載の発明において、前記接続配線は、前記複数層の上層絶縁膜における前記薄膜回路素子が設けられた層より下層の絶縁膜上に設けられていることを特徴とする半導体装置。 The semiconductor device according to claim 7, wherein the connection wiring is provided on an insulating film below the layer in which the thin film circuit element is provided in the upper insulating film of the plurality of layers. 請求項７に記載の発明において、前記薄膜回路素子は、渦巻き状の形状を備える誘導素子であることを特徴とする半導体装置。 8. The semiconductor device according to claim 7, wherein the thin film circuit element is an inductive element having a spiral shape. 請求項７に記載の発明において、前記上層絶縁膜上に、前記上層再配線の前記外部接続用の接続パッド部を除く部分を覆う最上層絶縁膜を有することを特徴とする半導体装置。 8. The semiconductor device according to claim 7, further comprising: an uppermost insulating film that covers a portion of the upper rewiring except for the connection pad portion for external connection on the upper insulating film. 請求項５または１１に記載の発明において、前記上層再配線の前記外部接続用の接続パッド部上に半田ボールが設けられていることを特徴とする半導体装置。 12. The semiconductor device according to claim 5, wherein a solder ball is provided on the connection pad portion for external connection of the upper layer rewiring. 請求項１または７に記載の発明において、前記半導体構成体は、前記再配線に接続された柱状電極と、該柱状電極の上端面を除き、少なくとも前記半導体基板の上面を覆う封止膜と、を有するものであることを特徴とする半導体装置。 The invention according to claim 1 or 7, wherein the semiconductor structure includes a columnar electrode connected to the rewiring, a sealing film that covers at least an upper surface of the semiconductor substrate except for an upper end surface of the columnar electrode, A semiconductor device comprising: ベース板と、前記ベース板上に設けられ、且つ、複数の接続パッドを有する半導体基板および該半導体基板上に前記接続パッドに電気的に接続されて設けられた再配線を有する半導体構成体と、前記半導体構成体の周囲における前記ベース板上に設けられた少なくとも１層の絶縁層と、前記半導体構成体および前記絶縁層上に設けられた上層絶縁膜と、前記上層絶縁膜の何れかの層上に前記半導体構成体の再配線の接続パッド部に電気的に接続されて設けられ、外部接続用の接続パッド部を備える少なくとも１層の上層再配線と、２つの端部を有し、前記再配線と前記上層再配線の何れかの層とのうちの一方と同一の平面上に設けられ、一端部が前記接続パッドに電気的に接続された薄膜回路素子と、前記再配線と前記上層再配線の何れかの層の他方と同一の平面上に設けられ、前記薄膜回路素子の他端部および前記接続パッドに電気的に接続された接続配線とを備えた半導体装置の製造方法において、
前記再配線と前記上層再配線の何れかの層の一方と前記薄膜回路素子とを同一の材料によって同時に形成し、
前記再配線と前記上層再配線の何れかの層の他方と前記接続配線とを同一の材料によって同時に形成することを特徴とする半導体装置の製造方法。 A semiconductor substrate having a base plate, a semiconductor substrate provided on the base plate and having a plurality of connection pads, and a rewiring provided on the semiconductor substrate and electrically connected to the connection pads; At least one insulating layer provided on the base plate around the semiconductor structure, an upper insulating film provided on the semiconductor structure and the insulating layer, and any one of the upper insulating films An upper layer redistribution layer having at least one layer provided with a connection pad portion for external connection, and two ends provided on the connection pad portion of the redistribution line of the semiconductor structure, A thin film circuit element provided on the same plane as one of the rewiring and any one of the upper layer rewirings and having one end electrically connected to the connection pad; the rewiring and the upper layer Any of the rewiring Provided on the other and the same plane, in the manufacturing method of a semiconductor device having a and electrically connected to the connection wiring to the other end portion and the connecting pads of the thin-film circuit element,
One of the layers of the rewiring and the upper layer rewiring and the thin film circuit element are simultaneously formed of the same material,
The method of manufacturing a semiconductor device, wherein the other of any one of the rewiring and the upper layer rewiring and the connection wiring are simultaneously formed of the same material. 請求項１４に記載の発明において、前記再配線と前記薄膜回路素子とを同一の平面上に形成し、前記上層再配線と前記接続配線とを同一の平面上に形成することを特徴とする半導体装置の製造方法。 15. The semiconductor according to claim 14, wherein the rewiring and the thin film circuit element are formed on the same plane, and the upper layer rewiring and the connection wiring are formed on the same plane. Device manufacturing method. 請求項１４に記載の発明において、前記上層再配線と前記薄膜回路素子とを同一の平面上に形成し、前記再配線と前記接続配線とを同一の平面上に形成することを特徴とする半導体装置の製造方法。 15. The semiconductor according to claim 14, wherein the upper layer rewiring and the thin film circuit element are formed on the same plane, and the rewiring and the connection wiring are formed on the same plane. Device manufacturing method. ベース板と、前記ベース板上に設けられ、且つ、複数の接続パッドを有する半導体基板および該半導体基板上に前記接続パッドに電気的に接続されて設けられた再配線を有する半導体構成体と、前記半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、前記半導体構成体および前記絶縁層上に設けられた複数層の上層絶縁膜と、前記各上層絶縁膜上に層間で互いに接続され、且つ、前記半導体構成体の再配線の接続パッド部に接続されて設けられ、外部接続用の接続パッド部を備える複数層の上層再配線と、２つの端部を有し、前記複数層の上層再配線のうちの１層と同一の平面上に設けられ、一端部が前記接続パッドに電気的に接続された薄膜回路素子と、前記複数層の上層再配線のうちの他の１層と同一の平面上に設けられ、前記薄膜回路素子の他端部および前記接続パッドに電気的に接続された接続配線とを備えた半導体装置の製造方法において、
前記複数層の上層再配線のうちの１層と前記薄膜回路素子とを同一の材料によって同時に形成し、
前記複数層の上層再配線のうちの他の１層と前記接続配線とを同一の材料によって同時に形成することを特徴とする半導体装置の製造方法。 A semiconductor substrate having a base plate, a semiconductor substrate provided on the base plate and having a plurality of connection pads, and a rewiring provided on the semiconductor substrate and electrically connected to the connection pads; An insulating layer provided on the base plate around the semiconductor structure, a plurality of upper insulating films provided on the semiconductor structure and the insulating layer, and an interlayer on each upper insulating film A plurality of upper rewiring layers connected to and connected to a connection pad portion of the rewiring of the semiconductor structure, and provided with a connection pad portion for external connection; A thin film circuit element provided on the same plane as one of the upper layer redistribution layers and having one end electrically connected to the connection pad, and another one of the upper redistribution layers of the plurality of layers On the same plane as the layer In the manufacturing method of a semiconductor device having a and electrically connected to the connection wiring to the other end portion and the connecting pads of the thin-film circuit element,
One layer of the plurality of upper layer rewirings and the thin film circuit element are simultaneously formed of the same material,
A method for manufacturing a semiconductor device, wherein the other layer of the plurality of upper layer rewirings and the connection wiring are simultaneously formed of the same material. 請求項１７に記載の発明において、前記接続配線を、前記複数層の上層絶縁膜における前記薄膜回路素子が設けられた層より上層の絶縁膜上に形成することを特徴とする半導体装置の製造方法。 18. The method of manufacturing a semiconductor device according to claim 17, wherein the connection wiring is formed on an insulating film in a layer above the layer in which the thin film circuit element is provided in the plurality of upper insulating films. . 請求項１７に記載の発明において、前記接続配線を、前記複数層の上層絶縁膜における前記薄膜回路素子が設けられた層より下層の絶縁膜上に形成することを特徴とする半導体装置の製造方法。
18. The method of manufacturing a semiconductor device according to claim 17, wherein the connection wiring is formed on an insulating film below the layer in which the thin film circuit element is provided in the plurality of upper insulating films. .
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