JP4442181B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4442181B2
JP4442181B2 JP2003347797A JP2003347797A JP4442181B2 JP 4442181 B2 JP4442181 B2 JP 4442181B2 JP 2003347797 A JP2003347797 A JP 2003347797A JP 2003347797 A JP2003347797 A JP 2003347797A JP 4442181 B2 JP4442181 B2 JP 4442181B2
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provided
rewiring
upper
layer
connection
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JP2005116714A (en
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伸治 脇坂
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カシオ計算機株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19042Component type being an inductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19102Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In a conventional semiconductor device, an integrated circuit is formed, a semiconductor substrate having connection pads is embedded in the wiring substrate, and terminals for external connection connected to the connection pads are formed on the wiring substrate. is there. Further, in such a semiconductor device, a thin film circuit element having two terminal portions is provided on an insulating film provided on a semiconductor substrate, and both terminal portions of the thin film circuit element are provided on the insulating film. Some are configured to be connected to the connection pad via the connector. Some thin film coil elements (inductive elements) are provided as thin film circuit elements. (For example, see Patent Document 1)

JP-A-9-181264

  However, in the above-described conventional semiconductor device, when a thin film coil element is provided as a thin film circuit element on a semiconductor substrate, the thin film coil element has a spiral shape, so one inner end of two terminal portions. The part is formed at the center of the spiral shape, and in order to connect the inner end to the connection pad, a dedicated connection wiring is formed under the insulating film, and the inner end of the thin film coil element is formed on the connection wiring. There is a problem in that the number of manufacturing steps increases because a dedicated contact hole for connecting the two must be formed in the insulating film.

  In view of the above, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can form a thin film circuit element without increasing the number of manufacturing steps.

The invention described in claim 1 is provided with a base plate, a semiconductor substrate provided on the base plate and having a plurality of connection pads, and electrically connected to the connection pads on the semiconductor substrate. A semiconductor structure having rewiring; an insulating layer provided on the base plate around the semiconductor structure; and at least one upper insulating film provided on the semiconductor structure and the insulating layer; At least one upper layer redistribution provided with a connection pad portion for external connection, provided on any layer of the upper insulating film and electrically connected to a connection pad portion for rewiring of the semiconductor structure; A thin film circuit element having two ends, provided on the same plane as one of the layers of the rewiring and the upper layer rewiring, and having one end electrically connected to the connection pad; The rewiring and the upper layer A wiring that is provided on the same plane as the other of the layers of the wiring and that is electrically connected to the other end of the thin film circuit element and the connection pad; It is.
The invention according to claim 2 is the invention according to claim 1, wherein the thin film circuit element is provided on the same plane as the rewiring, and the connection wiring is provided on the same plane as the upper layer rewiring. It is characterized by being.
According to a third aspect of the present invention, in the first aspect of the present invention, the thin film circuit element is provided on the same plane as the upper layer rewiring, and the connection wiring is provided on the same plane as the rewiring. It is characterized by being.
According to a fourth aspect of the present invention, in the first aspect of the present invention, the thin film circuit element is an inductive element having a spiral shape.
According to a fifth aspect of the present invention, in the first aspect of the invention, the upper layer insulating film has an uppermost layer insulating film covering a portion of the upper layer rewiring except for the connection pad portion for external connection on the upper layer insulating film. It is characterized by.
According to a sixth aspect of the invention, in the fifth aspect of the invention, a solder ball is provided on the connection pad portion of the upper layer rewiring.
The invention according to claim 7 is provided with a base plate, a semiconductor substrate provided on the base plate and having a plurality of connection pads, and electrically connected to the connection pads on the semiconductor substrate. A semiconductor structure having rewiring; an insulating layer provided on the base plate around the semiconductor structure; a plurality of upper insulating films provided on the semiconductor structure and the insulating layer; A plurality of upper layer rewirings connected to each other on each upper insulating film and connected to a connection pad portion for rewiring of the semiconductor structure, and provided with a connection pad portion for external connection; A thin film circuit element having one end, provided on the same plane as one layer of the plurality of upper layer rewirings, and having one end electrically connected to the connection pad; and The other one of the upper layer rewiring The semiconductor device characterized by being provided on the same plane, and an electrically connected connection wiring to the other end and the connection pad of the thin-film circuit elements and.
The invention according to an eighth aspect is the invention according to the seventh aspect, wherein the connection wiring is provided on an insulating film in a layer above the layer in which the thin film circuit element is provided in the upper insulating film in the plurality of layers. It is characterized by being.
The invention according to claim 9 is the invention according to claim 7, wherein the connection wiring is provided on an insulating film below the layer in which the thin film circuit element is provided in the upper insulating film of the plurality of layers. It is characterized by being.
The invention according to claim 10 is the invention according to claim 7, wherein the thin film circuit element is an inductive element having a spiral shape.
According to an eleventh aspect of the present invention, in the seventh aspect of the present invention, the upper layer insulating film is provided on the upper layer insulating film so as to cover a portion of the upper layer rewiring except the connection pad portion for external connection. It is characterized by.
The invention described in claim 12 is characterized in that, in the invention described in claim 5 or 11, a solder ball is provided on the connection pad portion for external connection of the upper layer rewiring. .
The invention according to claim 13 is the invention according to claim 1 or 7, wherein the semiconductor structure includes at least the semiconductor substrate except for a columnar electrode connected to the rewiring and an upper end surface of the columnar electrode. And a sealing film covering the upper surface of the substrate.
The invention described in claim 14 is provided with a base plate, a semiconductor substrate provided on the base plate and having a plurality of connection pads, and electrically connected to the connection pads on the semiconductor substrate. A semiconductor structure having rewiring; an at least one insulating layer provided on the base plate around the semiconductor structure; an upper insulating film provided on the semiconductor structure and the insulating layer; At least one upper layer redistribution provided with a connection pad portion for external connection, provided on any layer of the upper insulating film and electrically connected to a connection pad portion for rewiring of the semiconductor structure; A thin film circuit having two ends, provided on the same plane as one of the rewiring and any one of the upper layer rewirings, and having one end electrically connected to the connection pad Element and said rewiring A method of manufacturing a semiconductor device comprising a connection wiring provided on the same plane as the other of any one of the upper layer rewirings and electrically connected to the other end of the thin film circuit element and the connection pad In this case, one of the layers of the rewiring and the upper layer rewiring and the thin film circuit element are simultaneously formed of the same material, and the other of the layers of the rewiring and the upper layer rewiring and the connection The wiring is formed of the same material at the same time.
The invention according to claim 15 is the invention according to claim 14, wherein the rewiring and the thin film circuit element are formed on the same plane, and the upper layer rewiring and the connection wiring are on the same plane. It is characterized by forming.
The invention according to claim 16 is the invention according to claim 14, wherein the upper layer rewiring and the thin film circuit element are formed on the same plane, and the rewiring and the connection wiring are on the same plane. It is characterized by forming.
The invention described in claim 17 is provided with a base plate, a semiconductor substrate provided on the base plate and having a plurality of connection pads, and electrically connected to the connection pads on the semiconductor substrate. A semiconductor structure having rewiring; an insulating layer provided on the base plate around the semiconductor structure; a plurality of upper insulating films provided on the semiconductor structure and the insulating layer; A plurality of upper layer rewirings connected to each other on each upper insulating film and connected to a connection pad portion for rewiring of the semiconductor structure, and provided with a connection pad portion for external connection; A thin film circuit element having one end, provided on the same plane as one layer of the plurality of upper layer rewirings, and having one end electrically connected to the connection pad; and Other of the upper layer rewiring In the method of manufacturing a semiconductor device, comprising a connection wiring provided on the same plane as the layer and electrically connected to the other end of the thin film circuit element and the connection pad, One of the layers and the thin film circuit element are simultaneously formed of the same material, and the other one of the plurality of upper layer rewirings and the connection wiring are simultaneously formed of the same material. To do.
According to an eighteenth aspect of the present invention, in the invention of the seventeenth aspect, the connection wiring is formed on an insulating film above the layer in which the thin film circuit element is provided in the upper insulating film of the plurality of layers. It is characterized by.
According to a nineteenth aspect of the present invention, in the invention according to the seventeenth aspect, the connection wiring is formed on an insulating film below the layer in which the thin film circuit element is provided in the upper insulating film of the plurality of layers. It is characterized by.

  According to this invention, a semiconductor substrate having a connection pad and a rewiring connected to the connection pad is embedded, and a terminal for external connection is formed via an upper layer rewiring formed by being connected to the rewiring In the apparatus and the manufacturing method thereof, for example, the thin film circuit element is provided on the same plane as one of the rewiring and the upper layer rewiring, and the connection wiring is provided on the same plane as the other of the rewiring and the upper layer rewiring. Since it is connected to one end, one of the rewiring and upper layer rewiring and the thin film circuit element are simultaneously formed of the same material, and the other of the rewiring and upper layer rewiring and the connection wiring are formed of the same material. Thus, the thin film circuit elements can be formed without increasing the number of manufacturing steps.

(First embodiment)
1 is a plan view of a part of a semiconductor device as a first embodiment of the present invention, FIG. 2 is a sectional view taken along line II-II in FIG. 1, and FIG. 3 is a line III-III in FIG. FIG. This semiconductor device includes a base plate 1 having a planar square shape. The base plate 1 is made of glass fiber, aramid fiber, liquid crystal fiber or the like impregnated with epoxy resin, polyimide resin, BT (bismaleimide / triazine) resin, PPE (polyphenylene ether), silicon, glass, ceramics, It is made of an insulating material such as a single resin, or a metal material such as copper or aluminum.

  On the upper surface of the base plate 1, the lower surface of the planar rectangular semiconductor structure 2 having a size somewhat smaller than the size of the base plate 1 is bonded via an adhesive layer 3 made of a die bond material. In this case, the semiconductor structure 2 has a rewiring, a columnar electrode, and a sealing film, which will be described later, and is generally called a CSP (chip size package). Since a method of obtaining individual semiconductor structures 2 by dicing after forming rewiring, columnar electrodes, and a sealing film thereon is employed, it is also called wafer level CSP (W-CSP). However, in this case, the semiconductor structure 2 has a part of a structure for forming a spiral thin film coil element to be described later. Below, the structure of the semiconductor structure 2 is demonstrated.

  The semiconductor structure 2 includes a planar rectangular silicon substrate (semiconductor substrate) 4. The silicon substrate 4 is bonded to the base plate 1 via the adhesive layer 3. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 4, and a plurality of connection pads 5 and 6 made of aluminum metal or the like are provided on the periphery of the upper surface so as to be connected to the integrated circuit. Yes. In this case, connection pads indicated by reference numeral 6 are connected to both ends of a spiral thin film coil element described later, and are provided on the silicon substrate 4 at least two.

  An insulating film 7 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 4 except for the central part of the connection pads 5 and 6, and the central part of the connection pads 5 and 6 is provided through an opening 8 provided in the insulating film 7. Is exposed. A protective film (insulating film) 9 made of an epoxy resin, a polyimide resin, or the like is provided on the upper surface of the insulating film 7. In this case, an opening 10 is provided in the protective film 9 in a portion corresponding to the opening 8 of the insulating film 7.

  Underlying metal layers 11, 12, 13 made of copper or the like are provided from the upper surfaces of the connection pads 5, 6 exposed through the openings 8, 10 to predetermined positions on the upper surface of the protective film 9. A rewiring 14 made of copper and first and second connection wirings 15 and 16 are provided on the entire upper surface of the base metal layers 11, 12 and 13.

  A base metal layer 17 for a thin film coil element made of copper or the like is provided on the upper surface of the protective film 9 in a spiral shape. A thin film coil element (thin film circuit element) 18 made of copper is provided on the entire upper surface of the base metal layer 17 for the thin film coil element. The inner end portion of the thin film coil element 18 is a square connection pad portion 19. The base metal layer 17 including the outer end portion of the thin film coil element 18 is connected to the connection pad 6 for one thin film coil element through the base metal layer 12 including the first connection wiring 15.

  A columnar electrode 20 made of copper is provided on the upper surface of the connection pad portion of the rewiring 14. A columnar electrode 21 is provided on the upper surface of the connection pad portion 19 of the thin film coil element 18. A columnar electrode 22 made of copper is provided on the upper surface of the connection pad portion of the second connection wiring 16. On the upper surface of the protective film 9 including the rewiring 14, the first and second connection wirings 15 and 16, and the thin film coil element 18, a sealing film (insulating film) 23 made of epoxy resin, polyimide resin, or the like is the upper surface. Is provided so as to be flush with the upper surfaces of the columnar electrodes 20, 21, 22.

  Thus, the semiconductor structure 2 called W-CSP includes the silicon substrate 4, the connection pad 5, and the insulating film 7, and further includes the protective film 9, the rewiring 14, and the first and second connection wirings 15 and 16. The thin film coil element 18, the columnar electrodes 20, 21 and 22, and the sealing film 23 are configured.

  A rectangular frame-shaped insulating layer 24 is provided on the upper surface of the base plate 1 around the semiconductor structure 2 so that the upper surface is substantially flush with the upper surface of the semiconductor structure 2. The insulating layer 24 is made of, for example, a reinforcing material such as glass fiber or silica filler dispersed in a thermoplastic resin.

  An upper insulating film 25 is provided on the upper surfaces of the semiconductor structure 2 and the insulating layer 24 so that the upper surface is flat. The upper insulating film 25 is generally used as a build-up material used for a build-up substrate. For example, a reinforcing material such as a fiber or a filler is contained in a thermosetting resin such as an epoxy resin or a BT resin. It is a thing. In this case, the fiber is glass fiber, aramid fiber, or the like. The filler is a silica filler or a ceramic filler.

  On the upper surface of the upper insulating film 25, upper base metal layers 26 and 27 made of copper or the like are provided. An upper layer rewiring 28 and a third connection wiring 29 made of copper are provided on the entire upper surface of the upper base metal layers 26 and 27. The upper base metal layer 26 including the upper layer rewiring 28 is connected to the upper surface of the columnar electrode 20 through an opening 30 provided in the upper insulating film 25 in a portion corresponding to the central portion of the upper surface of the columnar electrode 20.

  The upper base metal layer 27 including one end portion of the third connection wiring 29 is formed on the upper surface of the columnar electrode 21 via the opening 31 provided in the upper insulating film 25 in a portion corresponding to the central portion of the upper surface of the columnar electrode 21. It is connected. The upper base metal layer 27 including the other end portion of the third connection wiring 29 is formed on the upper surface of the columnar electrode 22 through the opening 32 provided in the upper insulating film 25 in a portion corresponding to the center of the upper surface of the columnar electrode 22. It is connected to the. Therefore, the connection pad portion 19 of the thin film coil element 18 is interposed via the columnar electrode 21, the upper base metal layer 27 including the third connection wiring 29, the columnar electrode 22, and the base metal layer 13 including the second connection wiring 16. It is connected to the connection pad 6 for the other thin film coil element.

  An overcoat film (uppermost layer insulating film) 33 made of a solder resist or the like is provided on the upper surface of the upper layer insulating film 25 including the upper layer rewiring 28. An opening 34 is provided in the overcoat film 33 in a portion corresponding to the connection pad portion of the upper layer rewiring 28. Solder balls 35 are provided in and above the opening 34 so as to be connected to the connection pad portion of the upper layer rewiring 28. In FIG. 1, the plurality of solder balls 35 are illustrated only on the outer peripheral portion of the upper surface of the overcoat film 33, but actually, are arranged in a matrix on the upper surface of the overcoat film 33.

  By the way, the size of the base plate 1 is made somewhat larger than the size of the semiconductor structure 2 because the area where the solder balls 35 are arranged is increased as the number of connection pads 5 on the silicon substrate 4 increases. In order to make the size and pitch of the connection pad portion (portion in the opening 34 of the overcoat film 33) of the upper layer rewiring 28 larger than that of the columnar electrode 20. It is.

  Therefore, the connection pad portion of the upper layer rewiring 28 arranged in a matrix form not only the region corresponding to the semiconductor structure 2 but also the region corresponding to the insulating layer 24 provided outside the side surface of the semiconductor structure 2. It is also arranged on the top. That is, among the solder balls 35 arranged in a matrix, at least the outermost solder balls 35 are arranged around the semiconductor structure 2.

  Next, an example of a method for manufacturing this semiconductor device will be described. However, in this case, for the sake of illustration, the method for manufacturing the semiconductor device shown in FIG. 2 will be described, and the description of the second connection wiring 16 and the columnar electrode 22 shown in FIG. 3 will be omitted. First, a method for manufacturing the semiconductor structure 2 will be described.

  As shown in FIG. 4, on the silicon substrate 4 in a wafer state, connection pads 5 and 6 made of aluminum-based metal, an insulating film 7 made of silicon oxide or the like, and a protective film 9 made of epoxy-based resin or polyimide-based resin are formed. Provided are those in which the central portions of the connection pads 5 and 6 are exposed through the openings 8 and 10 formed in the insulating film 7 and the protective film 9. In the above, on the silicon substrate 4 in the wafer state, an integrated circuit having a predetermined function is formed in a region where each semiconductor structure is formed, and the connection pads 5 and 6 are integrated circuits formed in the corresponding regions, respectively. Is electrically connected.

  Next, as shown in FIG. 5, a base metal layer 41 is formed on the entire upper surface of the protective film 9 including the upper surfaces of the connection pads 5 and 6 exposed through the openings 8 and 10. In this case, the base metal layer 41 may be only a copper layer formed by electroless plating, may be only a copper layer formed by sputtering, or a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering. The same applies to the case of the upper base metal layer 55 described later.

  Next, a plating resist film 42 is patterned on the upper surface of the base metal layer 41. In this case, openings 43, 44, 45 are formed in the plating resist film 42 in portions corresponding to the rewiring 14 formation region, the first connection wiring 15 formation region, and the thin film coil element 18 formation region. Next, by performing electrolytic plating of copper using the base metal layer 41 as a plating current path, the rewiring 14 and the first connection are formed on the upper surface of the base metal layer 41 in the openings 43, 44, 45 of the plating resist film 42. The wiring 15 and the thin film coil element 18 are formed. Next, the plating resist film 42 is peeled off.

  Next, as shown in FIG. 6, a plating resist film 46 is formed on the upper surface of the base metal layer 41 including the rewiring 14, the first connection wiring 15, and the thin film coil element 18. In this case, openings 47 and 48 are formed in the plating resist film 46 in portions corresponding to the columnar electrode 20 formation region and the columnar electrode 21 formation region. Next, by performing electrolytic plating of copper using the base metal layer 41 as a plating current path, the upper surface of the connection pad portion of the rewiring 14 in the openings 47 and 48 of the plating resist film 46 and the connection pad portion of the thin film coil element 18 are formed. 19 Columnar electrodes 20 and 21 are formed on the upper surface.

  Next, the plating resist film 46 is peeled off, and then unnecessary portions of the base metal layer 41 are removed by etching using the columnar electrodes 20 and 21, the rewiring 14, the first connection wiring 15 and the thin film coil element 18 as a mask. Then, as shown in FIG. 7, the base metal layers 11, 12, and 17 remain only under the rewiring 14, the first connection wiring 15, and the thin film coil element 18.

  Next, as shown in FIG. 8, the protective film 9 including the columnar electrodes 20, 21, the rewiring 14, the first connection wiring 15, and the thin film coil element 18 is formed by screen printing, spin coating, die coating, or the like. A sealing film 23 made of an epoxy resin, a polyimide resin, or the like is formed on the entire upper surface so that its thickness is greater than the height of the columnar electrodes 20, 21. Therefore, in this state, the upper surfaces of the columnar electrodes 20 and 21 are covered with the sealing film 23.

  Next, the upper surface side of the sealing film 23 and the columnar electrodes 20 and 21 is appropriately polished to expose the upper surfaces of the columnar electrodes 20 and 21 and to expose the exposed columnar electrodes 20 and 21 as shown in FIG. The upper surface of the sealing film 23 including the upper surface of 21 is planarized. Here, the reason why the upper surfaces of the columnar electrode 20 and the coil element columnar electrode 17 are appropriately polished is that there is variation in the height of the columnar electrodes 20 and 21 formed by electrolytic plating. This is because the height of the columnar electrodes 20 and 21 is made uniform.

  Next, as shown in FIG. 10, the adhesive layer 3 is bonded to the entire lower surface of the silicon substrate 4. The adhesive layer 3 is made of a die bond material such as an epoxy resin or a polyimide resin, and is fixed to the silicon substrate 4 in a semi-cured state by heating and pressing. Next, the adhesive layer 3 fixed to the silicon substrate 4 is affixed to a dicing tape (not shown), passed through the dicing process shown in FIG. 11, and then peeled off from the dicing tape, as shown in FIG. A plurality of semiconductor structures 2 having the adhesive layer 3 on the lower surface of 4 are obtained.

  Since the semiconductor structure 2 obtained in this way has the adhesive layer 3 on the lower surface of the silicon substrate 4, it is extremely troublesome to provide an adhesive layer on the lower surface of the silicon substrate 4 of each semiconductor structure 2 after the dicing process. Work becomes unnecessary. In addition, the operation | work which peels from a dicing tape after a dicing process is very simple compared with the operation | work which each provides an adhesive layer on the lower surface of the silicon substrate 4 of each semiconductor structure 2 after a dicing process.

  Next, an example of manufacturing the semiconductor device shown in FIG. 2 using the semiconductor structure 2 obtained in this manner will be described. First, as shown in FIG. 12, the base plate 1 is prepared in such a size that a plurality of the base plates 1 shown in FIG. Next, the adhesive layer 3 bonded to the lower surface of the silicon substrate 4 of the semiconductor structure 2 is bonded to a plurality of predetermined locations on the upper surface of the base plate 1. In this bonding, the adhesive layer 3 is fully cured by heating and pressing.

  Next, the first insulating material 24a is formed on the upper surface of the base plate 1 between the semiconductor structural bodies 2 and outside the semiconductor structural bodies 2 arranged on the outermost periphery by, for example, a screen printing method or a spin coating method. Further, a sheet-like second insulating material 25a is disposed on the upper surface. The first insulating material 24a is made of, for example, a thermosetting resin or a material in which a reinforcing material such as glass fiber or silica filler is dispersed in the thermosetting resin.

  The sheet-like second insulating material 25a is not limited, but is preferably a build-up material. As this build-up material, a silica filler is mixed in a thermosetting resin such as an epoxy resin or a BT resin. Some thermosetting resins are in a semi-cured state. However, as the second insulating material 25a, a glass fiber impregnated with a thermosetting resin such as an epoxy-based resin, and a prepreg material that is in a sheet shape with the thermosetting resin being semi-cured, or a filler is not mixed, You may make it use the material which consists only of thermosetting resins.

  Next, the first and second insulating materials 24a and 25a are heated and pressurized using a pair of heating and pressing plates 53 and 54 shown in FIG. Thus, as shown in FIG. 13, the insulating layer 24 is formed on the upper surface of the base plate 1 between the semiconductor structural bodies 2 and outside the semiconductor structural bodies 2 arranged at the outermost periphery, and the semiconductor structural body 2 and the insulating layer 24 An upper insulating film 25 is formed on the upper surface.

  In this case, since the upper surface of the upper insulating film 25 is pressed by the lower surface of the upper heating / pressing plate 53, it becomes a flat surface. Therefore, a polishing step for flattening the upper surface of the upper insulating film 25 is unnecessary. For this reason, even if the size of the base plate 1 is relatively large, for example, about 500 × 500 mm, the flattening of the upper surface of the upper insulating film 25 can be easily performed for a plurality of semiconductor structures 2 arranged thereon. Can be done.

  Next, as shown in FIG. 14, openings 30 and 31 are formed in the upper insulating film 25 at portions corresponding to the central portions of the upper surfaces of the columnar electrodes 20 and 21 by laser processing or photolithography with laser beam irradiation. . Next, the epoxy smear etc. which generate | occur | produced in the opening parts 30 and 31 etc. are removed by a desmear process as needed.

  Next, as shown in FIG. 15, an upper base metal layer 55 is formed on the entire upper surface of the upper insulating film 25 including the upper surfaces of the columnar electrodes 20 and 21 exposed through the openings 30 and 31. Next, a plating resist film 56 is patterned on the upper surface of the upper base metal layer 55. In this case, openings 57 and 58 are formed in the plating resist film 56 in portions corresponding to the upper layer rewiring 28 formation region and the third connection wiring 29 formation region.

  Next, by performing electrolytic plating of copper using the upper base metal layer 55 as a plating current path, the upper layer rewiring 28 and the third layer are formed on the upper surface of the upper base metal layer 55 in the openings 57 and 58 of the plating resist film 56. Connection wiring 29 is formed. Next, the plating resist film 56 is peeled off, and then unnecessary portions of the upper base metal layer 55 are removed by etching using the upper layer rewiring 28 and the third connection wiring 29 as a mask, as shown in FIG. Upper base metal layers 26 and 27 remain only under upper layer rewiring 28 and third connection wiring 29.

  Next, as shown in FIG. 17, an overcoat film 33 made of a solder resist or the like is formed on the upper surface of the upper insulating film 25 including the upper rewiring 28 and the third connection wiring 29 by screen printing, spin coating, or the like. Form. In this case, an opening 34 is formed in the overcoat film 33 in a portion corresponding to the connection pad portion of the upper layer rewiring 28.

  Next, a solder ball 35 is formed in the opening 34 and above it by connecting it to the connection pad portion of the upper layer rewiring 28. Next, when the overcoat film 33, the upper insulating film 25, the insulating layer 24, and the base plate 1 are cut between the adjacent semiconductor structures 2, a plurality of semiconductor devices shown in FIG. 2 are obtained.

  As described above, in the above manufacturing method, in the step shown in FIG. 5, the rewiring 14, the first connection wiring 15 and the thin film coil element 18 are simultaneously formed on the upper surface of the base metal layer 41 with the same material. In the step shown in FIG. 15, columnar electrodes 20 and 21 are simultaneously formed of the same material on the upper surface of the connection pad portion of the rewiring 14 and the upper surface of the connection pad 19 of the thin film coil element 18, and in the step shown in FIG. Since the upper layer rewiring 28 and the third connection wiring 29 are simultaneously formed of the same material on the upper surface, the spiral thin film coil element 18 can be formed without increasing the number of manufacturing steps.

  In the above manufacturing method, a plurality of semiconductor structures 2 are arranged on the base plate 1 via the adhesive layer 3, and the upper layer rewiring 28, the third connection wiring, in particular, with respect to the plurality of semiconductor structures 2. 29 and the solder balls 35 are formed in a lump and then divided to obtain a plurality of semiconductor devices, so that the manufacturing process can be simplified. Further, after the step shown in FIG. 13, a plurality of semiconductor structures 2 can be transferred together with the base plate 1, so that the manufacturing process can be simplified.

(Second Embodiment)
18 is a cross-sectional view similar to FIG. 2 of the semiconductor device as the second embodiment of the present invention, and FIG. 19 is a cross-sectional view similar to FIG. 3 of the semiconductor device. In this semiconductor device, a significant difference from the cases shown in FIGS. 2 and 3 is that a thin film coil element 18 is provided on the upper surface of the upper insulating film 25.

  In this case, a first connection wiring 15 and a second connection wiring 16 are provided on the upper surface of the protective film 7 of the semiconductor structure 2 so as to be connected to the connection pads 6 and 6. Columnar electrodes 21 and 22 are provided on the upper surfaces of the connection pad portions of the first and second connection wirings 15 and 16. The outer end portion of the thin film coil element 18 is connected to the upper surface of the columnar electrode 21 via the third connection wiring 29 provided on the upper surface of the upper insulating film 25 and the opening 31 provided in the upper insulating film 25. Yes. The inner end of the thin film coil element 18 is connected to the upper surface of the columnar electrode 22 through an opening 32 provided in the upper insulating film 25.

  In this semiconductor device, the rewiring 14 and the first and second connection wirings 15 and 16 are simultaneously formed of the same material on the upper surface of the protective film 7. The columnar electrodes 20, 21, 22 are simultaneously formed of the same material on the upper surface of the connection pads of the second connection wires 15, 16, and the upper layer rewiring 28, the thin film coil element 18, and the third connection wiring are formed on the upper surface of the upper layer insulating film 25. 29 are simultaneously formed of the same material. Therefore, also in this case, the spiral thin film coil element 18 can be formed without increasing the number of manufacturing steps.

(Third embodiment)
In the first embodiment, as shown in FIGS. 2 and 3, the case where only one upper layer rewiring 28 is formed on the upper insulating film 25 has been described. However, the present invention is not limited to this, and two or more layers may be used. For example, two layers may be used as in the third embodiment of the present invention shown in FIGS. In this case, FIG. 20 shows a sectional view similar to FIG. 2, and FIG. 21 shows a sectional view similar to FIG.

  In this semiconductor device, a first upper insulating film 61 made of a buildup material or the like is provided on the upper surfaces of the semiconductor structure 2 and the insulating layer 24. A first upper layer rewiring 63 including an upper base metal layer 62 is provided through an opening 64 provided in the first upper layer insulating film 61 in a region excluding the substantially central portion of the upper surface of the first upper layer insulating film 61. It is connected to the upper surface of the columnar electrode 20 of the semiconductor structure 2.

  A thin film coil element 66 including an upper base metal layer 65 is provided on the upper surface of the first upper insulating film 61. The outer end portion of the thin-film coil element 66 has an opening provided in the third connection wiring 68 including the upper base metal layer 67 provided on the upper surface of the first upper insulating film 61 and the first upper insulating film 61. 69 and connected to the upper surface of the columnar electrode 21 of the semiconductor structure 2.

  A second upper insulating film 70 made of a build-up material or the like is provided on the upper surface of the first upper insulating film 61 including the first upper rewiring 63, the thin film coil element 66, and the third connection wiring 68. . A second upper layer rewiring 72 including the upper base metal layer 71 is provided through an opening 73 formed in the second upper layer insulating film 70 in a region excluding the substantially central portion of the upper surface of the second upper layer insulating film 70. The first upper layer rewiring 63 is provided connected to the connection pad portion.

  A fourth connection wiring 75 including an upper base metal layer 74 is provided on the upper surface of the second upper insulating film 70. One end portion of the fourth connection wiring 75 is connected to the inner end portion of the thin-film coil element 66 through the opening 76 provided in the second upper insulating film 70. The other end of the fourth connection wiring 75 includes an upper base metal layer 78 provided on the upper surface of the first upper insulating film 61 through an opening 76 provided in the second upper insulating film 70. It is connected to the relay connection pad 79. The relay connection pad 79 including the upper base metal layer 78 is connected to the upper surface of the columnar electrode 22 of the semiconductor structure 2 through the opening 80 provided in the first upper layer insulating film 61.

  An overcoat film 81 made of a solder resist or the like is provided on the upper surface of the second upper layer insulating film 70 including the second upper layer rewiring 72 and the fourth connection wiring 75. An opening 82 is provided in the overcoat film 81 in a portion corresponding to the connection pad portion of the second upper layer rewiring 72. Solder balls 83 are provided in the opening portion 82 and above the opening portion 82 so as to be connected to the connection pad portion of the second upper layer rewiring 72.

  In this semiconductor device, the first upper layer rewiring 63, the thin film coil element 66, the third connection wiring 68 and the relay connection pad 79 are simultaneously formed on the upper surface of the first upper insulating film 61 with the same material, A second upper layer rewiring 72 and a fourth connection wiring 75 are simultaneously formed of the same material on the upper surface of the second upper layer insulating film 70. Therefore, also in this case, the spiral thin film coil element 66 can be formed without increasing the number of manufacturing steps.

(Fourth embodiment)
22 shows a cross-sectional view similar to FIG. 20 of the semiconductor device as the fourth embodiment of the present invention, and FIG. 23 shows a cross-sectional view similar to FIG. 21 of the semiconductor device. In this semiconductor device, a significant difference from the case shown in FIGS. 20 and 21 is that a thin film coil element 66 is provided on the upper surface of the second upper insulating film 70.

  In this case, the outer end portion of the thin film coil element 66 is connected to the upper surface of the columnar electrode 21 of the semiconductor structure 2 via the fourth connection wiring 75 and the relay connection pad 79 provided on the upper surface of the second upper layer insulating film 70. It is connected to the. The inner end of the thin film coil element 66 is connected to the upper surface of the columnar electrode 22 of the semiconductor structure 2 via a third connection wiring 68 provided on the upper surface of the first upper insulating film 61.

  In this semiconductor device, the first upper layer rewiring 63, the third connection wiring 68, and the relay connection pad 79 are simultaneously formed of the same material on the upper surface of the first upper layer insulating film 61, and the second upper layer insulation is formed. The second upper layer rewiring 72, the thin film coil element 66, and the fourth connection wiring 75 are simultaneously formed of the same material on the upper surface of the film 70. Therefore, also in this case, the spiral thin film coil element 66 can be formed without increasing the number of manufacturing steps.

(Other embodiments)
In each of the above embodiments, the semiconductor structure 2 has the columnar electrode 20 provided on the connection pad portion of the rewiring 14 as the external connection electrode. However, the present invention is not limited to this. . For example, the semiconductor structure 2 may have only the rewiring 14 having a connection pad portion as an external connection electrode. The base plate 1 is not limited to a single member, and may be a multilayer printed circuit board in which insulating films and wirings are alternately stacked.

1 is a plan view of a part of a semiconductor device as a first embodiment of the present invention; Sectional drawing which follows the II-II line | wire of FIG. Sectional drawing which follows the III-III line of FIG. Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 15 is a sectional view of a step following FIG. 14. FIG. 16 is a cross-sectional view of the process following FIG. 15. FIG. 17 is a cross-sectional view of the process following FIG. 16. Sectional drawing similar to FIG. 2 of the semiconductor device as 2nd Embodiment of this invention. Sectional drawing similar to FIG. 3 of the semiconductor device as 2nd Embodiment. Sectional drawing similar to FIG. 2 of the semiconductor device as 3rd Embodiment of this invention. Sectional drawing similar to FIG. 3 of the semiconductor device as 3rd Embodiment. Sectional drawing similar to FIG. 20 of the semiconductor device as 4th Embodiment of this invention. Sectional drawing similar to FIG. 21 of the semiconductor device as 4th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Base board 2 Semiconductor structure 3 Adhesion layer 4 Silicon substrate 5, 6 Connection pad 7 Insulating film 9 Protective film 14 Rewiring 15 1st connection wiring 16 2nd connection wiring 18 Thin film coil element 20, 21, 22 Columnar electrode 23 Sealing film 24 Insulating layer 25 Upper layer insulating film 28 Upper layer rewiring 29 Third connection wiring 33 Overcoat film 35 Solder ball

Claims (19)

  1. A base plate,
    A semiconductor structure having a semiconductor substrate provided on the base plate and having a plurality of connection pads, and a rewiring provided on the semiconductor substrate and electrically connected to the connection pads;
    An insulating layer provided on the base plate around the semiconductor structure;
    At least one upper insulating film provided on the semiconductor structure and the insulating layer;
    At least one upper layer redistribution provided with a connection pad portion for external connection, provided on any layer of the upper insulating film and electrically connected to a connection pad portion for rewiring of the semiconductor structure;
    A thin film circuit element having two ends, provided on the same plane as one of the layers of the rewiring and the upper layer rewiring, and having one end electrically connected to the connection pad;
    A connection wiring provided on the same plane as the other of the layers of the rewiring and the upper layer rewiring, and electrically connected to the other end of the thin film circuit element and the connection pad;
    A semiconductor device comprising:
  2. 2. The semiconductor device according to claim 1, wherein the thin film circuit element is provided on the same plane as the rewiring, and the connection wiring is provided on the same plane as the upper layer rewiring. apparatus.
  3. 2. The semiconductor device according to claim 1, wherein the thin film circuit element is provided on the same plane as the upper layer rewiring, and the connection wiring is provided on the same plane as the rewiring. apparatus.
  4. 2. The semiconductor device according to claim 1, wherein the thin film circuit element is an inductive element having a spiral shape.
  5. 2. The semiconductor device according to claim 1, further comprising an uppermost insulating film that covers a portion of the upper-layer rewiring except for the connection pad portion for external connection on the upper-layer insulating film.
  6. 6. The semiconductor device according to claim 5, wherein a solder ball is provided on the connection pad portion for external connection.
  7. A base plate,
    A semiconductor structure having a semiconductor substrate provided on the base plate and having a plurality of connection pads, and a rewiring provided on the semiconductor substrate and electrically connected to the connection pads;
    An insulating layer provided on the base plate around the semiconductor structure;
    A plurality of upper insulating films provided on the semiconductor structure and the insulating layer;
    A plurality of upper layer rewirings that are connected to each other between the layers on each upper insulating film and connected to the connection pad portion of the rewiring of the semiconductor structure, and provided with a connection pad portion for external connection;
    A thin film circuit element having two ends, provided on the same plane as one of the upper layer rewirings of the plurality of layers, and having one end electrically connected to the connection pad;
    A connection wiring provided on the same plane as the other one layer of the plurality of upper layer rewirings, and electrically connected to the other end of the thin film circuit element and the connection pad;
    A semiconductor device comprising:
  8. 8. The semiconductor device according to claim 7, wherein the connection wiring is provided on an insulating film above the layer in which the thin film circuit element is provided in the upper insulating film of the plurality of layers.
  9. The semiconductor device according to claim 7, wherein the connection wiring is provided on an insulating film below the layer in which the thin film circuit element is provided in the upper insulating film of the plurality of layers.
  10. 8. The semiconductor device according to claim 7, wherein the thin film circuit element is an inductive element having a spiral shape.
  11. 8. The semiconductor device according to claim 7, further comprising: an uppermost insulating film that covers a portion of the upper rewiring except for the connection pad portion for external connection on the upper insulating film.
  12. 12. The semiconductor device according to claim 5, wherein a solder ball is provided on the connection pad portion for external connection of the upper layer rewiring.
  13. The invention according to claim 1 or 7, wherein the semiconductor structure includes a columnar electrode connected to the rewiring, a sealing film that covers at least an upper surface of the semiconductor substrate except for an upper end surface of the columnar electrode, A semiconductor device comprising:
  14. A semiconductor substrate having a base plate, a semiconductor substrate provided on the base plate and having a plurality of connection pads, and a rewiring provided on the semiconductor substrate and electrically connected to the connection pads; At least one insulating layer provided on the base plate around the semiconductor structure, an upper insulating film provided on the semiconductor structure and the insulating layer, and any one of the upper insulating films An upper layer redistribution layer having at least one layer provided with a connection pad portion for external connection, and two ends provided on the connection pad portion of the redistribution line of the semiconductor structure, A thin film circuit element provided on the same plane as one of the rewiring and any one of the upper layer rewirings and having one end electrically connected to the connection pad; the rewiring and the upper layer Any of the rewiring Provided on the other and the same plane, in the manufacturing method of a semiconductor device having a and electrically connected to the connection wiring to the other end portion and the connecting pads of the thin-film circuit element,
    One of the layers of the rewiring and the upper layer rewiring and the thin film circuit element are simultaneously formed of the same material,
    The method of manufacturing a semiconductor device, wherein the other of any one of the rewiring and the upper layer rewiring and the connection wiring are simultaneously formed of the same material.
  15. 15. The semiconductor according to claim 14, wherein the rewiring and the thin film circuit element are formed on the same plane, and the upper layer rewiring and the connection wiring are formed on the same plane. Device manufacturing method.
  16. 15. The semiconductor according to claim 14, wherein the upper layer rewiring and the thin film circuit element are formed on the same plane, and the rewiring and the connection wiring are formed on the same plane. Device manufacturing method.
  17. A semiconductor substrate having a base plate, a semiconductor substrate provided on the base plate and having a plurality of connection pads, and a rewiring provided on the semiconductor substrate and electrically connected to the connection pads; An insulating layer provided on the base plate around the semiconductor structure, a plurality of upper insulating films provided on the semiconductor structure and the insulating layer, and an interlayer on each upper insulating film A plurality of upper rewiring layers connected to and connected to a connection pad portion of the rewiring of the semiconductor structure, and provided with a connection pad portion for external connection; A thin film circuit element provided on the same plane as one of the upper layer redistribution layers and having one end electrically connected to the connection pad, and another one of the upper redistribution layers of the plurality of layers On the same plane as the layer In the manufacturing method of a semiconductor device having a and electrically connected to the connection wiring to the other end portion and the connecting pads of the thin-film circuit element,
    One layer of the plurality of upper layer rewirings and the thin film circuit element are simultaneously formed of the same material,
    A method for manufacturing a semiconductor device, wherein the other layer of the plurality of upper layer rewirings and the connection wiring are simultaneously formed of the same material.
  18. 18. The method of manufacturing a semiconductor device according to claim 17, wherein the connection wiring is formed on an insulating film in a layer above the layer in which the thin film circuit element is provided in the plurality of upper insulating films. .
  19. 18. The method of manufacturing a semiconductor device according to claim 17, wherein the connection wiring is formed on an insulating film below the layer in which the thin film circuit element is provided in the plurality of upper insulating films. .
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