JP4316624B2 - Semiconductor device - Google Patents

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JP4316624B2
JP4316624B2 JP2007012146A JP2007012146A JP4316624B2 JP 4316624 B2 JP4316624 B2 JP 4316624B2 JP 2007012146 A JP2007012146 A JP 2007012146A JP 2007012146 A JP2007012146 A JP 2007012146A JP 4316624 B2 JP4316624 B2 JP 4316624B2
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layer
heat dissipation
rewiring
semiconductor
insulating
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JP2007116198A (en
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伸治 脇坂
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Casio Computer Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

この発明は半導体装置に関する。   The present invention relates to a semiconductor device.

従来、ウエハ状態で外部接続用の柱状電極を形成し、その周囲に封止材を形成した後、ウエハをダイシングして個々の半導体装置となすウエハレベルパッケージ（ＷＬＰ）といわれる半導体装置が知られている。このような半導体装置には、上面に複数の接続パッドを有する半導体基板の下面に第１の保護膜が設けられ、半導体基板の上面および側面に、半導体基板の接続パッドに対応する部分に開口部を有する第２の保護膜が設けられ、第２の保護膜の上面に再配線が半導体基板の接続パッドに接続されて設けられ、再配線の接続パッド部上面に柱状電極が設けられ、柱状電極の周囲において再配線を含む第２の保護膜の上面に第３の保護膜が設けられたものがある（例えば、特許文献１参照）。   Conventionally, a semiconductor device called a wafer level package (WLP) is known in which a columnar electrode for external connection is formed in a wafer state, a sealing material is formed around the electrode, and the wafer is diced into individual semiconductor devices. ing. In such a semiconductor device, a first protective film is provided on the lower surface of the semiconductor substrate having a plurality of connection pads on the upper surface, and openings are formed on the upper surface and side surfaces of the semiconductor substrate in portions corresponding to the connection pads of the semiconductor substrate. And a rewiring is provided on the upper surface of the second protective film so as to be connected to the connection pad of the semiconductor substrate, and a columnar electrode is provided on the upper surface of the connection pad portion of the rewiring. In some cases, a third protective film is provided on the upper surface of the second protective film including the rewiring around (see, for example, Patent Document 1).

特開２００１−３２６２９９号公報JP 2001-326299 A

上記従来の半導体装置では、半導体基板の下面、側面および上面つまり全表面が第１〜第３の保護膜で覆われているため、塵埃や湿気および機械的破損に対する保護効果が増すが、その反面、半導体基板に設けられた集積回路から発せられる熱が第１〜第３の保護膜内にこもり、放熱性が悪いという問題があった。   In the conventional semiconductor device described above, the lower surface, side surface, and upper surface, that is, the entire surface of the semiconductor substrate are covered with the first to third protective films, so that the protection effect against dust, moisture and mechanical damage is increased. There is a problem that heat generated from the integrated circuit provided on the semiconductor substrate is trapped in the first to third protective films and heat dissipation is poor.

そこで、この発明は、放熱性を良くすることができる半導体装置を提供することを目的とする。   In view of the above, an object of the present invention is to provide a semiconductor device capable of improving heat dissipation.

請求項１に記載の発明は、ベース板と、前記ベース板上に設けられ、且つ、半導体基板、該半導体基板上に設けられた複数の接続パッド、前記複数の接続パッドを覆う絶縁膜、該絶縁膜上に形成された下地金属層、該下地金属層上に形成された再配線、該再配線上に形成された複数の入出力用柱状電極および放熱用柱状電極、前記複数の入出力用柱状電極および放熱用柱状電極の周囲の前記保護膜上に設けられた封止膜を有する半導体構成体と、前記半導体構成体上およびその周囲における前記ベース板上に設けられた絶縁層と、前記半導体構成体上における前記絶縁層上に前記半導体構成体の前記複数の入出力用柱状電極に接続されて設けられ、且つ、接続パッド部を有する少なくとも１層の上層再配線と、前記半導体構成体上における前記絶縁層上に前記半導体構成体の複数の放熱用柱状電極に接続されて設けられた放熱層と、前記半導体構成体上における前記絶縁層上に設けられ前記放熱層の一部を露出する開口部を有するオーバーコート膜とを備えていることを特徴とするものである。
請求項２に記載の発明は、請求項１に記載の発明において、前記放熱層は前記上層再配線と同一の材料にて形成されていることを特徴とするものである。
請求項３に記載の発明は、請求項１に記載の発明において、前記半導体構成体上における前記絶縁層と前記オーバーコート膜との間に上層絶縁膜が設けられていることを特徴とするものである。
請求項４に記載の発明は、請求項３に記載の発明において、前記放熱層と前記絶縁層との間に中継放熱層が設けられていることを特徴とするものである。
請求項５に記載の発明は、請求項４に記載の発明において、前記上層再配線と前記入出力用柱状電極との間に別の上層再配線が設けられていることを特徴とするものである。
請求項６に記載の発明は、請求項５に記載の発明において、前記放熱層は前記上層再配線と同一の材料にて形成されていることを特徴とするものである。
請求項７に記載の発明は、請求項６に記載の発明において、前記上層再配線の接続パッド部上に半田ボールが設けられていることを特徴とするものである。 The invention described in claim 1 includes a base plate, a semiconductor substrate, a plurality of connection pads provided on the semiconductor substrate, an insulating film covering the plurality of connection pads, A base metal layer formed on the insulating film, a rewiring formed on the base metal layer, a plurality of input / output columnar electrodes and a heat radiation columnar electrode formed on the rewiring, the plurality of input / output electrodes A semiconductor structure having a sealing film provided on the protective film around the columnar electrode and the heat-dissipating columnar electrode; an insulating layer provided on the base plate on and around the semiconductor structure; At least one upper layer rewiring provided on the insulating layer on the semiconductor structure, connected to the plurality of input / output columnar electrodes of the semiconductor structure, and having a connection pad portion; and the semiconductor structure Before Opening that exposes a radiating layer that is provided is connected to a plurality of heat radiating columnar electrodes of the semiconductor structure on an insulating layer, a portion of the provided in the insulating layer in the semiconductor structure on said heat radiation layer The overcoat film | membrane which has this is characterized by the above-mentioned.
According to a second aspect of the present invention, in the first aspect of the present invention, the heat dissipation layer is formed of the same material as the upper layer rewiring.
The invention according to claim 3 is the invention according to claim 1, characterized in that an upper insulating film is provided between the insulating layer and the overcoat film on the semiconductor structure. It is.
The invention according to claim 4 is the invention according to claim 3, wherein a relay heat dissipation layer is provided between the heat dissipation layer and the insulating layer.
The invention according to claim 5 is the invention according to claim 4, wherein another upper layer rewiring is provided between the upper layer rewiring and the input / output columnar electrode. is there.
The invention according to claim 6 is the invention according to claim 5, wherein the heat dissipation layer is formed of the same material as that of the upper layer rewiring.
According to a seventh aspect of the invention, in the sixth aspect of the invention, a solder ball is provided on the connection pad portion of the upper layer rewiring.

この発明によれば、半導体基板を有する半導体構成体の下面、側面および上面がベース板、絶縁層および上層絶縁膜で覆われていても、半導体構成体の複数の放熱用柱状電極に接続された放熱層の上面の少なくとも一部を外部に露出させているので、放熱性を良くすることができる。   According to this invention, even if the lower surface, the side surface, and the upper surface of the semiconductor structure having a semiconductor substrate are covered with the base plate, the insulating layer, and the upper insulating film, they are connected to the plurality of heat radiation columnar electrodes of the semiconductor structure. Since at least a part of the upper surface of the heat dissipation layer is exposed to the outside, heat dissipation can be improved.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示す。この半導体装置は平面矩形形状のベース板１を備えている。ベース板１は、ガラス繊維、アラミド繊維、液晶繊維等にエポキシ系樹脂、ポリイミド系樹脂、ＢＴ（ビスマレイミド・トリアジン）樹脂、ＰＰＥ（ポリフェニレンエーテル）等を含浸させたもの、あるいは、シリコン、ガラス、セラミックス、樹脂単体等の絶縁材料からなっている。 (First embodiment)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. The semiconductor device includes a base plate 1 having a planar rectangular shape. The base plate 1 is made of glass fiber, aramid fiber, liquid crystal fiber or the like impregnated with epoxy resin, polyimide resin, BT (bismaleimide / triazine) resin, PPE (polyphenylene ether) or the like, or silicon, glass, It is made of an insulating material such as ceramics or resin.

ベース板１の上面中央部には、ベース板１のサイズよりもある程度小さいサイズの平面矩形形状の半導体構成体２の下面がダイボンド材からなる接着層３を介して接着されている。この場合、半導体構成体２は、後述する再配線、柱状電極、封止膜を有しており、一般的にはＣＳＰ(chip size package)と呼ばれるものであり、特に、後述の如く、シリコンウエハ上に再配線、柱状電極、封止膜を形成した後、ダイシングにより個々の半導体構成体２を得る方法を採用しているため、特に、ウエハレベルＣＳＰ（Ｗ−ＣＳＰ）とも言われている。以下に、半導体構成体２の構成について説明する。   The lower surface of a planar rectangular semiconductor structure 2 having a size somewhat smaller than the size of the base plate 1 is bonded to the central portion of the upper surface of the base plate 1 via an adhesive layer 3 made of a die bond material. In this case, the semiconductor structure 2 has a rewiring, a columnar electrode, and a sealing film, which will be described later, and is generally called a CSP (chip size package). Since a method of obtaining individual semiconductor structures 2 by dicing after forming rewiring, columnar electrodes, and a sealing film thereon is employed, it is also called wafer level CSP (W-CSP). Below, the structure of the semiconductor structure 2 is demonstrated.

半導体構成体２はシリコン基板（半導体基板）４を備えている。シリコン基板４は接着層３を介してベース板１に接着されている。シリコン基板４の上面中央部には所定の機能の集積回路（図示せず）が設けられ、上面周辺部にはアルミニウム系金属等からなる複数の接続パッド５が集積回路に接続されて設けられている。接続パッド５の中央部を除くシリコン基板４の上面には酸化シリコン等からなる絶縁膜６が設けられ、接続パッド５の中央部は絶縁膜６に設けられた開口部７を介して露出されている。   The semiconductor structure 2 includes a silicon substrate (semiconductor substrate) 4. The silicon substrate 4 is bonded to the base plate 1 via the adhesive layer 3. An integrated circuit (not shown) having a predetermined function is provided at the center of the upper surface of the silicon substrate 4, and a plurality of connection pads 5 made of aluminum-based metal or the like are provided at the periphery of the upper surface so as to be connected to the integrated circuit. Yes. An insulating film 6 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 4 excluding the central portion of the connection pad 5, and the central portion of the connection pad 5 is exposed through an opening 7 provided in the insulating film 6. Yes.

絶縁膜６の上面にはエポキシ系樹脂やポリイミド系樹脂等からなる保護膜（絶縁膜）８が設けられている。この場合、絶縁膜６の開口部７に対応する部分における保護膜８には開口部９が設けられている。両開口部７、９を介して露出された接続パッド５の上面から保護膜８の上面の所定の箇所にかけて、銅等からなる下地金属層１０が設けられている。下地金属層１０の上面全体には銅からなる再配線１１が設けられている。   A protective film (insulating film) 8 made of an epoxy resin, a polyimide resin, or the like is provided on the upper surface of the insulating film 6. In this case, an opening 9 is provided in the protective film 8 at a portion corresponding to the opening 7 of the insulating film 6. A base metal layer 10 made of copper or the like is provided from the upper surface of the connection pad 5 exposed through the openings 7 and 9 to a predetermined portion of the upper surface of the protective film 8. A rewiring 11 made of copper is provided on the entire upper surface of the base metal layer 10.

保護膜８の上面中央部の所定の箇所には銅等からなる複数の放熱用下地金属層１２が設けられている。放熱用下地金属層１２の上面全体には銅からなる放熱用再配線１３が設けられている。放熱用下地金属層１２および放熱用再配線１３は、どことも接続されていないが、それら同志で接続するようにしてもよい。   A plurality of base metal layers 12 for heat dissipation made of copper or the like are provided at predetermined locations in the central portion of the upper surface of the protective film 8. A heat dissipating rewiring 13 made of copper is provided on the entire upper surface of the heat dissipating base metal layer 12. The base metal layer 12 for heat dissipation and the rewiring 13 for heat dissipation are not connected anywhere, but may be connected together.

再配線１１の接続パッド部上面には高さ５０μｍ〜２００μｍの銅からなる柱状電極１４が設けられている。放熱用再配線１３の接続パッド部上面に放熱用柱状電極１５が設けられている。再配線１１および放熱用再配線１３を含む保護膜８の上面にはエポキシ系樹脂やポリイミド系樹脂等からなる封止膜（絶縁膜）１６がその上面が柱状電極１４および放熱用柱状電極１５の上面と面一となるように設けられている。   A columnar electrode 14 made of copper having a height of 50 μm to 200 μm is provided on the upper surface of the connection pad portion of the rewiring 11. A heat dissipation columnar electrode 15 is provided on the upper surface of the connection pad portion of the heat dissipation rewiring 13. On the upper surface of the protective film 8 including the rewiring 11 and the heat dissipating rewiring 13, a sealing film (insulating film) 16 made of epoxy resin, polyimide resin or the like is formed on the upper surface of the columnar electrode 14 and the heat dissipating columnar electrode 15. It is provided so as to be flush with the upper surface.

柱状電極１４と放熱用柱状電極１５について説明する。柱状電極１４は、再配線１４を介してシリコン基板４の主面上に形成された集積回路を構成する各素子や配線（図示せず）に接続された接続パッド５に接続され、これを外部回路に接続するための回路接続用（入出力用）電極である。これに対し、放熱用柱状電極１５はシリコン基板４の主面上に形成された集積回路（図示せず）を駆動する際に該集積回路から発生する熱を外部に放出するための放熱用電極である。   The columnar electrode 14 and the heat radiation columnar electrode 15 will be described. The columnar electrode 14 is connected to a connection pad 5 connected to each element and wiring (not shown) constituting the integrated circuit formed on the main surface of the silicon substrate 4 via the rewiring 14, and this is connected to the outside. It is a circuit connection (input / output) electrode for connecting to a circuit. On the other hand, the heat dissipation columnar electrode 15 is a heat dissipation electrode for releasing heat generated from the integrated circuit when driving the integrated circuit (not shown) formed on the main surface of the silicon substrate 4. It is.

放熱用柱状電極１５はシリコン基板４から発生する熱を十分に放出することができるようにその個数が設定される。放熱用柱状電極１５は、柱状電極１４と同一の材料および同一の工程で形成すると効率的である。また、その高さを柱状電極１４と同一にするため、再配線１１と同一の材料および同一の工程で形成される放熱用再配線１３上に形成されることが望ましい。   The number of the heat radiation columnar electrodes 15 is set so that the heat generated from the silicon substrate 4 can be sufficiently released. It is efficient to form the heat radiation column electrode 15 by the same material and the same process as the column electrode 14. Further, in order to make the height the same as that of the columnar electrode 14, it is desirable to form on the heat radiation rewiring 13 formed by the same material and the same process as the rewiring 11.

放熱用再配線１３は、図１においては放熱用柱状電極１５と同一の幅とされ、相互に分離されたものとして図示されているが、発生される熱を十分に吸収できる面積にすることが望ましく、放熱用柱状電極１５よりも大きい幅としたり、上述の如く、相互に連続する一体のものとして形成してもよい。   In FIG. 1, the heat redistribution wiring 13 has the same width as the heat radiation columnar electrode 15 and is illustrated as being separated from each other. However, the heat redistribution wiring 13 should have an area capable of sufficiently absorbing the generated heat. Desirably, the width may be larger than that of the heat-dissipating columnar electrode 15 or may be formed as an integral one continuous with each other as described above.

このように、Ｗ−ＣＳＰと呼ばれる半導体構成体２は、シリコン基板４、接続パッド５、絶縁膜６を含み、さらに、保護膜８、再配線１１、放熱用再配線１３、柱状電極１４、放熱用柱状電極１５、封止膜１６を含んで構成されている。   As described above, the semiconductor structure 2 called W-CSP includes the silicon substrate 4, the connection pad 5, and the insulating film 6, and further includes a protective film 8, a rewiring 11, a heat rewiring 13, a columnar electrode 14, and a heat dissipation. The columnar electrode 15 and the sealing film 16 are included.

半導体構成体２の周囲におけるベース板１の上面には矩形枠状の絶縁層１７がその上面が半導体構成体２の上面とほぼ面一となるように設けられている。絶縁層１７は、通常、プリプレグ材と言われるもので、例えば、ガラス繊維やアラミド繊維にエポキシ系樹脂やＢＴ樹脂等の熱硬化性樹脂を含浸させたものである。   A rectangular frame-shaped insulating layer 17 is provided on the upper surface of the base plate 1 around the semiconductor structure 2 so that the upper surface is substantially flush with the upper surface of the semiconductor structure 2. The insulating layer 17 is usually referred to as a prepreg material. For example, a glass fiber or an aramid fiber is impregnated with a thermosetting resin such as an epoxy resin or a BT resin.

半導体構成体２および絶縁層１７の上面には絶縁層１８がその上面を平坦とされて設けられている。絶縁層１８は、ビルドアップ基板に用いられる、通常、ビルドアップ材と言われるもので、例えば、エポキシ系樹脂やＢＴ樹脂等の熱硬化性樹脂中に繊維やフィラー等の補強材を含有させたものである。この場合、繊維は、ガラス繊維やアラミド繊維等である。フィラーは、シリカフィラーやセラミックス系フィラー等である。   An insulating layer 18 is provided on the upper surface of the semiconductor structure 2 and the insulating layer 17 so that the upper surface is flat. The insulating layer 18 is generally used as a build-up material used for a build-up substrate. For example, a reinforcing material such as a fiber or a filler is contained in a thermosetting resin such as an epoxy resin or a BT resin. Is. In this case, the fiber is glass fiber, aramid fiber, or the like. The filler is a silica filler or a ceramic filler.

絶縁層１８の上面の中央部を除く領域の所定の箇所には銅等からなる上層下地金属層１９が設けられている。上層下地金属層１９の上面全体には銅からなる上層再配線２０が設けられている。上層下地金属層１９を含む上層再配線２０は、柱状電極１４の上面中央部に対応する部分における絶縁層１８に設けられた開口部２１を介して柱状電極１４の上面に接続されている。   An upper base metal layer 19 made of copper or the like is provided in a predetermined portion of the region excluding the central portion of the upper surface of the insulating layer 18. An upper layer rewiring 20 made of copper is provided on the entire upper surface of the upper base metal layer 19. The upper layer rewiring 20 including the upper base metal layer 19 is connected to the upper surface of the columnar electrode 14 through an opening 21 provided in the insulating layer 18 in a portion corresponding to the central portion of the upper surface of the columnar electrode 14.

絶縁層１８の上面中央部には銅等からなる放熱用下地金属層２２が島状に設けられている。放熱用下地金属層２２の上面全体には銅からなる放熱層２３が設けられている。放熱用下地金属層２２を含む放熱層２３は、放熱用柱状電極１５の上面中央部に対応する部分における絶縁層１８に設けられた開口部２４を介して放熱用柱状電極１５の上面に接続されている。   A heat-dissipating base metal layer 22 made of copper or the like is provided in an island shape at the center of the upper surface of the insulating layer 18. A heat dissipation layer 23 made of copper is provided on the entire upper surface of the heat dissipation base metal layer 22. The heat dissipation layer 23 including the heat dissipation base metal layer 22 is connected to the upper surface of the heat dissipation columnar electrode 15 through an opening 24 provided in the insulating layer 18 in a portion corresponding to the center of the upper surface of the heat dissipation columnar electrode 15. ing.

上層再配線２０および放熱層２３を含む絶縁層１８の上面にはソルダーレジスト等からなるオーバーコート膜２５が設けられている。上層再配線２０の接続パッド部に対応する部分におけるオーバーコート膜２５には開口部２６が設けられている。開口部２６内およびその上方には半田ボール２７が上層再配線２０の接続パッド部に接続されて設けられている。複数の半田ボール２７は、オーバーコート膜２５の上面の中央部を除く領域にマトリクス状に配置されている。放熱層２３の中央部に対応する部分におけるオーバーコート膜２５には開口部２８が設けられている。したがって、放熱層２３の中央部はこの開口部２８を介して外部に露出されている。   An overcoat film 25 made of a solder resist or the like is provided on the upper surface of the insulating layer 18 including the upper layer rewiring 20 and the heat dissipation layer 23. An opening 26 is provided in the overcoat film 25 in a portion corresponding to the connection pad portion of the upper layer rewiring 20. Solder balls 27 are provided in and above the opening 26 so as to be connected to the connection pad portion of the upper layer rewiring 20. The plurality of solder balls 27 are arranged in a matrix in a region excluding the central portion of the upper surface of the overcoat film 25. An opening 28 is provided in the overcoat film 25 at a portion corresponding to the central portion of the heat dissipation layer 23. Therefore, the central portion of the heat dissipation layer 23 is exposed to the outside through the opening 28.

以上のように、この半導体装置では、シリコン基板１を有する半導体構成体２の下面、側面および上面がベース板１、絶縁層１７、絶縁層１８およびオーバーコート膜２５で覆われていても、半導体構成体２の放熱用柱状電極１５（放熱用再配線１３および放熱用下地金属層１２を含む）に接続された放熱層２３（放熱用下地金属層２２を含む）をオーバーコート膜（最上層の上層絶縁膜）２５の開口部２８を介して外部に露出させているので、放熱性を良くすることができる。   As described above, in this semiconductor device, even if the lower surface, the side surface, and the upper surface of the semiconductor structure 2 having the silicon substrate 1 are covered with the base plate 1, the insulating layer 17, the insulating layer 18, and the overcoat film 25, A heat dissipation layer 23 (including the heat dissipation base metal layer 22) connected to the heat dissipation columnar electrode 15 (including the heat dissipation rewiring 13 and the heat dissipation base metal layer 12) of the structure 2 is overcoated with the overcoat film (uppermost layer). Since it is exposed to the outside through the opening 28 of the (upper insulating film) 25, heat dissipation can be improved.

ところで、ベース板１のサイズを半導体構成体２のサイズよりもある程度大きくしているのは、シリコン基板４上の接続パッド５の数の増加に応じて、半田ボール２７の配置領域を半導体構成体２のサイズよりもある程度大きくし、これにより、上層再配線２０の接続パッド部（オーバーコート膜２５の開口部２６内の部分）のサイズおよびピッチを柱状電極１４のサイズおよびピッチよりも大きくするためである。   By the way, the size of the base plate 1 is made somewhat larger than the size of the semiconductor structure 2 because the area where the solder balls 27 are arranged is increased as the number of connection pads 5 on the silicon substrate 4 increases. In order to make the size and pitch of the connection pad portion (the portion in the opening 26 of the overcoat film 25) of the upper layer rewiring 20 larger than the size of the columnar electrode 14, It is.

このため、マトリクス状に配置された上層再配線２０の接続パッド部は、半導体構成体２に対応する領域のみでなく、半導体構成体２の側面の外側に設けられた絶縁層１７に対応する領域上にも配置されている。つまり、マトリクス状に配置された半田ボール２７のうち、少なくとも最外周の半田ボール２７は半導体構成体２よりも外側に位置する周囲に配置されている。   For this reason, the connection pad portion of the upper layer rewiring 20 arranged in a matrix form not only the region corresponding to the semiconductor structure 2 but also the region corresponding to the insulating layer 17 provided outside the side surface of the semiconductor structure 2. It is also arranged on the top. That is, among the solder balls 27 arranged in a matrix, at least the outermost solder balls 27 are arranged around the semiconductor structure 2.

次に、この半導体装置の製造方法の一例について説明するに、まず、半導体構成体２の製造方法の一例について説明する。この場合、まず、図２に示すように、ウエハ状態のシリコン基板４上にアルミニウム系金属等からなる接続パッド５、酸化シリコン等からなる絶縁膜６およびエポキシ系樹脂やポリイミド系樹脂等からなる保護膜８が設けられ、接続パッド５の中央部が絶縁膜６および保護膜８に形成された開口部７、９を介して露出されたものを用意する。この場合、ウエハ状態のシリコン基板４の上面において各半導体構成体が形成される領域には所定の機能の集積回路が形成され、接続パッド５はそれぞれ対応する領域に形成された集積回路に電気的に接続されている。   Next, an example of a method for manufacturing the semiconductor device 2 will be described. In this case, first, as shown in FIG. 2, on the silicon substrate 4 in a wafer state, a connection pad 5 made of aluminum metal or the like, an insulating film 6 made of silicon oxide or the like, and a protection made of epoxy resin or polyimide resin or the like. A film 8 is provided, and a central portion of the connection pad 5 is exposed through openings 7 and 9 formed in the insulating film 6 and the protective film 8. In this case, an integrated circuit having a predetermined function is formed in a region where each semiconductor structure is formed on the upper surface of the silicon substrate 4 in a wafer state, and the connection pads 5 are electrically connected to the integrated circuits formed in the corresponding regions. It is connected to the.

次に、図３に示すように、両開口部７、９を介して露出された接続パッド５の上面を含む保護膜８の上面全体に下地金属層３１を形成する。この場合、下地金属層３１は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。これは、後述する上層下地金属層４５の場合も同様である。   Next, as shown in FIG. 3, a base metal layer 31 is formed on the entire upper surface of the protective film 8 including the upper surfaces of the connection pads 5 exposed through the openings 7 and 9. In this case, the base metal layer 31 may be only a copper layer formed by electroless plating, may be only a copper layer formed by sputtering, or a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering. The same applies to the case of the upper base metal layer 45 described later.

次に、下地金属層３１の上面にメッキレジスト膜３２をパターン形成する。この場合、再配線１１形成領域および放熱用再配線１３形成領域に対応する部分におけるメッキレジスト膜３２には開口部３３、３４が形成されている。次に、下地金属層３１をメッキ電流路とした銅の電解メッキを行なうことにより、メッキレジスト膜３２の開口部３３、３４内の下地金属層３１の上面に再配線１１および放熱用再配線１３を形成する。次に、メッキレジスト膜３２を剥離する。   Next, a plating resist film 32 is patterned on the upper surface of the base metal layer 31. In this case, openings 33 and 34 are formed in the plating resist film 32 in portions corresponding to the rewiring 11 forming region and the heat dissipating rewiring 13 forming region. Next, by performing electrolytic plating of copper using the base metal layer 31 as a plating current path, the rewiring 11 and the heat dissipation rewiring 13 are formed on the upper surface of the base metal layer 31 in the openings 33 and 34 of the plating resist film 32. Form. Next, the plating resist film 32 is peeled off.

次に、図４に示すように、再配線１１および放熱用再配線１３を含む下地金属層３１の上面にメッキレジスト膜３５をパターン形成する。この場合、柱状電極１４形成領域および放熱用柱状電極１５形成領域に対応する部分におけるメッキレジスト膜３５には開口部３６、３７が形成されている。次に、下地金属層３１をメッキ電流路とした銅の電解メッキを行なうことにより、メッキレジスト膜３５の開口部３６、３７内の再配線１１および放熱用再配線１３の接続パッド部上面に柱状電極１４および放熱用柱状電極１５を形成する。   Next, as shown in FIG. 4, a plating resist film 35 is formed on the upper surface of the base metal layer 31 including the rewiring 11 and the heat dissipating rewiring 13. In this case, openings 36 and 37 are formed in the plating resist film 35 in portions corresponding to the columnar electrode 14 formation region and the heat radiation columnar electrode 15 formation region. Next, by performing electrolytic plating of copper using the base metal layer 31 as a plating current path, a columnar shape is formed on the upper surface of the connection pad portion of the rewiring 11 and the rewiring rewiring 13 in the openings 36 and 37 of the plating resist film 35. The electrode 14 and the columnar electrode 15 for heat dissipation are formed.

次に、メッキレジスト膜３５を剥離し、次いで、柱状電極１４、放熱用柱状電極１５、再配線１１および放熱用再配線１３をマスクとして下地金属層３１の不要な部分をエッチングして除去すると、図５に示すように、再配線１１および放熱用再配線１３下にのみ下地金属層１０および放熱用下地金属層１２が残存される。   Next, the plating resist film 35 is peeled off, and then unnecessary portions of the base metal layer 31 are removed by etching using the columnar electrode 14, the heat radiation columnar electrode 15, the rewiring 11 and the heat radiation rewiring 13 as a mask. As shown in FIG. 5, the base metal layer 10 and the heat dissipation base metal layer 12 remain only under the rewiring 11 and the heat dissipation rewiring 13.

次に、図６に示すように、スクリーン印刷法、スピンコーティング法、ダイコート法等により、柱状電極１４、放熱用柱状電極１５、再配線１１および放熱用再配線１３を含む保護膜８の上面全体にエポキシ系樹脂やポリイミド系樹脂等からなる封止膜１６をその厚さが柱状電極１４および放熱用柱状電極１５の高さよりも厚くなるように形成する。したがって、この状態では、柱状電極１４および放熱用柱状電極１５の上面は封止膜１６によって覆われている。   Next, as shown in FIG. 6, the entire upper surface of the protective film 8 including the columnar electrode 14, the heat radiation columnar electrode 15, the rewiring 11, and the heat radiation rewiring 13 is formed by screen printing, spin coating, die coating, or the like. Further, the sealing film 16 made of epoxy resin, polyimide resin or the like is formed so that its thickness is thicker than the height of the columnar electrode 14 and the columnar electrode 15 for heat dissipation. Therefore, in this state, the upper surfaces of the columnar electrode 14 and the heat radiation columnar electrode 15 are covered with the sealing film 16.

次に、封止膜１６、柱状電極１４および放熱用柱状電極１５の上面側を適宜に研磨し、図７に示すように、柱状電極１４および放熱用柱状電極１５の上面を露出させ、且つ、この露出された柱状電極１４および放熱用柱状電極１５の上面を含む封止膜１６の上面を平坦化する。ここで、柱状電極１４および放熱用柱状電極１５の上面側を適宜に研磨するのは、電解メッキにより形成される柱状電極１４および放熱用柱状電極１５の高さにばらつきがあるため、このばらつきを解消して、柱状電極１４および放熱用柱状電極１５の高さを均一にするためである。   Next, the upper surfaces of the sealing film 16, the columnar electrode 14 and the heat radiation columnar electrode 15 are appropriately polished to expose the upper surfaces of the columnar electrode 14 and the heat radiation columnar electrode 15 as shown in FIG. The upper surface of the sealing film 16 including the exposed upper surfaces of the columnar electrodes 14 and the heat radiation columnar electrodes 15 is planarized. Here, the reason why the upper surface side of the columnar electrode 14 and the heat radiation columnar electrode 15 is appropriately polished is that the height of the columnar electrode 14 and the heat radiation columnar electrode 15 formed by electrolytic plating varies. This is because the height of the columnar electrode 14 and the columnar electrode 15 for heat dissipation is made uniform.

次に、図８に示すように、シリコン基板４の下面全体に接着層３を接着する。接着層３は、エポキシ系樹脂、ポリイミド系樹脂等のダイボンド材からなるものであり、加熱加圧により、半硬化した状態でシリコン基板４に固着する。次に、シリコン基板４に固着された接着層３をダイシングテープ（図示せず）に貼り付け、図９に示すダイシング工程を経た後に、ダイシングテープから剥がすと、図１に示すように、シリコン基板４の下面に接着層３を有する半導体構成体２が複数個得られる。   Next, as shown in FIG. 8, the adhesive layer 3 is bonded to the entire lower surface of the silicon substrate 4. The adhesive layer 3 is made of a die bond material such as an epoxy resin or a polyimide resin, and is fixed to the silicon substrate 4 in a semi-cured state by heating and pressing. Next, the adhesive layer 3 fixed to the silicon substrate 4 is affixed to a dicing tape (not shown), passed through the dicing step shown in FIG. 9, and then peeled off from the dicing tape, as shown in FIG. A plurality of semiconductor structures 2 having the adhesive layer 3 on the lower surface of 4 are obtained.

このようにして得られた半導体構成体２では、シリコン基板４の下面に接着層３を有するため、ダイシング工程後に各半導体構成体２のシリコン基板４の下面にそれぞれ接着層を設けるといった極めて面倒な作業が不要となる。なお、ダイシング工程後にダイシングテープから剥がす作業は、ダイシング工程後に各半導体構成体２のシリコン基板４の下面にそれぞれ接着層を設ける作業に比べれば、極めて簡単である。   Since the semiconductor structure 2 obtained in this way has the adhesive layer 3 on the lower surface of the silicon substrate 4, it is extremely troublesome to provide an adhesive layer on the lower surface of the silicon substrate 4 of each semiconductor structure 2 after the dicing process. Work becomes unnecessary. In addition, the operation | work which peels from a dicing tape after a dicing process is very simple compared with the operation | work which each provides an adhesive layer on the lower surface of the silicon substrate 4 of each semiconductor structure 2 after a dicing process.

次に、このようにして得られた半導体構成体２を用いて、図１に示す半導体装置を製造する場合の一例について説明する。まず、図１０に示すように、図１に示すベース板１を複数枚採取することができる大きさで、限定する意味ではないが、平面形状が矩形形状のベース板１を用意する。次に、ベース板１の上面の所定の複数箇所にそれぞれ半導体構成体２のシリコン基板４の下面に接着された接着層３を接着する。ここでの接着は、加熱加圧により、接着層３を本硬化させる。   Next, an example of manufacturing the semiconductor device shown in FIG. 1 using the semiconductor structure 2 obtained in this way will be described. First, as shown in FIG. 10, the base plate 1 is prepared in such a size that a plurality of the base plates 1 shown in FIG. Next, the adhesive layer 3 bonded to the lower surface of the silicon substrate 4 of the semiconductor structure 2 is bonded to a plurality of predetermined locations on the upper surface of the base plate 1. In this bonding, the adhesive layer 3 is fully cured by heating and pressing.

次に、半導体構成体２間および最外周に配置された半導体構成体２の外側におけるベース板１の上面に、例えば、格子状でシート状の第１の絶縁材料１７ａを位置決めして配置し、さらにその上面にシート状の第２の絶縁材料１８ａを配置する。なお、第１の絶縁材料１７ａを配置した後に、半導体構成体２を配置するようにしてもよい。   Next, for example, a grid-like and sheet-like first insulating material 17a is positioned and arranged on the upper surface of the base plate 1 between the semiconductor structural bodies 2 and outside the semiconductor structural bodies 2 disposed on the outermost periphery. Further, a sheet-like second insulating material 18a is disposed on the upper surface. Note that the semiconductor structure 2 may be disposed after the first insulating material 17a is disposed.

格子状の第１の絶縁材料１７ａは、ガラス繊維にエポキシ系樹脂等の熱硬化性樹脂を含浸させ、熱硬化性樹脂を半硬化状態にしてシート状となしたプリプレグ材に、型抜き加工やエッチング等により複数の矩形形状の貫通孔４１を形成することにより得られる。この場合、第１の絶縁材料１７ａは、平坦性を得るためにシート状であることが好ましいが、必ずしもプリプレグ材に限られるものではなく、熱硬化性樹脂や、熱硬化性樹脂中にガラス繊維やシリカフィラー等の補強材を分散させたものであってもよい。   The lattice-shaped first insulating material 17a is formed by impregnating glass fibers with a prepreg material in which a glass fiber is impregnated with a thermosetting resin such as an epoxy resin and the thermosetting resin is semi-cured into a sheet shape. It is obtained by forming a plurality of rectangular through holes 41 by etching or the like. In this case, the first insulating material 17a is preferably in the form of a sheet in order to obtain flatness, but is not necessarily limited to the prepreg material, and is not limited to a thermosetting resin or a glass fiber in the thermosetting resin. Alternatively, a reinforcing material such as silica filler may be dispersed.

シート状の第２の絶縁材料１８ａは、限定する意味ではないが、ビルドアップ材が好ましく、このビルドアップ材としては、エポキシ系樹脂やＢＴ樹脂等の熱硬化性樹脂中にシリカフィラーを混入させ、熱硬化性樹脂を半硬化状態にしたものがある。しかしながら、第２の絶縁材料１８ａとして、上述のプリプレグ材、またはフィラーが混入されない、熱硬化性樹脂のみからなる材料を用いるようにしてもよい。   The sheet-like second insulating material 18a is not limited, but a build-up material is preferable. As this build-up material, a silica filler is mixed in a thermosetting resin such as an epoxy resin or a BT resin. Some thermosetting resins are in a semi-cured state. However, as the second insulating material 18a, the above-described prepreg material or a material made of only a thermosetting resin that is not mixed with the filler may be used.

ここで、第１の絶縁材料１７ａの貫通孔４１のサイズは半導体構成体２のサイズよりもやや大きくなっている。このため、第１の絶縁材料１７ａと半導体構成体２との間には隙間４２が形成されている。この隙間４２の間隔は、一例として、０．２ｍｍ程度である。また、第１の絶縁材料１７ａの厚さは、半導体構成体２の厚さよりも厚く、後述の如く、加熱加圧されたときに、隙間４２を十分に埋めることができる程度の厚さとなっている。   Here, the size of the through hole 41 of the first insulating material 17 a is slightly larger than the size of the semiconductor structure 2. For this reason, a gap 42 is formed between the first insulating material 17 a and the semiconductor structure 2. As an example, the gap 42 is about 0.2 mm. Further, the thickness of the first insulating material 17a is thicker than the thickness of the semiconductor structure 2, and is a thickness that can sufficiently fill the gap 42 when heated and pressurized as will be described later. Yes.

次に、図１１に示すように、一対の加熱加圧板４３、４４を用いて、第１および第２の絶縁材料１７ａ、１８ａを加熱加圧する。すると、第１の絶縁材料１７ａ中の溶融された熱硬化性樹脂が押し出されて、図１０に示す、第１の絶縁材料１７ａと半導体構成体２との間の隙間４２に充填され、その後の冷却により各半導体構成体２および各半導体構成体２間のベース板１に固着した状態で固化する。かくして、図１１に示すように、半導体構成体２間および最外周に配置された半導体構成体２の外側におけるベース板１の上面に絶縁層１７が形成され、半導体構成体２および絶縁層１７の上面に絶縁層１８が形成される。   Next, as shown in FIG. 11, the first and second insulating materials 17 a and 18 a are heated and pressurized using a pair of heating and pressing plates 43 and 44. Then, the molten thermosetting resin in the first insulating material 17a is pushed out and filled in the gap 42 between the first insulating material 17a and the semiconductor structure 2 shown in FIG. By cooling, the semiconductor structure 2 and the base plate 1 between the semiconductor structures 2 are solidified in a fixed state. Thus, as shown in FIG. 11, the insulating layer 17 is formed on the upper surface of the base plate 1 between the semiconductor structural bodies 2 and outside the semiconductor structural bodies 2 arranged at the outermost periphery, and the semiconductor structural body 2 and the insulating layers 17 An insulating layer 18 is formed on the upper surface.

この場合、絶縁層１８の上面は、上側の加熱加圧板４３の下面によって押さえ付けられるため、平坦面となる。したがって、絶縁層１８の上面を平坦化するための研磨工程は不要である。このため、ベース板１のサイズが例えば５００×５００ｍｍ程度と比較的大きくても、その上に配置された複数の半導体構成体２に対して絶縁層１８の上面の平坦化を一括して簡単に行なうことができる。   In this case, since the upper surface of the insulating layer 18 is pressed by the lower surface of the upper heating and pressing plate 43, it becomes a flat surface. Therefore, a polishing step for flattening the upper surface of the insulating layer 18 is unnecessary. For this reason, even if the size of the base plate 1 is relatively large, for example, about 500 × 500 mm, the flattening of the upper surface of the insulating layer 18 can be easily performed collectively for the plurality of semiconductor structures 2 arranged thereon. Can be done.

次に、図１２に示すように、レーザビームを照射するレーザ加工により、柱状電極１４および放熱用柱状電極１５の上面中央部に対応する部分における絶縁層１８に開口部２１、２４を形成する。次に、必要に応じて、開口部２１、２４内等に発生したエポキシスミア等をデスミア処理により除去する。   Next, as shown in FIG. 12, openings 21 and 24 are formed in the insulating layer 18 at portions corresponding to the center portions of the upper surfaces of the columnar electrode 14 and the heat radiation columnar electrode 15 by laser processing with laser beam irradiation. Next, the epoxy smear etc. which generate | occur | produced in the opening parts 21 and 24 etc. are removed by a desmear process as needed.

次に、図１３に示すように、開口部２１、２４を介して露出された柱状電極１４および放熱用柱状電極１５の上面を含む絶縁層１８の上面全体に上層下地金属層４５を形成する。次に、上層下地金属層４５の上面にメッキレジスト膜４６をパターン形成する。この場合、上層再配線２０形成領域および放熱層２３形成領域に対応する部分におけるメッキレジスト膜４６には開口部４７、４８が形成されている。   Next, as shown in FIG. 13, the upper base metal layer 45 is formed on the entire upper surface of the insulating layer 18 including the upper surfaces of the columnar electrode 14 and the heat-dissipating columnar electrode 15 exposed through the openings 21 and 24. Next, a plating resist film 46 is patterned on the upper surface of the upper base metal layer 45. In this case, openings 47 and 48 are formed in the plating resist film 46 at portions corresponding to the upper layer rewiring 20 formation region and the heat dissipation layer 23 formation region.

次に、上層下地金属層４５をメッキ電流路とした銅の電解メッキを行なうことにより、メッキレジスト膜４６の開口部４７、４８内の上層下地金属層４５の上面に上層再配線２０および放熱層２３を形成する。次に、メッキレジスト膜４６を剥離し、次いで、上層再配線２０および放熱層２３をマスクとして上層下地金属層４５の不要な部分をエッチングして除去すると、図１４に示すように、上層再配線２０および放熱層２３下にのみ上層下地金属層１９および放熱用下地金属層２２が残存される。   Next, by performing electrolytic plating of copper using the upper base metal layer 45 as a plating current path, the upper layer rewiring 20 and the heat dissipation layer are formed on the upper surface of the upper base metal layer 45 in the openings 47 and 48 of the plating resist film 46. 23 is formed. Next, the plating resist film 46 is peeled off, and then unnecessary portions of the upper base metal layer 45 are removed by etching using the upper layer rewiring 20 and the heat dissipation layer 23 as a mask, as shown in FIG. The upper base metal layer 19 and the heat dissipating base metal layer 22 remain only under 20 and the heat dissipating layer 23.

次に、図１５に示すように、スクリーン印刷法やスピンコーティング法等により、上層再配線２０および放熱層２３を含む絶縁層１８の上面にソルダーレジスト等からなるオーバーコート膜２５を形成する。この場合、上層再配線２０の接続パッド部に対応する部分におけるオーバーコート膜２５には開口部２６が形成されている。また、放熱層２３の中央部に対応する部分における第２の下層絶縁膜２５には開口部２８が形成されている。   Next, as shown in FIG. 15, an overcoat film 25 made of a solder resist or the like is formed on the upper surface of the insulating layer 18 including the upper layer rewiring 20 and the heat dissipation layer 23 by a screen printing method, a spin coating method, or the like. In this case, an opening 26 is formed in the overcoat film 25 in a portion corresponding to the connection pad portion of the upper layer rewiring 20. An opening 28 is formed in the second lower insulating film 25 in a portion corresponding to the central portion of the heat dissipation layer 23.

次に、開口部２６内およびその上方に半田ボール２７を上層再配線２０の接続パッド部に接続させて形成する。次に、互いに隣接する半導体構成体２間において、オーバーコート膜２５、絶縁層１８、絶縁層１７およびベース板１を切断すると、図１に示す半導体装置が複数個得られる。   Next, solder balls 27 are formed in and above the opening 26 by connecting to the connection pad portion of the upper layer rewiring 20. Next, when the overcoat film 25, the insulating layer 18, the insulating layer 17, and the base plate 1 are cut between adjacent semiconductor structures 2, a plurality of semiconductor devices shown in FIG. 1 are obtained.

以上のように、上記製造方法では、ベース板１上に複数の半導体構成体２を接着層３を介して配置し、複数の半導体構成体２に対して、特に、上層再配線２０、放熱層２３および半田ボール２７の形成を一括して行い、その後に分断して複数個の半導体装置を得ているので、製造工程を簡略化することができる。また、図１１に示す製造工程以降では、ベース板１と共に複数の半導体構成体２を搬送することができるので、これによっても製造工程を簡略化することができる。   As described above, in the above manufacturing method, a plurality of semiconductor structures 2 are arranged on the base plate 1 via the adhesive layer 3, and the upper layer rewiring 20, the heat dissipation layer, in particular, with respect to the plurality of semiconductor structures 2. 23 and solder balls 27 are formed in a lump and then divided into a plurality of semiconductor devices, so that the manufacturing process can be simplified. Moreover, since the several semiconductor structure 2 can be conveyed with the base board 1 after the manufacturing process shown in FIG. 11, a manufacturing process can also be simplified by this.

（第２実施形態）
図１６はこの発明の第２実施形態としての半導体装置の断面図を示す。この半導体装置において、図１に示す場合と異なる点は、ベース板１の下面中央部に放熱用下地金属層５１および放熱層５２が設けられ、放熱層５２を含む放熱用下地金属層５１が、ベース板１と半導体構成体２のシリコン基板４との間に設けられた中継放熱層５３に、ベース板１に設けられた貫通孔５４を介して接続された点である。 (Second Embodiment)
FIG. 16 is a sectional view of a semiconductor device as a second embodiment of the present invention. In this semiconductor device, the difference from the case shown in FIG. 1 is that a heat dissipation base metal layer 51 and a heat dissipation layer 52 are provided at the center of the lower surface of the base plate 1, and the heat dissipation base metal layer 51 including the heat dissipation layer 52 is This is a point connected to a relay heat dissipation layer 53 provided between the base plate 1 and the silicon substrate 4 of the semiconductor structure 2 through a through hole 54 provided in the base plate 1.

この場合、中継放熱層５３は銅箔からなり、ベース板１の上面中央部に予め積層されている。そして、シリコン基板４の下面は、中継放熱層５３の上面に、導電性樹脂や導電性ペースト等からなる導電性接着層５５を介して接着されている。導電性接着層５５を用いるのは、シリコン基板４から中継放熱層５３への熱伝導を良くするためである。また、貫通孔５４は、上層絶縁膜１８に開口部２１をレーザ加工により形成する前または形成した後に、レーザ加工により形成されている。さらに、放熱用下地金属層５１および放熱層５２は、上層下地金属層１９および上層再配線２０の形成と同時に形成されている。   In this case, the relay heat dissipation layer 53 is made of copper foil and is laminated in advance on the center of the upper surface of the base plate 1. The lower surface of the silicon substrate 4 is bonded to the upper surface of the relay heat dissipation layer 53 via a conductive adhesive layer 55 made of a conductive resin, a conductive paste, or the like. The reason why the conductive adhesive layer 55 is used is to improve the heat conduction from the silicon substrate 4 to the relay heat dissipation layer 53. The through hole 54 is formed by laser processing before or after the opening 21 is formed in the upper insulating film 18 by laser processing. Further, the heat-dissipating base metal layer 51 and the heat-dissipating layer 52 are formed simultaneously with the formation of the upper base metal layer 19 and the upper layer rewiring 20.

そして、この半導体装置では、シリコン基板１を有する半導体構成体２の下面、側面および上面がベース板１、絶縁層１７、絶縁層１８およびオーバーコート膜２５で覆われていても、放熱層２３（放熱用下地金属層２２を含む）をオーバーコート膜２５の開口部２８を介して外部に露出させているほかに、半導体構成体２のシリコン基板４に導電性接着層５５および中継放熱層５３を介して接続された放熱層５２（放熱用下地金属層５１を含む）をベース板１の下面に露出させているので、放熱性をより一層良くすることができる。   In this semiconductor device, even if the lower surface, side surface, and upper surface of the semiconductor structure 2 having the silicon substrate 1 are covered with the base plate 1, the insulating layer 17, the insulating layer 18, and the overcoat film 25, the heat dissipation layer 23 ( In addition to exposing the heat dissipation base metal layer 22 to the outside through the opening 28 of the overcoat film 25, the conductive adhesive layer 55 and the relay heat dissipation layer 53 are formed on the silicon substrate 4 of the semiconductor structure 2. Since the heat dissipation layer 52 (including the heat dissipating base metal layer 51) is exposed on the lower surface of the base plate 1, heat dissipation can be further improved.

（第３実施形態）
上記第１実施形態では、図１に示すように、絶縁層１８上に上層再配線２０を１層だけ形成した場合について説明したが、これに限らず、２層以上としてもよく、例えば、図１７に示すこの発明の第３実施形態のように、２層としてもよい。すなわち、半導体構成体２および絶縁層１７の上面にはビルドアップ材等からなる絶縁層６１が設けられている。 (Third embodiment)
In the first embodiment, the case where only one upper layer rewiring 20 is formed on the insulating layer 18 as shown in FIG. 1 has been described. However, the present invention is not limited to this, and two or more layers may be used. As in the third embodiment of the present invention shown in FIG. That is, the insulating layer 61 made of a build-up material or the like is provided on the upper surfaces of the semiconductor structure 2 and the insulating layer 17.

絶縁層６１の上面の中央部を除く領域には第１の上層下地金属層６２を含む第１の上層再配線６３が絶縁層６１に形成された開口部６４を介して半導体構成体２の柱状電極１４の上面に接続されて設けられている。絶縁層６１の上面中央部には中継下地金属層６５を含む中継放熱層６６が絶縁層６１に形成された開口部６７を介して半導体構成体２の放熱用柱状電極１５の上面に接続されて設けられている。   A first upper layer rewiring 63 including a first upper base metal layer 62 is formed in a region of the semiconductor structure 2 in a column shape of the semiconductor structure 2 through an opening 64 formed in the insulating layer 61 in a region excluding the central portion of the upper surface of the insulating layer 61. It is connected to the upper surface of the electrode 14. A relay heat dissipation layer 66 including a relay base metal layer 65 is connected to the upper surface of the heat dissipation columnar electrode 15 of the semiconductor structure 2 through an opening 67 formed in the insulating layer 61 at the center of the upper surface of the insulating layer 61. Is provided.

第１の上層再配線６３および中継放熱層６６を含む絶縁層６１の上面にはビルドアップ材等からなる上層絶縁膜６８が設けられている。上層絶縁膜６８の上面の中央部を除く領域には第２の上層下地金属層６９を含む第２の上層再配線７０が上層絶縁膜６８に形成された開口部７１を介して第１の上層再配線６３の接続パッド部に接続されて設けられている。上層絶縁膜６８の上面中央部には放熱用下地金属層７２を含む放熱層７３が上層絶縁膜６８に形成された開口部７４を介して中継放熱層６６に接続されて設けられている。   An upper insulating film 68 made of a build-up material or the like is provided on the upper surface of the insulating layer 61 including the first upper layer rewiring 63 and the relay heat dissipation layer 66. In a region other than the central portion of the upper surface of the upper insulating film 68, a second upper layer rewiring 70 including the second upper base metal layer 69 is provided via the opening 71 formed in the upper insulating film 68. It is connected to the connection pad portion of the rewiring 63. A heat dissipation layer 73 including a heat dissipation base metal layer 72 is connected to the relay heat dissipation layer 66 through an opening 74 formed in the upper insulating film 68 at the center of the upper surface of the upper insulating film 68.

第２の上層再配線７０および放熱層７３を含む上層絶縁膜６８の上面にはソルダーレジスト等からなるオーバーコート膜（最上層の上層絶縁膜）７５が設けられている。第２の上層再配線７０の接続パッド部に対応する部分におけるオーバーコート膜７５には開口部７６が設けられている。開口部７６内およびその上方には半田ボール７７が第２の上層再配線７０の接続パッド部に接続されて設けられている。放熱層７３の中央部に対応する部分におけるオーバーコート膜７５には開口部７８が設けられている。したがって、放熱層７３の中央部はこの開口部７８を介して外部に露出されている。   On the upper surface of the upper insulating film 68 including the second upper rewiring 70 and the heat dissipation layer 73, an overcoat film (uppermost upper insulating film) 75 made of a solder resist or the like is provided. An opening 76 is provided in the overcoat film 75 in a portion corresponding to the connection pad portion of the second upper layer rewiring 70. Solder balls 77 are provided in and above the opening 76 so as to be connected to the connection pad portion of the second upper layer rewiring 70. An opening 78 is provided in the overcoat film 75 in a portion corresponding to the central portion of the heat dissipation layer 73. Therefore, the central portion of the heat dissipation layer 73 is exposed to the outside through the opening 78.

（その他の実施形態）
上記各実施形態において、ベース板１は、１枚の部材としているが、このベース板５は、絶縁膜および配線が交互に積層された多層印刷回路板としてもよい。ただし、このベース板５に放熱層を形成する場合は、最下層の絶縁層の下面に放熱層を形成し、少なくとも、その一部が外部に露出するようにすることが望ましい。また、ベース板５の下面に放熱層を形成する場合、放熱層を露出してベース板の下面をオーバーコート膜で被覆するようにしてもよい。 (Other embodiments)
In each of the above embodiments, the base plate 1 is a single member. However, the base plate 5 may be a multilayer printed circuit board in which insulating films and wirings are alternately laminated. However, when a heat dissipation layer is formed on the base plate 5, it is desirable to form a heat dissipation layer on the lower surface of the lowermost insulating layer so that at least a part thereof is exposed to the outside. Further, when a heat dissipation layer is formed on the lower surface of the base plate 5, the heat dissipation layer may be exposed and the lower surface of the base plate may be covered with an overcoat film.

この発明の第１実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as a first embodiment of the present invention. 図１に示す半導体装置の製造方法の一例において、当初用意したものの断面図。Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く工程の断面図。Sectional drawing of the process following FIG. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図９に続く工程の断面図。Sectional drawing of the process following FIG. 図１０に続く工程の断面図。Sectional drawing of the process following FIG. 図１１に続く工程の断面図。Sectional drawing of the process following FIG. 図１２に続く工程の断面図。Sectional drawing of the process following FIG. 図１３に続く工程の断面図。Sectional drawing of the process following FIG. 図１４に続く工程の断面図。FIG. 15 is a sectional view of a step following FIG. 14. この発明の第２実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 2nd Embodiment of this invention. この発明の第３実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 3rd Embodiment of this invention.

符号の説明Explanation of symbols

１ ベース板
２ 半導体構成体
３ 接着層
４ シリコン基板
５ 接続パッド
１１ 再配線
１３ 放熱用再配線
１４ 柱状電極
１５ 放熱用柱状電極
１６ 封止膜
１７ 絶縁層
１８ 絶縁層
２０ 上層再配線
２３ 放熱層
２５ オーバーコート膜
２７ 半田ボール
２８ 開口部 DESCRIPTION OF SYMBOLS 1 Base board 2 Semiconductor structure 3 Adhesion layer 4 Silicon substrate 5 Connection pad 11 Rewiring 13 Heat radiation rewiring 14 Columnar electrode 15 Heat radiation columnar electrode 16 Sealing film 17 Insulating layer 18 Insulating layer 20 Upper layer rewiring 23 Heat radiation layer 25 Overcoat film 27 Solder ball 28 Opening

Claims (7)

ベース板と、前記ベース板上に設けられ、且つ、半導体基板、該半導体基板上に設けられた複数の接続パッド、前記複数の接続パッドを覆う絶縁膜、該絶縁膜上に形成された下地金属層、該下地金属層上に形成された再配線、該再配線上に形成された複数の入出力用柱状電極および放熱用柱状電極、前記複数の入出力用柱状電極および放熱用柱状電極の周囲の前記保護膜上に設けられた封止膜を有する半導体構成体と、前記半導体構成体上およびその周囲における前記ベース板上に設けられた絶縁層と、前記半導体構成体上における前記絶縁層上に前記半導体構成体の前記複数の入出力用柱状電極に接続されて設けられ、且つ、接続パッド部を有する少なくとも１層の上層再配線と、前記半導体構成体上における前記絶縁層上に前記半導体構成体の複数の放熱用柱状電極に接続されて設けられた放熱層と、前記半導体構成体上における前記絶縁層上に設けられ前記放熱層の一部を露出する開口部を有するオーバーコート膜とを備えていることを特徴とすることを特徴とする半導体装置。 A base plate, a semiconductor substrate provided on the base plate, a plurality of connection pads provided on the semiconductor substrate, an insulating film covering the plurality of connection pads, and a base metal formed on the insulating film Layer, rewiring formed on the base metal layer, a plurality of input / output columnar electrodes and heat dissipation columnar electrodes formed on the rewiring, and the periphery of the plurality of input / output columnar electrodes and heat dissipation columnar electrodes A semiconductor structure having a sealing film provided on the protective film, an insulating layer provided on the base plate on and around the semiconductor structure, and on the insulating layer on the semiconductor structure Connected to the plurality of input / output columnar electrodes of the semiconductor structure, and having at least one upper layer redistribution having a connection pad portion, and the semiconductor on the insulating layer on the semiconductor structure Structure Body and a plurality of connected to the heat radiating columnar electrode provided with the heat dissipation layer, and an overcoat layer having an opening exposing a portion of the provided on the insulating layer and the heat dissipation layer in the semiconductor structure on A semiconductor device comprising the semiconductor device. 請求項１に記載の発明において、前記放熱層は前記上層再配線と同一の材料にて形成されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the heat dissipation layer is formed of the same material as that of the upper layer rewiring. 請求項１に記載の発明において、前記半導体構成体上における前記絶縁層と前記オーバーコート膜との間に上層絶縁膜が設けられていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein an upper insulating film is provided between the insulating layer and the overcoat film on the semiconductor structure. 請求項３に記載の発明において、前記放熱層と前記絶縁層との間に中継放熱層が設けられていることを特徴とする半導体装置。   The semiconductor device according to claim 3, wherein a relay heat dissipation layer is provided between the heat dissipation layer and the insulating layer. 請求項４に記載の発明において、前記上層再配線と前記入出力用柱状電極との間に別の上層再配線が設けられていることを特徴とする半導体装置。   5. The semiconductor device according to claim 4, wherein another upper layer rewiring is provided between the upper layer rewiring and the input / output columnar electrode. 請求項５に記載の発明において、前記放熱層は前記上層再配線と同一の材料にて形成されていることを特徴とする半導体装置。   6. The semiconductor device according to claim 5, wherein the heat dissipation layer is made of the same material as that of the upper layer rewiring. 請求項６に記載の発明において、前記上層再配線の接続パッド部上に半田ボールが設けられていることを特徴とする半導体装置。
7. The semiconductor device according to claim 6, wherein a solder ball is provided on a connection pad portion of the upper layer rewiring.
JP2007012146A 2007-01-23 2007-01-23 Semiconductor device Expired - Fee Related JP4316624B2 (en)

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