JP2009010320A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2009010320A
JP2009010320A JP2008030060A JP2008030060A JP2009010320A JP 2009010320 A JP2009010320 A JP 2009010320A JP 2008030060 A JP2008030060 A JP 2008030060A JP 2008030060 A JP2008030060 A JP 2008030060A JP 2009010320 A JP2009010320 A JP 2009010320A
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semiconductor
insulating layer
semiconductor structure
semiconductor device
substrate
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Ichiro Kono
一郎 河野
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability of bonding between a base board and a semiconductor substrate of semiconductor component in a semiconductor device having a semiconductor component called CSP on the base board. <P>SOLUTION: A lower surface of a silicon board 3 of a semiconductor component 2 is adhered directly to an upper surface of a base board 1 consisting of a silicon substrate. In this case, the bonding reliability between the base board 1 and the silicon substrate 3 of the semiconductor component 2 can be improved in a temperature cycle test because of the same thermal expansion coefficient of the base board 1 and the silicon substrate 3 of the semiconductor component 3. Since an insulating layer 21 provided on an upper surface of the base board 1 around the semiconductor component 2 has a second insulating layer 23 made of a thermoplastic resin, the insulating layer 21 can be relatively easily peeled off by heating when any kind of trouble happens after an insulating layer 21 is formed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

この発明は半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

従来の半導体装置には、ＣＳＰ(chip size package)と呼ばれる半導体構成体のシリコン基板を該半導体構成体よりもサイズの大きいベース板上に直接固着したものがある（例えば、特許文献１参照）。この場合、半導体構成体の周囲におけるベース板上には絶縁層が設けられている。半導体構成体および絶縁層上には上層絶縁膜が設けられている。上層絶縁膜上には上層配線が設けられている。上層配線の接続パッド部上には半田ボールが設けられている。   Some conventional semiconductor devices have a silicon substrate of a semiconductor structure called CSP (chip size package) directly fixed on a base plate having a size larger than that of the semiconductor structure (see, for example, Patent Document 1). In this case, an insulating layer is provided on the base plate around the semiconductor structure. An upper insulating film is provided on the semiconductor structure and the insulating layer. An upper wiring is provided on the upper insulating film. Solder balls are provided on the connection pad portions of the upper layer wiring.

特開２００５−２１６９３６号公報JP 2005-216936 A

上記従来の半導体装置の製造方法では、まず、プリプレグ材からなるベース板形成用シートを用意する。この場合、ベース板形成用シートを構成するプリプレグ材中のエポキシ系樹脂等からなる熱硬化性樹脂は半硬化状態となっている。そして、ベース板形成用シートの上面に半導体構成体のシリコン基板の下面を仮圧着（仮固着）する。   In the conventional method for manufacturing a semiconductor device, first, a base plate forming sheet made of a prepreg material is prepared. In this case, the thermosetting resin made of an epoxy resin or the like in the prepreg material constituting the base plate forming sheet is in a semi-cured state. Then, the lower surface of the silicon substrate of the semiconductor structure is temporarily bonded (temporarily fixed) to the upper surface of the base plate forming sheet.

次に、半導体構成体の周囲におけるベース板の上面に、スクリーン印刷法等により液状のエポキシ系樹脂等からなる熱硬化性樹脂を塗布することにより、絶縁層形成用層を形成する。次に、半導体構成体および絶縁層形成用層の上面にビルドアップ材からなる上層絶縁膜形成用シートを配置する。この場合、上層絶縁膜形成用シートを構成するビルドアップ材中のエポキシ系樹脂等からなる熱硬化性樹脂は半硬化状態となっている。   Next, an insulating layer forming layer is formed by applying a thermosetting resin made of a liquid epoxy resin or the like to the upper surface of the base plate around the semiconductor structure by a screen printing method or the like. Next, an upper insulating film forming sheet made of a build-up material is disposed on the upper surfaces of the semiconductor structure and the insulating layer forming layer. In this case, the thermosetting resin made of an epoxy resin or the like in the build-up material constituting the upper insulating film forming sheet is in a semi-cured state.

次に、一対の加熱加圧板を用いて上下からベース板形成用シート、絶縁層形成用層および上層絶縁膜形成用シートを熱硬化性樹脂の硬化温度以上の温度で加熱加圧する。すると、ベース板形成用シート中の熱硬化性樹脂が硬化することにより、ベース板が形成され、且つ、ベース板の上面に半導体構成体のシリコン基板の下面が直接固着される。また、半導体構成体の周囲におけるベース板の上面に絶縁層が形成され、半導体構成体および絶縁層の上面に上層絶縁膜が形成される。以下の工程は省略する。   Next, the base plate forming sheet, the insulating layer forming layer, and the upper insulating film forming sheet are heated and pressed from above and below using a pair of heating and pressing plates at a temperature equal to or higher than the curing temperature of the thermosetting resin. Then, the base plate is formed by curing the thermosetting resin in the base plate forming sheet, and the lower surface of the silicon substrate of the semiconductor structure is directly fixed to the upper surface of the base plate. An insulating layer is formed on the upper surface of the base plate around the semiconductor structure, and an upper insulating film is formed on the upper surfaces of the semiconductor structure and the insulating layer. The following steps are omitted.

しかしながら、上記従来の半導体装置では、半導体構成体のシリコン基板とベース板を構成するプリプレグ材との熱膨張係数（シリコン基板で３×１０-5／℃、ガラス布基材エボキシ樹脂基板で３．０×１０-6／℃）が約１桁異なるため、温度サイクル試験を行なうと、ベース板と半導体構成体のシリコン基板との界面の負荷が大きくなり、当該界面における接合の信頼性が低下するという問題があった。 However, in the above-described conventional semiconductor device, the coefficient of thermal expansion between the silicon substrate of the semiconductor structure and the prepreg material forming the base plate (3 × 10 −5 / ° C. for the silicon substrate, 3. 0 × 10 −6 / ° C.) differs by about an order of magnitude, so when a temperature cycle test is performed, the load on the interface between the base plate and the silicon substrate of the semiconductor structure increases, and the reliability of bonding at the interface decreases. There was a problem.

そこで、この発明は、ベース板と半導体構成体の半導体基板との接合の信頼性を向上することができる半導体装置およびその製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can improve the reliability of bonding between a base plate and a semiconductor substrate of a semiconductor structure, and a manufacturing method thereof.

請求項１に記載の発明に係る半導体装置は、半導体基板からなるベース板と、前記ベース板の上面に直接固着され、前記ベース板を構成する半導体基板と同一の材料からなる半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する半導体構成体と、前記半導体構成体の周囲における前記ベース板の上面に設けられた絶縁層と、前記半導体構成体および前記絶縁層上に設けられた上層絶縁膜と、前記上層絶縁膜上に前記半導体構成体の外部接続用電極に接続されて設けられた上層配線とを具備することを特徴とするものである。
請求項２に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記半導体構成体の半導体基板は半導体基板からなる前記ベース板の上面に原子間接合により接合されていることを特徴とするものである。
請求項３に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記ベース板および前記半導体構成体の半導体基板はシリコン基板であることを特徴とするものである。
請求項４に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記絶縁層は、熱硬化性樹脂からなる方形枠状の第１の絶縁層と、前記第１の絶縁層の内面、下面および上面に設けられた熱可塑性樹脂からなる第２の絶縁層とからなることを特徴とするものである。
請求項５に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記第１の絶縁層は熱硬化性ポリイミド系樹脂からなり、前記第２の絶縁層は熱可塑性ポリイミド系樹脂からなることを特徴とするものである。
請求項６に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記半導体構成体は、前記外部接続用電極としての柱状電極を有するものであることを特徴とするものである。
請求項７に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記上層配線の接続パッド部上に柱状電極が設けられていることを特徴とするものである。
請求項８に記載の発明に係る半導体装置は、請求項７に記載の発明において、前記柱状電極の周囲に封止膜が設けられていることを特徴とするものである。
請求項９に記載の発明に係る半導体装置は、請求項８に記載の発明において、前記柱状電極上に半田ボールが設けられていることを特徴とするものである。
請求項１０に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記上層配線の接続パッドを除く部分を覆うオーバーコート膜を有することを特徴とするものである。
請求項１１に記載の発明に係る半導体装置は、請求項１０に記載の発明において、前記上層配線の接続パッド上に半田ボールが設けられていることを特徴とするものである。
請求項１２に記載の発明に係る半導体装置の製造方法は、半導体ウエハの上面に、各々が前記半導体ウエハと同一の材料からなる半導体基板および該半導体基板上に設けられた封止膜および複数の外部接続用電極を有する複数の半導体構成体の前記半導体基板の下面を室温の真空中で直接固着する工程と、前記半導体構成体の周囲における前記半導体ウエハの上面に絶縁層を形成する工程と、前記半導体構成体および前記絶縁層上に上層絶縁膜を形成する工程と、前記上層絶縁膜上に上層配線を前記半導体構成体の外部接続用電極に接続させて形成する工程と、前記半導体構成体間における前記半導体ウエハ、前記絶縁層および前記上層絶縁膜を切断して半導体装置を複数個得る工程と、を有することを特徴とするものである。
請求項１３に記載の発明に係る半導体装置の製造方法は、半導体ウエハを準備する工程と、それぞれ、封止膜および複数の外部接続用電極を有する複数の半導体構成体形成体が、前記半導体ウエハと同一の材料からなる一枚の半導体基板上に離間して形成された半導体構成体集合体を準備する工程と、前記半導体構成体集合体の前記半導体基板の下面を前記半導体ウエハの上面に原子間接合により固着する工程と、各前記半導体構成体形成体間の前記半導体基板を除去し、封止膜および複数の外部接続用電極を有する複数の半導体構成体を得る工程と、前記半導体構成体の周囲における前記半導体ウエハの上面に絶縁層を形成する工程と、前記半導体構成体および前記絶縁層上に上層絶縁膜を形成する工程と、前記上層絶縁膜上に上層配線を前記半導体構成体の外部接続用電極に接続させて形成する工程と、前記半導体構成体間における前記半導体ウエハ、前記絶縁層および前記上層絶縁膜を切断して半導体装置を複数個得る工程と、を有することを特徴とするものである。
請求項１４に記載の発明に係る半導体装置の製造方法は、請求項１３に記載の発明において、半導体構成体集合体は、前記半導体構成体形成体の離間部に封止膜を有することを特徴とするものである。
請求項１５に記載の発明に係る半導体装置の製造方法は、請求項１４に記載の発明において、前記半導体構成体形成体の離間部の前記封止膜を、前記半導体構成体集合体の前記半導体基板の下面を前記半導体ウエハの上面に固着した後、除去する工程を有することを特徴とするものである。
請求項１６に記載の発明に係る半導体装置の製造方法は、請求項１３に記載の発明において、前記半導体構成体集合体の前記半導体基板の下面を前記半導体ウエハの上面に固着する前における半導体構成体集合体は、離間部に封止膜を有していないことを特徴とするものである。
請求項１７に記載の発明に係る半導体装置の製造方法は、請求項１３に記載の発明において、前記半導体ウエハと、前記半導体構成体集合体の前記半導体基板とは、サイズが同一であることを特徴とするものである。
請求項１８に記載の発明に係る半導体装置の製造方法は、請求項１２または１３に記載の発明において、前記半導体ウエハおよび前記半導体構成体の半導体基板はシリコン基板であることを特徴とするものである。
請求項１９に記載の発明に係る半導体装置の製造方法は、請求項１８に記載の発明において、前記半導体ウエハの上面に前記半導体構成体のシリコン基板の下面を直接固着する工程は、室温の真空中において、前記半導体ウエハの上面および前記半導体構成体のシリコン基板の下面を、不活性ガスイオンビームまたは不活性ガス高速原子ビームを照射することにより、スパッタエッチングし、次いで、前記半導体ウエハの上面に前記半導体構成体のシリコン基板の下面を重ね合わせて接合する工程であることを特徴とするものである。
請求項２０に記載の発明に係る半導体装置の製造方法は、請求項１２または１３に記載の発明において、前記絶縁層を形成する工程は、前記半導体構成体の周囲における前記ベース板の上面に、硬化状態の熱硬化性樹脂からなる格子状の第１の絶縁層および前記第１の絶縁層の下面および上面に設けられた熱可塑性樹脂からなる第２の絶縁層形成用層からなる格子状の絶縁層形成用シートを配置し、加熱加圧板を用いて加熱加圧することにより、前記半導体構成体の周囲における前記ベース板の上面に、格子状の第１の絶縁層の表面に熱可塑性樹脂からなる第２の絶縁層が形成された構造の絶縁層を形成する工程であることを特徴とするものである。
請求項２１に記載の発明に係る半導体装置の製造方法は、請求項２０に記載の発明において、前記第１の絶縁層形成用層は熱硬化性ポリイミド系樹脂からなり、前記第２の絶縁層は熱可塑性ポリイミド系樹脂からなることを特徴とするものである。 According to a first aspect of the present invention, there is provided a semiconductor device comprising: a base plate made of a semiconductor substrate; a semiconductor substrate made of the same material as the semiconductor substrate that is directly fixed to the upper surface of the base plate and constitutes the base plate; A semiconductor structure having a plurality of external connection electrodes provided on a substrate, an insulating layer provided on an upper surface of the base plate around the semiconductor structure, and provided on the semiconductor structure and the insulating layer And an upper wiring line provided on the upper insulating film so as to be connected to the external connection electrode of the semiconductor structure.
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the semiconductor substrate of the semiconductor structure is bonded to the upper surface of the base plate made of a semiconductor substrate by interatomic bonding. It is a feature.
A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, wherein the base plate and the semiconductor substrate of the semiconductor structure are silicon substrates.
A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the first aspect, wherein the insulating layer is a rectangular frame-shaped first insulating layer made of a thermosetting resin, and the first insulating layer. And a second insulating layer made of a thermoplastic resin provided on the inner surface, the lower surface, and the upper surface.
A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to the first aspect, wherein the first insulating layer is made of a thermosetting polyimide resin, and the second insulating layer is a thermoplastic polyimide resin. It is characterized by comprising.
A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to the first aspect, wherein the semiconductor structure has a columnar electrode as the external connection electrode. .
A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to the first aspect, wherein a columnar electrode is provided on a connection pad portion of the upper wiring.
The semiconductor device according to an eighth aspect of the present invention is the semiconductor device according to the seventh aspect, wherein a sealing film is provided around the columnar electrode.
A semiconductor device according to a ninth aspect of the present invention is the semiconductor device according to the eighth aspect, wherein a solder ball is provided on the columnar electrode.
A semiconductor device according to a tenth aspect of the present invention is the semiconductor device according to the first aspect, further comprising an overcoat film that covers a portion of the upper wiring except for the connection pads.
A semiconductor device according to an eleventh aspect of the present invention is the semiconductor device according to the tenth aspect, wherein solder balls are provided on the connection pads of the upper wiring.
According to a twelfth aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a semiconductor substrate made of the same material as the semiconductor wafer; a sealing film provided on the semiconductor substrate; Directly fixing the lower surface of the semiconductor substrate of a plurality of semiconductor structures having external connection electrodes in a vacuum at room temperature; forming an insulating layer on the upper surface of the semiconductor wafer around the semiconductor structure; Forming an upper insulating film on the semiconductor structure and the insulating layer; forming an upper wiring on the upper insulating film by connecting to an external connection electrode of the semiconductor structure; and the semiconductor structure And a step of cutting the semiconductor wafer, the insulating layer and the upper insulating film between them to obtain a plurality of semiconductor devices.
According to a thirteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a step of preparing a semiconductor wafer; and a plurality of semiconductor structure forming bodies each having a sealing film and a plurality of external connection electrodes. And a step of preparing a semiconductor structure assembly formed on a single semiconductor substrate made of the same material as that separated from each other, and the lower surface of the semiconductor substrate of the semiconductor structure assembly is attached to the upper surface of the semiconductor wafer. A step of fixing by inter-junction, a step of removing the semiconductor substrate between the semiconductor structure forming bodies to obtain a plurality of semiconductor structures having a sealing film and a plurality of external connection electrodes, and the semiconductor structure Forming an insulating layer on the upper surface of the semiconductor wafer around the substrate, forming an upper insulating film on the semiconductor structure and the insulating layer, and forming an upper wiring on the upper insulating film A step of forming the semiconductor structure by connecting to an external connection electrode; and a step of cutting the semiconductor wafer, the insulating layer, and the upper insulating film between the semiconductor structures to obtain a plurality of semiconductor devices. It is characterized by having.
According to a fourteenth aspect of the present invention, in the semiconductor device manufacturing method according to the thirteenth aspect of the present invention, the semiconductor structure aggregate includes a sealing film at a separation portion of the semiconductor structure forming body. It is what.
According to a fifteenth aspect of the present invention, in the semiconductor device manufacturing method according to the fifteenth aspect of the present invention, the sealing film in the separation portion of the semiconductor structure forming body is used as the semiconductor of the semiconductor structure aggregate. The method includes a step of removing after fixing the lower surface of the substrate to the upper surface of the semiconductor wafer.
According to a sixteenth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the thirteenth aspect of the present invention, wherein the semiconductor structure before the lower surface of the semiconductor substrate of the semiconductor structure assembly is fixed to the upper surface of the semiconductor wafer. The body assembly is characterized in that it does not have a sealing film in the separation portion.
According to a seventeenth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the thirteenth aspect of the present invention, wherein the semiconductor wafer and the semiconductor substrate of the semiconductor assembly aggregate are the same size. It is a feature.
The method of manufacturing a semiconductor device according to claim 18 is characterized in that, in the invention according to claim 12 or 13, the semiconductor wafer and the semiconductor substrate of the semiconductor structure are silicon substrates. is there.
According to a nineteenth aspect of the present invention, in the semiconductor device manufacturing method according to the eighteenth aspect, the step of directly fixing the lower surface of the silicon substrate of the semiconductor structure to the upper surface of the semiconductor wafer is performed at room temperature. The upper surface of the semiconductor wafer and the lower surface of the silicon substrate of the semiconductor structure are sputter etched by irradiating with an inert gas ion beam or an inert gas fast atom beam, and then on the upper surface of the semiconductor wafer. It is a step of overlapping and bonding the lower surface of the silicon substrate of the semiconductor structure.
According to a twentieth aspect of the present invention, in the semiconductor device manufacturing method according to the twelfth or thirteenth aspect of the present invention, the step of forming the insulating layer is performed on the upper surface of the base plate around the semiconductor structure. A lattice-shaped first insulating layer made of a cured thermosetting resin and a second insulating layer forming layer made of a thermoplastic resin provided on the lower surface and the upper surface of the first insulating layer. An insulating layer forming sheet is placed and heated and pressed using a heating and pressing plate, so that the top surface of the base plate around the semiconductor structure is made of thermoplastic resin on the surface of the grid-like first insulating layer. This is a step of forming an insulating layer having a structure in which the second insulating layer is formed.
According to a twenty-first aspect of the present invention, in the method for manufacturing a semiconductor device according to the twenty-second aspect, the first insulating layer forming layer is made of a thermosetting polyimide resin, and the second insulating layer. Is made of a thermoplastic polyimide resin.

請求項１および請求項１２に記載の発明によれば、半導体基板からなるベース板の上面に、ベース板を構成する半導体基板と同一の材料からなる半導体構成体の半導体基板の下面を直接固着しているので、ベース板と半導体構成体の半導体基板との熱膨張係数が同一であり、温度サイクル試験を行なっても、ベース板と半導体構成体の半導体基板との接合の信頼性を向上することができる。   According to the first and twelfth aspects of the present invention, the lower surface of the semiconductor substrate made of the same material as that of the semiconductor substrate constituting the base plate is directly fixed to the upper surface of the base plate made of the semiconductor substrate. Therefore, the coefficient of thermal expansion of the base plate and the semiconductor substrate of the semiconductor structure is the same, and the reliability of bonding between the base plate and the semiconductor substrate of the semiconductor structure is improved even if the temperature cycle test is performed. Can do.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示す。この半導体装置は平面方形状のシリコン基板（半導体基板）からなるベース板１を備えている。ベース板１の上面には、ベース板１のサイズよりもある程度小さいサイズの平面方形状の半導体構成体２の下面が直接固着されている。 (First embodiment)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. This semiconductor device includes a base plate 1 made of a planar rectangular silicon substrate (semiconductor substrate). On the upper surface of the base plate 1, the lower surface of the planar rectangular semiconductor structure 2 having a size somewhat smaller than the size of the base plate 1 is directly fixed.

半導体構成体２は、一般的にはＣＳＰと呼ばれるものであり、シリコン基板（半導体基板）３を備えている。シリコン基板３の下面はベース板１の上面に直接固着されている。シリコン基板３の上面には所定の機能の集積回路（図示せず）が設けられ、上面周辺部にはアルミニウム系金属等からなる複数の接続パッド４が集積回路に接続されて設けられている。   The semiconductor structure 2 is generally called a CSP and includes a silicon substrate (semiconductor substrate) 3. The lower surface of the silicon substrate 3 is directly fixed to the upper surface of the base plate 1. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 3, and a plurality of connection pads 4 made of aluminum-based metal or the like are provided on the periphery of the upper surface so as to be connected to the integrated circuit.

接続パッド４の中央部を除くシリコン基板３の上面には酸化シリコン等からなる絶縁膜５が設けられ、接続パッド４の中央部は絶縁膜５に設けられた開口部６を介して露出されている。絶縁膜５の上面にはポリイミド系樹脂等からなる保護膜７が設けられている。絶縁膜５の開口部６に対応する部分における保護膜７には開口部８が設けられている。   An insulating film 5 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 3 excluding the central portion of the connection pad 4, and the central portion of the connection pad 4 is exposed through an opening 6 provided in the insulating film 5. Yes. A protective film 7 made of polyimide resin or the like is provided on the upper surface of the insulating film 5. An opening 8 is provided in the protective film 7 at a portion corresponding to the opening 6 of the insulating film 5.

保護膜７の上面には配線９が設けられている。配線９は、保護膜７の上面に設けられた銅等からなる下地金属層１０と、下地金属層１０の上面に設けられた銅からなる上部金属層１１との２層構造となっている。配線９の一端部は、絶縁膜５および保護膜７の開口部６、８を介して接続パッド４に接続されている。   A wiring 9 is provided on the upper surface of the protective film 7. The wiring 9 has a two-layer structure of a base metal layer 10 made of copper or the like provided on the upper surface of the protective film 7 and an upper metal layer 11 made of copper provided on the upper surface of the base metal layer 10. One end of the wiring 9 is connected to the connection pad 4 through the openings 6 and 8 of the insulating film 5 and the protective film 7.

配線９の接続パッド部上面には銅からなる柱状電極（外部接続用電極）１２が設けられている。配線９を含む保護膜７の上面にはエポキシ系樹脂等からなる封止膜１３がその上面が柱状電極１２の上面と面一となるように設けられている。   A columnar electrode (external connection electrode) 12 made of copper is provided on the upper surface of the connection pad portion of the wiring 9. A sealing film 13 made of an epoxy resin or the like is provided on the upper surface of the protective film 7 including the wiring 9 so that the upper surface is flush with the upper surface of the columnar electrode 12.

半導体構成体２の周囲におけるベース板１の上面には方形枠状の絶縁層２１が設けられている。絶縁層２１は、方形枠状の第１の絶縁層２２の内面、下面および上面に第２の絶縁層２３が設けられた構造となっている。この場合、第１の絶縁層２２は熱硬化性ポリイミド系樹脂からなっている。第２の絶縁層２３は熱可塑性ポリイミド系樹脂からなっている。   A rectangular frame-shaped insulating layer 21 is provided on the upper surface of the base plate 1 around the semiconductor structure 2. The insulating layer 21 has a structure in which the second insulating layer 23 is provided on the inner surface, the lower surface, and the upper surface of the rectangular frame-shaped first insulating layer 22. In this case, the first insulating layer 22 is made of a thermosetting polyimide resin. The second insulating layer 23 is made of a thermoplastic polyimide resin.

半導体構成体２および絶縁層２１の上面にはポリイミド系樹脂やエポキシ系樹脂等からなる上層絶縁膜２４が設けられている。半導体構成体２の柱状電極１２の上面中央部に対応する部分における上層絶縁膜２４には開口部２５が設けられている。   An upper insulating film 24 made of polyimide resin, epoxy resin, or the like is provided on the upper surfaces of the semiconductor structure 2 and the insulating layer 21. An opening 25 is provided in the upper insulating film 24 at a portion corresponding to the central portion of the upper surface of the columnar electrode 12 of the semiconductor structure 2.

上層絶縁膜２４の上面には上層配線２６が設けられている。上層配線２６は、上層絶縁膜２４の上面に設けられた銅等からなる下地金属層２７と、下地金属層２７の上面に設けられた銅からなる上部金属層２８との２層構造となっている。上層配線２６の一端部は、上層絶縁膜２４の開口部２５を介して半導体構成体２の柱状電極１２の上面に接続されている。   An upper wiring 26 is provided on the upper surface of the upper insulating film 24. The upper wiring 26 has a two-layer structure of a base metal layer 27 made of copper or the like provided on the upper surface of the upper insulating film 24 and an upper metal layer 28 made of copper provided on the upper surface of the base metal layer 27. Yes. One end of the upper layer wiring 26 is connected to the upper surface of the columnar electrode 12 of the semiconductor structure 2 through the opening 25 of the upper layer insulating film 24.

上層配線２６の接続パッド部上面には銅からなる柱状電極２９が設けられている。上層配線２６を含む上層絶縁膜２４の上面にはエポキシ系樹脂等からなる封止膜３０がその上面が柱状電極２９の上面と面一となるように設けられている。柱状電極２９の上面には半田ボール３１が設けられている。   A columnar electrode 29 made of copper is provided on the upper surface of the connection pad portion of the upper layer wiring 26. A sealing film 30 made of epoxy resin or the like is provided on the upper surface of the upper insulating film 24 including the upper wiring 26 so that the upper surface is flush with the upper surface of the columnar electrode 29. A solder ball 31 is provided on the upper surface of the columnar electrode 29.

（製造方法の第１の例）
次に、この半導体装置の製造方法の第１の例について説明する。まず、図２に示すように、ウエハ状態の単なるシリコン基板からなるベース板（以下、半導体ウエハ４１という）を準備する。なお、図２において、符号４２で示す領域は、個片化するための切断ラインに対応する領域である。 (First example of manufacturing method)
Next, a first example of this semiconductor device manufacturing method will be described. First, as shown in FIG. 2, a base plate made of a simple silicon substrate in a wafer state (hereinafter referred to as a semiconductor wafer 41) is prepared. In FIG. 2, an area indicated by reference numeral 42 is an area corresponding to a cutting line for singulation.

また、半導体構成体２を準備する。この半導体構成体２は、ウエハ状態のシリコン基板３上の各半導体構成体形成領域に集積回路（図示せず）、接続パッド４、絶縁膜５、保護膜７、下地金属層１０および上部金属層１１からなる２層構造の配線９、柱状電極１２および封止膜１３を形成した後に、ダイシングにより個片化することにより得られる。   Moreover, the semiconductor structure 2 is prepared. The semiconductor structure 2 includes an integrated circuit (not shown), a connection pad 4, an insulating film 5, a protective film 7, a base metal layer 10 and an upper metal layer in each semiconductor structure forming region on the silicon substrate 3 in a wafer state. 11 is formed by dicing into individual pieces after forming the wiring layer 9, the columnar electrode 12 and the sealing film 13 having a two-layer structure made of 11.

次に、半導体ウエハ４１の上面の複数の半導体構成体配置領域に複数の半導体構成体２のシリコン基板３の下面を常温接合法と呼ばれる接合方法により直接固着する（特開平１０−９２７０２号公報参照）。すなわち、図示していないが、まず、室温の真空中（真空チャンバー内）において、半導体ウエハ４１の上面および半導体構成体２のシリコン基板３の下面を、不活性ガスイオンビームまたは不活性ガス高速原子ビームを照射することにより、スパッタエッチングする。すると、半導体ウエハ４１の上面および半導体構成体２のシリコン基板３の下面に存在する吸着ガスや自然酸化膜等が剥離される。   Next, the lower surface of the silicon substrate 3 of the plurality of semiconductor structures 2 is directly fixed to a plurality of semiconductor structure arrangement regions on the upper surface of the semiconductor wafer 41 by a bonding method called a room temperature bonding method (see Japanese Patent Laid-Open No. 10-92702). ). That is, although not shown, first, in a vacuum at room temperature (in a vacuum chamber), the upper surface of the semiconductor wafer 41 and the lower surface of the silicon substrate 3 of the semiconductor structure 2 are made to pass through an inert gas ion beam or an inert gas fast atom. Sputter etching is performed by irradiating a beam. As a result, the adsorbed gas, natural oxide film, and the like existing on the upper surface of the semiconductor wafer 41 and the lower surface of the silicon substrate 3 of the semiconductor structure 2 are peeled off.

次に、そのまま室温の真空中（真空チャンバー内）において、半導体ウエハ４１の上面に半導体構成体２のシリコン基板３の下面を重ね合わせると、半導体ウエハ４１の上面および半導体構成体２のシリコン基板３の下面が極めて平滑であることにより、無加熱、無加圧で、半導体ウエハ４１の上面に半導体構成体２のシリコン基板３の下面が原子間接合により強固に接合される。   Next, when the lower surface of the silicon substrate 3 of the semiconductor structure 2 is superimposed on the upper surface of the semiconductor wafer 41 in a vacuum at room temperature (in a vacuum chamber), the upper surface of the semiconductor wafer 41 and the silicon substrate 3 of the semiconductor structure 2 are overlapped. Since the lower surface of the semiconductor substrate 2 is extremely smooth, the lower surface of the silicon substrate 3 of the semiconductor structure 2 is firmly bonded to the upper surface of the semiconductor wafer 41 by interatomic bonding without heating and without pressure.

次に、図３に示すように、半導体構成体の周囲における半導体ウエハ４１の上面に格子状の絶縁層形成用シート２１ａをピン等で位置決めしながら配置する。格子状の絶縁層形成用シート２１ａは、硬化状態の熱硬化性ポリイミド系樹脂シートからなる第１の絶縁層２２の下面および上面に熱可塑性ポリイミド系樹脂からなる第２の絶縁層形成用層２３ａ、２３ｂが設けられ、パンチング等により、複数の方形状の開口部４３が形成されたものからなっている。   Next, as shown in FIG. 3, a lattice-shaped insulating layer forming sheet 21 a is arranged on the upper surface of the semiconductor wafer 41 around the semiconductor structure while being positioned with pins or the like. The lattice-shaped insulating layer forming sheet 21a includes a second insulating layer forming layer 23a made of a thermoplastic polyimide resin on the lower surface and the upper surface of the first insulating layer 22 made of a cured thermosetting polyimide resin sheet. 23b, and a plurality of rectangular openings 43 are formed by punching or the like.

この場合、絶縁層形成用シート２１ａの開口部４３のサイズは半導体構成体２のサイズよりもやや大きくなっている。このため、絶縁層形成用シート２１ａと半導体構成体２との間には隙間４４が形成されている。第１の絶縁層２２および第２の絶縁層形成用層２３ａ、２３ｂの厚さおよび隙間４４の寸法は、後述の如く、加熱加圧されたときに、第１の絶縁層２２および第２の絶縁層形成用層２３ａ、２３ｂによって隙間４４を十分に埋めることができる程度となっている。   In this case, the size of the opening 43 of the insulating layer forming sheet 21 a is slightly larger than the size of the semiconductor structure 2. For this reason, a gap 44 is formed between the insulating layer forming sheet 21 a and the semiconductor structure 2. The thickness of the first insulating layer 22 and the second insulating layer forming layers 23a and 23b and the dimension of the gap 44 are set so that the first insulating layer 22 and the second insulating layer 22 are heated and pressurized as will be described later. The gap 44 is sufficiently filled with the insulating layer forming layers 23a and 23b.

一例として、絶縁層形成用シート２１ａの厚さは半導体構成体２の厚さよりも５μｍ以上厚くなっている。隙間４４の寸法は３０μｍ以上となっている。第１の絶縁層２２と第２の絶縁層形成用層２３ａ、２３ｂとの厚さの比は、第１の絶縁層２２の厚さが９０〜５０％、第２の絶縁層形成用層２３ａ、２３ｂの合計厚さが１０〜５０％となっている。   As an example, the thickness of the insulating layer forming sheet 21 a is 5 μm or more thicker than the thickness of the semiconductor structure 2. The dimension of the gap 44 is 30 μm or more. The thickness ratio between the first insulating layer 22 and the second insulating layer forming layers 23a and 23b is such that the thickness of the first insulating layer 22 is 90 to 50%, and the second insulating layer forming layer 23a. , 23b has a total thickness of 10 to 50%.

次に、図４に示すように、一対の加熱加圧板４５、４６を用いて上下から絶縁層形成用シート２１ａを真空中で加熱加圧する。この場合、上側の加熱加圧板４５の下面側および下側の加熱加圧板４６の上面側には離型フィルム４７、４８が配置されている。加熱加圧条件は、一例として、圧力を９．８×１０-4Ｐａ以上とし、開始時点の温度を４０℃とし、それから３〜５分で２００℃に上昇させ、この温度を１０分保持し、それから３〜１０分で室温に戻す。 Next, as shown in FIG. 4, the insulating layer forming sheet 21 a is heated and pressurized in vacuum from above and below using a pair of heating and pressing plates 45 and 46. In this case, release films 47 and 48 are disposed on the lower surface side of the upper heating and pressing plate 45 and the upper surface side of the lower heating and pressing plate 46. As an example of the heating and pressurizing conditions, the pressure is set to 9.8 × 10 −4 Pa or more, the temperature at the start point is set to 40 ° C., the temperature is increased to 200 ° C. in 3 to 5 minutes, and this temperature is maintained for 10 minutes. Then return to room temperature in 3-10 minutes.

この加熱加圧により、絶縁層形成用シート２１ａ中の熱可塑性ポリイミド系樹脂からなる第２の絶縁層形成用層２３ａ、２３ｂが軟化して、図３に示す隙間４４に充填され、その後の冷却により固化して、半導体構成体２の周囲における半導体ウエハ４１の上面には方形枠状の絶縁層２１が形成される。この状態では、絶縁層２１は、格子状の第１の絶縁層２２の表面に第２の絶縁層２３が設けられた構造となっている。なお、第１の絶縁層２２は、予め硬化された熱硬化性ポリイミド系樹脂によって形成されているため、加熱加圧されてもほとんど変形しない。   By this heat and pressure, the second insulating layer forming layers 23a and 23b made of thermoplastic polyimide resin in the insulating layer forming sheet 21a are softened and filled in the gap 44 shown in FIG. Thus, the rectangular frame-like insulating layer 21 is formed on the upper surface of the semiconductor wafer 41 around the semiconductor structure 2. In this state, the insulating layer 21 has a structure in which the second insulating layer 23 is provided on the surface of the lattice-like first insulating layer 22. In addition, since the 1st insulating layer 22 is formed with the thermosetting polyimide type resin hardened | cured previously, even if it heat-presses, it hardly deform | transforms.

ここで、何らかのトラブルが発生し、絶縁層２１を剥離する必要が生じたとする。このような場合には、絶縁層２１が格子状の第１の絶縁層２２の表面に第２の絶縁層２３が設けられた構造となっているので、２００℃以上に加熱すると、第２の絶縁層２３を構成する熱可塑性ポリイミド系樹脂が軟化し、専用の治具等を用いて絶縁層２１を比較的容易に剥離することができる。したがって、その後に残った半導体ウエハ４１および複数の半導体構成体２をそのまま再利用することができる。   Here, it is assumed that some trouble occurs and the insulating layer 21 needs to be peeled off. In such a case, since the insulating layer 21 has a structure in which the second insulating layer 23 is provided on the surface of the lattice-like first insulating layer 22, the second insulating layer 21 is heated to 200 ° C. or higher. The thermoplastic polyimide resin constituting the insulating layer 23 is softened, and the insulating layer 21 can be peeled relatively easily using a dedicated jig or the like. Therefore, the remaining semiconductor wafer 41 and the plurality of semiconductor structures 2 can be reused as they are.

さて、半導体構成体２の周囲における半導体ウエハ４１の上面に方形枠状の絶縁層２１を形成したら、次に、図５に示すように、半導体構成体２および絶縁層２１の上面に、スクリーン印刷法やスピンコート法等により、ポリイミド系樹脂やエポキシ系樹脂等からなる上層絶縁膜２４を形成する。次に、半導体構成体２の柱状電極１２の上面中央部に対応する部分における上層絶縁膜２４に、フォトリソグラフィ法あるいはレーザビームを照射するレーザ加工により、開口部２５を形成する。   Now, after forming the rectangular frame-shaped insulating layer 21 on the upper surface of the semiconductor wafer 41 around the semiconductor structure 2, next, screen printing is performed on the upper surfaces of the semiconductor structure 2 and the insulating layer 21, as shown in FIG. The upper insulating film 24 made of polyimide resin, epoxy resin, or the like is formed by a method, a spin coating method, or the like. Next, an opening 25 is formed in the upper insulating film 24 at a portion corresponding to the center of the upper surface of the columnar electrode 12 of the semiconductor structure 2 by photolithography or laser processing that irradiates a laser beam.

次に、図６に示すように、上層絶縁膜２４の開口部２５を介して露出された半導体構成体２の柱状電極１２の上面を含む上層絶縁膜２４の上面全体に下地金属層２７を形成する。この場合、下地金属層２７は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。   Next, as shown in FIG. 6, a base metal layer 27 is formed on the entire upper surface of the upper insulating film 24 including the upper surface of the columnar electrode 12 of the semiconductor structure 2 exposed through the opening 25 of the upper insulating film 24. To do. In this case, the base metal layer 27 may be only a copper layer formed by electroless plating, may be only a copper layer formed by sputtering, or a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

次に、下地金属層２７の上面にメッキレジスト膜４９をパターン形成する。この場合、上部金属層２８形成領域に対応する部分におけるメッキレジスト膜４９には開口部５０が形成されている。次に、下地金属層２７をメッキ電流路とした銅の電解メッキを行なうことにより、メッキレジスト膜４９の開口部５０内の下地金属層２７の上面に上部金属層２８を形成する。次に、メッキレジスト膜４９を剥離する。   Next, a plating resist film 49 is formed on the upper surface of the base metal layer 27 by patterning. In this case, an opening 50 is formed in the plating resist film 49 in a portion corresponding to the upper metal layer 28 formation region. Next, the upper metal layer 28 is formed on the upper surface of the base metal layer 27 in the opening 50 of the plating resist film 49 by performing electrolytic plating of copper using the base metal layer 27 as a plating current path. Next, the plating resist film 49 is peeled off.

次に、図７に示すように、上部金属層２８を含む下地金属層２７の上面にメッキレジスト膜５１をパターン形成する。この場合、上部金属層２８の接続パッド部つまり柱状電極２９形成領域に対応する部分におけるレジスト膜５１には開口部５２が形成されている。次に、下地金属層２７をメッキ電流路とした銅の電解メッキを行うことにより、メッキレジスト膜５１の開口部５２内の上部金属層２８の接続パッド部上面に柱状電極２９を形成する。   Next, as shown in FIG. 7, a plating resist film 51 is patterned on the upper surface of the base metal layer 27 including the upper metal layer 28. In this case, an opening 52 is formed in the resist film 51 in the connection pad portion of the upper metal layer 28, that is, the portion corresponding to the columnar electrode 29 formation region. Next, by performing electrolytic plating of copper using the base metal layer 27 as a plating current path, the columnar electrode 29 is formed on the upper surface of the connection pad portion of the upper metal layer 28 in the opening 52 of the plating resist film 51.

次に、メッキレジスト膜５１を剥離し、次いで、上部金属層２８をマスクとして下地金属層２７の不要な部分をエッチングして剥離すると、図８に示すように、上部金属層２８下にのみ下地金属層２７が残存される。この状態では、下地金属層２７およびその上面に形成された上部金属層２８により、上層配線２６が形成されている。   Next, the plating resist film 51 is peeled off, and then unnecessary portions of the base metal layer 27 are etched and peeled using the upper metal layer 28 as a mask to remove the base only under the upper metal layer 28 as shown in FIG. The metal layer 27 remains. In this state, the upper wiring 26 is formed by the base metal layer 27 and the upper metal layer 28 formed on the upper surface thereof.

次に、図９に示すように、上層配線２６および柱状電極２９を含む上層絶縁膜２４の上面に、スクリーン印刷法やスピンコート法等により、エポキシ系樹脂等からなる封止膜３０をその厚さが柱状電極２９の高さよりもやや厚くなるように形成する。したがって、この状態では、柱状電極２９の上面は封止膜３０によって覆われている。   Next, as shown in FIG. 9, a sealing film 30 made of an epoxy resin or the like is formed on the upper surface of the upper insulating film 24 including the upper wiring 26 and the columnar electrode 29 by screen printing, spin coating, or the like. Is formed to be slightly thicker than the height of the columnar electrode 29. Therefore, in this state, the upper surface of the columnar electrode 29 is covered with the sealing film 30.

次に、封止膜３０の上面側を適宜に研削して除去することにより、図１０に示すように、柱状電極２９の上面を露出させるとともに、この露出された柱状電極２９の上面を含む封止膜３０の上面を平坦化する。次に、図１１に示すように、柱状電極２９の上面に半田ボール３１を形成する。次に、図１２に示すように、切断ライン４２に沿って、封止膜３０、上層絶縁膜２４、絶縁層２１および半導体ウエハ４１を切断すると、図１に示す半導体装置が複数個得られる。   Next, by appropriately grinding and removing the upper surface side of the sealing film 30, as shown in FIG. 10, the upper surface of the columnar electrode 29 is exposed, and the sealing including the exposed upper surface of the columnar electrode 29 is performed. The upper surface of the stop film 30 is flattened. Next, as shown in FIG. 11, solder balls 31 are formed on the upper surfaces of the columnar electrodes 29. Next, as shown in FIG. 12, when the sealing film 30, the upper insulating film 24, the insulating layer 21, and the semiconductor wafer 41 are cut along the cutting line 42, a plurality of semiconductor devices shown in FIG. 1 are obtained.

このようにして得られた半導体装置では、シリコン基板からなるベース板１の上面に、ベース板１を構成するシリコン基板と同一の材料からなる半導体構成体２のシリコン基板３の下面を直接固着しているので、ベース板１と半導体構成体２のシリコン基板３との熱膨張係数が同一であり、温度サイクル試験を行なっても、ベース板１と半導体構成体２のシリコン基板３との接合の信頼性を向上することができる。   In the semiconductor device thus obtained, the lower surface of the silicon substrate 3 of the semiconductor structure 2 made of the same material as the silicon substrate constituting the base plate 1 is directly fixed to the upper surface of the base plate 1 made of the silicon substrate. Therefore, the thermal expansion coefficients of the base plate 1 and the silicon substrate 3 of the semiconductor structure 2 are the same, and even if the temperature cycle test is performed, the bonding between the base plate 1 and the silicon substrate 3 of the semiconductor structure 2 Reliability can be improved.

（製造方法の第２の例）
次に、図１に示す半導体装置の製造方法の第２の例について説明する。まず、図２に示すような当初の工程において、図１３に示すように、半導体ウエハ４１のほかに、半導体構成体集合体６１を準備する。この場合も、図１３において、符号４２で示す領域は、個片化するための切断ラインに対応する領域である。 (Second example of manufacturing method)
Next, a second example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. First, in the initial step as shown in FIG. 2, a semiconductor assembly aggregate 61 is prepared in addition to the semiconductor wafer 41 as shown in FIG. 13. Also in this case, in FIG. 13, an area indicated by reference numeral 42 is an area corresponding to a cutting line for singulation.

半導体構成体集合体６１は、ウエハ状態のシリコン基板３上の切断ライン４２で囲まれた各半導体装置形成領域の中央部に集積回路（図示せず）、接続パッド４、絶縁膜５、保護膜７、下地金属層１０および上部金属層１１からなる２層構造の配線９、柱状電極１２および封止膜１３を形成したものである。この場合、半導体構成体集合体６１のシリコン基板３サイズは半導体ウエハ４１のサイズと同じである。   The semiconductor structure assembly 61 is formed of an integrated circuit (not shown), a connection pad 4, an insulating film 5, and a protective film at the center of each semiconductor device formation region surrounded by the cutting line 42 on the silicon substrate 3 in the wafer state. 7, a wiring 9 having a two-layer structure including a base metal layer 10 and an upper metal layer 11, a columnar electrode 12, and a sealing film 13 are formed. In this case, the size of the silicon substrate 3 of the semiconductor assembly aggregate 61 is the same as the size of the semiconductor wafer 41.

ここで、この半導体構成体集合体６１について、図２に示す半導体構成体２を複数個得るためのダイシング前のウエハ状態のもの（以下、比較品という）と比較して説明する。比較品では、ウエハ状態のシリコン基板３上の各半導体構成体形成領域に接続パッド４等を形成し、各半導体構成体形成領域間においてダイシングすることにより、図２に示す半導体構成体２が複数個得られる。   Here, the semiconductor structure assembly 61 will be described in comparison with a wafer state before dicing (hereinafter referred to as a comparative product) for obtaining a plurality of semiconductor structures 2 shown in FIG. In the comparative product, the connection pads 4 and the like are formed in each semiconductor structure forming region on the silicon substrate 3 in a wafer state, and a plurality of semiconductor structures 2 shown in FIG. 2 are obtained by dicing between each semiconductor structure forming region. Can be obtained.

これに対し、半導体構成体集合体６１では、ウエハ状態のシリコン基板３上の切断ライン４２で囲まれた各半導体装置形成領域の中央部（つまり、実質的な半導体構成体形成領域）に接続パッド４等を形成しているため、図１３において点線で示すように、ウエハ状態のシリコン基板３上の切断ライン４２で囲まれた各半導体装置形成領域の中央部に対応する部分が封止膜１３および複数の柱状電極１２を有する半導体構成体形成体６２となっている。この場合、各半導体構成体形成体６２間の離間部におけるウエハ状態のシリコン基板３上には、下から順に、絶縁膜５、保護膜７および封止膜１３が形成されている。   On the other hand, in the semiconductor structure assembly 61, a connection pad is provided at the center of each semiconductor device formation region (that is, a substantial semiconductor structure formation region) surrounded by the cutting line 42 on the silicon substrate 3 in the wafer state. 4 and so on, as shown by a dotted line in FIG. 13, a portion corresponding to the central portion of each semiconductor device formation region surrounded by the cutting line 42 on the silicon substrate 3 in the wafer state is the sealing film 13. In addition, a semiconductor structure forming body 62 having a plurality of columnar electrodes 12 is formed. In this case, the insulating film 5, the protective film 7, and the sealing film 13 are formed in order from the bottom on the silicon substrate 3 in the wafer state in the separation portion between the semiconductor structure forming bodies 62.

さて、半導体ウエハ４１および半導体構成体集合体６１を準備したら、次に、上記常温接合法と呼ばれる接合方法により、室温の真空中（真空チャンバー内）において、無加熱、無加圧で、半導体ウエハ４１の上面に半導体構成体集合体６１のシリコン基板３の下面を原子間接合により強固に接合する。   Now that the semiconductor wafer 41 and the semiconductor assembly aggregate 61 are prepared, the semiconductor wafer is then heated in a vacuum at room temperature (within a vacuum chamber) by a bonding method called the room temperature bonding method without heating or pressure. The lower surface of the silicon substrate 3 of the semiconductor structure assembly 61 is firmly bonded to the upper surface of 41 by interatomic bonding.

次に、図１４に示すように、半導体構成体集合体６１の半導体構成体形成体６２の上面にレジスト膜６３をパターン形成する。次に、レジスト膜６３をマスクとしてＡｒスパッタエッチングを行ない、レジスト膜６３下の半導体構成体形成体６２以外の領域における封止膜１３、保護膜７、絶縁膜５およびシリコン基板３を除去すると、図１５に示すようになる。   Next, as shown in FIG. 14, a resist film 63 is patterned on the upper surface of the semiconductor structure forming body 62 of the semiconductor structure assembly 61. Next, Ar sputter etching is performed using the resist film 63 as a mask to remove the sealing film 13, the protective film 7, the insulating film 5, and the silicon substrate 3 in a region other than the semiconductor structure forming body 62 below the resist film 63. As shown in FIG.

すなわち、レジスト膜６３下の半導体構成体形成体６２以外の領域における封止膜１３、保護膜７、絶縁膜５およびシリコン基板３が除去されることにより、レジスト膜６３下に半導体構成体形成体６２およびシリコン基板３が残存され、この残存された半導体構成体形成体６２およびシリコン基板３により半導体構成体２が構成されている。次に、レジスト膜６３を剥離すると、図２に示す状態と同じとなる。以下、上記製造方法の第１の例の場合と同様の工程を経ると、図１に示す半導体装置が複数個得られる。   That is, by removing the sealing film 13, the protective film 7, the insulating film 5, and the silicon substrate 3 in regions other than the semiconductor structure forming body 62 under the resist film 63, the semiconductor structure forming body is formed under the resist film 63. 62 and the silicon substrate 3 remain, and the remaining semiconductor structure forming body 62 and the silicon substrate 3 constitute the semiconductor structure 2. Next, when the resist film 63 is peeled, the state shown in FIG. 2 is obtained. Thereafter, through the same steps as in the first example of the manufacturing method, a plurality of semiconductor devices shown in FIG. 1 are obtained.

以上のように、この半導体装置の製造方法では、半導体ウエハ４１と同一サイズのシリコン基板３を有する半導体構成体集合体６１を用いることで、複数の半導体構成体形成体６２を同時に半導体ウエハ４１上に常温接合することできるので、半導体構成体２を１個ずつ常温接合する場合と比較して、より短い時間で接合することができる。   As described above, in this method of manufacturing a semiconductor device, by using the semiconductor structure assembly 61 having the silicon substrate 3 having the same size as the semiconductor wafer 41, a plurality of semiconductor structure forming bodies 62 can be simultaneously mounted on the semiconductor wafer 41. Therefore, the semiconductor components 2 can be bonded in a shorter time compared to the case where the semiconductor structures 2 are bonded one by one at room temperature.

ところで、図１４に示すように、ウエハ状態のシリコン基板からなる半導体ウエハ４１の上面に半導体構成体集合体６１のウエハ状態のシリコン基板３を接合しているので、レジスト膜６３下の半導体構成体形成体６２以外の領域におけるシリコン基板３をＡｒスパッタエッチングするとき、エッチング選択性がないため、半導体ウエハ４１の上面側もエッチングされるおそれがある。   By the way, as shown in FIG. 14, since the silicon substrate 3 in the wafer state of the semiconductor structure aggregate 61 is bonded to the upper surface of the semiconductor wafer 41 made of the silicon substrate in the wafer state, the semiconductor structure under the resist film 63 is bonded. When the silicon substrate 3 in the region other than the formation body 62 is subjected to Ar sputter etching, the upper surface side of the semiconductor wafer 41 may be etched due to lack of etching selectivity.

そこで、この場合のエッチング時間をシリコン基板３の厚さに応じて制御すればよい。ただし、ジャストエッチングは困難であるので、シリコン基板３が若干残存されるようにしてもよく、あるいは半導体ウエハ４１の上面側が若干エッチングされるようにしてもよく、いずれにしても別に支障はない。なお、Ａｒスパッタエッチングの代わりに、ＣＯ2レーザの照射によるレーザ加工を行なうようにしてもよいが、この場合、レーザ照射時間をシリコン基板３の厚さに応じて制御すればよい。 Therefore, the etching time in this case may be controlled according to the thickness of the silicon substrate 3. However, since the just etching is difficult, the silicon substrate 3 may be left slightly, or the upper surface side of the semiconductor wafer 41 may be slightly etched. Note that laser processing by CO 2 laser irradiation may be performed instead of Ar sputter etching. In this case, the laser irradiation time may be controlled in accordance with the thickness of the silicon substrate 3.

（製造方法の第３の例）
次に、図１に示すの半導体装置の製造方法の第３の例に説明する。まず、図１３に示すような当初の工程において、図１６に示すように、半導体ウエハ４１のほかに、半導体構成体集合体７１を準備する。この場合も、図１６において、符号４２で示す領域は、個片化するための切断ラインに対応する領域である。 (Third example of manufacturing method)
Next, a third example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. First, in an initial step as shown in FIG. 13, a semiconductor assembly aggregate 71 is prepared in addition to the semiconductor wafer 41 as shown in FIG. Also in this case, in FIG. 16, an area indicated by reference numeral 42 is an area corresponding to a cutting line for singulation.

半導体構成体集合体７１において、図１３に示す半導体構成体集合体６１と異なる点は、半導体構成体形成体６２間の離間部における封止膜１３、保護膜７および絶縁膜５が予めエッチングにより除去されている点である。この場合も、半導体構成体形成体６２は、封止膜１３および複数の柱状電極１２を有する構造となっている。   The semiconductor structure aggregate 71 differs from the semiconductor structure aggregate 61 shown in FIG. 13 in that the sealing film 13, the protective film 7, and the insulating film 5 in the space between the semiconductor structure forming bodies 62 are etched in advance. It is a point that has been removed. Also in this case, the semiconductor structure forming body 62 has a structure having the sealing film 13 and the plurality of columnar electrodes 12.

さて、半導体ウエハ４１および半導体構成体集合体７１を準備したら、次に、上記常温接合法と呼ばれる接合方法により、室温の真空中（真空チャンバー内）において、無加熱、無加圧で、半導体ウエハ４１の上面に半導体構成体集合体６１のシリコン基板３の下面を原子間接合により強固に接合する。   Now that the semiconductor wafer 41 and the semiconductor assembly aggregate 71 are prepared, the semiconductor wafer is then heated in a vacuum at room temperature (within a vacuum chamber) by a bonding method called the room temperature bonding method, without heating and without pressure. The lower surface of the silicon substrate 3 of the semiconductor structure assembly 61 is firmly bonded to the upper surface of 41 by interatomic bonding.

次に、図１７に示すように、半導体構成体集合体７１の半導体構成体形成体６２の上面にレジスト膜７２をパターン形成する。次に、レジスト膜７２をマスクとしてＡｒスパッタエッチングを行ない、レジスト膜７２下の半導体構成体形成体６２以外の領域におけるシリコン基板３を除去すると、図１８に示すようになる。   Next, as shown in FIG. 17, a resist film 72 is patterned on the upper surface of the semiconductor structure forming body 62 of the semiconductor structure assembly 71. Next, Ar sputter etching is performed using the resist film 72 as a mask to remove the silicon substrate 3 in a region other than the semiconductor structure forming body 62 under the resist film 72, as shown in FIG.

すなわち、レジスト膜７２下の半導体構成体形成体６２以外の領域におけるシリコン基板３が除去されることにより、レジスト膜７２下の半導体構成体形成体６２下にシリコン基板３が残存され、この残存されたシリコン基板３およびその上の半導体構成体形成体６２により半導体構成体２が構成されている。次に、レジスト膜７２を剥離すると、図２に示す状態と同じとなる。以下、上記製造方法の第１の例の場合と同様の工程を経ると、図１に示す半導体装置が複数個得られる。   That is, by removing the silicon substrate 3 in the region other than the semiconductor structure forming body 62 under the resist film 72, the silicon substrate 3 remains under the semiconductor structure forming body 62 under the resist film 72. The semiconductor structure 2 is constituted by the silicon substrate 3 and the semiconductor structure forming body 62 thereon. Next, when the resist film 72 is peeled, the state shown in FIG. 2 is obtained. Thereafter, through the same steps as in the first example of the manufacturing method, a plurality of semiconductor devices shown in FIG. 1 are obtained.

以上のように、この半導体装置の製造方法でも、半導体ウエハ４１と同一サイズのシリコン基板３を有する半導体構成体集合体６１を用いることで、複数の半導体構成体形成体６２を同時に半導体ウエハ４１上に常温接合することできるので、半導体構成体２を１個ずつ常温接合する場合と比較して、より短い時間で接合することができる。   As described above, also in this method of manufacturing a semiconductor device, by using the semiconductor structure assembly 61 having the silicon substrate 3 having the same size as the semiconductor wafer 41, a plurality of semiconductor structure forming bodies 62 can be simultaneously mounted on the semiconductor wafer 41. Therefore, the semiconductor components 2 can be bonded in a shorter time compared to the case where the semiconductor structures 2 are bonded one by one at room temperature.

ところで、この場合も、シリコン基板３と半導体ウエハ４１との間にエッチング選択性がないため、エッチング時間をシリコン基板３の厚さに応じて制御するようにすればよい。また、ジャストエッチングは困難であるので、シリコン基板３が若干残存されるようにしてもよく、あるいは半導体ウエハ４１の上面側が若干エッチングされるようにしてもよく、いずれにしても別に支障はない。   In this case as well, since there is no etching selectivity between the silicon substrate 3 and the semiconductor wafer 41, the etching time may be controlled in accordance with the thickness of the silicon substrate 3. Since just etching is difficult, the silicon substrate 3 may be left slightly, or the upper surface side of the semiconductor wafer 41 may be slightly etched. In any case, there is no problem.

なお、Ａｒスパッタエッチングの代わりに、ＣＯ2レーザの照射によるレーザ加工を行なうようにしてもよいが、この場合、レーザ照射時間をシリコン基板３の厚さに応じて制御すればよい。また、不要なシリコン基板３を除去するため、ＣＦ4ガスをプラズマ化してＦラジカルでシリコン基板３をドライエッチングしてもよい。その場合も、エッチング時間をシリコン基板３の厚さに応じて制御するようにすればよい。 Note that laser processing by CO 2 laser irradiation may be performed instead of Ar sputter etching. In this case, the laser irradiation time may be controlled in accordance with the thickness of the silicon substrate 3. In order to remove the unnecessary silicon substrate 3, the silicon substrate 3 may be dry-etched with F radicals by converting CF 4 gas into plasma. In this case, the etching time may be controlled according to the thickness of the silicon substrate 3.

（第２実施形態）
図１９はこの発明の第２実施形態としての半導体装置の断面図を示す。この半導体装置において、図１に示す半導体装置と異なる点は、柱状電極２９および封止膜３０を有せず、上層配線２６を含む上層絶縁膜２４の上面にソルダーレジスト等からなるオーバーコート膜３２が設けられ、上層配線２６の接続パッド部に対応する部分におけるオーバーコート膜３２に設けられた開口部３３内およびその上方に半田ボール３１が上層配線２６の接続パッド部に接続されて設けられた点である。 (Second Embodiment)
FIG. 19 is a sectional view of a semiconductor device as a second embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that the columnar electrode 29 and the sealing film 30 are not provided, and an overcoat film 32 made of a solder resist or the like is formed on the upper surface of the upper insulating film 24 including the upper wiring 26. The solder balls 31 are connected to the connection pad portions of the upper wiring 26 in and above the openings 33 provided in the overcoat film 32 in the portions corresponding to the connection pad portions of the upper wiring 26. Is a point.

（その他の実施形態）
上記各実施形態に示された半導体装置２は一例に過ぎず、本発明の半導体構成体は、半導体基板上の集積回路を外部に接続するための外部接続用電極を有する如何なる半導体構成体でも適用可能である。 (Other embodiments)
The semiconductor device 2 shown in each of the above embodiments is merely an example, and the semiconductor structure of the present invention can be applied to any semiconductor structure having an external connection electrode for connecting an integrated circuit on a semiconductor substrate to the outside. Is possible.

この発明の第１実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as a first embodiment of the present invention. 図１に示す半導体装置の製造方法の第１の例において、当初の工程の断面図。Sectional drawing of the first process in the 1st example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く工程の断面図。Sectional drawing of the process following FIG. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図９に続く工程の断面図。Sectional drawing of the process following FIG. 図１０に続く工程の断面図。Sectional drawing of the process following FIG. 図１１に続く工程の断面図。Sectional drawing of the process following FIG. 図１に示す半導体装置の製造方法の第２の例において、当初の工程の断面図。Sectional drawing of the original process in the 2nd example of the manufacturing method of the semiconductor device shown in FIG. 図１３に続く工程の断面図。Sectional drawing of the process following FIG. 図１４に続く工程の断面図。FIG. 15 is a sectional view of a step following FIG. 14. 図１５に続く工程の断面図。FIG. 16 is a cross-sectional view of the process following FIG. 15. 図１に示す半導体装置の製造方法の第３の例において、当初の工程の断面図。Sectional drawing of the original process in the 3rd example of the manufacturing method of the semiconductor device shown in FIG. 図１７に続く工程の断面図。FIG. 18 is a cross-sectional view of the process following FIG. 17. この発明の第２実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 2nd Embodiment of this invention.

符号の説明Explanation of symbols

１ ベース板
２ 半導体構成体
３ シリコン基板
４ 接続パッド
５ 絶縁膜
７ 保護膜
９ 配線
１２ 柱状電極
１３ 封止膜
２１ 絶縁層
２２ 第１の絶縁層
２３ 第２の絶縁層
２４ 上層絶縁膜
２６ 上層配線
２９ 柱状電極
３０ 封止膜
３１ 半田ボール
３２ オーバーコート膜
４１ 半導体ウエハ
２１ａ 絶縁層形成用シート
２３ａ、２３ｂ 第２の絶縁層形成用層
６１、７１ 半導体構成体集合体
６２ 半導体構成体形成体 DESCRIPTION OF SYMBOLS 1 Base board 2 Semiconductor structure 3 Silicon substrate 4 Connection pad 5 Insulating film 7 Protective film 9 Wiring 12 Columnar electrode 13 Sealing film 21 Insulating layer 22 1st insulating layer 23 2nd insulating layer 24 Upper layer insulating film 26 Upper layer wiring 29 Columnar electrode 30 Sealing film 31 Solder ball 32 Overcoat film 41 Semiconductor wafer 21a Insulating layer forming sheet 23a, 23b Second insulating layer forming layer 61, 71 Semiconductor structure assembly 62 Semiconductor structure forming body

Claims (21)

半導体基板からなるベース板と、前記ベース板の上面に直接固着され、前記ベース板を構成する半導体基板と同一の材料からなる半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する半導体構成体と、前記半導体構成体の周囲における前記ベース板の上面に設けられた絶縁層と、前記半導体構成体および前記絶縁層上に設けられた上層絶縁膜と、前記上層絶縁膜上に前記半導体構成体の外部接続用電極に接続されて設けられた上層配線とを具備することを特徴とする半導体装置。   A base plate made of a semiconductor substrate, a semiconductor substrate made of the same material as the semiconductor substrate constituting the base plate, which is directly fixed to the upper surface of the base plate, and a plurality of external connection electrodes provided on the semiconductor substrate. A semiconductor structure having, an insulating layer provided on an upper surface of the base plate around the semiconductor structure, an upper insulating film provided on the semiconductor structure and the insulating layer, and an upper insulating film A semiconductor device comprising an upper layer wiring connected to an external connection electrode of the semiconductor structure. 請求項１に記載の発明において、前記半導体構成体の半導体基板は半導体基板からなる前記ベース板の上面に原子間接合により接合されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the semiconductor substrate of the semiconductor structure is bonded to the upper surface of the base plate made of the semiconductor substrate by interatomic bonding. 請求項１に記載の発明において、前記ベース板および前記半導体構成体の半導体基板はシリコン基板であることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein a semiconductor substrate of the base plate and the semiconductor structure is a silicon substrate. 請求項１に記載の発明において、前記絶縁層は、熱硬化性樹脂からなる方形枠状の第１の絶縁層と、前記第１の絶縁層の内面、下面および上面に設けられた熱可塑性樹脂からなる第２の絶縁層とからなることを特徴とする半導体装置。   2. The invention according to claim 1, wherein the insulating layer includes a rectangular frame-shaped first insulating layer made of a thermosetting resin, and a thermoplastic resin provided on an inner surface, a lower surface and an upper surface of the first insulating layer. A semiconductor device comprising: a second insulating layer comprising: 請求項４に記載の発明において、前記第１の絶縁層は熱硬化性ポリイミド系樹脂からなり、前記第２の絶縁層は熱可塑性ポリイミド系樹脂からなることを特徴とする半導体装置。   5. The semiconductor device according to claim 4, wherein the first insulating layer is made of a thermosetting polyimide resin, and the second insulating layer is made of a thermoplastic polyimide resin. 請求項１に記載の発明において、前記半導体構成体は、前記外部接続用電極としての柱状電極を有するものであることを特徴とする半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor structure includes a columnar electrode as the external connection electrode. 請求項１に記載の発明において、前記上層配線の接続パッド部上に柱状電極が設けられていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein a columnar electrode is provided on a connection pad portion of the upper wiring. 請求項７に記載の発明において、前記柱状電極の周囲に封止膜が設けられていることを特徴とする半導体装置。   The semiconductor device according to claim 7, wherein a sealing film is provided around the columnar electrode. 請求項８に記載の発明において、前記柱状電極上に半田ボールが設けられていることを特徴とする半導体装置。   9. The semiconductor device according to claim 8, wherein a solder ball is provided on the columnar electrode. 請求項１に記載の発明において、前記上層配線の接続パッドを除く部分を覆うオーバーコート膜を有することを特徴とする半導体装置。   The semiconductor device according to claim 1, further comprising an overcoat film that covers a portion of the upper wiring except for a connection pad. 請求項１０に記載の発明において、前記上層配線の接続パッド上に半田ボールが設けられていることを特徴とする半導体装置。   11. The semiconductor device according to claim 10, wherein solder balls are provided on connection pads of the upper layer wiring. 半導体ウエハの上面に、各々が前記半導体ウエハと同一の材料からなる半導体基板および該半導体基板上に設けられた封止膜および複数の外部接続用電極を有する複数の半導体構成体の前記半導体基板の下面を原子間接合により固着する工程と、
前記半導体構成体の周囲における前記半導体ウエハの上面に絶縁層を形成する工程と、
前記半導体構成体および前記絶縁層上に上層絶縁膜を形成する工程と、
前記上層絶縁膜上に上層配線を前記半導体構成体の外部接続用電極に接続させて形成する工程と、
前記半導体構成体間における前記半導体ウエハ、前記絶縁層および前記上層絶縁膜を切断して半導体装置を複数個得る工程と、
を有することを特徴とする半導体装置の製造方法。 A semiconductor substrate having a plurality of semiconductor structures each including a semiconductor substrate made of the same material as the semiconductor wafer, a sealing film provided on the semiconductor substrate, and a plurality of external connection electrodes on an upper surface of the semiconductor wafer. Fixing the lower surface by interatomic bonding;
Forming an insulating layer on the upper surface of the semiconductor wafer around the semiconductor structure;
Forming an upper insulating film on the semiconductor structure and the insulating layer;
Forming an upper wiring on the upper insulating film by connecting to an external connection electrode of the semiconductor structure;
Cutting the semiconductor wafer, the insulating layer, and the upper insulating film between the semiconductor structures to obtain a plurality of semiconductor devices;
A method for manufacturing a semiconductor device, comprising: 半導体ウエハを準備する工程と、
それぞれ、封止膜および複数の外部接続用電極を有する複数の半導体構成体形成体が、前記半導体ウエハと同一の材料からなる一枚の半導体基板上に離間して形成された半導体構成体集合体を準備する工程と、
前記半導体構成体集合体の前記半導体基板の下面を前記半導体ウエハの上面に原子間接合により固着する工程と、
各前記半導体構成体形成体間の前記半導体基板を除去し、封止膜および複数の外部接続用電極を有する複数の半導体構成体を得る工程と、
前記半導体構成体の周囲における前記半導体ウエハの上面に絶縁層を形成する工程と、
前記半導体構成体および前記絶縁層上に上層絶縁膜を形成する工程と、
前記上層絶縁膜上に上層配線を前記半導体構成体の外部接続用電極に接続させて形成する工程と、
前記半導体構成体間における前記半導体ウエハ、前記絶縁層および前記上層絶縁膜を切断して半導体装置を複数個得る工程と、
を有することを特徴とする半導体装置の製造方法。 A step of preparing a semiconductor wafer;
A plurality of semiconductor structure forming bodies each having a sealing film and a plurality of external connection electrodes are formed on a single semiconductor substrate made of the same material as the semiconductor wafer and separated from each other. The process of preparing
Fixing the lower surface of the semiconductor substrate of the semiconductor structure assembly to the upper surface of the semiconductor wafer by interatomic bonding;
Removing the semiconductor substrate between the semiconductor structure forming bodies to obtain a plurality of semiconductor structures having a sealing film and a plurality of external connection electrodes;
Forming an insulating layer on the upper surface of the semiconductor wafer around the semiconductor structure;
Forming an upper insulating film on the semiconductor structure and the insulating layer;
Forming an upper wiring on the upper insulating film by connecting to an external connection electrode of the semiconductor structure;
Cutting the semiconductor wafer, the insulating layer, and the upper insulating film between the semiconductor structures to obtain a plurality of semiconductor devices;
A method for manufacturing a semiconductor device, comprising: 請求項１３に記載の発明において、半導体構成体集合体は、前記半導体構成体形成体の離間部に封止膜を有することを特徴とする半導体装置の製造方法。   14. The method of manufacturing a semiconductor device according to claim 13, wherein the semiconductor structure aggregate includes a sealing film in a separation portion of the semiconductor structure forming body. 請求項１４に記載の発明において、前記半導体構成体形成体の離間部の前記封止膜を、前記半導体構成体集合体の前記半導体基板の下面を前記半導体ウエハの上面に固着した後、除去する工程を有することを特徴とする半導体装置の製造方法。   15. The invention according to claim 14, wherein the sealing film in the separation portion of the semiconductor structure forming body is removed after the lower surface of the semiconductor substrate of the semiconductor structure assembly is fixed to the upper surface of the semiconductor wafer. A method for manufacturing a semiconductor device, comprising: a step. 請求項１３に記載の発明において、前記半導体構成体集合体の前記半導体基板の下面を前記半導体ウエハの上面に固着する前における半導体構成体集合体は、離間部に封止膜を有していないことを特徴とする半導体装置の製造方法。   14. The semiconductor structure assembly according to claim 13, wherein the semiconductor structure assembly before the lower surface of the semiconductor substrate of the semiconductor structure assembly is fixed to the upper surface of the semiconductor wafer does not have a sealing film at a separation portion. A method of manufacturing a semiconductor device. 請求項１３に記載の発明において、前記半導体ウエハと、前記半導体構成体集合体の前記半導体基板とは、サイズが同一であることを特徴とする半導体装置の製造方法。   14. The method of manufacturing a semiconductor device according to claim 13, wherein the semiconductor wafer and the semiconductor substrate of the semiconductor assembly aggregate have the same size. 請求項１２または１３に記載の発明において、前記半導体ウエハおよび前記半導体構成体の半導体基板はシリコン基板であることを特徴とする半導体装置の製造方法。   14. The method of manufacturing a semiconductor device according to claim 12, wherein the semiconductor wafer and the semiconductor substrate of the semiconductor structure are silicon substrates. 請求項１８に記載の発明において、前記半導体ウエハの上面に前記半導体構成体のシリコン基板の下面を直接固着する工程は、室温の真空中において、前記半導体ウエハの上面および前記半導体構成体のシリコン基板の下面を、不活性ガスイオンビームまたは不活性ガス高速原子ビームを照射することにより、スパッタエッチングし、次いで、前記半導体ウエハの上面に前記半導体構成体のシリコン基板の下面を重ね合わせて接合する工程であることを特徴とする半導体装置の製造方法。   19. The method according to claim 18, wherein the step of directly fixing the lower surface of the silicon substrate of the semiconductor structure to the upper surface of the semiconductor wafer includes the upper surface of the semiconductor wafer and the silicon substrate of the semiconductor structure in a vacuum at room temperature. Sputter etching is performed by irradiating the lower surface of the semiconductor substrate with an inert gas ion beam or an inert gas fast atom beam, and then the lower surface of the silicon substrate of the semiconductor structure is bonded to the upper surface of the semiconductor wafer. A method for manufacturing a semiconductor device, wherein: 請求項１２または１３に記載の発明において、前記絶縁層を形成する工程は、前記半導体構成体の周囲における前記半導体ウエハの上面に、硬化状態の熱硬化性樹脂からなる格子状の第１の絶縁層および前記第１の絶縁層の下面および上面に設けられた熱可塑性樹脂からなる第２の絶縁層形成用層からなる格子状の絶縁層形成用シートを配置し、加熱加圧板を用いて加熱加圧することにより、前記半導体構成体の周囲における前記半導体ウエハの上面に、格子状の第１の絶縁層の表面に熱可塑性樹脂からなる第２の絶縁層が形成された構造の絶縁層を形成する工程であることを特徴とする半導体装置の製造方法。   14. The invention according to claim 12 or 13, wherein the step of forming the insulating layer includes a lattice-shaped first insulation made of a thermosetting resin in a cured state on the upper surface of the semiconductor wafer around the semiconductor structure. And a lattice-shaped insulating layer forming sheet made of a second insulating layer forming layer made of a thermoplastic resin provided on the lower surface and the upper surface of the first insulating layer, and heated using a heating and pressing plate By applying pressure, an insulating layer having a structure in which a second insulating layer made of thermoplastic resin is formed on the surface of the lattice-shaped first insulating layer is formed on the upper surface of the semiconductor wafer around the semiconductor structure. A method for manufacturing a semiconductor device, characterized by comprising: 請求項２０に記載の発明において、前記第１の絶縁層は熱硬化性ポリイミド系樹脂からなり、前記第２の絶縁層形成用層は熱可塑性ポリイミド系樹脂からなることを特徴とする半導体装置の製造方法。   The semiconductor device according to claim 20, wherein the first insulating layer is made of a thermosetting polyimide resin, and the second insulating layer forming layer is made of a thermoplastic polyimide resin. Production method.
JP2008030060A 2007-05-28 2008-02-12 Semiconductor device and method of manufacturing the same Pending JP2009010320A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006270009A (en) * 2005-02-25 2006-10-05 Seiko Epson Corp Method for manufacturing electronic device
JP2007116198A (en) * 2007-01-23 2007-05-10 Casio Comput Co Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006270009A (en) * 2005-02-25 2006-10-05 Seiko Epson Corp Method for manufacturing electronic device
JP2007116198A (en) * 2007-01-23 2007-05-10 Casio Comput Co Ltd Semiconductor device

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