JP2007123941A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

Info

Publication number
JP2007123941A
JP2007123941A JP2007029902A JP2007029902A JP2007123941A JP 2007123941 A JP2007123941 A JP 2007123941A JP 2007029902 A JP2007029902 A JP 2007029902A JP 2007029902 A JP2007029902 A JP 2007029902A JP 2007123941 A JP2007123941 A JP 2007123941A
Authority
JP
Japan
Prior art keywords
insulating film
rewiring
semiconductor device
manufacturing
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007029902A
Other languages
Japanese (ja)
Other versions
JP4577316B2 (en
Inventor
Takeshi Wakabayashi
猛 若林
Shinji Wakizaka
伸治 脇坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP2007029902A priority Critical patent/JP4577316B2/en
Publication of JP2007123941A publication Critical patent/JP2007123941A/en
Application granted granted Critical
Publication of JP4577316B2 publication Critical patent/JP4577316B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To reduce processing step number for forming upper-layer rewiring of a semiconductor device by forming the upper-layer rewiring with a method other than electroplating. <P>SOLUTION: A semiconductor construction body 2 which is called a CSP is bonded on the upper surface center of a base plate 1 via an adhesive layer 3. A rectangular frame-shaped insulating layer 14 composed of a resin is formed on the upper surface of the base plate 1 in such a way that the upper surface of the insulating layer forms almost the same plane as the upper surface of the semiconductor construction body 2. On the upper surface of the semiconductor construction body 2 and of the insulating layer 14, an insulating film 15 composed of a prepreg material is formed with its upper surface flat. The upper-layer rewiring 16 formed by patterning a metal plate is formed on predetermined places of the upper surface of the insulating film 15. In this case, frustum-shaped protruding electrodes 17 formed integrally on the lower surface of the upper-layer rewiring 16 encroach on the insulating film 15 to make them contact respectively to the upper surface centers of pillar-shaped electrodes 12. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device.

従来の半導体装置には、ＣＳＰ（ｃｈｉｐ ｓｉｚｅ ｐａｃｋａｇｅ）と呼ばれるものがある。このＣＳＰは、複数の外部接続用の接続パッドが形成された半導体基板の上面に絶縁膜が設けられ、絶縁膜の各接続パッドに対応する部分に開口部が設けられ、開口部を介して露出された接続パッドの上面から絶縁膜の上面の所定の箇所にかけて再配線が設けられたものである。この場合、開口部を介して露出された接続パッドの上面を含む絶縁膜の上面全体に下地金属層を形成し、下地金属層をメッキ電流路とした銅の電解メッキにより、下地金属層の上面の所定の箇所に再配線を形成し、再配線をマスクとして下地金属層の不要な部分をエッチングして除去して、再配線下にのみ下地金属層を残存させている。   Some conventional semiconductor devices are called CSP (chip size package). In this CSP, an insulating film is provided on the upper surface of a semiconductor substrate on which a plurality of connection pads for external connection are formed, and an opening is provided in a portion corresponding to each connection pad of the insulating film, and is exposed through the opening. Rewiring is provided from the upper surface of the formed connection pad to a predetermined location on the upper surface of the insulating film. In this case, a base metal layer is formed on the entire top surface of the insulating film including the top surface of the connection pad exposed through the opening, and the top surface of the base metal layer is formed by electrolytic plating of copper using the base metal layer as a plating current path. A rewiring is formed at a predetermined position, and unnecessary portions of the base metal layer are removed by etching using the rewiring as a mask to leave the base metal layer only under the rewiring.

ところで、上記従来の半導体装置の製造方法では、絶縁膜の各接続パッドに対応する部分に開口部を形成し、メッキ電流路としての下地金属層をスパッタ法や無電解メッキ法により形成して再配線を電解メッキにより形成する方法であるため、工程数が多く、生産性が低いものであった。   By the way, in the above conventional semiconductor device manufacturing method, an opening is formed in a portion corresponding to each connection pad of the insulating film, and a base metal layer as a plating current path is formed by sputtering or electroless plating. Since the wiring is formed by electrolytic plating, the number of processes is large and the productivity is low.

そこで、この発明は、工程数を低減して生産性を向上することができる半導体装置の製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can improve productivity by reducing the number of steps.

請求項１に記載の発明は、複数の外部接続用電極を有する半導体構成体の上面を絶縁膜で覆う工程と、前記絶縁層上に前記各外部接続用電極に対応する突起電極を有する金属板を配置する工程と、前記金属板の各突起電極を前記絶縁膜に食い込ませて前記各外部接続用電極に接続する工程と、前記金属板をパターニングして再配線を形成する工程とを有することを特徴とするものである。
請求項２に記載の発明は、請求項１に記載の発明において、前記半導体構成体は、接続パッドと、該接続パッドに接続された柱状の外部接続用電極と、該外部接続用電極の周囲に設けられた封止膜とを含むことを特徴とするものである。
請求項３に記載の発明は、請求項２に記載の発明において、前記半導体構成体は、前記接続パッドと前記外部接続用電極とを接続する再配線を含むことを特徴とするものである。
請求項４に記載の発明は、請求項１に記載の発明において、前記絶縁膜はシートであることを特徴とするものである。
請求項５に記載の発明は、請求項４に記載の発明において、前記絶縁膜の上面は平坦であることを特徴とするものである。
請求項６に記載の発明は、請求項１に記載の発明において、前記金属板の突起電極を前記絶縁膜に食い込ませる工程は前記絶縁膜が半硬化の状態で行ない、この後、加熱により、前記絶縁膜を本硬化させるとともに、前記金属板を前記絶縁膜上に固着することを特徴とするものである。
請求項７に記載の発明は、請求項１に記載の発明において、前記金属板よりも厚めの金属板の下面をハーフウェットエッチングすることにより、前記突起電極を前記金属板下に一体的に且つ裁頭円錐形状に形成することを特徴とするものである。
請求項８に記載の発明は、請求項１に記載の発明において、前記突起電極を、前記金属板下に金属ペーストを印刷して裁頭円錐形状に形成することを特徴とするものである。
請求項９に記載の発明は、請求項１に記載の発明において、前記半導体構成体の上面を前記絶縁膜で覆う工程の前に、ベース板上に、各々が半導体基板上に設けられた複数の外部接続用電極を有する複数の半導体構成体を相互に離間させて配置する工程と、前記各半導体構成体の周側面に絶縁層を形成する工程とを有し、この後、前記半導体構成体および前記絶縁層の上面を前記絶縁膜で覆うことを特徴とするものである。
請求項１０に記載の発明は、請求項９に記載の発明において、前記金属板をパターニングして前記再配線を形成する工程の後、前記半導体構成体間における前記絶縁膜および前記絶縁層を切断して少なくとも前記半導体構成体が１つ含まれる半導体装置に分離することを特徴とするものである。
請求項１１に記載の発明は、請求項１０に記載の発明において、前記切断は、前記半導体構成体が複数個含まれるように切断することを特徴とするものである。
請求項１２に記載の発明は、請求項１０に記載の発明において、前記切断工程で前記絶縁膜および前記絶縁層を切断するとともに前記ベース板を切断し、前記半導体装置として前記ベース板を備えたものを得ることを特徴とするものである。
請求項１３に記載の発明は、請求項１に記載の発明において、前記金属板をパターニングして再配線を形成する工程の後、前記絶縁膜および前記再配線上に１層以上の上層の絶縁膜と、前記上層の絶縁膜上に形成され下層の再配線の接続パッド部に接続された上層の再配線を形成する工程を有することを特徴とするものである。
請求項１４に記載の発明は、請求項１３に記載の発明において、前記最上層の再配線の接続パッド部を除く部分を覆う上層の絶縁膜を形成する工程を有することを特徴とするものである。
請求項１５に記載の発明は、請求項１３に記載の発明において、前記上層の再配線の少なくとも一部は突起電極を有し、該突起電極を前記下層の絶縁膜に食い込ませて前記下層の再配線の接続パッド部に接続する工程を有することを特徴とするものである。
請求項１６に記載の発明は、請求項１３に記載の発明において、前記最上層の再配線の接続パッド部上に半田ボールを形成する工程を有することを特徴とするものである。 The invention according to claim 1 is a metal plate having a step of covering an upper surface of a semiconductor structure having a plurality of external connection electrodes with an insulating film, and a protruding electrode corresponding to each of the external connection electrodes on the insulating layer Disposing each protruding electrode of the metal plate into the insulating film and connecting it to the external connection electrode, and patterning the metal plate to form a rewiring. It is characterized by.
According to a second aspect of the present invention, in the first aspect of the invention, the semiconductor structure includes a connection pad, a columnar external connection electrode connected to the connection pad, and a periphery of the external connection electrode. And a sealing film provided on the substrate.
According to a third aspect of the present invention, in the second aspect of the present invention, the semiconductor structure includes a rewiring that connects the connection pad and the external connection electrode.
According to a fourth aspect of the invention, in the first aspect of the invention, the insulating film is a sheet.
According to a fifth aspect of the present invention, in the fourth aspect of the present invention, the upper surface of the insulating film is flat.
The invention according to claim 6 is the invention according to claim 1, wherein the step of causing the protruding electrode of the metal plate to bite into the insulating film is performed in a state where the insulating film is semi-cured, and thereafter, by heating, The insulating film is fully cured, and the metal plate is fixed on the insulating film.
According to a seventh aspect of the invention, in the first aspect of the invention, the lower surface of the metal plate thicker than the metal plate is half-wet etched, so that the protruding electrode is integrated under the metal plate and It is formed in a truncated cone shape.
The invention described in claim 8 is characterized in that, in the invention described in claim 1, the protruding electrode is formed in a truncated cone shape by printing a metal paste under the metal plate.
According to a ninth aspect of the present invention, in the first aspect of the present invention, before the step of covering the upper surface of the semiconductor structure with the insulating film, a plurality of parts each provided on the base plate on the semiconductor substrate are provided. A plurality of semiconductor structures having external connection electrodes, and a step of forming an insulating layer on a peripheral side surface of each semiconductor structure, and thereafter the semiconductor structure And the upper surface of the said insulating layer is covered with the said insulating film, It is characterized by the above-mentioned.
The invention according to claim 10 is the invention according to claim 9, wherein after the step of patterning the metal plate to form the rewiring, the insulating film and the insulating layer between the semiconductor structural bodies are cut. Then, the semiconductor device is separated into at least one semiconductor structure.
According to an eleventh aspect of the present invention, in the invention according to the tenth aspect, the cutting is performed so as to include a plurality of the semiconductor structural bodies.
The invention according to claim 12 is the invention according to claim 10, wherein the insulating film and the insulating layer are cut in the cutting step, the base plate is cut, and the base plate is provided as the semiconductor device. It is characterized by obtaining things.
According to a thirteenth aspect of the present invention, in the first aspect of the invention, after the step of patterning the metal plate to form a rewiring, one or more upper insulating layers are formed on the insulating film and the rewiring. And a step of forming an upper layer rewiring formed on the upper insulating film and connected to the connection pad portion of the lower layer rewiring.
The invention described in claim 14 is characterized in that, in the invention described in claim 13, the method further comprises a step of forming an upper insulating film covering a portion excluding the connection pad portion of the uppermost rewiring. is there.
According to a fifteenth aspect of the invention, in the invention of the thirteenth aspect, at least a part of the rewiring in the upper layer has a protruding electrode, and the protruding electrode bites into the insulating film in the lower layer to It has the process of connecting to the connection pad part of rewiring.
A sixteenth aspect of the present invention is the method according to the thirteenth aspect, further comprising a step of forming a solder ball on the connection pad portion of the uppermost rewiring.

そして、この発明によれば、金属板に形成された突起電極を絶縁膜に食い込ませて外部接続用電極に接続し、この後、金属板をパターニングして再配線を形成しているので、工程数が低減し、生産性を向上することができる。   And according to this invention, since the protruding electrode formed on the metal plate is bitten into the insulating film and connected to the external connection electrode, and thereafter, the metal plate is patterned to form the rewiring. The number can be reduced and productivity can be improved.

図１はこの発明の一実施形態としての半導体装置の断面図を示したものである。この半導体装置は、シリコン、ガラス、セラミックス、樹脂、金属等からなる平面矩形形状のベース板１を備えている。   FIG. 1 shows a cross-sectional view of a semiconductor device as an embodiment of the present invention. This semiconductor device includes a flat rectangular base plate 1 made of silicon, glass, ceramics, resin, metal, or the like.

ベース板１の上面中央部には、ベース板１のサイズよりもある程度小さいサイズの平面矩形形状の半導体構成体２の下面がダイボンド材からなる接着層３を介して接着されている。この場合、半導体構成体２は、後述する再配線、柱状電極、封止膜を有しており、一般的にはＣＳＰと呼ばれるものであり、特に、後述の如く、シリコンウエハ上に再配線、柱状電極、封止膜を形成した後、ダイシングにより個々の半導体構成体２を得る方法を採用しているため、特に、ウエハレベルＣＳＰ（Ｗ−ＣＳＰ）とも言われている。以下に、半導体構成体２の構成について説明する。   The lower surface of a planar rectangular semiconductor structure 2 having a size somewhat smaller than the size of the base plate 1 is bonded to the central portion of the upper surface of the base plate 1 via an adhesive layer 3 made of a die bond material. In this case, the semiconductor structure 2 has a rewiring, a columnar electrode, and a sealing film, which will be described later, and is generally called CSP. In particular, as described later, rewiring on a silicon wafer, Since a method of obtaining individual semiconductor structures 2 by dicing after forming the columnar electrode and the sealing film is adopted, it is particularly called wafer level CSP (W-CSP). Below, the structure of the semiconductor structure 2 is demonstrated.

半導体構成体２はシリコン基板（半導体基板）４を備えている。シリコン基板４は接着層３を介してベース板１に接着されている。シリコン基板４の上面中央部には集積回路（図示せず）が設けられ、上面周辺部にはアルミニウム系金属等からなる複数の接続パッド５が集積回路に接続されて設けられている。接続パッド５の中央部を除くシリコン基板４の上面には酸化シリコン等からなる絶縁膜６が設けられ、接続パッド５の中央部は絶縁膜６に設けられた開口部７を介して露出されている。   The semiconductor structure 2 includes a silicon substrate (semiconductor substrate) 4. The silicon substrate 4 is bonded to the base plate 1 via the adhesive layer 3. An integrated circuit (not shown) is provided at the center of the upper surface of the silicon substrate 4, and a plurality of connection pads 5 made of aluminum-based metal or the like are provided connected to the integrated circuit at the periphery of the upper surface. An insulating film 6 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 4 excluding the central portion of the connection pad 5, and the central portion of the connection pad 5 is exposed through an opening 7 provided in the insulating film 6. Yes.

絶縁膜６の上面にはエポキシ系樹脂やポリイミド系樹脂等からなる保護膜（絶縁膜）８が設けられている。この場合、絶縁膜６の開口部７に対応する部分における保護膜８には開口部９が設けられている。両開口部７、９を介して露出された接続パッド５の上面から保護膜８の上面の所定の箇所にかけて下地金属層１０が設けられている。下地金属層１０の上面全体には銅からなる再配線１１が設けられている。   A protective film (insulating film) 8 made of an epoxy resin, a polyimide resin, or the like is provided on the upper surface of the insulating film 6. In this case, an opening 9 is provided in the protective film 8 at a portion corresponding to the opening 7 of the insulating film 6. A base metal layer 10 is provided from the upper surface of the connection pad 5 exposed through both openings 7 and 9 to a predetermined portion of the upper surface of the protective film 8. A rewiring 11 made of copper is provided on the entire upper surface of the base metal layer 10.

再配線１１の接続パッド部上面には銅からなる柱状電極（外部接続用電極）１２が設けられている。再配線１１を含む保護膜８の上面にはエポキシ系樹脂やポリイミド系樹脂等からなる封止膜（絶縁膜）１３がその上面が柱状電極１２の上面と面一となるように設けられている。このように、Ｗ−ＣＳＰと呼ばれる半導体構成体２は、シリコン基板４、接続パッド５、絶縁膜６を含み、さらに、保護膜８、再配線１１、柱状電極１２、封止膜１３を含んで構成されている。   A columnar electrode (external connection electrode) 12 made of copper is provided on the upper surface of the connection pad portion of the rewiring 11. A sealing film (insulating film) 13 made of an epoxy resin, a polyimide resin, or the like is provided on the upper surface of the protective film 8 including the rewiring 11 so that the upper surface is flush with the upper surface of the columnar electrode 12. . As described above, the semiconductor structure 2 called W-CSP includes the silicon substrate 4, the connection pad 5, and the insulating film 6, and further includes the protective film 8, the rewiring 11, the columnar electrode 12, and the sealing film 13. It is configured.

半導体構成体２の周囲におけるベース板１の上面にはエポキシ系樹脂やポリイミド系樹脂等からなる矩形枠状の絶縁層１４がその上面が半導体構成体２の上面とほぼ面一となるように設けられている。半導体構成体２および絶縁層１４の上面には絶縁膜１５がその上面を平坦とされて設けられている。絶縁膜１５は、例えば、プリプレグ材と言われるもので、ガラス繊維にエポキシ系樹脂を含浸させたものである。   A rectangular frame-like insulating layer 14 made of epoxy resin or polyimide resin is provided on the upper surface of the base plate 1 around the semiconductor structure 2 so that the upper surface is substantially flush with the upper surface of the semiconductor structure 2. It has been. An insulating film 15 is provided on the upper surfaces of the semiconductor structure 2 and the insulating layer 14 with the upper surfaces thereof being flat. The insulating film 15 is a so-called prepreg material, for example, in which glass fiber is impregnated with an epoxy resin.

絶縁膜１５の上面の所定の箇所には、銅からなる金属板をパターニングしてなる上層再配線１６が設けられている。この場合、上層再配線１６の下面において柱状電極１２の上面中央部に対応する部分には裁頭円錐形状の突起電極１７が一体的に形成されている。突起電極１７は絶縁膜１５に食い込まされて柱状電極１２の上面中央部に接続されている。   An upper layer rewiring 16 formed by patterning a metal plate made of copper is provided at a predetermined position on the upper surface of the insulating film 15. In this case, a truncated conical projection electrode 17 is integrally formed on the lower surface of the upper layer rewiring 16 at a portion corresponding to the center of the upper surface of the columnar electrode 12. The protruding electrode 17 is bitten into the insulating film 15 and connected to the center of the upper surface of the columnar electrode 12.

上層再配線１６を含む絶縁膜１５の上面にはソルダーレジスト等からなる上層絶縁膜１８が設けられている。上層再配線１６の接続パッド部に対応する部分における上層絶縁膜１８には開口部１９が設けられている。開口部１９内およびその上方には半田ボール２０が上層再配線１６の接続パッド部に接続されて設けられている。複数の半田ボール２０は、上層絶縁膜１８上にマトリクス状に配置されている。   An upper insulating film 18 made of a solder resist or the like is provided on the upper surface of the insulating film 15 including the upper rewiring 16. An opening 19 is provided in the upper insulating film 18 in a portion corresponding to the connection pad portion of the upper layer rewiring 16. Solder balls 20 are provided in and above the opening 19 so as to be connected to the connection pad portion of the upper layer rewiring 16. The plurality of solder balls 20 are arranged in a matrix on the upper insulating film 18.

ところで、ベース板１のサイズを半導体構成体２のサイズよりもある程度大きくしているのは、シリコン基板４上の接続パッド５の数の増加に応じて、半田ボール２０の配置領域を半導体構成体２のサイズよりもある程度大きくし、これにより、上層再配線１６の接続パッド部（上層絶縁膜１８の開口部１９内の部分）のサイズおよびピッチを柱状電極１２のサイズおよびピッチよりも大きくするためである。   By the way, the size of the base plate 1 is made somewhat larger than the size of the semiconductor structure 2 because the area where the solder balls 20 are arranged is increased as the number of connection pads 5 on the silicon substrate 4 increases. In order to increase the size and pitch of the connection pad portion of the upper layer rewiring 16 (the portion in the opening 19 of the upper layer insulating film 18) and the pitch of the columnar electrode 12 to a certain extent. It is.

このため、マトリクス状に配置された上層再配線１６の接続パッド部は、半導体構成体２に対応する領域のみでなく、半導体構成体２の周側面の外側に設けられた絶縁層１４に対応する領域上にも配置されている。つまり、マトリクス状に配置された半田ボール２０のうち、少なくとも最外周の半田ボール２０は半導体構成体２よりも外側に位置する周囲に配置されている。   For this reason, the connection pad portion of the upper layer rewiring 16 arranged in a matrix shape corresponds not only to the region corresponding to the semiconductor structure 2 but also to the insulating layer 14 provided outside the peripheral side surface of the semiconductor structure 2. It is also arranged on the area. That is, among the solder balls 20 arranged in a matrix, at least the outermost solder balls 20 are arranged around the semiconductor structure 2.

このように、この半導体装置では、シリコン基板４上に、接続パッド５、絶縁膜６を有するのみでなく、保護膜８、再配線１１、柱状電極１２、封止膜１３等をも形成した半導体構成体２の周囲およびそれらの上面に絶縁層１４および絶縁膜１５を設け、絶縁膜１５の上面に、該絶縁膜１５に形成された開口部１６を介して柱状電極１２に接続される、金属板をパターニングしてなる上層再配線１６を設ける構成を特徴としている。   As described above, in this semiconductor device, not only the connection pad 5 and the insulating film 6 are formed on the silicon substrate 4, but also a semiconductor in which the protective film 8, the rewiring 11, the columnar electrode 12, the sealing film 13 and the like are formed. An insulating layer 14 and an insulating film 15 are provided around the structure 2 and on the upper surface thereof, and the upper surface of the insulating film 15 is connected to the columnar electrode 12 through an opening 16 formed in the insulating film 15. The upper layer rewiring 16 formed by patterning the plate is provided.

この場合、絶縁膜１５の上面が平坦であることにより、後述する如く、以降の工程で形成する上層再配線１６や半田ボール２０の上面の高さ位置を均一にし、ボンディング時の信頼性を向上することができる。また、後述する如く、金属板をパターニングして形成する上層再配線１６の厚さを均一にすることができる上、上層再配線１６に段差が生じないようにすることができる。   In this case, since the upper surface of the insulating film 15 is flat, as will be described later, the upper layer rewiring 16 and the upper surface of the solder ball 20 to be formed in the subsequent steps are made uniform in height, thereby improving the reliability during bonding. can do. Further, as will be described later, the thickness of the upper layer rewiring 16 formed by patterning the metal plate can be made uniform, and a step can be prevented from occurring in the upper layer rewiring 16.

次に、この半導体装置の製造方法の一例について説明するに、まず、半導体構成体２の製造方法の一例について説明する。この場合、まず、図２に示すように、ウエハ状態のシリコン基板（半導体基板）４上にアルミニウム系金属等からなる接続パッド５、酸化シリコン等からなる絶縁膜６およびエポキシ系樹脂やポリイミド系樹脂等からなる保護膜８が設けられ、接続パッド５の中央部が絶縁膜６および保護膜８に形成された開口部７、９を介して露出されたものを用意する。上記において、ウエハ状態のシリコン基板４には、各半導体構成体が形成される領域に所定の機能の集積回路が形成され、接続パッド５は、それぞれ、対応する領域に形成された集積回路に電気的に接続されているものである。   Next, an example of a method for manufacturing the semiconductor device 2 will be described. In this case, first, as shown in FIG. 2, on a silicon substrate (semiconductor substrate) 4 in a wafer state, a connection pad 5 made of an aluminum-based metal, an insulating film 6 made of silicon oxide or the like, and an epoxy resin or a polyimide resin. A protective film 8 made of the like is provided, and the connection pad 5 is exposed through the openings 7 and 9 formed in the insulating film 6 and the protective film 8. In the above, on the silicon substrate 4 in the wafer state, an integrated circuit having a predetermined function is formed in a region where each semiconductor structure is formed, and the connection pad 5 is electrically connected to the integrated circuit formed in the corresponding region. Connected.

次に、図３に示すように、両開口部７、９を介して露出された接続パッド５の上面を含む保護膜８の上面全体に下地金属層１０を形成する。この場合、下地金属層１０は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。   Next, as shown in FIG. 3, a base metal layer 10 is formed on the entire upper surface of the protective film 8 including the upper surface of the connection pad 5 exposed through the openings 7 and 9. In this case, the base metal layer 10 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

次に、下地金属層１０の上面にメッキレジスト膜２１をパターン形成する。この場合、再配線１１形成領域に対応する部分におけるメッキレジスト膜２１には開口部２２が形成されている。次に、下地金属層１０をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜２１の開口部２２内の下地金属層１０の上面に再配線１１を形成する。次に、メッキレジスト膜２１を剥離する。   Next, a plating resist film 21 is patterned on the upper surface of the base metal layer 10. In this case, an opening 22 is formed in the plating resist film 21 in a portion corresponding to the rewiring 11 formation region. Next, by performing copper electrolytic plating using the base metal layer 10 as a plating current path, the rewiring 11 is formed on the upper surface of the base metal layer 10 in the opening 22 of the plating resist film 21. Next, the plating resist film 21 is peeled off.

次に、図４に示すように、再配線１１を含む下地金属層１０の上面にメッキレジスト膜２３をパターン形成する。この場合、柱状電極１２形成領域に対応する部分におけるメッキレジスト膜２３には開口部２４が形成されている。次に、下地金属層１０をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜２３の開口部２４内の再配線１１の接続パッド部上面に柱状電極１２を形成する。   Next, as shown in FIG. 4, a plating resist film 23 is formed on the upper surface of the base metal layer 10 including the rewiring 11. In this case, an opening 24 is formed in the plating resist film 23 in a portion corresponding to the columnar electrode 12 formation region. Next, the columnar electrode 12 is formed on the connection pad portion upper surface of the rewiring 11 in the opening 24 of the plating resist film 23 by performing electrolytic plating of copper using the base metal layer 10 as a plating current path.

次に、メッキレジスト膜２３を剥離し、次いで、柱状電極１２および再配線１１をマスクとして下地金属層１０の不要な部分をエッチングして除去すると、図５に示すように、再配線１１下にのみ下地金属層１０が残存される。   Next, the plating resist film 23 is peeled off, and then unnecessary portions of the base metal layer 10 are removed by etching using the columnar electrodes 12 and the rewiring 11 as a mask. As shown in FIG. Only the base metal layer 10 remains.

次に、図６に示すように、スクリーン印刷法、スピンコーティング法、ダイコート法等により、柱状電極１２および再配線１１を含む保護膜８の上面全体にエポキシ系樹脂やポリイミド系樹脂等からなる封止膜１３をその厚さが柱状電極１２の高さよりも厚くなるように形成する。したがって、この状態では、柱状電極１２の上面は封止膜１３によって覆われている。   Next, as shown in FIG. 6, the entire upper surface of the protective film 8 including the columnar electrode 12 and the rewiring 11 is sealed with an epoxy resin, a polyimide resin, or the like by screen printing, spin coating, die coating, or the like. The stop film 13 is formed so that its thickness is greater than the height of the columnar electrode 12. Therefore, in this state, the upper surface of the columnar electrode 12 is covered with the sealing film 13.

次に、封止膜１３および柱状電極１２の上面側を適宜に研磨し、図７に示すように、柱状電極１２の上面を露出させ、且つ、この露出された柱状電極１２の上面を含む封止膜１３の上面を平坦化する。ここで、柱状電極１２の上面側を適宜に研磨するのは、電解メッキにより形成される柱状電極１２の高さにばらつきがあるため、このばらつきを解消して、柱状電極１２の高さを均一にするためである。   Next, the upper surface side of the sealing film 13 and the columnar electrode 12 is appropriately polished to expose the upper surface of the columnar electrode 12 and to include the exposed upper surface of the columnar electrode 12 as shown in FIG. The upper surface of the stop film 13 is flattened. Here, the reason why the upper surface side of the columnar electrode 12 is appropriately polished is that there is a variation in the height of the columnar electrode 12 formed by electrolytic plating, so this variation is eliminated and the height of the columnar electrode 12 is made uniform. It is to make it.

次に、図８に示すように、シリコン基板４の下面全体に接着層３を接着する。接着層３は、エポキシ系樹脂、ポリイミド系樹脂等のダイボンド材からなるものであり、加熱加圧により、半硬化した状態でシリコン基板４に固着する。次に、シリコン基板４に固着された接着層３をダイシングテープ（図示せず）に貼り付け、図９に示すダイシング工程を経た後に、ダイシングテープから剥がすと、図１に示すように、シリコン基板４の下面に接着層３を有する半導体構成体２が複数個得られる。   Next, as shown in FIG. 8, the adhesive layer 3 is bonded to the entire lower surface of the silicon substrate 4. The adhesive layer 3 is made of a die bond material such as an epoxy resin or a polyimide resin, and is fixed to the silicon substrate 4 in a semi-cured state by heating and pressing. Next, the adhesive layer 3 fixed to the silicon substrate 4 is affixed to a dicing tape (not shown), passed through the dicing process shown in FIG. 9, and then peeled off from the dicing tape, as shown in FIG. A plurality of semiconductor structures 2 having the adhesive layer 3 on the lower surface of 4 are obtained.

このようにして得られた半導体構成体２では、シリコン基板４の下面に接着層３を有するため、ダイシング工程後に各半導体構成体２のシリコン基板４の下面にそれぞれ接着層を設けるといった極めて面倒な作業が不要となる。なお、ダイシング工程後にダイシングテープから剥がす作業は、ダイシング工程後に各半導体構成体２のシリコン基板４の下面にそれぞれ接着層を設ける作業に比べれば、極めて簡単である。   Since the semiconductor structure 2 obtained in this way has the adhesive layer 3 on the lower surface of the silicon substrate 4, it is extremely troublesome to provide an adhesive layer on the lower surface of the silicon substrate 4 of each semiconductor structure 2 after the dicing process. Work becomes unnecessary. In addition, the operation | work which peels from a dicing tape after a dicing process is very simple compared with the operation | work which each provides an adhesive layer on the lower surface of the silicon substrate 4 of each semiconductor structure 2 after a dicing process.

次に、このようにして得られた半導体構成体２を用いて、図１に示す半導体装置を製造する場合の一例について説明する。まず、図１０に示すように、図１に示すベース板１を複数枚採取することができる大きさで、限定する意味ではないが、平面形状が矩形形状のベース板１を用意する。次に、ベース板１の上面の所定の複数箇所にそれぞれ半導体構成体２のシリコン基板４の下面に接着された接着層３を接着する。ここでの接着は、加熱加圧により、接着層３を本硬化させる。   Next, an example of manufacturing the semiconductor device shown in FIG. 1 using the semiconductor structure 2 obtained in this way will be described. First, as shown in FIG. 10, the base plate 1 is prepared in such a size that a plurality of the base plates 1 shown in FIG. Next, the adhesive layer 3 bonded to the lower surface of the silicon substrate 4 of the semiconductor structure 2 is bonded to a plurality of predetermined locations on the upper surface of the base plate 1. In this bonding, the adhesive layer 3 is fully cured by heating and pressing.

次に、図１１に示すように、スクリーン印刷法、スピンコーティング法、ダイコート法等により、半導体構成体２を含むベース板１の上面全体にエポキシ系樹脂やポリイミド樹脂等からなる絶縁層１４をその厚さが半導体構成体２の高さよりも厚くなるように形成する。したがって、この状態では、半導体構成体２の上面は絶縁層１４によって覆われている。   Next, as shown in FIG. 11, an insulating layer 14 made of epoxy resin, polyimide resin, or the like is formed on the entire upper surface of the base plate 1 including the semiconductor structure 2 by screen printing, spin coating, die coating, or the like. It is formed so that the thickness is greater than the height of the semiconductor structure 2. Therefore, in this state, the upper surface of the semiconductor structure 2 is covered with the insulating layer 14.

次に、少なくとも絶縁層１４の上面側を適宜に研磨することにより、図１２に示すように、柱状電極１２の上面を露出させ、且つ、この露出された柱状電極１２の上面を含む封止膜１３の上面（つまり半導体構成体２の上面）および絶縁層１４の上面を平坦化する。   Next, at least the upper surface side of the insulating layer 14 is appropriately polished, so that the upper surface of the columnar electrode 12 is exposed and the sealing film including the exposed upper surface of the columnar electrode 12 as shown in FIG. The upper surface of 13 (that is, the upper surface of the semiconductor structure 2) and the upper surface of the insulating layer 14 are planarized.

次に、図１３に示すように、半導体構成体２および絶縁層１４の上面にシート状の絶縁材料１５ａを載置する。この場合、絶縁材料１５ａは、例えば、プリプレグ材と言われるもので、ガラス繊維にエポキシ系樹脂を含浸させ、エポキシ系樹脂を半硬化状態としたものである。なお、絶縁材料１５ａは、平坦性を得るために、シート状であることが好ましいが、必ずしもプリプレグ材に限られるものではなく、エポキシ系樹脂やポリイミド系樹脂等の熱硬化性樹脂のみからなるものであってもよい。   Next, as shown in FIG. 13, a sheet-like insulating material 15 a is placed on the upper surfaces of the semiconductor structure 2 and the insulating layer 14. In this case, the insulating material 15a is, for example, a prepreg material, in which an epoxy resin is impregnated into a glass fiber to make the epoxy resin semi-cured. The insulating material 15a is preferably in the form of a sheet in order to obtain flatness, but is not necessarily limited to a prepreg material, and is made only of a thermosetting resin such as an epoxy resin or a polyimide resin. It may be.

次に、絶縁材料１５ａの上面に、金属板１６ａの下面の所定の箇所に裁頭円錐形状の突起電極１７が形成されたものを位置合わせして載置する。すなわち、突起電極１７の先端部を柱状電極１２の上面中央部上における絶縁材料１５ａの上面に載置する。なお、突起電極１７を有する金属板１６ａの形成方法については後で説明する。   Next, on the upper surface of the insulating material 15a, the one in which the truncated conical projection electrodes 17 are formed at predetermined positions on the lower surface of the metal plate 16a is positioned and placed. That is, the tip of the protruding electrode 17 is placed on the upper surface of the insulating material 15 a on the center of the upper surface of the columnar electrode 12. A method for forming the metal plate 16a having the protruding electrodes 17 will be described later.

次に、図１４に示すように、加熱加圧により、裁頭円錐形状の突起電極１７を絶縁材料１５ａに食い込ませて柱状電極１２の上面中央部に当接させ、且つ、絶縁材料１５ａ中のエポキシ系樹脂を本硬化させる。すると、半導体構成体２の上面を含む絶縁層１４の上面に絶縁膜１５が形成されるとともに、この絶縁膜１５の上面に金属板１６ａが固着される。   Next, as shown in FIG. 14, the frustoconical protruding electrode 17 is bitten into the insulating material 15 a by heat and pressure so as to contact the center of the upper surface of the columnar electrode 12, and the insulating material 15 a The epoxy resin is fully cured. Then, the insulating film 15 is formed on the upper surface of the insulating layer 14 including the upper surface of the semiconductor structure 2, and the metal plate 16 a is fixed to the upper surface of the insulating film 15.

次に、金属板１６ａをフォトリソグラフィ法によりパターニングすると、図１５に示すように、絶縁膜１５の上面の所定の箇所に上層再配線１６が形成される。この状態では、上層再配線１６は、絶縁膜１５に食い込んだ突起電極１７を介して柱状電極１２の上面中央部に接続されている。   Next, when the metal plate 16a is patterned by photolithography, the upper layer rewiring 16 is formed at a predetermined position on the upper surface of the insulating film 15, as shown in FIG. In this state, the upper layer rewiring 16 is connected to the center of the upper surface of the columnar electrode 12 through the protruding electrode 17 that has digged into the insulating film 15.

次に、図１６に示すように、スクリーン印刷法やスピンコーティング法等により、上層再配線１６を含む絶縁膜１５の上面全体にソルダーレジストからなる上層絶縁膜１８を形成する。この場合、上層再配線１６の接続パッド部に対応する部分における上層絶縁膜１８には開口部１９が形成されている。次に、開口部１９内およびその上方に半田ボール２０を上層再配線１６の接続パッド部に接続させて形成する。   Next, as shown in FIG. 16, an upper insulating film 18 made of a solder resist is formed on the entire upper surface of the insulating film 15 including the upper rewiring 16 by screen printing, spin coating, or the like. In this case, an opening 19 is formed in the upper insulating film 18 in a portion corresponding to the connection pad portion of the upper rewiring 16. Next, a solder ball 20 is formed in the opening 19 and above it by connecting it to the connection pad portion of the upper layer rewiring 16.

次に、図１７に示すように、互いに隣接する半導体構成体２間において、上層絶縁膜１８、絶縁膜１５、絶縁層１４およびベース板１を切断すると、図１に示す半導体装置が複数個得られる。   Next, as shown in FIG. 17, when the upper insulating film 18, the insulating film 15, the insulating layer 14, and the base plate 1 are cut between adjacent semiconductor structures 2, a plurality of semiconductor devices shown in FIG. 1 are obtained. It is done.

以上のように、上記製造方法では、金属板１６ａに形成された突起電極１７を絶縁膜１５に食い込ませて半導体構成体２の柱状電極１２に接続し、この後、金属板１６ａをパターニングして上層再配線１６を形成しているので、絶縁膜１５に層間接続用の開口部を形成する必要がなく、また、電解メッキではないので、下地金属層を成膜したりその不要部分を除去したりする必要もなく、したがって工程数が低減し、生産性を向上することができる。   As described above, in the above manufacturing method, the protruding electrode 17 formed on the metal plate 16a is bitten into the insulating film 15 and connected to the columnar electrode 12 of the semiconductor structure 2, and then the metal plate 16a is patterned. Since the upper layer rewiring 16 is formed, it is not necessary to form an opening for interlayer connection in the insulating film 15, and since it is not electrolytic plating, a base metal layer is formed or unnecessary portions thereof are removed. Therefore, the number of processes can be reduced and productivity can be improved.

また、絶縁膜１５の上面が平坦であることにより、以降の工程で形成する上層再配線１６や半田ボール２０の上面の高さ位置を均一にし、ボンディング時の信頼性を向上することができる。また、金属板をパターニングして形成する上層再配線１６の厚さを均一にすることができる上、上層再配線１６に段差が生じないようにすることができる。   Further, since the upper surface of the insulating film 15 is flat, the height positions of the upper surfaces of the upper layer rewiring 16 and the solder balls 20 formed in the subsequent steps can be made uniform, and the reliability during bonding can be improved. In addition, the thickness of the upper layer rewiring 16 formed by patterning the metal plate can be made uniform, and a step can be prevented from occurring in the upper layer rewiring 16.

さらに、ベース板１上に複数の半導体構成体２を接着層３を介して配置し、複数の半導体構成体２に対して絶縁沿う１４、絶縁膜１５、上層再配線１６、上層絶縁膜１８および半田ボール２０の形成を一括して行い、その後に分断して複数個の半導体装置を得ているので、製造工程を簡略化することができる。また、図１２に示す製造工程以降では、ベース板１と共に複数の半導体構成体２を搬送することができるので、これによっても製造工程を簡略化することができる。   Further, a plurality of semiconductor structures 2 are arranged on the base plate 1 via the adhesive layer 3, and the insulating film 15, the upper layer rewiring 16, the upper layer insulating film 18, Since the solder balls 20 are formed in a lump and then divided to obtain a plurality of semiconductor devices, the manufacturing process can be simplified. In addition, after the manufacturing process shown in FIG. 12, a plurality of semiconductor structures 2 can be transported together with the base plate 1, so that the manufacturing process can be simplified.

ここで、突起電極１７を有する金属板１６ａの形成方法について説明する。この場合、まず、図１８に示すように、一定の厚さの金属板１６ｂの上面全体に上面レジスト膜３１を形成するとともに、下面の所定の箇所（つまり突起電極１７形成領域）に平面円形状の下面レジスト膜３２を形成する。次に、図１９に示すように、ハーフウェットエッチングを行なうと、エッチングが等方的に進行することにより、下面レジスト膜３２が存在しない領域に厚さが薄くなった金属板１６ａが形成され、且つ、この厚さが薄くなった金属板１６ａの下面において下面レジスト膜４２が存在する領域に裁頭円錐形状の突起電極１７が形成される。次に、両レジスト膜４１、４２を除去すると、図２０に示すように、突起電極１７を有する金属板１６ａが得られる。   Here, a method of forming the metal plate 16a having the protruding electrodes 17 will be described. In this case, first, as shown in FIG. 18, the upper resist film 31 is formed on the entire upper surface of the metal plate 16b having a constant thickness, and a planar circular shape is formed at a predetermined position on the lower surface (that is, the projecting electrode 17 formation region). The lower resist film 32 is formed. Next, as shown in FIG. 19, when half wet etching is performed, the etching proceeds isotropically to form a metal plate 16a having a reduced thickness in a region where the lower resist film 32 does not exist, In addition, the truncated conical projection electrode 17 is formed in a region where the lower resist film 42 exists on the lower surface of the metal plate 16a having the reduced thickness. Next, when the resist films 41 and 42 are removed, a metal plate 16a having the protruding electrodes 17 is obtained as shown in FIG.

次に、突起電極１７を有する金属板１６ａの寸法の一例について説明する。当初の金属板１６ｂの厚さを１００μｍ程度とし、突起電極１７の高さを８０μｍ程度とすると、突起電極１７を有する金属板１６ａの厚さは２０μｍ程度となる。また、突起電極１７の根元の径を５０μｍ程度とし、頭部の径を２０μｍ程度とする。   Next, an example of the dimension of the metal plate 16a having the protruding electrode 17 will be described. If the initial thickness of the metal plate 16b is about 100 μm and the height of the protruding electrode 17 is about 80 μm, the thickness of the metal plate 16a having the protruding electrode 17 is about 20 μm. Further, the base diameter of the protruding electrode 17 is set to about 50 μm, and the head diameter is set to about 20 μm.

このようにした場合には、図１３に示す絶縁材料１５ａとして、ＦＲ−４のガラス繊維にエポキシ系樹脂を含浸させたプリプレグ材を用いるとともに、その厚さを突起電極１７の高さに対応して８０μｍ程度とすると、加熱温度９５〜１１５℃の範囲において、この絶縁材料１５ａに突起電極１７を良好に食い込ませることができる。   In this case, as the insulating material 15a shown in FIG. 13, a prepreg material in which an epoxy resin is impregnated with a glass fiber of FR-4 is used, and the thickness corresponds to the height of the protruding electrode 17. When the thickness is about 80 μm, the protruding electrode 17 can be satisfactorily bitten into the insulating material 15a in the heating temperature range of 95 to 115 ° C.

突起電極１７の他の形成方法としては、金属板の一面の所定の箇所に印刷された銀ペーストなどからなる導電ペーストを硬化させて、突起電極を形成するようにしてもよい。この場合、一例として、金属板の厚さを２０μｍ程度とし、硬化銀ペーストからなる突起電極の高さを８０μｍ程度とし、根元の径を４００μｍ程度とし、頭部の径を２００μｍ程度とする。   As another method for forming the protruding electrode 17, the protruding electrode may be formed by curing a conductive paste made of silver paste or the like printed on a predetermined portion of one surface of the metal plate. In this case, as an example, the thickness of the metal plate is about 20 μm, the height of the protruding electrode made of hardened silver paste is about 80 μm, the root diameter is about 400 μm, and the head diameter is about 200 μm.

なお、各部材の厚さは上記に限定されるものではなく、金属板１６ａの厚さは５０〜２００μｍ、絶縁材料１５ａの厚さは２０〜１５０μｍとすることが可能である。この場合、金属板１６ａに形成する突起電極１７の高さは絶縁材料１５ａの厚さと同一かそれよりも少し高い、典型的には、２０μｍ程度以下高い寸法とすればよい。また、金属板１６ａは、銅の単層からなるものに限らず、例えば、ニッケル等のベース板と銅等の突起電極形成板とからなる二層積層構造のものでもよい。   The thickness of each member is not limited to the above. The thickness of the metal plate 16a can be 50 to 200 μm, and the thickness of the insulating material 15a can be 20 to 150 μm. In this case, the height of the protruding electrode 17 formed on the metal plate 16a may be the same as or slightly higher than the thickness of the insulating material 15a, typically about 20 μm or less. Further, the metal plate 16a is not limited to a single layer of copper, and may be of a two-layer structure including a base plate made of nickel or the like and a protruding electrode forming plate made of copper or the like.

また、上記実施形態においては、半田ボール２０を、半導体構成体２上およびその周囲の絶縁層１４上の全面に対応してマトリクス状に配列されるよう設けているが、半田ボール２０を半導体構成体２の周囲の絶縁層１４上に対応する領域上にのみ設けるようにしてもよい。その場合、半田ボール２０を半導体構成体２の全周囲ではなく、半導体構成体２の４辺の中、１〜３辺の側方のみに設けてもよい。また、このような場合には、絶縁層１４を矩形枠状のものとする必要はなく、半田ボール２０を設ける辺の側方のみに配置されるようにしてもよい。   In the above embodiment, the solder balls 20 are provided so as to be arranged in a matrix corresponding to the entire surface of the semiconductor structure 2 and the surrounding insulating layer 14. It may be provided only on the region corresponding to the insulating layer 14 around the body 2. In that case, the solder balls 20 may be provided not on the entire periphery of the semiconductor structure 2 but only on the sides of the 1st to 3rd sides of the 4 sides of the semiconductor structure 2. In such a case, the insulating layer 14 does not need to have a rectangular frame shape, and may be disposed only on the side where the solder ball 20 is provided.

（変形例）
上記実施形態では、例えば、図１に示すように、絶縁膜１５上に上層再配線１６および上層絶縁膜１８をそれぞれ１層ずつ形成した場合について説明したが、これに限らず、それぞれ２層ずつ以上としてもよく、例えば、図２１に示す変形例のように、それぞれ２層ずつとしてもよい。 (Modification)
In the embodiment described above, for example, as shown in FIG. 1, the case where one upper layer rewiring 16 and one upper layer insulating film 18 are formed on the insulating film 15 has been described. For example, two layers may be provided as in the modification shown in FIG.

すなわち、半導体構成体２および絶縁層１４の上面にはプリプレグ材等からなる第１の上層絶縁膜４１が設けられている。第１の上層絶縁膜４１の上面には第１の上層再配線４２が第１の上層絶縁膜４１に食い込んだ突起電極４３を介して柱状電極１２の上面に接続されて設けられている。第１の上層再配線４２を含む第１の上層絶縁膜４１の上面にはプリプレグ材からなる等からなる第２の上層絶縁膜４４が設けられている。第２の上層絶縁膜４４の上面には第２の上層再配線４５が第２の上層絶縁膜４４に食い込んだ突起電極４６を介して第１の上層再配線４２の接続パッド部上面に接続されて設けられている。   That is, the first upper insulating film 41 made of a prepreg material or the like is provided on the upper surfaces of the semiconductor structure 2 and the insulating layer 14. A first upper layer rewiring 42 is provided on the upper surface of the first upper insulating film 41 so as to be connected to the upper surface of the columnar electrode 12 via a protruding electrode 43 that has penetrated into the first upper insulating film 41. A second upper layer insulating film 44 made of a prepreg material or the like is provided on the upper surface of the first upper layer insulating film 41 including the first upper layer rewiring 42. A second upper layer rewiring 45 is connected to an upper surface of the connection pad portion of the first upper layer rewiring 42 via a protruding electrode 46 that has penetrated into the second upper layer insulating film 44 on the upper surface of the second upper layer insulating film 44. Is provided.

第２の上層再配線４５を含む第２の上層絶縁膜４４の上面にはソルダーレジスト等からなる第３の上層絶縁膜４７が設けられている。第２の上層再配線４５の接続パッド部に対応する部分における第３の上層絶縁膜４７には開口部４８が設けられている。開口部４８内およびその上方には半田ボール４９が第２の上層再配線４５の接続パッド部に接続されて設けられている。   A third upper layer insulating film 47 made of a solder resist or the like is provided on the upper surface of the second upper layer insulating film 44 including the second upper layer rewiring 45. An opening 48 is provided in the third upper-layer insulating film 47 in a portion corresponding to the connection pad portion of the second upper-layer rewiring 45. Solder balls 49 are provided in and above the opening 48 so as to be connected to the connection pad portion of the second upper layer rewiring 45.

（他の変形例）
また、図１７に示す場合には、互いに隣接する半導体構成体２間において切断したが、これに限らず、２個またはそれ以上の半導体構成体２を１組として切断し、例えば、図２２に示す他の変形例のように、２個の半導体構成体２を１組として切断し、マルチチップモジュール型の半導体装置を得るようにしてもよい。この場合、２個で１組の半導体構成体２は同種、異種のいずれであってもよい。 (Other variations)
In the case shown in FIG. 17, the semiconductor structures 2 adjacent to each other are cut. However, the present invention is not limited to this, and two or more semiconductor structures 2 are cut as one set. As in another modification shown, two semiconductor structures 2 may be cut as a set to obtain a multichip module type semiconductor device. In this case, the two sets of semiconductor structures 2 may be of the same type or different types.

（その他の実施形態）
なお、上記各実施形態において、半導体構成体２は、外部接続用電極として、接続パッド５の他に、再配線１１、柱状電極１２を有するものとしたが、本発明は、半導体構成体２の外部接続用電極として接続パッド５のみを有するもの、或いは接続パッド５、および接続パッド部を有する再配線１１を有するものに適用することが可能である。 (Other embodiments)
In each of the embodiments described above, the semiconductor structure 2 has the rewiring 11 and the columnar electrode 12 in addition to the connection pad 5 as the external connection electrode. The present invention can be applied to an electrode having only the connection pad 5 as an external connection electrode, or one having the connection pad 5 and the rewiring 11 having the connection pad portion.

この発明の一実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as an embodiment of the present invention. 図１に示す半導体装置の製造方法の一例において、当初用意したものの断面図。Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く工程の断面図。Sectional drawing of the process following FIG. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図９に続く工程の断面図。Sectional drawing of the process following FIG. 図１０に続く工程の断面図。Sectional drawing of the process following FIG. 図１１に続く工程の断面図。Sectional drawing of the process following FIG. 図１２に続く工程の断面図。Sectional drawing of the process following FIG. 図１３に続く工程の断面図。Sectional drawing of the process following FIG. 図１４に続く工程の断面図。FIG. 15 is a cross-sectional view of the process following FIG. 14. 図１５に続く工程の断面図。FIG. 16 is a cross-sectional view of the process following FIG. 15. 図１６に続く工程の断面図。FIG. 17 is a cross-sectional view of the process following FIG. 16. 突起電極を有する銅板の形成に際し、当初の工程の断面図。Sectional drawing of an original process in the case of formation of the copper plate which has a protruding electrode. 図１８に続く工程の断面図。FIG. 19 is a cross-sectional view of the process following FIG. 18. 図１９に続く工程の断面図。FIG. 20 is a cross-sectional view of the process following FIG. 19. この発明の変形例としての半導体装置の断面図。Sectional drawing of the semiconductor device as a modification of this invention. この発明の他の変形例としての半導体装置の断面図。Sectional drawing of the semiconductor device as another modification of this invention.

符号の説明Explanation of symbols

１ ベース板
２ 半導体構成体
３ 接着層
４ シリコン基板
５ 接続パッド
６ 絶縁膜
８ 保護膜
１０ 下地金属層
１１ 再配線
１２ 柱状電極
１３ 封止膜
１４ 絶縁層
１５ 絶縁膜
１６ 上層再配線
１７ 突起電極
１８ 上層絶縁膜
２０ 半田ボール DESCRIPTION OF SYMBOLS 1 Base board 2 Semiconductor structure 3 Adhesion layer 4 Silicon substrate 5 Connection pad 6 Insulating film 8 Protective film 10 Underlayer metal layer 11 Rewiring 12 Columnar electrode 13 Sealing film 14 Insulating layer 15 Insulating film 16 Upper layer rewiring 17 Projection electrode 18 Upper insulating film 20 Solder ball

Claims (16)

複数の外部接続用電極を有する半導体構成体の上面を絶縁膜で覆う工程と、
前記絶縁層上に前記各外部接続用電極に対応する突起電極を有する金属板を配置する工程と、
前記金属板の各突起電極を前記絶縁膜に食い込ませて前記各外部接続用電極に接続する工程と、
前記金属板をパターニングして再配線を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 Covering an upper surface of a semiconductor structure having a plurality of external connection electrodes with an insulating film;
Disposing a metal plate having protruding electrodes corresponding to the external connection electrodes on the insulating layer;
A step of causing each protruding electrode of the metal plate to bite into the insulating film and connecting to each external connection electrode;
Patterning the metal plate to form a rewiring;
A method for manufacturing a semiconductor device, comprising: 請求項１に記載の発明において、前記半導体構成体は、接続パッドと、該接続パッドに接続された柱状の外部接続用電極と、該外部接続用電極の周囲に設けられた封止膜とを含むことを特徴とする半導体装置の製造方法。   In the invention according to claim 1, the semiconductor structure includes a connection pad, a columnar external connection electrode connected to the connection pad, and a sealing film provided around the external connection electrode. A method for manufacturing a semiconductor device, comprising: 請求項２に記載の発明において、前記半導体構成体は、前記接続パッドと前記外部接続用電極とを接続する再配線を含むことを特徴とする半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 2, wherein the semiconductor structure includes a rewiring that connects the connection pad and the external connection electrode. 請求項１に記載の発明において、前記絶縁膜はシートであることを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a sheet. 請求項４に記載の発明において、前記絶縁膜の上面は平坦であることを特徴とする半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 4, wherein an upper surface of the insulating film is flat. 請求項１に記載の発明において、前記金属板の突起電極を前記絶縁膜に食い込ませる工程は前記絶縁膜が半硬化の状態で行ない、この後、加熱により、前記絶縁膜を本硬化させるとともに、前記金属板を前記絶縁膜上に固着することを特徴とする半導体装置の製造方法。   In the invention according to claim 1, the step of causing the protruding electrode of the metal plate to bite into the insulating film is performed in a state where the insulating film is semi-cured, and then the insulating film is fully cured by heating, A method of manufacturing a semiconductor device, wherein the metal plate is fixed onto the insulating film. 請求項１に記載の発明において、前記金属板よりも厚めの金属板の下面をハーフウェットエッチングすることにより、前記突起電極を前記金属板下に一体的に且つ裁頭円錐形状に形成することを特徴とする半導体装置の製造方法。   In the invention according to claim 1, the bottom surface of the metal plate thicker than the metal plate is half-wet etched to form the protruding electrode integrally and in a truncated cone shape under the metal plate. A method of manufacturing a semiconductor device. 請求項１に記載の発明において、前記突起電極を、前記金属板下に金属ペーストを印刷して裁頭円錐形状に形成することを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the protruding electrode is formed in a truncated cone shape by printing a metal paste under the metal plate. 請求項１に記載の発明において、前記半導体構成体の上面を前記絶縁膜で覆う工程の前に、ベース板上に、各々が半導体基板上に設けられた複数の外部接続用電極を有する複数の半導体構成体を相互に離間させて配置する工程と、前記各半導体構成体の周側面に絶縁層を形成する工程とを有し、この後、前記半導体構成体および前記絶縁層の上面を前記絶縁膜で覆うことを特徴とする半導体装置の製造方法。   In the invention according to claim 1, before the step of covering the upper surface of the semiconductor structure with the insulating film, a plurality of external connection electrodes each provided on the semiconductor substrate are provided on the base plate. A step of disposing semiconductor structures apart from each other and a step of forming an insulating layer on a peripheral side surface of each semiconductor structure, and then insulating the top surfaces of the semiconductor structure and the insulating layer from each other A method for manufacturing a semiconductor device, comprising covering with a film. 請求項９に記載の発明において、前記金属板をパターニングして前記再配線を形成する工程の後、前記半導体構成体間における前記絶縁膜および前記絶縁層を切断して少なくとも前記半導体構成体が１つ含まれる半導体装置に分離することを特徴とする半導体装置の製造方法。   The invention according to claim 9, wherein after the step of patterning the metal plate to form the rewiring, the insulating film and the insulating layer between the semiconductor constituents are cut to form at least the semiconductor constituent 1. A method of manufacturing a semiconductor device, comprising: separating the semiconductor device into two semiconductor devices. 請求項１０に記載の発明において、前記切断は、前記半導体構成体が複数個含まれるように切断することを特徴とする半導体装置の製造方法。   11. The method of manufacturing a semiconductor device according to claim 10, wherein the cutting is performed so that a plurality of the semiconductor structural bodies are included. 請求項１０に記載の発明において、前記切断工程で前記絶縁膜および前記絶縁層を切断するとともに前記ベース板を切断し、前記半導体装置として前記ベース板を備えたものを得ることを特徴とする半導体装置の製造方法。   The semiconductor device according to claim 10, wherein the insulating film and the insulating layer are cut in the cutting step and the base plate is cut to obtain the semiconductor device including the base plate. Device manufacturing method. 請求項１に記載の発明において、前記金属板をパターニングして再配線を形成する工程の後、前記絶縁膜および前記再配線上に１層以上の上層の絶縁膜と、前記上層の絶縁膜上に形成され下層の再配線の接続パッド部に接続された上層の再配線を形成する工程を有することを特徴とする半導体装置の製造方法。   2. The invention according to claim 1, wherein after the step of patterning the metal plate to form a rewiring, one or more upper insulating films on the insulating film and the rewiring, and on the upper insulating film A method for manufacturing a semiconductor device, comprising: forming an upper layer rewiring connected to a connection pad portion of a lower layer rewiring. 請求項１３に記載の発明において、前記最上層の再配線の接続パッド部を除く部分を覆う上層の絶縁膜を形成する工程を有することを特徴とする半導体装置の製造方法。   14. The method of manufacturing a semiconductor device according to claim 13, further comprising a step of forming an upper insulating film that covers a portion excluding the connection pad portion of the uppermost rewiring. 請求項１３に記載の発明において、前記上層の再配線の少なくとも一部は突起電極を有し、該突起電極を前記下層の絶縁膜に食い込ませて前記下層の再配線の接続パッド部に接続する工程を有することを特徴とする半導体装置の製造方法。   14. The invention according to claim 13, wherein at least a part of the upper layer rewiring has a protruding electrode, and the protruding electrode bites into the lower insulating film and is connected to the connection pad portion of the lower layer rewiring. A method for manufacturing a semiconductor device, comprising: a step. 請求項１３に記載の発明において、前記最上層の再配線の接続パッド部上に半田ボールを形成する工程を有することを特徴とする半導体装置の製造方法。   14. The method of manufacturing a semiconductor device according to claim 13, further comprising a step of forming a solder ball on a connection pad portion of the uppermost rewiring.
JP2007029902A 2007-02-09 2007-02-09 Manufacturing method of semiconductor device Expired - Fee Related JP4577316B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007029902A JP4577316B2 (en) 2007-02-09 2007-02-09 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007029902A JP4577316B2 (en) 2007-02-09 2007-02-09 Manufacturing method of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2003142830A Division JP2004349361A (en) 2003-05-21 2003-05-21 Semiconductor device and its manufacturing method

Publications (2)

Publication Number Publication Date
JP2007123941A true JP2007123941A (en) 2007-05-17
JP4577316B2 JP4577316B2 (en) 2010-11-10

Family

ID=38147342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007029902A Expired - Fee Related JP4577316B2 (en) 2007-02-09 2007-02-09 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP4577316B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008288481A (en) * 2007-05-21 2008-11-27 Casio Comput Co Ltd Semiconductor device and method for manufacturing the same
JP2009027042A (en) * 2007-07-20 2009-02-05 Sanyo Electric Co Ltd Circuit module, method of manufacturing circuit module and mobile device
CN111668168A (en) * 2019-03-08 2020-09-15 江苏长电科技股份有限公司 Packaging structure and forming method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1032224A (en) * 1996-07-15 1998-02-03 Shinko Electric Ind Co Ltd Semiconductor device and manufacture thereof
JP2002176235A (en) * 2000-12-06 2002-06-21 Ibiden Co Ltd Connected material and its producing method and method for producing connection structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1032224A (en) * 1996-07-15 1998-02-03 Shinko Electric Ind Co Ltd Semiconductor device and manufacture thereof
JP2002176235A (en) * 2000-12-06 2002-06-21 Ibiden Co Ltd Connected material and its producing method and method for producing connection structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008288481A (en) * 2007-05-21 2008-11-27 Casio Comput Co Ltd Semiconductor device and method for manufacturing the same
JP2009027042A (en) * 2007-07-20 2009-02-05 Sanyo Electric Co Ltd Circuit module, method of manufacturing circuit module and mobile device
CN111668168A (en) * 2019-03-08 2020-09-15 江苏长电科技股份有限公司 Packaging structure and forming method thereof
CN111668168B (en) * 2019-03-08 2022-06-10 江苏长电科技股份有限公司 Packaging structure and forming method thereof

Also Published As

Publication number Publication date
JP4577316B2 (en) 2010-11-10

Similar Documents

Publication Publication Date Title
JP2004349361A (en) Semiconductor device and its manufacturing method
JP3945483B2 (en) Manufacturing method of semiconductor device
JP3925809B2 (en) Semiconductor device and manufacturing method thereof
JP4055717B2 (en) Semiconductor device and manufacturing method thereof
JP4012496B2 (en) Semiconductor device
JP4851794B2 (en) Semiconductor device
JP4609317B2 (en) Circuit board
JP2004119728A (en) Method of manufacturing circuit device
US20040092129A1 (en) Method for manufacturing circuit devices
JP4379693B2 (en) Semiconductor device and manufacturing method thereof
JP4135390B2 (en) Semiconductor device and manufacturing method thereof
JP4577316B2 (en) Manufacturing method of semiconductor device
JP3925503B2 (en) Semiconductor device
KR20040030301A (en) Method of manufacturing circuit device
JP2008288481A (en) Semiconductor device and method for manufacturing the same
JP5137320B2 (en) Semiconductor device and manufacturing method thereof
JP2007116198A (en) Semiconductor device
JP4321758B2 (en) Semiconductor device
JP2002076166A (en) Resin sealing type semiconductor device and its manufacturing method
JP4316623B2 (en) Manufacturing method of semiconductor device
JP4913372B2 (en) Semiconductor device
JP2006229111A (en) Process for manufacturing semiconductor device and semiconductor device
JP4461801B2 (en) Semiconductor device and manufacturing method thereof
JP2008060298A (en) Semiconductor constitutional body and its manufacturing method, and semiconductor device and its manufacturing method
JP2005116714A (en) Semiconductor device and its manufacturing method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070209

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091117

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100112

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100406

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100526

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100727

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100809

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130903

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130903

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130903

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130903

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees